Problem 10.1
By Vehid Suljic
Using the parameters in Table 6.1 compare the hand-calculated effective digital
switching resistance using Eq. (10.6) to the empirically derived values given in table
10.1.
Using equation 10.6 ,
Rn = VDD/[0.5 KPn (W/L) (VDD-Vthn)2]
Pluging in values for the parameters from table 6.1 we obtain switching resistance,
Rn = 4.7K (L/W)
However, empirically derived Rn in table 10.1 is Rn = 15K (L/W) which is very different
from hand calculated results above.
This is due to the mobility (µ, Kpn = µ Cox’ ) that is not constant with applied voltage
(electric field).
Problem 10.5
Indira Priyadarshini. Vemula
For the following circuits estimate the delay between the input and the output. Use
the 50nm (short channel CMOS)process. Verify the estimates with spice?
a)
tdelay=0.7*Rn*Ctot
=0.7*34K/10*(62.5 aF*10+20 Ff)
=49.08 ps
***PROBLEM 10.5A****
.control
destroy all
run
plot vout vin ylimit 0 1
.endc
.option scale=50n
.ic v(vout)=1
.tran 10p 500p UIC
vin vin 0 dc 0 pulse 0 1 200p 100p
M1 vout vin 0 0 NMOS L=1 W=10
C1 vout 0 20f
**models included
b)
Rn=3.4K+3.4K
=6.8K
tdelay=0.7*6.8K*(62.5 Af*10+20 fF)
=98.17 ps
***PROBLEM 10.5B****
.control
destroy all
run
plot vout vin ylimit 0 1
.endc
.option scale=50n
.tran 10p 4n UIC
vdd vdd 0 dc 1
vin vin 0 dc 0 pulse 0 1 100p 100p 100p 1n 2n
M1 vout vin n1 0 NMOS L=1 W=10
M2 n1 vdd 0 0 NMOS L=10 W=10
C1 vout 0 20f IC=1
**models included
We are doing this problem using short channel process, but here the length of the MOFET is 10 which
cause the resistance to increase. This results in increase in time delay when compared to the calculated
value.
C)
tdelay=0.7*Rp*Ctot
=0.7*68K/20(62.5 Af*20*20+20 fF)
=107.1 ps
***PROBLEM 10.5c****
.control
destroy all
run
plot vout vin
.endc
.option scale=50n
.ic v(vout)=0 v(vin)=1
.tran 10p 8n UIC
vdd vdd 0 dc 1
vin vin 0 dc 0 pulse 1 0 200p 100p
M1 vout vin vdd vdd PMOS L=20 W=20
C1 vout 0 20f
**models included
We are doing this problem using short channel process, but here the length of the MOFET is 20 which
cause the resistance to increase. This results in increase in time delay when compared to the calculated
value.
d)
tdelay=0.35*Rp*Cox*l2+0.7*Rp*CL*l
=(0.35*3.4K*1.25Ff*16)+(0.7*3.4K*10Ff*4)
=119 ps
***PROBLEM 10.5d****
.control
destroy all
run
plot vout vin ylimit 0 1
.endc
.option scale=50n
.tran 10p 12n 5n UIC
vdd vdd 0 dc 1
vin vin 0 dc 0 pulse 0 1 5n 100p 100p 5n 10n
M1 vin 0 n1 vdd PMOS L=1 W=20
M2 n1 0 n2 vdd PMOS L=1 W=20
M3 n2 0 n3 vdd PMOS L=1 W=20
M4 n3 0 vout vdd PMOS L=1 W=20
C1 vout 0 10f
**models included
PROBLEM # 11.1
Meshack Pavan.A
Estimate the noise margins for the inverters used to generate Fig. 11.4.
Solution: From the graphs in Fig. 11.4 and the text in p11.3, we have
VOH
VOL
VIL
VIH
=
=
=
=
5V
0V
1.8V
2.1V
Long channel
Process
Therefore, noise margins,
NMH = VOH - VIH = 5 – 2.1 = 2.9V
NML = VIL - VOL = 1.8 – 0 = 1.8V
For the short channel process, similarly from the graph and text in the book,
VOH
VOL
VIL
VIH
= 1V
= 0V
= 400mV
= 500mV
So, noise margins,
NMH = VOH - VIH = 1 – 0.5 = 0.5V = 500mV
NML = VIL - VOL = 0.4 – 0 = 0.4V = 400mV
Assignment #10
Vinay Dindi
EE510
Due Date-4/12/04
11.2) Design and simulate the DC characteristics of an inverter with Vsp
approximately equal to VTHn. Estimate the resulting noise margins for the design.
For Vsp~=Vthn, (ßn/ ßp) should be as large as possible.
Let (ßn/ ßp)=90
So Wn=30*Wp assuming KPn=KPp and Ln=Lp
If Wp=10, then Wn=300.
Substituting these values in equation 11.4,
we get Vsp=0.32. (Vtn=Vtp=0.28V from Table 6.3)
From simulations we obtain Vsp~=0.27V.
John Spratt
EE 510 Chap 10 HW
Problem 11.5: Repeat Ex. 11.6 using the long channel process with a 30/10 inverter.
Solution:
*** Top Level Netlist ***
vdd
vdd
0
Vin
vin
0
C1
Vout 0 50fF
M1
M2
DC
DC
5
0
Vout Vin 0 0 NMOS L=1u W=10u
Vout Vin Vdd Vdd PMOS L=1u W=30u
Simulation:
tPHL=69ps
tPLH=67ps
pulse 0 5 1n 0p 0p 1n 2n
4/4/2004
John Spratt
EE 510 Chap 10 HW
Taking into account the output capacitance of the MOS’s:
tPHL=.7*Rp*Ctot=.7*45k/30*(1.75f*(30+10)+50f)=126ps
tPLH=.7*Rn*Ctot=.7*15k/10*(1.75f*(30+10)+50f)=126ps
W/O taking into account the output capacitance of the MOS’s:
tPHL=.7*Rp*Ctot=.7*45k/30*(50f)=52.5ps
tPLH=.7*Rn*Ctot=.7*15k/10*(50f)=52.5ps
W/O appears to be closer to the sim.
4/4/2004
Problem 11.6
Steve Bard
Estimate the oscillation frequency of an 11-stage ring oscillator using 30/10 inverters in
the long-channel CMOS process. Compare your hand calculations to the simulation
results.
Solution: The frequency is about 250 MHz when calculated by hand. When simulated on
SPICE, the frequency is higher, reaching 495 MHz. The hand calculations are shown
below, and the SPICE simulation is shown on the next page.
f rosc =
1
n(t PHL + t PLH )
t PHL + t PLH = 0.7(Rn + R p )CTOT
CTOT =
5
(C oxP + C oxN )
2
L
15 k
=
= 1 .5 k
W
10
L
45 k
R p = 45 k
=
= 1 .5 k
W
30
R n = 15 k
C oxP = 1.75 fF ⋅ W ⋅ L = 52.5 fF
C oxN = 1.75 fF ⋅ W ⋅ L = 17.5 fF
CTOT =
5
(52.5 fF + 17.5 fF ) = 175 fF
2
t PHL + t PLH = 0.7(1.5k + 1.5k )(175 fF ) = 368 ps
1
f rosc =
≈ 250MHz
11(368 ps )
From the SPICE simulation, the frequency = 1/T = 1 / 2.02 ns = 495 MHz.
*** Problem 11.6 ***
.control
destroy all
run
plot vout
.endc
.option scale=1u
.tran .1n 6.5n uic
vdd
R1
vdd
vout
0
0
DC
1MEG
5
**********D********G*******S*******B****
M1
vout1
vout
0
0
M2
vout1
vout
vdd
vdd
M3
vout2
vout1
0
0
M4
vout2
vout1
vdd
vdd
M5
vout3
vout2
0
0
M6
vout3
vout2
vdd
vdd
M7
vout4
vout3
0
0
M8
vout4
vout3
vdd
vdd
M9
vout5
vout4
0
0
M10
vout5
vout4
vdd
vdd
M11
vout6
vout5
0
0
M12
vout6
vout5
vdd
vdd
M13
vout7
vout6
0
0
M14
vout7
vout6
vdd
vdd
M15
vout8
vout7
0
0
M16
vout8
vout7
vdd
vdd
M17
vout9
vout8
0
0
M18
vout9
vout8
vdd
vdd
M19
vout10
vout9
0
0
M20
vout10
vout9
vdd
vdd
M21
vout
vout10
0
0
M22
vout
vout10
vdd
vdd
.MODEL NMOS NMOS LEVEL = 3
.MODEL PMOS PMOS LEVEL = 3
.end
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30
NMOS L=1 W=10
PMOS L=1 W=30