THE ANALOG DEVICES SOLUTIONS BULLETIN
Volume 11, Issue 3
RF ICs
Contents
Highly Integrated Mixers Enable
High Performance Radio Designs . . . . 1
Full Range of High Performance
RF/IF Amplifiers . . . . . . . . . . . . . . . . . 2
RF Power Detector Delivers
RMS and Envelope Outputs . . . . . . . . . 3
Design Tools Simplify RF Systems
Development . . . . . . . . . . . . . . . . . . . . 3
ISM Band Transmitters and
Transceivers Deliver Robust
RF Performance . . . . . . . . . . . . . . . . . 4
Single-Chip, Multiband 3G
Femtocell Transceiver . . . . . . . . . . . . . 4
Integrated RF ICs for Next Generation
Wireless Communications . . . . . . . . . . 5
Powering a Fractional-N Synthesizer
with Low Noise LDO Regulator . . . . . . . 6
Low Power, 18 GHz Prescaler
Family Enables Cost-Effective
Phase-Locked Signal Generation . . . . . 6
Highly Integrated Mixers Enable High Performance Radio Designs
with Wide Dynamic Range, High Linearity, and Low Noise
Analog Devices’ RF IC portfolio now includes a series of high performance RF mixers suitable for
applications requiring the highest linearity and a low noise figure typically found in next generation
communication systems. These new mixers lessen design complexity, offer best-in-class
performance, and reduce bill of materials cost.
For narrow-band applications, the ADL535x family of single- and dual-channel integrated passive
mixers delivers the industry’s highest levels of performance and integration. The newest members of the
family, the single-channel ADL5353 and dual-channel ADL5354, incorporate an RF balun, LO switch for
dual LO frequency applications, LO driver, and integrated IF amplifier on a single chip. The ADL5353 and
ADL5354 extend the frequency coverage of Analog Devices’ mixer portfolio up to 2900 MHz.
The best-in-class input IP3 and noise figure performance allow these mixers to be used in a
variety of receiver designs, including in systems where the radio receiver will be operating in the
presence of large interfering signals. The ADL536x family of integrated passive mixers is suitable for
applications requiring the highest levels of linearity and dynamic range.
The 10 MHz to 6000 MHz ADL5801 and ADL5802 high linearity active mixers are suitable for
applications requiring high dynamic range and broadband frequency coverage. The ADL5801
also integrates a power detector that enables automatic optimization of IIP3, noise figure, and
bias current commensurate with the input signal level. The ADL5801 and ADL5802 mixers
can be configured for both upconversion and downconversion supporting an output up to 3 GHz.
High Performance Data Converters
Drive Improvements in Clock
Phase Noise . . . . . . . . . . . . . . . . . . . . 7
Common to the three mixer families, an IIP3 and noise figure optimization feature has been
integrated to provide flexibility in fine tuning the IIP3 and noise figure performance. The mixer
product family enhances ADI’s broad RF product portfolio so now designers can source their
complete RF signal chain from the industry’s most trusted and broadline RF IC supplier.
New VGAs Provide Unprecedented
Levels of Performance and
Integration . . . . . . . . . . . . . . . . . . . . . 8
Visit www.analog.com/rfmixers for information on the entire mixer family.
Visit our new website for
data sheets, samples,
and additional
resources.
Part
RF Frequency LO Frequency Conversion Input IP3
Noise
Supply
Price
Number Range (MHz) Range (MHz) Gain (dB) (dBm) Figure (dB) Current (mA) ($U.S.)
Narrow-Band Single-Channel with IF Amplifier
ADL5353 2200 to 2900 2230 to 3150
8.7
24.5
9.8
186
6.98
ADL5355 1200 to 2500 1230 to 2470
8.4
27
9.2
190
6.98
ADL5357 500 to 1700 730 to 1670
8.6
26.6
9.1
190
6.98
Narrow-Band Dual-Channel with IF Amplifier
ADL5354 2200 to 2900 1850 to 2870
8
25
10
359
9.98
ADL5356 1200 to 2500 1230 to 2470
8.2
31
9.9
350
9.98
ADL5358 500 to 1700 530 to 1670
8.3
25.2
9.9
350
9.98
Narrow-Band with No IF Amplifier
ADL5363* 2200 to 2900 2400 to 3100
–7.8
31.5
9
100
5.99
ADL5365 1200 to 2500 1230 to 2470
–7.3
36
8.3
95
5.99
ADL5367 500 to 1700 730 to 1670
–7.7
34
8.3
97
5.99
Wideband Active Mixer
ADL5801 10 to 6000
10 to 6000
1.8
28.5
9.75
130
5.15
ADL5802 10 to 6000
10 to 6000
1.5
28
11
220
5.15
*Preproduction.
www.analog.com/V11RFICs
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Analog Devices Offers a Full Line of High Performance RF/IF Amplifiers
With unprecedented levels of performance, the RF amplifier product families include LNAs (low noise amplifiers), IFAs
(intermediate frequency amplifiers), driver amplifiers, and gain blocks, all of which are fully specified for operation over temperature,
supply voltage, and operating frequency, thereby easing the selection and design-in process. Within each RF amplifier family, Analog
Devices optimized the performance to cover both broadband and narrow-band applications with the minimum number of external
passive components, providing considerable savings in board area and design complexity. The amplifiers are offered in the standard
SOT-89 package, as well as in smaller and more compact LFCSP packaging to further promote board area savings. The entire
amplifier family also exhibits high performance levels on low power consumptions, making them well-suited for the push toward
smaller and lower power consuming systems.
Low Noise Amplifiers (LNAs)
Part
Frequency
Number
Range (MHz)
Gain
(dB)
Output IP3
(dBm)
P1dB
(dBm)
NF
(dB)
5 V Current
(mA)
Specs
@ (MHz)
Package
ADL55211
400 to 4000
20.8
37.0
21.8
0.92
60
900
3 mm × 3 mm,
8-lead LFCSP
ADL55231
400 to 4000
21.5
34.0
21.0
0.82
60
900
3 mm × 3 mm,
8-lead LFCSP
Output IP3
(dBm)
P1dB
(dBm)
NF
(dB)
5 V Current
(mA)
Specs
@ (MHz)
Package
13 V bias is also supported.
2Includes external input match.
Intermediate Frequency Amplifiers (IFAs)
Part
Frequency
Gain
Number
Range (MHz)
(dB)
ADL55301
DC to 1000
16.8
37.0
21.8
3.0
110
190
2 mm × 3 mm,
8-lead LFCSP
ADL5531
20 to 500
20.9
41.0
20.4
2.5
100
70
3 mm × 3 mm,
8-lead LFCSP
ADL5534 (dual)
20 to 500
21.0
40.4
20.4
2.5
98
70
ADL5535
ADL5536
20 to 1000
20 to 1000
16.1
19.4
45.5
49.0
18.9
19.7
3.2
2.7
97
105
190
380
Frequency
Range (MHz)
400 to 2700
2300 to 4000
Gain
(dB)
13.2
14.0
Output IP3
(dBm)
42.0
41.0
P1dB
(dBm)
25.7
25.7
NF
(dB)
4.4
4.0
5 V Current
(mA)
104
90
Specs
@ (MHz)
2140
2600
ADL5322
700 to 1000
19.9
45.3
27.9
5.0
320
900
3 mm × 3 mm,
8-lead LFCSP
ADL5323
1700 to 2400
19.5
45.5
28.0
5.0
320
2140
3 mm × 3 mm,
8-lead LFCSP
ADL5604
700 to 2700
12.2
42.2
29.1
4.6
318
2630
4 mm × 4 mm,
16-lead LFCSP
Gain Blocks
Part
Number
Frequency
Range (MHz)
Gain
(dB)
Output IP3
(dBm)
P1dB
(dBm)
NF
(dB)
5 V Current
(mA)
Specs
@ (MHz)
Package
AD83531
1 to 2700
19.8
23.6
9.1
5.3
41
900
2 mm × 3 mm,
8-lead LFCSP
AD83541
1 to 2700
19.5
19.0
4.6
4.2
23
900
2 mm × 3 mm,
8-lead LFCSP
ADL5541
50 to 6000
14.7
39.2
16.3
3.8
90
2000
3 mm × 3 mm,
8-lead LFCSP
ADL5542
50 to 6000
18.7
39.0
18.0
3.2
93
2000
ADL5601
ADL5602
50 to 4000
50 to 4000
15.3
19.5
43.0
42.0
19.1
19.3
3.7
3.3
83
89
900
2000
5 mm × 5 mm,
16-lead LFCSP
SOT-89
SOT-89
13 V bias is also supported.
Driver Amplifiers
Part
Number
ADL5320
ADL5321
Package
SOT-89
SOT-89
3 mm × 3 mm,
8-lead LFCSP
SOT-89
SOT-89
13 V bias is also supported.
2
For data sheets, samples, and additional resources, visit www.analog.com/V11RFICs
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High Performance RF Power Detector Simultaneously Delivers RMS and Envelope Outputs
Improving the PAE (power added efficiency) of high powered amplifiers continues to be a challenge for wireless and broadband
equipment manufacturers. Next generation WiMAX systems and LTE mobile data and voice systems are adopting OFDM (orthogonal
frequency division multiplexed) modulation that supports a large number of subcarriers. The high peak-to-average ratio of these
modulated signals causes PAs (power amplifiers) to be backed off from their maximum transmit powers significantly, thereby making
the PA less efficient. To improve PA efficiency, an envelope detector has become increasing popular. In drain modulation architectures,
an envelope detector modulates the PA power supply from the incoming RF signal, thereby only giving the PA the power needed to
properly transmit the RF signal. Traditional architectures leave the PA biased at a much higher power level in order to ensure the PA
can properly transmit peak power but are not capable of reducing PA bias when transmitting lower RF power.
Operating within the 1 MHz to 4 GHz frequency range, ADI’s new ADL5511 TruPwr™ rms and envelope detector offers a new highly
integrated, high performance RF detector by combining two RF functions on one small chip. The envelope output is presented as a
voltage that is proportional to the envelope of the input signal. The rms output is a linear in V/V output voltage that is independent
of the peak-to-average ratio of the input signal. The extracted envelope can be used for power amplifier linearization and efficiency
enhancements, and the rms output can be used for true power measurement. The ADL5511 offers best-in-class performance,
including ±0.25 dB rms and envelope detection accuracy vs. temperature and a ±1 dB dynamic range of 40 dB. The ADL5511 is
specified across the industry’s widest temperature range of –40°C to +125°C, making it ideal for high temperature environments
found in remote radio heads and power amplifiers. The ADL5511 detector is sampling now, and more information is available at
www.analog.com/adl5511.
RMS and Envelope Response to a Single Carrier
W-CDMA Signal (Test Model 1-64)
VPOS
15
ADL5511
20pF
500
BIAS AND POWERDOWN CONTROL
PWDN 4
14
FLT4
RMS
G = 1.8
11
VRMS
ENVELOPE
G = 1.4
10
VENV
9
EREF
RFIN 2
250
10k
FLT1
3
400
5pF
250
0.5pF
0.8pF
VPOS
13
6
7
8
12
NC
VPOS
16
1
FLT2
5
FLT3
COMM
Design Tools to Simplify RF System Development
Analog Devices supports its broad RF IC portfolio with a comprehensive suite of design tools. RF system design is an extremely
complex and time-consuming process. ADI’s design tools reduce your design risk and time to market by making the overall
RF-to-digital design process simpler, faster, more accurate, and more robust. Reduce risk and ease your RF systems development
by downloading these free tools now!
ADIsimRF™
ADIsimRF design tool provides calculations for the most important parameters within the RF signal chain, including cascaded gain,
noise figure, IP3, P1dB, and total power consumption.
ADIsimPLL™
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive
PLL synthesizer design and simulation tool available today and removes at least one iteration from the design process.
ADIsimSRD™ Design Studio
ADIsimSRD Design Studio is a very powerful tool that enables real-time simulation and optimization of many of the parameters in a
typical wireless system using the ADF7xxx family of short range transceivers and transmitters. It greatly simplifies the design process
by creating a path along which a user can be guided and breaking down the design workflow into a number of distinct tasks.
ADIsimCLK™
ADIsimCLK is developed specifically for ADI’s range of ultralow jitter clock distribution and clock generation products. It allows the
designer to work at a higher level and directly modify parameters such as the loop bandwidth, divide ratios, phase offsets, and output
frequencies, and the effects of the changes on performance are shown instantly.
For data sheets, samples, and additional resources, visit www.analog.com/V11RFICs
RF_ICs_Solutions_Bulletin_v11_is3.indd 3
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ISM Band Transmitters and Transceivers Deliver Robust RF Performance
Analog Devices’ ADF7xxx series of transmitters and transceivers provide for low cost, robust wireless connections in a variety of
industrial applications. Covering both licensed and unlicensed sub-1 GHz and 2.4 GHz frequency bands, these products feature
excellent radio performance, low power consumption, data rates, and link robustness.
The highly integrated ADF7241 operates in the global 2.4 GHz ISM band supporting the IEEE 802.15.4 PHY protocol standard at
250 kbps on a single chip and has been designed with emphasis on flexibility, radio performance, and low current consumption.
A robust, very low power consumption, custom 8-bit processor implements radio control and packet management. The processor
can execute firmware modules from internal RAM memory, providing the flexibility to upgrade to changes in protocol standards
and to maintain system robustness in the field. The receive path of the ADF7241 RF transceiver is based on a zero-IF architecture
enabling best-in-class blocking and high selectivity performance. The transceiver’s low power consumption makes it effective for
battery-powered systems, such as wireless sensor networks, automatic meter reading, industrial wireless control, wireless audio
and video, consumer electronics, and ZigBee® applications
The ADF7023-J is a highly integrated 2FSK/GFSK/MSK/GMSK transceiver supporting data rates from 1 kbps to 300 kbps and designed
for operation in the 902 MHz to 958 MHz frequency band, which covers the ARIB Standard T96 band at 950 MHz. It delivers best-in-class
radio performance, low power consumption (12.8 mA Rx current), and flexibility provided by the same custom 8-bit processor used in
the ADF7241. The ADF7023-J is well-suited for smart grid metering communications for electric, water, and gas systems, home
energy management systems (HEMS), and home and building automation applications.
Single-Chip, Multiband 3G Femtocell Transceiver
As the 3G smartphone revolution continues to expand, users are looking for ways to get better coverage in their homes while operators
look for ways to offload their overcrowded macrocell networks. The perfect solution for both is the in-home femtocell; however, using
traditional high performance macrocell components is cost prohibitive, and power consumption would be unacceptable. To enable the
home femtocell, a highly integrated, low power transceiver is required to enable these platforms.
Solution ADI’s new ADF4602 is a 3G transceiver integrated circuit (IC) offering unparalleled integration and feature set. The ADF4602 is
ideally suited to high performance 3G femtocells providing cellular fixed mobile converged (FMC) services. With only a handful of
external components, a full multiband transceiver is implemented. UMTS Band 1 through Band 6 and Band 8 through Band 10 are
supported in a single device.
The receiver is based on a direct conversion architecture. This architecture is the ideal choice for highly integrated wideband
CDMA (W-CDMA) receivers, reducing the bill of materials by fully integrating all interstage filtering. The front end includes three high
performance, single-ended low noise amplifiers (LNAs), allowing the device to support triband applications. The single-ended input
structure eases interface and reduces the matching components required for small footprint single-ended duplexers. The excellent
device linearity achieves good performance with a large range of SAW and ceramic filter duplexers. The integrated receive baseband
filters offer selectable bandwidth, enabling the device to receive both W-CDMA and GSM-EDGE radio signals. The selectable bandwidth
filter, coupled with the multiband LNA input structure, allows GSM-EDGE signals to be monitored as part of a UMTS home base station.
The transmitter uses an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise,
eliminating the need for external transmit SAW filters. The fully integrated phase-locked loops (PLLs) provide high performance and
low power fractional-N frequency synthesis for both receive and transmit sections. Special precautions have been taken to provide
the isolation demanded by frequency division duplex (FDD) systems. All VCO and loop filter components are fully integrated.
ADF4602 Features
4
•Single-chip multiband 3G transceiver
•Integrated synthesizers including PLL filters
•3GPP 25.104 release 6 W-CDMA/HSPA compatible
•Integrated PA bias control DACs/GPOs
•UMTS band coverage
•W-CDMA and GSM receive baseband filter options
•Local area Class BS in Band 1 to Band 6 and Band 8
to Band 10
•Easy to use with minimal calibration
•Direct conversion transmitter and receiver
•Simple gain, frequency, mode programming
•Minimal external components
•Low supply current
•Integrated multiband multimode monitoring
•50 mA typical Rx current
•No Tx SAW or Rx interstage SAW filters
•50 mA to 100 mA Tx current (varies with output power)
•Integrated power management (3.1 V to 3.6 V supply)
•6 mm × 6 mm, 40-lead LFCSP package
•Automatic Rx dc offset control
For data sheets, samples, and additional resources, visit www.analog.com/V11RFICs
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Integrated RF ICs for Next Generation Wireless Communications
Integration of wireless communications infrastructure radio transceiver cards provides many challenges as, until now, standalone
discrete devices were required for optimum performance across many different process technologies. For example, the radio receiver
downconversion stage is often implemented and designed with discrete SiGe mixers, GaAs IF and LO amplifiers, CMOS PLL, and
discrete GaAs VCOs—thus, matching process technology for optimum performance.
Analog Devices’ SiGe BiCMOS RF ICs are highly integrated frequency translation devices that deliver optimum performance on a single
chip. The ADRF660x and ADRF670x series of RF downconverters and I/Q upconverters integrate the entire frequency conversion stage
in one compact RF IC and offer performance that, until now, could only be attainable through discrete circuit implementations.
The ADRF660x active mixers and ADRF670x modulators offer the highest linearity
IP3 specifications and signal power levels required by demanding multicarrier,
multistandard radio transceivers. The ADRF6655 is a flexibile broadband
upconversion/downconversion solution, and the ADRF6750 further integrates a
wide dynamic range digital step attenuator. Two new integrated RF demodulators
provide highly integrated solutions without any compromise in performance.
The ADRF6850 saves considerable board space, reduces cost, and simplifies
development by integrating a 60 dB VGA (variable gain amplifier), a fractional-N
PLL (phase-locked loop) synthesizer with VCO (voltage controlled oscillator), and
two baseband ADC drivers all in an 8 mm × 8 mm LFCSP package. The new
ADRF6801 RF demodulator integrates ADI’s leading fractional-N PLL synthesizer
and low phase noise VCO with a high dynamic range demodulator. The ADRF6801
also includes other value-added features, such as an RF balun, three LDOs, and
the necessary baseband buffer amplifiers.
Integrated RF ICs
Part Number
Function
Frequency Range (MHz)
Price ($U.S.)
ADRF6601
Downconverter with PLL + VCO
450 to 1600
8.98
ADRF6602
Downconverter with PLL + VCO
1350 to 2750
8.98
ADRF6603
Downconverter with PLL + VCO
1450 to 2850
8.98
ADRF6604
Downconverter with PLL + VCO
1600 to 3250
8.98
ADRF6655
Upconverter/downconverter with PLL + VCO
IF to 2500
8.98
ADRF6701*
I/Q modulator with PLL + VCO
550 to 1000
9.98
ADRF6702*
I/Q modulator with PLL + VCO
1550 to 2200
9.98
ADRF6703*
I/Q modulator with PLL + VCO
1900 to 2450
9.98
ADRF6704*
I/Q modulator with PLL + VCO
2400 to 2800
9.98
ADRF6750
I/Q modulator with PLL + VCO and attenuator
950 to 1575
9.98
ADRF6801
Quadrature demodulator with PLL + VCO
750 to 1150
9.98
ADRF6850
Quadrature demodulator with PLL + VCO
100 to 1000
9.98
*Preproduction.
For data sheets, samples, and additional resources, visit www.analog.com/V11RFICs
RF_ICs_Solutions_Bulletin_v11_is3.indd 5
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Powering a Fractional-N Synthesizer with a Low Noise LDO Regulator
for Reduced Phase Noise
Wideband voltage controlled oscillators (VCOs) may have increased sensitivity to power supply noise; therefore,
ultralow noise regulators are recommended for best performance. In this application, we provide a Circuits from the Lab™ reference
circuit that has been developed to get the best phase noise performance from the ADF4350 using a low noise LDO regulator (ADP150).
The circuit shown utilizes the ADF4350, a fully integrated fractional-N PLL and VCO that can generate frequencies from 137.5 MHz
to 4400 MHz. The ADF4350 is powered from the ultralow noise 3.3 V ADP150 regulator for optimal LO phase noise performance.
The lower integrated rms
LOCK
V
V
DETECT
noise of the ADP150 LDO
ADP150
16 17
30
26
25
4
28
6
32
10
V
=
of only 9 μV rms (10 Hz to
V = 5.5V
3.3V
MUXOUT LD
V
DV
AV
CE PDB
V SDV
1 VIN VOUT 5
1nF 1nF
C
100 kHz) helps to minimize
B+ 14
RF
COUT FREF
29 REF
1𝛍F
1𝛍F
51𝛀
2 GND
V
VCO phase noise and reduce
RF
B– 15
1 CLK
ON
2 DATA
3 EN
NC 4
3.9nH
the impact of VCO pushing
3 LE
OFF
(the VCO equivalent of power
A+ 12
RF
ADF4350
NC = NO CONNECT
22 R
supply rejection). The ADP150
RF
A– 13
ADP150
4.7k𝛀
=
V
V = 5.5V
20
V
represents the industry’s
3.3V
1 VIN VOUT 5
C
C
CP
7
lowest noise LDO in the
1𝛍F
1𝛍F
39nF
2 GND
smallest package at the lowest
2700pF
SW
5
ON
360𝛀
3 EN
NC 4
CP
SD
D
AGND A
TEMP VCOM V
cost. It is available in a 4-ball,
OFF
8
31
9
11 18 21
27
19
23
24
0.8 mm × 0.8 mm, 0.4 mm
NC = NO CONNECT
pitch WLCSP or a convenient
10pF
0.1𝛍F 10pF
0.1𝛍F 10pF
5-lead TSOT package. Adding
the ADP150s to the design,
therefore, has minimal impact on system cost and board area while providing a significant improvement in phase noise.
Read the complete circuit note and download design files at www.analog.com/CN0147.
VCO
DD
OUT
IN
VCO
IN
DD
RF
DD
DD
P
IN
IN
OUT
VCO
OUT
IN
IN
OUT
SPI-COMPATIBLE SERIAL BUS
OUT
3.9nH
1nF
OUT
SET
OUT
TUNE
1nF
680𝛀
OUT
GND
GND
GNDVCO
GND
1200pF
REF
0.1𝛍F
Low Power, 18 GHz Prescaler Family Enables Cost-Effective Phase-Locked Signal Generation
The traditional approach to generate programmable phase-locked signals uses a VCO and PLL IC in the classical phase-locked loop
configuration. In applications where the VCO frequency is significantly higher than the PLL IC input range, a prescaler is necessary.
Many microwave applications require low cost solutions extending up to 18 GHz for VSAT and point-to-point applications. A prescaler
function is, therefore, essential in these types of systems.
Solution
The ADF5000, ADF5001, and ADF5002 are a new family of low power, fixed divide ratio prescalers operating up to 18 GHz. These
three parts provide divide by 2, 4, and 8 functionality, respectively. All three parts operate off a 3.3 V supply and have differential
100 Ω RF outputs to allow direct interface to the differential RF inputs of PLLs such as the ADF4156 and ADF4106. With current
draw typically 26 mA, these parts consume less than half the power of alternatives. Single sideband phase noise of –150 dBc/Hz is
achieved. These parts are capable of operation up to 105°C and are available in a small 3 mm × 3 mm LFCSP package.
ADF5000/ADF5001/ADF5002 Features
18GHz RF
•Divide by 2, 4, 8 prescalers
LNA
•High frequency operation: 4 GHz to 18 GHz
2GHz IF
ADF5001 18GHz
DIV 4 PRESCALER
16GHz IF
•Integrated RF decoupling capacitors
•Low power consumption—active mode: 26 mA;
power-down mode: 7 mA
DOWNCONVERTER
PLL
DIPLEXER
ADF4106
•Low phase noise: −150 dBc/Hz
•Single dc supply: 3.3 V compatible with
ADF4xxx PLLs
PA
UPCONVERTER
2GHz IF
•Temperature range: −40°C to +105°C
•Small package: 3 mm × 3 mm LFCSP
Applications
•Point-to-point radios
•VSAT radios
•Communications test equipment
6
For data sheets, samples, and additional resources, visit www.analog.com/V11RFICs
RF_ICs_Solutions_Bulletin_v11_is3.indd 6
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High Performance Data Converters Drive Improvements in Clock Phase Noise
As high resolution data converters push to faster and faster sample rates, the demand for cost-effective clocking solutions with
extremely good phase noise grows. The relationship between the purity of the sampling clock and the SNR (signal-to-noise ratio)
one can achieve from an ADC has been well documented. Maintaining a predefined level of SNR when increasing the sample rate
of a data converter necessitates cleaner clocks. The latest in high speed converters requires wideband jitter performance of <200 fs rms
to realize the performance of which they are inherently capable.
To further complicate matters, many applications have cause to rely on an external clock reference as a time base, a reference which
may already be sufficiently corrupted by sources that cannot be controlled. As such, it is necessary to find a means by which to filter
the noise off the base reference for any converter sampling system.
Analog Devices has introduced a family of dual loop clock devices
Part Number
Outputs
FOUT
Features
(AD9523, AD9523-1, AD9524) that use two PLLs in series with one
14 differential/
EEPROM,
AD9523
≤1.0 GHz clean-up loop
another to enable such systems to generate the clean converter
28 CMOS +1
clocks they need from a relatively noisy reference. These devices
14 differential/
EEPROM,
AD9523-1
≤1.0 GHz clean-up loop
contain two PLLs in series. The first (front end) PLL relies on an
28 CMOS +1
external oscillator and narrow loop filter to establish a very clean
6 differential/
EEPROM,
AD9524
≤1.0 GHz clean-up loop
reference source for the second (back end) PLL, which uses a wider
12 CMOS +1
loop filter and an on-chip VCO to upconvert the reference signal to
the desired sample clock rate. With individual dividers on each output channel and flexible output buffers that can be programmed to support
a variety of standard interface logic, these devices are often sufficient to source every clock signal required in a system.
AD9523-1
–80
1: 1kHz, –120.0dBc/Hz
2: 10kHz, –130.6dBc/Hz
3: 100kHz, –137.4dBc/Hz
4: 1MHz, –145.7dBc/Hz
5: 10MHz, –159.6dBc/Hz
6: 40MHz, –160.3dBc/Hz
7: 800kHz, –143.7dBc/Hz
–90
PHASE NOISE (dBc/Hz)
–100
REFA
–110
–120
PLL1
REFB
PLL2
1
–130
2
–140
–150
–160
–170
–180
100
7
3
1k
100k
10k
FREQUENCY (Hz)
1M
CONTROL
INTERFACE
(SDI AND I 2 C)
SPI
4
NOISE:
ANALYSIS RANGE x: START 10kHz TO STOP 40MHz
INTG NOISE: –78.1dBc/40MHz
RMS NOISE: 175.4𝛍RAD
10.0mdeg
RMS JITTER: 151.4fs
RESIDUAL FM: 2.1kHz
5
ZERO
DELAY
6
EEPROM
14 CLOCK
DISTRIBUTION
10M
Using Multichannel DDS to Implement Phase Coherent Switching
The standard single-channel direct digital
synthesizer (DDS) does not switch between
frequencies in a phase coherent manner. By
design, DDS frequency transitions are phase
continuous. However, the Circuits from the Lab
reference circuit shown demonstrates how to
configure the AD9958/AD9959 multichannel DDS
for a robust phase coherent FSK (frequency shift
keying) modulator by summing the outputs of the
multichannel DDS together.
3.3V
1.8V
VS VCP VS_DRV
AVDD
3.3V
DVDD
DVDD_I/O
1.8V
50𝛀
CH0_IOUT
1.8V
LVPECL
LVPECL
500MSPS
REF CLK
REF CLK
XTAL
AD9520
ADTT1-1
CH0_IOUT
50𝛀
CH1_IOUT
AD9958/AD9959
1.8V
CH1_IOUT
SYNC_CLK
(ON/OFF)
P3
(ON/OFF)
P2
A multichannel DDS virtually eliminates
temperature and timing issues between
CLOCK
channels compared to synchronizing multiple
DATA SOURCE PRS
EDGES MUST MEET
single-channel devices for the same application.
SETUP/HOLD TIME REQUIREMENTS
WITH RESPECT TO SYNC_CLK
For instance, multichannel DDS outputs, though
independent, share the same system clock
edges in the chip. Consequently, the system clock edges across multiple chips would not track as well over temperature and power
supply deviations compared to an integrated multichannel DDS. As a result, a multichannel DDS is better suited for producing a closer
to ideal phase coherent frequency transition at the summed output. Read the complete circuit note at www.analog.com/CN0186.
For data sheets, samples, and additional resources, visit www.analog.com/V11RFICs
RF_ICs_Solutions_Bulletin_v11_is3.indd 7
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at RF and IF Frequencies
ADI’s new ADL5201, ADL5202, ADL5240, and ADL5243
VGAs offer breakthrough levels of integration—combining
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The ADL5201 and its dual version, the ADL5202, are
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combines a digital step attenuator and a gain block into a single IC, while the ADL5243 combines a DSA, gain block,
and broadband ¼ W driver amplifier in a single IC, without any sacrifice in performance. Either the amplifier or the
DSA can be first in the signal chain, maximizing system flexibility by allowing the VGA to be used in multiple places
throughout a design. Samples of the new VGAs are available now.
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