Design Methodology Using
Verilog Models
Ignatius Bezzam
Arasan Chip Systems
San Jose, CA, USA
Topics
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Introduction
Design Methodology Flow
Library Features
Case Study: USB3.0 Analog PHY
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Transmitter Model
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Loop Filter
Receiver Model
Simulation Results
Conclusions
December 9, 2009
Arasan Confidential
Page 2
Introduction
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Design of Complex Analog Circuits
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Large number of simulations – computation intensive and
time consuming
Susceptible to changes in process parameters
• Can lead to redesigning of blocks and simulations
• Leads to increased TTM
Modeling Analog Blocks using HDLs
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Digital Circuit Simulations are quick
• Reduces design and simulation times
• Reduces actual analog design iterations if modeled
accurately
Bridges the gap between analog and digital design flows
Design Methodology Flow
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Slide 4
MSOffice1 spello libraTry
, 11/25/2009
Analog Model Library Features
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Basic Blocks – PLL(VCO, Charge Pump, PFD, Frequency
Divider), ADCs, Multipliers, Adders
Models of completely analog blocks are realized using
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I/O Transfer Characteristics eg., VCO
Solving Transfer Functions eg., Filters
Full digital blocks are realized in RTL eg., Multipliers,
Adders etc.,
All models must be parameterizable for easy
customization
All models must be able to adopt to process parameter
changes
USB 3.0 Analog PHY Model
Analog
Digital
Link
status
state
m/c
Transmit PLL
Transmit driver
D-PHY
Link
Data
Path
A‐PHY
CDR
Device function
processor
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A/D
Power management
PHY
management
interface
Slide 6
MSOffice3 No A/D but Serializer
, 11/25/2009
USB 3.0 Transmitter Model
Data
Retiming Block:
Parallel to Serial
Converter
D+
TX
Driver
D-
clock
phases
fref
Spread Spectrum Clock
PLL
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SSC PLL
PFD, Divider
and Sigma-Delta
modulator are
purely digital
blocks
Charge pump,
VCO and Loop
Filter are purely
analog blocks
Loop Filter
n0/d0
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R1
Z-1
Z-1
n1/d0
C2
Z-1
C1
n2/d0
-(d1/d0)
Z-1
-(d2/d0)
n0 + n1 z −1 + n2 z −2
H ( z) =
d 0 + d1 z −1 + d 2 z − 2
sR1C1 + 1
H (s) = 2
s C1C2 R1 + s (C1 + C2 )
Bilinear
Transformation
USB 3.0 Receiver Model
D+
ADC
Equalizer
Comma
Detector
Recovered
Data
Recovered
Clock
D-
Phase Detector
CDR PLL
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ADC, CDR PLL can be purely analog models
Equalizer can be purely digital model
High speed digital blocks can be optimized by pipelining
Simulation Results
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Transmitter Waveforms
Simulation Reults
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Transmitter Waveforms
Simulation Results
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Transmitter Waveforms
Conclusions
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Any new logic to be added can be modeled first in verilog,
proven by simulating and then incorporated in the actual
circuit design process
Any changes in process parameters which might lead to
design changes can be predicted without actual circuit
design
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Verilog models can act like catalysts for the analog design
process
Architecture Optimization time is reduced
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Maintaining libraries for different process and different process
corners
Specially for digital assisted analog techniques in deep sub-micron
Models must be made parameterizable for easy
customization