Physics 309
October 2013
Lab 3: Building an amplifier with a junction Field-Effect Transistor (jFET)
Preamble You will characterize a jFET and then use your data to design and build an
amplifier. This amplifier will be useful in subsequent labs in Physics 309.
Please read the note on how FETs work and how to use them published by InterFET and
posted on the Notes section of the class web page or read the appropriate sections in The
Art of Electronics by Horowitz and Hill. The notes below are meant to provide a bit of
orientation to those more detailed and useful treatments. Please also see the data sheet for
the particular jFET we will use, the J310, posted on the Manuals and Spec Sheets part
of the class web page.
What is a jFET? (pronounced jayfet Rhymes with play-set.) It is a three-terminal
semiconductor device in which the current flow through the main channel of the device,
from Drain to Source, is controlled by a voltage applied at the third terminal, called the
Gate. A voltage bias at the Gate enlarges or shrinks the region within which charge carriers
are depleted, altering the geometry of the conductive path from Drain to Source. We will
explore an analogy to an ordinary valve in household plumbing. This analogy can be fairly
precise if we ignore how water valves actually work. See Figure 1.
A
V
B
Figure 1: In plumbing, water flows from A to B
in response to a pressure difference between A and
B. Applying pressure at the valve, V, changes the
shape of the channel and alters the flow rate. At
low flow rates the system will act resistively: flow
Gate
will be proportional to the pressure difference from
A to B and the constant of proportionality will depend on the pressure applied to V. Once the pressure difference from A to B is large enough to inSource duce turbulence the flow speed becomes constant
so flow is independent of pressure at high pressure.
Water flow into the valve at V is negligible.
Drain
We could imagine characterizing the water valve in a very similar way to your diode measurements, by measuring flow through the deivce as a function of pressure across it. The
difference from the diode is that here we have a third terminal, the valve, and we will make
a new IV curve, or Flow-Pressure curve, for each of several valve settings. For any particular
valve setting, we should expect flow is proportional to pressure difference at low pressures.
Once turbulence sets in and the speed becomes constant, the total flow rate only depends
on area of the valve, not the pressure. We should expect a constant flow for any one valve
setting in this regime, but the size of that flow depends on the valve setting. This is shown
schematically in Figure 2
What to measure: Look at the j310 data sheet and you will find curves which look a
lot like Fig. 2 You will measure IV curves of your jFETS for several values of the voltage
1
Saturated flow
Water flow from A to B
Onset of turbulence
0
Resistive
Flow
PV = low
PV = high
Pressure difference from A to B
Figure 2: Flow-Pressure diagrams for several different valve settings for a plumbing valve.
Actual plumbing valves probably do not perform like this, but jFETs do.
difference from Gate to Source, VGS . We will leave you to design the circuit and corresponding
measurement strategy, but first let’s review IV curves and offer some advice.
Let’s review the process of measuring the IV curve of a two terminal device. The device
might be a resistor, a diode like the ones you have measured, a lightbulb or even a crazy
thing as shown in Figure 3. In planning the measurements you wire your unknown device in
series with a resistor and apply a voltage VT across the pair. The voltages across the device
and across the resistor sum to the total applied voltage.
VT = VD + VR .
(1)
The current through the device equals the current through the resistor, which is the voltage
across the resistor divided by its resistance.
ID = IR = VR /RL =
VT − VD
.
RL
(2)
We have put a subscript on RL to stand for Load resistance just to be very clear that we are
denoting the resistance of the added resistor, not that of the unknown device.
Notice that Eq. 2 provides a relation between ID and VD once the measurement parameters
VT and RL are specified. The relation is linear and it is called a Load Line. It is plotted
as a black dashed line in Fig. 3. If the device allows no current to pass, there will be no
voltage across the resistor. Therefore the full VT is applied to the device. This would result
in a data point at (VD , ID ) = (VT , 0). If, on the other hand, the device has 0 volts across it
at any current the full applied voltage will fall across the resistor and the current through it
2
and the device will be ID = VT /RL . This corresponds to the point (VD , ID ) = (0, VT /RL ).
These correspond to the right and left hand ends of the dashed line in Fig. 3. For almost
any actual device, neither the voltage nor the current will be precisely 0, and so the pair of
values measured, VD , ID ) will lie somewhere else along the load line.
Current through device
VT /R L
VT
ID
Voltage across device
RL
Device
VT
VD
Figure 3: An example IV curve. For any particular choice of VT and RL the point (VD , ID )
must lie along the dashed load line. As VT is swept from 0 to a large value the full device
IV curve is traced.
The process of measuring an IV curve is to sweep the total applied voltage, VT across some
range and at each VT measure a pair of values, corresponding to VD and ID .
We are just describing what you have done already: You do not set VD and measure ID .
You set VT and from a measurement infer VD and ID .
You will do this for a series of different values of the voltage difference between the gate and
the source of a jFET. Look at the IV curves in the j310 data sheet and note the approximate
range (and sign!) of the voltages and currents you should expect to measure. You have two
DACs and plenty of ADCs. You will probably build a circuit a bit like that shown in Figure
3. What is the largest voltage your DACs can supply? What is the largest that RL can
be so that the DAC can drive the largest current you anticipate through RL and still have
enough voltage left for the FET? Select a resistor RL whose resistance is below the maximum
plausible value. Where within the circuit will you need to measure voltages? Remember,
you might already know the DAC voltages without an ADC because you command them to
a particular value. Draw the circuit you want to use and then build it.
There are a few more options to go wrong here than with the diode so look at the pictures
in the data sheet to identify which lead is which and pay attention as you wire your circuit.
We have included Fig. 4 to illustrate two points. It is the result we got using a correct mea3
surement strategy and program applied to a mis-wired circuit. The points are: a miswired
circuit can do things which are very confusing; and it is harder than you might guess to do
any real harm. After making this graph, the jFET was twisted around to the desired shape
and a perfectly complete and useful set of data were collected.
Figure 4: The title of the file containing this graph is whats this fet.png. There are 72
distinct ways to connect a jFET and load resistor to two DACs an ADC and Ground using
all four connections and not connecting either DAC directly to Ground. This circuit displays
the behaviour of one of those and demonstrates that the jFET can survive many types of
wiring error.
Once you have made a plot of the Drain-to-Source current, IDS as a function of Drain-toSource voltage, VDS for several values of the Gate voltage please analyze your graph for the
following.
In the large VDS regime where IDS is nearly independent of VDS , Plot current vs VGS . Find
the pinch off voltage which is the value of VGS which forces IDS = 0.
In the small VDS regime where the jFET acts resistive, infer a resistance from the slope of
IDS with respect to VDS and plot Ref f ective agains VGS .
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Analysis of your jFET IV Curve:
The amplifier shown in Figure 5 is an ACcoupled, self-biased amplifier. You will use the
properties of a transistor you have measured
VSUPPLY
to choose component values to make this cirRL
cuit work.
There is one very useful property of a jFET
which you have not measured, and let’s start
D
Output
G
there. The input current, by which we mean
the current flowing into the Gate, is essenInput
S
tially 0. It is often a nA (10−9 Amperes) and
sometimes a pA (10−12 A). This allows you to
Rs
RG
choose a very large value of the input resistor, RG . Here 105 or 106 Ω will suffice but we
have made amplifiers in special settings where
RG = 1011 Ω. Because no current flows into
the gate, and on average no current flows into
Figure 5: A jFET amplifier based on the
the capacitor, the current through RG is 0 on
transistor you have characterized. RG
average and VG = 0.
holds VG = 0. Choosing a value of
We are using the nomenclature that when one
RLoad sets the amplification of the circuit.
location is specified for a voltage, as in VG we
Choosing Rsource makes VGS negative and
are referring to the voltage difference between
sets the current through the transistor.
that location, in this example the Gate Voltage, and circuit ground. When two locations
are given, as in VGS we are referring to the difference in voltage between the two locations,
in this case the Gate and the Source.
The current flowing through the jFET continues through RS , so VS will be positive and
VGS slightly negative. This biases the jFET, so the choice of resistance RS sets the average
current through the transistor.
A change, ∆IDS , in the current flowing through the transistor results in a change in the
voltage drop across the load resistor, so the choice of RL governs the size of the output
signal.
Measuring the Transconductance:
You have measured jFET IV characteristics for several values of the gate-to-source voltage,
VGS Perhaps your data look like Figure 6. We expect that there is a threshold voltage VT
below which no current flows. Sometimes this is called a pinch off voltage. In the saturation
region and above the threshold, we expect the current to be quadratic in gate-to-source
voltage.
IDS = k(VGS − VT )2 .
(3)
Determine IDS as a function of V GS and at fixed V DS from your data. Since you have not
collected data on the same exact set of VDS values for each curve tracing, you will need a
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Current Drain to Source
Saturated Regime
0
Voltage difference from Drain to Source
Figure 6: Find the transconductance in the saturated region by measuring how the Drain
current IDS depends on VGS at fixed drain voltage VD . Repeat this for several different values
of VDS .
strategy to pick out the right values. We did it by forming a mask and averaging current
readings within the mask. For each VGS curve,
>>>mask = (vds > 3.0) & (vds < 3.5)
>>>current=ids[mask].mean()
Determine the current slope, k, and the threshold
√ voltage, VT from your data. One excellent
way to see if your data obey Eq. 3 is to plot IDS against VGS , which should be linear and
should extrapolate to zero current at VGS = VT .
The amplification of your circuit, called the gain, is the ratio of the output to the input
voltage variation.
∆VOU T = G∆VGS = ∆IDS RL
(4)
where the last term is simply the statement that variation in the output corresponds to
variation in the voltage across RL . See FIgure 7. This leads to
G=
∆IDS
RL = gm RL
∆VGS
(5)
where we have introduced the transconductance explicitly,
gm (IDS ) =
6
d IDS
.
d VGS
(6)
Determine gm from your fits to Eq. 3.
I
DS
VS
RL
Saturated Regime
!VGS
0
V
Supply
!VDS
Figure 7: The amplitude of output voltage variations, ∆VDS , is the load resistance times the
current variations arising from ∆VGS .
Choosing the Source and Load Resistances
Let’s build our amplifier to operate at IDS = 10 mA.
Use your fit to Eq. 3 to determine the gate to source voltage corresponding to IDS = 10mA.
The desired value of RS satisfies
VGS = −IDS RS .
(7)
Use your expression for gm (10mA) to choose a value of RL which gives you a voltage gain
equal to approximately 30.
Build and test your amplifier.
Build an amplifier with those values of resistances. Give it a small amplitude sinewave
from the function generator and measure the amplifier gain.
This amplifier will be non-linear for large input signals. A very powerful way to measure
non-linearity is to amplify a sine wave, fourier transform the output and search for harmonics
of the input frequency. This technique exploits the fact that sin2 ωt looks like 1/2 sin 2ωt.
Please vary the amplitude of input signal and measure the amplitudes of higher harmonics
in the output signal.
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