Power Management
Texas Instruments Incorporated
Using the UCC3580-1 controller for highly
efficient 3.3-V/100-W isolated supply design
By Brian M. King (Email: b-king1@ti.com)
Advanced Analog Products
Power-supply modules offer an attractive solution for
providing the bulk power conversion in telecom systems.
Modules offer a ready-made solution in a single package
but can be quite expensive. The alternative, of course, is
to build a power supply from discrete components. A discrete design can dramatically reduce production costs but
requires a more intense engineering effort. For those willing
to invest the effort, Figures 1 and 2 present a discrete
solution that provides up to 100 W at 3.3 V from an isolated
48-V input. This design matches or exceeds the performance, consumes less board area, and costs significantly
less than many half-brick modules that have the same
power requirements.
This design uses a UCC3580-1 to control an activeclamp forward converter with self-driven synchronous
rectifiers. The topology allows the circuit to achieve efficiencies of up to 93%. Additional features included in the
design are remote sense connections for point-of-load
regulation, input undervoltage, input overvoltage, output
overvoltage, and overcurrent protection.
Circuit description
Both an n-channel FET (Q1) and a p-channel FET (Q2)
drive the 6-turn, primary winding of the active-clamp
transformer. The UCC3580-1 controller provides the drive
for both MOSFETs. The n-channel drive is provided
straight from the UCC3580-1, while the p-channel drive is
inverted through the circuit of C7, D9, and R100. Figure 3
shows the drain-source waveforms of the primary and secondary MOSFETs.
While Q1 is on, power is delivered to the secondary, and
magnetizing energy is being stored in the transformer.
During this time, Q2 is off, and the clamp capacitor (C2) is
out of the circuit and remains charged at a constant voltage
level. When Q1 turns off, the leakage and magnetizing
currents charge up the drain-to-source capacitance of Q1.
Once the drain-to-source voltage of Q1 exceeds the voltage
across the clamp capacitor, the body diode of Q2 begins to
conduct. With the body diode of Q2 conducting, the magnetizing current now begins to charge the clamp capacitor.
Some time after the body diode of Q2 has begun to
conduct, the controller turns on Q2. This provides zerocurrent switching for Q2. The clamp capacitor continues
to charge until the magnetizing current is reduced to 0 A.
At this point, the magnetizing current reverses, and the
clamp capacitor begins to discharge until the controller
turns off the p-channel FET. After Q2 turns off, the clamp
capacitor remains at a fixed voltage. There is a fixed delay
before Q1 turns on. During this delay, the energy in the
parasitic components discharges the VDS of Q1 towards
Figure 1. Power stage schematic
C106
4700 pF
2 kV
Q3
FZT655
49.9 kΩ
35-V to
75-V Input
VIN+
D3
12 V
C24
1 µF
100 V C2 0.1 µF
200 V
87 65
N_DRV
4
Q2
IRF6217
321
6 7
T1
PA0369
2 9
6T
4
Q8
Q5
Q1
Si7846DP
VOUT+
+ C11
+ C12
+ C1
180 µF
180 µF
180 µF
6.3 V
6.3 V
6.3 V
Q9
1T
8
R103
0.1
1W
VOUT = 3.3 V @ 30 A
Q5, Q6, Q8, Q9 = HAT2099H
D2
C8
10 µF MMSD914
C23
C22
1 µF 1 µF
100 V 100 V
VIN–
L1
PA0373
1 11
BIAS
R12
C102
10 µF
6.3 V
VOUT–
Q6
D100
R2
0.1
1W
BAT54
I_SNS
R101
1 kΩ
C100
1 µF
D101
5.1 V
P_DRV
SENSE–
Q100
MMBT3904
BIAS2
C101
10 µF
8
Analog and Mixed-Signal Products
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4Q 2002
Analog Applications Journal
Power Management
Texas Instruments Incorporated
Figure 2. Control stage schematic
I_SNS
C9
0.1 µF
D9
BAT54
DELAY SHDN
SS
LINE
VDD
REF
EAIN
OUT1
PGND EAOUT
OUT2 OSC1
CLK
OSC2
GND RAMP
1
2
3
4
5
6
7
8
N_DRV
P_DRV
C7
1 µF
16 V
R100
10 kΩ
VIN+
R32
150
kΩ
C17
0.1 µF
1
U4
R31 TL331DBV 3
9.53 kΩ
R21
100 kΩ
REF R41
4.99 kΩ
16
15
14
13
12
11
10
9
C16
100 pF
4
C104
1 µF
REF
R5
4.02
kΩ
C4
330 pF
R25
10 kΩ
C103
100 pF
R26
10 kΩ
C19
1000 pF
U7
H11A817B
VOUT+
4
1
3
2
R28
499 Ω
R24
23.7
kΩ
C14
3300
pF
R27
1 kΩ
R6
45.3 kΩ
SENSE+
R23
750
C15
Ω
33 pF C13
1000
pF
R22
49.9 kΩ
R37
30.1 kΩ
SENSE–
BIAS2
U5
H11A817B
R30 10 kΩ
ON/OFF
R9
26.7 kΩ
R20
10 Ω
U2
TLV431A
C3
100 pF
Q4
MMBT3904
5
R102
10 Ω
BIAS2
C5
0.1 µF
R7
100 kΩ
R8
150 kΩ
BIAS
VIN+
C6
0.1 µF
U1
UCC2580D-1
R4
200 kΩ
BIAS
R16
34.8 kΩ
R3
1 kΩ
R29
3.48 kΩ
4
1
3
2
C105
R38 1 µF
10 kΩ
VOUT+
R33
10 kΩ
R35
499 Ω
U6
TLV431A
2
R19
10 Ω
C18
100 pF
R34
4.53 kΩ
SENSE–
BAS16
D4
VIN. This allows softer turn-on and reduces switching
losses in Q1 (see Figure 4).
The secondary power stage consists of the synchronous
rectifiers (Q5, Q6, Q8, and Q9) and the output filter (L1,
C1, C11, C12, and C102). When Q1 is on, the voltage on
the secondary of T1 ensures that both Q8 and Q9 are on,
while Q5 and Q6 are off. During this time, a voltage equal
to the input voltage divided by the turns ratio of the
Figure 3. Power MOSFET drain waveforms
transformer is applied across the gate-to-source of Q8 and
Q9, and also across the drain-to-source of Q5 and Q6. Also
during this time, the gate-to-source voltage of Q5 and Q6
is essentially 0 V and is equal to the inductor current
times the rds(on) of Q8 and Q9.
When Q2 is off, the voltage on the secondary of T1
reverses, and ensures that both Q5 and Q6 are on, while
Q8 and Q9 are off. During this time, the magnitude of the
Figure 4. Turn-on of primary-side
n-channel MOSFET
Q1: 50 V/div
VDS: 50 V/div
Q2: 50 V/div
Q5 & Q6: 10 V/div
VGS: 5 V/div
Q8 & Q9: 10 V/div
Time Scale: 1 µs/div
Time Scale: 100 ns/div
9
Analog Applications Journal
4Q 2002
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Analog and Mixed-Signal Products
Power Management
Texas Instruments Incorporated
Output Voltage (V)
transformer secondary voltage is equal to the clamp
Figure 5. Line and load regulation
capacitor voltage minus the input voltage, divided by
the transformer turns ratio. The peak clamp capacitor voltage will determine the maximum voltage
3.306
stress across the gate-to-source of Q5 and Q6, and
also across the drain-to-source of Q8 and Q9. During
3.304
VIN = 36 V
this time, the gate-to-source voltage of Q8 and Q9 is
essentially 0 V and is equal to the inductor current
3.302
times the rds(on) of Q5 and Q6.
VIN = 48 V
Two bias voltages are used in this active-clamp
3.3
design, one for the primary side and one for the
secondary side. The circuit composed of C8, D2, D3,
VIN = 72 V
3.298
L1, Q3, and R12 produces the primary-side bias. D2,
R12, and Q3 form a linear regulator, which is func3.296
tional only during startup, or during a fault condition.
5
30
0
10
15
20
25
L1 contains an auxiliary winding that is used to
Load Current (A)
produce the primary-side bias during normal operation. The main winding of L1 has 4 turns, while the
auxiliary winding has 16 turns. The auxiliary winding
charges C8 to a voltage equal to the output voltage
times the 16:4 turns ratio of the inductor, minus the diode
The feedback network is typical of most isolated forward
drop of D3.
converters. The TLV431 (U2) incorporates a voltage referThe circuit composed of C100, C101, D100, D101, Q100,
ence and transconductance error amplifier into one package.
and R101 produces the secondary-side bias. This bias is
Providing type III compensation around U2 compensates
required to drive the feedback optocoupler (U7) and the
the voltage-mode converter. The current transfer ratio of
TLV431 (U2). D100 and C100 peak detect the transformer
U7 and the values of R27 and R28 determine the gain of
secondary voltage. R101, D101, and Q100 form a linear
the optocoupler circuit. The error amplifier of the
regulator. The linear regulator is necessary to ensure that
UCC3580-1 is used in an inverting configuration, with a
the bias voltage is independent of the input voltage.
gain of 1 V/V.
Without the linear regulator circuit, a second feedback
The shutdown pin of the UCC3580-1 provides overcurrent
loop is introduced into the compensation circuit, which
protection. The current is sensed at the source of Q1 by
complicates the compensation design.
resistors R2 and R103. Resistor R16 lowers the shutdown
Breaking the feedback path with R19 and R20 provides
threshold voltage, which improves the converter’s efficiency
remote sensing. By connecting the remote sense terminals
by decreasing the required resistance of R2 and R103.
directly to the desired regulation point, the converter
The UCC3580-1 and resistors R8 and R9 control the input
compensates for any voltage drops between the output of
undervoltage protection. The comparator circuit of U4 conthe supply and the load. The remote sense terminals must
trols input overvoltage protection. Both input overvoltage
always be connected to the converter output and output
and input undervoltage circuits provide hysteresis. The
return. If remote sensing is not required, R19 and R20
circuit of U5 and U6 provides output overvoltage protecmay be shorted, in which case regulation will be provided
tion. When the input to U6 exceeds the TLV431 reference
directly at the converter output filter.
voltage, the converter shuts downs until the overvoltage
condition is gone, at which point a normal soft-start cycle
is initiated.
Figure 6. Output ripple voltage
Performance
The circuit operates from input voltages between
36 and 75 V and at load currents of up to 30 A. The
output voltage typically varies by only 4 mV (0.1%)
over the entire line and load range (see Figure 5).
Most power modules with similar power requirements list line and load regulations below 0.2%. The
output ripple voltage of this design is kept below 26
mV (0.8%) over line and load, as shown in Figure 6.
Power modules offer similar ripple performance.
Ripple Voltage (mV)
30
25
VIN = 72 V
20
15
VIN = 36 V
10
VIN = 48 V
5
0
0
5
10
15
20
Load Current (A)
25
30
10
Analog and Mixed-Signal Products
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Power Management
Texas Instruments Incorporated
Efficiency (%)
Figure 7 compares the efficiency of this design to
Figure 7. Comparison of typical efficiencies
the efficiency of modules from two leading module
manufacturers. The data are given for a 48-V input
and 25°C ambient temperature. Module A is typical
94
of the majority of 3.3-V, half-brick, 100-W modules.
92
Module B is an example of one of the few modules
90
that list efficiency at greater than 90%. The discrete
Module B
Discrete Solution
88
design competes very well with even the most effi86
cient power-supply modules. The efficiency peaks
84
at 93% at around 12 A and drops to 89% at full82
rated load.
Module A
80
The efficiency, package, and thermal environment
78
all conspire to limit the maximum load current for an
76
application. While power modules may be rated for
30 A of load current, the current may actually be
74
limited to a fraction of this by the internal device
5
30
10
15
20
25
junction temperatures. The same is true of the
Load Current (A)
discrete design. Modules have an advantage in this
arena because they often are constructed with materials that provide good heat-sinking properties. With
a discrete design, however, the designer has the opportuConclusion
nity to lay out the circuit board to accommodate for the
The decision whether to build a discrete power supply or to
power dissipation of hot components. Even with an excelbuy premanufactured modules involves trade-offs involving
lent layout, at these power levels, both the modules and
cost, schedule, and risk. Designing a power supply based
discrete solution typically require some forced air flow to
on a reference design, such as the one presented here,
achieve the maximum rated current.
significantly lowers the risk associated with the discrete
To compare the thermal performance of the discrete
approach. In situations where schedule is key, modules are
design to that of the power modules, the circuit was conthe logical choice. However, migrating to a discrete power
structed on a 2-oz. copper, 4-layer PCB in a half-brick
supply yields significant cost savings, particularly in highfootprint (2.3″ x 2.2″). The safe-operating-area (SOA)
volume applications.
curves of the modules and the discrete design are shown
in Figure 8 for a 48-V input and 300 linear feet per minute
Related Web sites
(lfm) of air flow. The good heat sinking and high efficiency
analog.ti.com
of Module B allow it to operate at higher currents than
www.ti.com/sc/device/partnumber
both Module A and the discrete design. However, even the
Replace partnumber with TL331, TLV431A, UCC2580-1
good heat sinking of Module A cannot make up for its low
or UCC3580-1
efficiency. Incorporating the discrete design into a larger
PCB allows more copper to be tied to the hot components
(the power MOSFETs) to provide a wider SOA.
Figure 8. Comparison of SOA curves
Maximum Ambient
Temperature (°C)
95
Module B
85
Discrete
Solution
75
65
55
Module A
45
35
25
0
5
10
15
20
Load Current (A)
25
30
11
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