10Gb/s Channel Modeling
Modeling and Analysis of Interconnects for RFIC
1
2002 Empowering Profitability
Presentation
#2
RFIC interconnect
Outline
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Introduction
Electrical Modeling Solution
EMPOWERING Design Flow
Differential VCO Design
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Spiral Inductor Design
On-chip Interconnects
QFN Package
Conclusion
References
RFIC Design
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Industry challenge
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Great demand on high performance
Increasing operating frequency while decreasing
size
Reducing development costs and time-to-market
Electrical modeling has become one of the
most important factors
An accurate electrical model of
interconnect is an essential part of doing
design
What Is An Interconnect for
RFIC?
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Path used to carry a signal from one point to another
On-chip interconnects
w Spiral inductor
w MIM capacitor
BYP
w Routing traces
Tune
Package
GND
w C4 Bump
SHDN
w Bondwire
w Solderball
VCC
GND
w Traces
GND
OUTIP
GND
OUTIN
GND
OUTQN
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GND
OUTQP
GND
IND
Why are Interconnects
Important to Model?
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At lower frequencies, the main loss occurs in the conductor, which is
negligible. Most designers will assume an ideal short in between
connection points
Active
Component
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At higher frequencies, there are now 2 loss mechanisms - conductor
and substrate loss. The conductor loss is now an important due to
skin effect. Substrate loss will be dominant in the lossy dielectric
medium of silicon
Active
Component
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Active
Component
L
R
C
L
R
C
Active
Component
Neglecting these 2 modeling parameters will mean the electrical
performance will be off from expected results, which will cause a
loss in profitability
Electrical Modeling
Physical Geometry
IC-1
wire
lead frame
wire
signal line
PKG-1
IC-2
PKG-2
PCB
Electrical Modeling
- EM Simulation Based
- Measurement Based
Electrical Model
L
L
R
C
R
C
Driver
IC-1
PKG-1
PCB
PKG-2
Receiver
IC-2
Electrical Modeling Procedure
Initial Design
Simulation Based
Modeling
Modification
No
OK?
Electrical Model
Yes
Sample Fabrication
No
Measurement Based
Modeling
OK?
Yes
Ansoft Electrical Modeling
Solution
Design Automation
Ansoft Optimetrics
Full-Wave
SPICE
Fields
Fields/Radiation
Full-Wave SPICE
S-Parameters
Current/Radiation
Full-Wave SPICE
S-Parameters
Ansoft SIWave
Ansoft HFSS
Ansoft Designer
Planar EM
Zuken
Cadence
GDSII
Avanti
Mentor
DXF
Quasi-Static
AnsoftLinks
IGES
STEP
ACIS
Ansoft TPA
Ansoft SpiceLink
SPICE/DML/IBIS
RLC
SPICE/DML/IBIS
RLC(G)
Fields
Ansoft Electrical Modeling
Advantage
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Ansoft has a strategic advantage over all of
EDA software companies because of:
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Advanced Technology
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Adaptive meshing
PEEC
Solve-on-demand
Integrated translation to 3rd party layout programs
Diversity of Solving techniques
Adaptive Mesh
Geometry
Geometry
(no
(no mesh
mesh data)
data)
Initial
23981 tets
Create
Create Initial
Initial Mesh
Mesh
Calculate
Calculate Field
Field
Calculate
Calculate
Field
Field Accuracy
Accuracy
∆E
∆E Acceptable?
Acceptable?
Yes
Display
Display
Simulation
Simulation Results
Results
Final
320620tets
No
Refine
Refine Mesh
Mesh
Integration
Zuken
Cadence
Avanti
Mentor
AnsoftLinks
IGES
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By having this tight integration to layout tools, it
saves the engineer time in redrawing structure
Allows engineer to solve the problems as close to
the actual product as possible.
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STEP
Surface Roughness
Etched traces
Process variability
Allows the engineer to pull data from many
different sources. Not “pigeon-holed”
Diversity of Solving Techniques
BEM
PEEC 2D FEM
Parametrics
Solving Method
FEM
Sensitivity
RLCG
Transient
Analysis
MOM
Harmonic
Balance
Spice SubCircuits
Desired Output
Optimization
DML
IBIS
Eye Diagrams
S,Y,Z Parameters
BER
N-Port
Devices
FWS
Fields
Radiation
Q-Factor
EMPOWERING Design Flow
Power, Ground / BGA
S-, Y-, ZR, L, C
TPA / SIwave
AnsoftLinks
Ansoft Designer
Circuit/System/Planar EM
Zuken
Cadence
Avanti
Mentor
GDSII
DXF
Matrix / Parameters
S-, Y-, ZR, L, C
HFSS / SpiceLink
with Optimetrics
Differential VCO
[1]
LC Tank
Resonator
Differential VCO
Feedback
Gain block
Differential VCO Layout
VCO_Core
AnsoftLinks for Virtuoso
GDSII Translator
2D Profiles
3D Solid
Model
Center-tapped Multi-layer
Differential Spiral Inductor
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[2]
Parasitic coupling between two inductors is canceled by differential mode
Differential Q is higher than Single-ended
Self-resonance frequency is higher than single-ended
Port1
Center-tap
Port3
Port2
Stack-up for Spiral Inductor
Metal 8
εr = 3.6
Metal 7
Metal 6
Passivation=0.875um
TM8=0.9um
Copper
εr = 4
SiO2=0.65um
εr = 4
TM7=0.35um
SiO2=0.45um
Copper
TM6=0.35um
Copper
εr = 4
εr = 11.9
Conductivity = 13.3333 S/m
SiO2=4.4um
Silicon=300um
Spiral Inductor Design
Optimetrics
(Rs, Ls, Cs, Rsub,
Csub , Cox)
3D model generated
and parameterized as a
function of (Ri, W, S, N)
Resulting schematic saved and
parsed to provide Optimetrics
with circuit values.
Model Solved In HFSS
Random/Gradient optimization
performed to match circuit
response to HFSS results.
Solutions exported for
use in Designer
simulation
Designer circuit specified
and parameterized (Rs, Ls,
Cs, Rsub, Csub , Cox)
S-Parameter
S22, S33
S11
S12, S13, S21, S31
S23, S32
Differential Q-factor
Single-ended Q
Differential Q
Phase Noise Comparison
Spiral Inductor
Ideal Inductor
On-chip Interconnects
Which Interconnects are Important to
Model?
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LC tank circuits are used for the oscillation frequencies. Interconnects can add capacitance and
inductance to these values which can throw off the expected oscillation point.
Which Interconnects are Important to
Model?
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Reversed biased diodes are used as capacitors at a known value. The interconnects
between these connections will invariably add to these capacitor's value.
Which Interconnects are Important to
Model?
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The interconnects between the VCO core cell will generate negative resistance which is
the source of oscillation. It is important to know the parasitics that are present which will
determine the oscillation point
Figure 1: Interconnect in between Varactor Diodes
Simplifying the Model
Varactors
Out to
Spiral
4 Transistors
4 Transistors
Interconnect structures
of importance
Spiral to Varactor Interconnect
Trace Parasitics
0.006 nH
0.006 nH
0.04 ohms
Source
0.04 ohms
6.4 fF
0.04 ohms
0.05 nH
0.05 nH
0.04 ohms
15.3 fF
Sink
Ground Parasitics
Varactor to Varactor Interconnect
Trace Parasitics
Source
0.01 nH
0.01 nH
0.06 ohms
0.06 ohms
6.6 fF
0.04 ohms
0.05 nH
0.05 nH
0.04 ohms
17 fF
Sink
Ground Parasitics
Transistor to Varactor Interconnect
Trace Parasitics
0.02 nH
Source
0.02 nH
0.13 ohms
0.13 ohms
5.4 fF
0.04 ohms
0.05 nH
0.05 nH
0.04 ohms
16.1 fF
Sink
Ground Parasitics
QFN Package
[3][4]
Mold Compound
Gold Wire
Die Attach Material
Cu Leadframe
Down
Bond
Exposed Die
Paddle
Ground Bond
3.0 mm
q Package Descriptions:
GND OUTIP GND OUTIN
BYP
GND
Tune
OUTQN
3.0 mm
0.5 mm
GND
GND
SHDN
OUTQP
GND
IND
VCC GND
0.3 mm 0.5 mm
Package height
Body size
Exposed pad
mm
Die size
mm
Die thickness
0.9 mm
3 x 3 mm
1.25 x 1.25
1.0 x 1.0
0.30 mm
Package Model in HFSS
Port2
Port4
Die
Port1
Port3
Gold Wire
Exposed Die
Paddle
Cu Leadframe
Vias
Ports
Package Analysis in HFSS
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Final mesh size : 320620
tets
Lumped gap source used
Solve surface option
ZERO_ORDER=1
S-parameter
S-parameter
LC VCO with Interconnects
Spectral Plot
Output Frequency & Power
Interconnects
Ideal
Conclusion
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Electrically modeling interconnects for RFICs is very important to
the first time success of the design.
Ansoft’s suite of software provides all of the necessary electrical
simulation engines to perform accurate simulations of the RFIC.
w Spiral Inductor – HFSS, Designer
w Interconnects - Spicelink
w QFN Package – HFSS, Spicelink
w Circuit/System Analysis - Designer
An electrical model was made for every part of the differential
VCO core including the interconnects.
Using the extracted models, in depth analysis of the RFIC
system within Designer provides results that are used to obtain
phase noise plots.
Optimizing the phase noise provides the engineer a way to
improve the design and improve profitability.
References
1.
2.
3.
4.
P. Andreani, H. Sjoland, “Tail Current Noise
Suppression in RF CMOS VCOs,” IEEE Jour. SolidState Circuits, Vol. 37, No. 3, March 2002
A. M. Niknejad, J. L. Tham, and R. G. Meyer, "FullyIntegrated Low Phase Noise Bipolar Differential VCOs
at 2.9 and 4.4 GHz," Proceedings of the 25th European
Solid-State Circuits Conference, 1999. p. 198-201.
http://www.amkor.com/products/notes_papers/MLF_Ap
pNote_0301.pdf
http://www.jedec.org/ , JEDEC standard, “MO-220d”