1
Supplementary Problems
CHAPTER 2
Problem 1 Explain the operation of a MOS switch.
Solution: One advantage of MOS technology is
that it provides a good switch. Figure 2.48(a) shows a
MOS transistor that is to be used as a switch. Either
terminal, A or B, can be the drain or source of the
MOS transistor depending on the terminal voltages.
For an n-channel transistor, if terminal A is at a higher
potential than terminal B, then terminal A is the drain
and terminal B is the source. The ON resistance
consists of the series combination of r D , r S, and
whatever channel resistance exists. The contribution
from r D and r S is small such that the primary
consideration is the channel resistance.
C
Problem 2 How can a JFET be used to supply a
constant current to a variable load?
A
B
(a)
0V–OFF
5V–ON
Circuit
1
In the ON state of the switch, the voltage across
the switch should be small and vGS should be large.
Therefore, the MOS device is assumed to be in the
non-saturation region.
In the OFF state of the switch, VGS £ VT and rOFF
is ideally infinite. Of course, it is never infinite, but
because it is so large, the performance in the OFF
state is dominated by the drain-bulk and source-bulk
leakage current as well as subthreshold leakage from
drain to source.
For the n channel MOS transistor the gate voltage
must be considerably larger than either the drain or
source voltage in order to ensure that the MOS
transistor in ON. The bulk is taken to the most negative
potential for the n channel switch. Typical terminal
voltages are given in Fig. 2.48(b).
G
(0 to 2V)
(0 to 2V)
S
D
Circuit
2
(b)
Fig. 2.48 (a) An n-channel MOS switch (b)
MOS switch with typical terminal voltages
Solution: A JFET can be used to supply a constant
current to a variable load by connecting its gate
directly to its source, as illustrated in Fig. 2.49. Here,
the resistor R D is regarded as the (variable) load
resistance.
To be able to supply a current that is independent
of RD, the JFET must remain in its pinch off region.
The condition for pinch-off is | VDS | > |VP | – | VGS |.
Because VGS = 0 in this case, the condition reduces
to | VDS | > | VP |.
2
Linear Integrated Circuits
+VDD
were horizontal: rd = D VDS /D ID with D ID = 0. The
JFET can be used to supply a constant current equal
to some value less than I DSS by biasing it
appropriately.
+VDD
IDSS
RD
RD
=
Problem 3 Find the ideal value for IC2, IC3, and IC4
for the current mirror shown in Fig. 2.51. Assume
that b1 = b2 = 100, b3 = 200, b4 = 150, IBias = 2 mA.
IDSS
Solution:
(a) n-channel JFET current source
+VDD
RD
+12 V
–VDD
5
IDSS
2 mA
RD
=
1
Q1
IDSS
b = 100
IC2
IC3
1K
1K
IC4
1K
2
Q2
3
Q3
4
Q4
b = 100
b = 200
b = 150
(b) p-channel JFET current source
Fig. 2.49
JFET constant current sources
The constant current produced by the JFET is
then ID = IDSS, because that is the drain current in the
pinch-off region when VGS = 0. So long as the JFET is
in its pinch-off region, the line corresponding to VGS
= 0 is essentially horizontal, meaning that the same
current flows regardless of VDS (see Fig. 2.50). In
reality, the line rises slightly to the right, so the current
source is not perfect. Of course no current source is
perfect. The JFET current source would be perfect if
rd were infinite, which would be the case if the line
ID
Constant-current region
VGS = 0
DVDS
IDSS
rd =
|Vp|
DID
DVDS
DID
VDS
Fig. 2.50 A JFET current source maintains an
essentially constant current equal to IDSS in the
pinch-off region. If the characteristic were
perfectly flat, then D ID would be zero, and vd
would be infinite
Fig. 2.51
For Problem 3
Neglecting IB,
IC2 = b2/b1 ´ 2 mA
= 100/100 ´ 2 mA = 2 mA
IC3 = b3/b1 ´ 2 mA
= 200/100 ´ 2 mA = 4 mA
IC4 = b4/b1 ´ 2 mA = 150/100 ´ 2 mA = 3 mA
Problem 4 For the current mirror circuit shown
in Fig. 2.52, PMOS transistors provide the mirror
current provided by M1. The W/L ratios are specified
for each transistor. NMOS transistor M5 is used to
bias the current mirror. A bias voltage of 1.2 V is
applied to the gate of M1 transistor. KPn = 8.16 ´ 16–
5
A/V2 and KPp = 2.83 ´ 10–5 A/V2. Determine the
bias current ID1, and the ideal currents for ID2, ID3
and ID4. VTN = 0.7 V, VTP = –0.82 V.
Solution: First, the bS for each transistor need to
be calculated.
W1
28
= 2.83 ´ 10–5 ×
2
L1
= 3.96 ´ 10–4
b 1 = KPP
b 2 = KPP ×
W2
28
= 2.83 ´ 10–5 ×
2
L2
Supplementary Problems
6
W = 28 M
1
L 2
2
ID2
M5
M3
W = 56
L 2
3
IBIAS (ID1)
VBIAS 1
(1.2 V)
M2
W = 28
L 2
M4 W = 42
L 2
RL2
ID3
RL3
= 5.974 ´ 10–4
W
b 5 = KPp × 5 = 8.16 ´ 10–5 × 10
L5
2
= 4.08 ´ 10–4
Next, calculate the bias current.
5
4
ID4
RL4
W 10
=
2
L
3
IBias = ID1 =
C5
2
(VGSS – VTS)2
4.08 s 10 4
(1.2 – 0.7)2 = 50 mA
2
Next, calculate the reflected currents for ID2, ID3,
and ID4
=
Fig. 2.52 A MOSFET current mirror with three
reflected currents
–4
= 3.96 ´ 10
W
b 3 = KPP × 3 = 2.83 ´ 10–5 × 56
L3
2
–4
= 7.92 ´ 10
W
b 4 = KPP × 4 = 2.83 ´ 10–5 × 42
L4
2
I D2 =
C2
3.96 s 10 4
´ ID1 =
´ 50 mA = 50 mA
C1
3.96 s 10 4
I D3 =
C3
7.92 s 10 4
´ ID1 =
´ 50 mA = 100 mA
C1
3.96 s 10 4
I D4 =
C4
5.974 s 10 4
´ ID1 =
´ 50 mA = 150 mA
C1
3.96 s 10 4
4
Linear Integrated Circuits
CHAPTER 3
+12 V
Problem 1 What are the currents and voltages in
the single-ended output circuit of Fig. 1?
+8.61 V
+12 V
+12 V
–0.7 V
3 kW
–12 V
(a)
+12 V
5 kW
–12 V
Fig. 1
1.13 mA
1.13 mA
Problem 1
Solution: Ideally, the tail current IT is
IT =
12 V
= 2.4 mA
5 k8
1.13 mA
Each emitter current IE is
2.4 mA
= 1.2 mA
2
The collector on the right has a quiescent voltage
IE =
of
VC = 12 V – (1.2 mA) (3 k W) = 8.4 V
The collector on the left has 12 V.
Including VBE drop across each emitter diode
IT =
–12 V
(b)
Fig. 2
Solution for Problem 1
Solution:
IT =
12 V 0.7 V
= 2.26 mA
5 k8
15 V
= 2 mA,
7.5 k8
The ac emitter resistance r e¢ =
IE = 1 mA
25 mV
= 25 W
1 mA
The voltage gain is
2.26
= 1.13 mA
2
VC = 12 V – (1.13 mA) (3 kW) = 8.61 V
IE =
A =
Fig. 4 (a) shows the dc voltages and Fig. 4 (b)
shows the dc currents.
Problem 2 In Fig. 2 what is the ac output voltage?
If b = 300, what is the input impedance of the
differential amplifier?
1.13 mA
2.26 mA
5 k8
= 200
25 8
The ac output voltage is
Vout = 200 (1 mV) = 200 mV
is
The input impedance of the differential amplifier
Zin (base) = 2 (300) (25 W) =15 k W
5
Supplementary Problems
Problem 3 Repeat Example 2 by including VBE
voltage drop across each emitter diode.
The voltage gain for the single-ended output is
A =
IE = 0.995 mA, re¢ = 26.2 W, A = 191
Solution:
The ac output voltage is
The ac output voltage is
Vout = 150 (7 mV) = 1.05 V
Vout = 191 (1 mV) = 191 mV
is
The input impedance of the differential amplifier
Z in = 2 (300) (26.2 W) = 15.7 kW
+15 V
5 kW
1 M8
= 150
2 (3.33 k8)
The input impedance of the base is
Z in = 2 (300) (3.33 kW) = 2 MW
Problem 6 For the ideal differential amplifier
shown in Fig. 5, find (a) the dc output voltages VO1
and VO2. (b) the single-ended output gain vO1/(vi1 –
vi2), (c) the double-ended gain (vO1 – vO2)/(vi1 – vi2).
+15 V
5 kW
–
vout
+
6 kW
6 kW
vo1 vo2
1 mV
vi1
vi2
7.5 kW
–15 V
Fig. 3
Problem 4
v1 = 0.
Repeat Problem 2 for v2 = 1 mV and
–15 V
Fig. 5
Solution: Instead of driving the non inverting input
we are driving the inverting input. Ideally, the output
voltage has the same magnitude of 200 mV, but it is
inverted. The input impedance is approximately
15 kW.
Problem 5 Find the ac output voltage in Fig. 4.
If b = 300, what is the input impedance of the
differential amplifier?
Solution:
2 mA
For Problem 2
Ideally,
Solution:
(a) The emitter current in each transistor is
I E = I/2 = (2 mA)/2 = 1 mA » IC
Therefore,
V O1 = VO2 = VCC – ICRC
= 15 – (1 mA)(6 kW) = 9 V
(b) The emitter resistance of each transistor is
re = 0.026 = 0.026 = 26 W
IE
1 mA
15 V
= 15 mA
IT =
1 M8
RC
6 k8
vo1
=
=
= –115.4
vi1 vi 2
2re
52 8
Since the emitter current in each transistor is half
of the tail current,
re¢ =
25 mV
= 3.33 kW
7.5 NA
For Problem 6
(c)
vo1 vo 2
RC
6 k8
=
=
= – 230.8
vi1 vi 2
rea
26 8
6
Linear Integrated Circuits
Problem 7 Calculate the common-mode gain for
the differential amplifier in Fig. 6.
Solution:
+9 V
Using RE = ro = 200 kW gives
AC =
=
10 kW
C Rc
ri 2 ( C 1) RE
75 (10 k8)
11 k8 2 (76) ( 200 k8)
= 24.7
10 kW
Q1
Vi
Vi1
´ 10–3
R1
1 kW
R2
8.2 kW
Q2
Q3
5.1 kW
–9 V
b1 = b2 = b = 75
ri1 = ri2 = ri = 11 kW
Q3
ro = 200 kW
b3 = 75
Fig. 6
For Example 7
7
Supplementary Problems
CHAPTER 4
CMRR¢, dB
Problem 1 Calculate the differential gain in each
of the following cases.
Solution: See Fig. 1.
Problem 2 A certain op-amp has an open loop
voltage gain of 100,000 and a common-mode voltage
gain of 0.2. Determine the CMRR and express it in
decibels.
100
90
80
70
60
50
40
30
20
10
0
1
10 100 1
Hz
Solution:
A OL = 100,000 and ACM = 0.2
CMRR =
AOL
100,000
=
= 500,000
Acm
0.2
Expressed in decibels
CMRR = 20 log (500,000) = 114 dB
Fig. 2
V2
Problem 3 Discuss the CMRR of the 741 at
different frequencies with the help of Fig. 2.
Solution: For the 741, CMRR is 90 dB at low
frequencies (see Fig. 4.32). Given equal signals, one a
desired signal, and the other a common mode signal,
V1
+
+
AVOL = 200,000
±Vid = 50 mV
Vout = Vid . AVOL
–
10 100
MHz
+15 V
AVOL = 200,000
Vid = V1 – V2
kHz
Frequency
For Problem 2
+VCC
V1
10 100 1
V2
Vout = ±10 V
–
Vout = AVOL ¥ Vid
= 200,000 ¥ 50 mV
Vout = +10 V
–VCC
(a)
–15 V
(b)
+15 V
+15 V
V1 = 1 V
+
–
AVOL = 200,000
Vid = 50 mV
–
+
V2 = 999.95 mV
Fig. 1
For Problem 1
V2 = 1 V
Vout = –10 V
–
Vout = AVOL ¥ Vid
Vid = V1 – V2
= 999.95 mV – 1 V
Vid = –50 mV
+
+
AVOL = 200,000
Vid = 50 mV
Vout = +10 V
–
V1 = 999.95 mV
–15 V
(c)
= 200,000 ¥ –50 mV
Vout = –10 V
–15 V
(d)
8
Linear Integrated Circuits
MPP in volts
the desired signal will be 90 dB larger at the output
than the common-mode signal. In ordinary numbers,
this means that the desired signal will be
approximately 30,000 times larger than the commonmode signal.
At higher frequencies, reactive effects degrade
CMRR. It is approximately 75 dB at 1 kHz 56 dB at
10 kHz and 20 dB at 1 MHz.
Problem 4 What is the CMRR of a 741C when the
input frequency is 100 kHz?
Problem 5 Discuss with the help of an illustration
maximum peak-to-peak (MPP) output of an op-amp.
Solution: The MPP value of an amplifier is the
maximum peak-to-peak output that the amplifier can
produce. Since the quiescent output of an op-amp is
ideally zero, the ac output voltage can swing
positively or negatively. For load resistances that
are much larger than R out, the output voltage can
swing almost to the supply voltages.
With a nonideal op-amp, the output cannot swing
all the way to the value of the supply voltages because
there are small voltage drops in the final stage of the
op-amp. When the load resistance is not large
compared to Rout, some of the amplified voltage is
dropped across R out , which means that the final
output voltage is smaller.
Figure 3 shows MPP versus load resistance for a
741C with supply voltages of ± 15 V. MPP value is
approximately 27 V for an RL of 10 k W. This means
that the output saturates positively at +13.5 V and
negatively at – 13.5 V. When the load resistance
decreases, MPP also decreases. For a load resistance
of 275 W, MPP decreases to 16 V, which means that
the output saturates positively at + 8 V and negatively
at – 8 V.
Problem 6 What is the open-loop voltage gain of
the 741C ÿ when the input frequency is 1 kHz,
10 kHz, 100 kHz?
Fig. 3
0.5 1.0 2.0
5.0
Load resistance, kW
10
For Problem 5
Solution:
The voltage gain at
1 kHz = 1000
10 kHz = 100
100 kHz = 10
The voltage gain decreases by a factor of 10 each
time the frequency increases by a factor of 10.
fc
100,000
70,700
Voltage gain
Solution: The CMRR of a 741C is approximately
40 dB at 100 kHz (Fig. 2). This is equivalent to 100,
which means that the desired signal receives 100 times
more amplification than a common-mode signal when
the input frequency is 100 kHz.
30
28
26
24
22
20
18
16
14
12
10
8
6
0.1 0.2
10,000
1000
100
10
0
funity
1
10
Hz
Fig. 4
100
1
10
100
kHz
Frequency
1
MHz
For Problem 6
Problem 7
(a) Determine the value of R1 required to give Av
= – 25 given RF = 55 k W
(b) If Vin = 50 mV, determine I1, IF and V0.
Solution:
(a) R1 =
RF
55
=
kW = 2.2 k W
25
25
(b) I1 =
50 mV
Vin
=
= 22.73 mA
R1
2.2 k8
Supplementary Problems
IF = – I1 = – 22.73 mA
Vo = Av Vin = – (25 ´ 50 mV) = – 1.25 V
The error voltage is
Verror =
RF
R1
+
Vin
IB(–)
A
–
Vid
Problem 9 Suppose the 741C of the preceding
example is replaced by another 741C that has a voltage
gain of only 20,000 (worst case value on data sheet).
Recalculate the values of A CL, V out, and V error.
Comment upon the results.
vo
+
IB(+)
Fig. 5
For Problem 7
Problem 8 If the 741C of Fig. 6 has an open loop
gain of 100,000, what is the closed loop gain? What
are the output and error voltages equal to?
+15 V
+
+
741C
–
Vin
–15 V
–
Fig. 6
R1
98 kW
R2
2 kW
10 kW
+
vout
–
For Problem 8
Solution: The voltage divider has a feedback
fraction of
b=
2 k8
R2
=
= 0.02
R1 R2
100 k8
The closed loop gain
ACL =
100,000
A
=
1 (100,000) (0.02)
1 AC
= 49.975
An approximate value of ACL is given by
ACL = 1 =
C
50 mV
Vout
=
= 0.5 mV
100,000
A
Note: The error voltage is very small. This is typical of
op-amps with feedback because the open-loop voltage is
quite high.
IF
–
I1
9
1
= 50
0.02
This is an accurate approximation for the gain of
amplifiers that use non-inverting feedback.
If Vin = 1 mV, the output voltage is
Vout = ACL Vin = 50 (1 mV) = 50 mV
Solution:
ACL =
A
1
=
= 49.875
1 AC
1 ( 20,000) ( 0.02)
Without negative feedback the overall voltage gain
has dropped from 100,000 to 20,000, a decrease of 80
per cent. With negative feedback, we have less overall
voltage gain, but in return we get a fabulously stable
closed-loop voltage gain. In this example, the closedloop voltage gain decreases from 49.975 to 49.875, a
decrease of only 0.2 per cent. Therefore, the closedloop gain is nearly independent of the op-amp
voltage gain.
Since ACL is nearly 50
Vout = 50 (1 mV) = 50 mV
50 mV
= 2.5 mV
20,000
Compared with the preceding example, the error
voltage has increased by a factor of 5. When the openloop voltage gain drops by a factor of 5, the error
voltage increases by a factor of 5. Therefore, the
output voltage still remains at approximately 50 mV.
Attempted changes in output voltage are fed back to
the input producing an error voltage that
automatically compensates for the output change.
Verror =
Problem 10 Show examples of typical op-amp device
pinouts. Explain.
Solution: Most op-amps are in the form of
integrated circuits which typically contain one, two
or four amplifiers. Figure 7 shows examples of device
pinouts. The pins of the integrated circuits are
numbered anticlockwise when viewed from above
(the side away from the pins), as shown in Fig. 7. The
10
Linear Integrated Circuits
14 Output
Output 1
13 Inv inp
Inv inp 2
– +
+ –
Non-inv inp 3
Offse
1
null
Inv inp 2
Non-inv
inp 3
V
–
–
+
8 NC
Output 1
7 V+
Inv inp 2
6 Output
Offset
5
null
4
8 V+
– +
Non-inv
inp 3
V
–
(a) Single op-amp
Fig. 7
V+ 4
11 V –
7 Output
Non-inv inp 5
6 Inv inp
Inv inp 6
9 Inv inp
5 Non-inv inp
Output 7
8 Output
+ –
4
12 Non-inv inp
(b) Dual op-amp
– +
+ –
10 Non-inv inp
(c) Quad op-amp
Single op-amp, dual op-amp and quad op-amp device pinouts
orientation of the device is indicated by a notch at
one end of the package, or by a dot against pin
number one or both. The label NC against a pin
represents no connection, V – indicates the negative
supply connection, and V +, the positive supply. Some
devices have 'offset null' inputs which may be used
to remove the effects of an offset voltage. The circuity
required for this null function differs from one device
to another.
Problem 11 Illustrate and explain the 4007
MOSFET array.
13
6
Q1
(p)
2
1
3
8
11
12
10
5
Q2
(n)
7 (GND)
Q6
(n)
Q4
(n)
4
9
Fig. 8 Function diagram of the 4007
CMOS pair plus inverter
G
IN
(p)
R1
B
D
p-channel MOSFET
D
1-5k0
(n)
G
B
S
n-channel MOSFET
7
Fig. 9 Internal input-protection network (within
dotted lines) on each input of the 4007 mB and
MOSFET terminal notations G = Gate, D = Drain,
S = Source, B = Bulk substrate
In use, the input terminals must not be allowed to
rise above VDD (the supply voltage) or fall below VSS
(zero volts).
Q5
(p)
Q3
(p)
S
14
mB
Solution: The 4007 mB is the cheapest (and possibly
the most useful) of all transistor array ICs and is
actually a member of the CMOS digital IC family.
Figure 8 shows the functional diagram and pin
numbering of the IC, which houses two
complementary pairs of independently accessible
MOSFETs plus a complementary pair that is
connected as a simple CMOS inverter.
14 (VDD)
This input of each MOSFET pair is internally
connected to the standard CMOS protection network
(Fig. 9) and all six MOSFETs are enhancement-mode
devices, Q1, Q3, and Q5 are p-channel types and Q2,
Q4 and Q6 are n-channel types. Figure 9 also shows
the terminal notations of the two MOSFET types, the
B terminal represents the bulk substrate.
mB dual
Problem 12 How will you disable 4007
complementary MOSFET pairs?
mB
Solution: Each MOSFET element of the 4007 mB
can be used as either digital or analog (linear)
amplifier and all unused elements must be suitably
disabled, by connecting them as standard CMOS
inverters and tying their inputs to ground, as shown
in Fig. 10.
Supplementary Problems
VDD (+ve)
VDD (+ve)
14
14
6
Q1 – Q 2
7
13
8
10
0V
14
11
Q5 – Q 6
9
VDD (+ve)
7
12
3
4
0V
2
Q3 – Q 4
7
1
5
0V
Fig. 10 Individual 4007 mB complementary
MOSFET pairs can be disabled by connecting
them as CMOS inverters and grounding their
inputs
11
Individual MOSFET pairs can be disabled by tying
their source to their substrate (B) and leaving the
drain open circuit.
12
Linear Integrated Circuits
CHAPTER 5
Problem 1 Calculate the output voltage of an opamp summing amp for the following sets of voltages
and resistors. Use Rf = 1 MW in all cases.
(a) V1 = +1 V, V2 = +2 V, V3 = +3 V, R1 = 500 kW,
R2 = 1 M W , R3 = 1 M W
(b) V1 = –2 V, V2 = +3 V, V3 = +1 V, R1 = 200 kW,
R2 = 500 kW, R3 = 1 MW
Rf
Problem 3 How can the tendency of an op-amp
differentiator to oscillate be avoided?
Solution: To avoid oscillations, a practical op-amp
differentiator usually includes some resistance in
series with the capacitor as shown in Fig. 3. A typical
value for this added resistance is between 0.01 R to
0.1 R. With this resistance, the closed-loop voltage
gain is between 10 and 100. The aim is to limit the
closed-loop voltage gain at higher frequencies,
where the oscillation problem arises.
R
R1
V1
R2
V2
+VCC
–
R3
V0
V3
C
vin
–
vout
0.01R to 0.1R
+
+
–VEE
Fig. 1
For Problem 1
Solution:
(a) V O = –
Fig. 3
8
1000 k8
1000 k8
8 ( 1 V) 1000 k8 ( 2 V) 1000 k8 ( 3 V)!"
1000 k
500 k
= – [2(1 V) + 1(2 V) + 1(3 V)] = –7 V
(b) V O = –
8
1000 k8
1000 k8
8 ( 2 V) 500 k8 ( 3 V) 1000 k8 ( 1 V)!"
1000 k
200 k
= – [5(–2 V) + 2(3 V) + 1(1 V)] = +3 V
Problem 2 Illustrate the output of (a) an integrator
and (b) a differentiator, when the input is a train of
rectangular pulses.
Solution:
Figure 2.
For Problem 3
Problem 4 Illustrate and briefly explain a 4-input
audio mixer.
Solution: Figure 4 illustrates the circuit of a 4-input
audio mixer by ac coupling the input signals and
giving R5 the same value as the feedback resistor.
Input 1
Input 2
Input 3
Input 4
C1
220 n
R1
100 k
C2
220 n
R2
100 k
C3
220 n
R3
100 k
C4
220 n
R4
100 k
R6
100 k
+9 V
2 –
3
R5
100 k
Vin
7
6
741
+
4
Out
–9 V
0V
0
Fig. 4
T
0
Problem 5 Illustrate a summing amplifier using
both sides of the op-amp. Also give the relevant
formulas.
vin
–V
vout
Solution:
T
(a)
Fig. 2
For Problem 5.87
4-input audio mixer
(b)
Vout = A1v1 + A2v2 + A3v3 + A4v4
A1 =
RF
R1
Supplementary Problems
Problem 7 Determine the output voltage of the DAC
in Fig. 5.91 (a).
RF
A2 =
R2
A3 =
R4 || R5 RF
1 R1|| R2 R3 R4 || R5 A4 =
R3|| R5 RF
1 R1|| R2 R4 R3|| R5 Solution: The sequence of four-digit binary codes
represented by the waveforms in Fig. 7 are applied to
the input. A HIGH level is a binary 1 and a LOW level
is a binary 0. The least significant digit is DO.
200 kW
D0
R1
v1
10 kW
100 kW
D1
RF
v2
R2
50 kW
–
25 kW
+
D2
–
vout
Vout
D3
+
R3
v3
(a)
R5
+5 V
0
+5 V
D1
0
+5 V
0
D2
+5 V
D3
0
v4
0 1 2 3 4 5 6 7 8 9 10 11 12 1314 15
D0
R4
Fig. 5 Summing amplifier using both sides of
the op-amp
(b)
Problem 6 Describe the operation of a scaling adder.
Solution: One method of D/A conversion uses a
scaling adder with input resistor values that represent
the binary weights of the input digital code. Figure 6
shows a four-digit digital to analog converter (DAC)
of this type called a binary-weighted resistor DAC.
The switch symbols represent transistor switches for
applying each of the four binary digits to the inputs.
The inverting (–) input is at virtual ground, and so
the output voltage is proportional to the current
through feedback resistor (sum of input currents). The
lowest-value resistor R corresponds to the highest
weighted binary input (23). All of the other resistors
are multiples of R and corresponds to binary weights
22, 21 and 20.
+V
8R
20
Rf
4R
1
2
2R
22
13
–
Vout
+
R
23
Fig. 6 A scaling adder as a four-digit digital to
analog converter (DAC)
Fig. 7
For Problem 7
First, determine the current for each of the
weighted inputs. Since the inverting input of the opamp is at 0 V (virtual ground) and a binary 1
corresponds to a HIGH level (+5 V), the current
through any of the input resistors equals 5 V divided
by resistance value.
IO =
5V
5V
= 0.025 mA, I1 =
= 0.05 mA,
200 k8
100 k8
I2 =
5V
5V
= 0.1 mA, I3 =
= 0.2 mA
50 k8
25 k8
There is no current at the inverting op-amp input
because of its extremely high impedance. Therefore,
all of the input current flows through Rf. Since one
end of Rf is at 0 V (virtual ground), the drop across Rf
equals the output voltage, which is negative with
respect to virtual ground.
V out(D ) = (10 kW) (–0.02 mA) = –0.25 V; Vout(D )
0
1
= (10 kW)(–0.05 mA)
= –0.5 V
Binary input
0
–0.25
–0.50
–0.75
–1.00
–1.25
–1.50
–1.75
–2.00
–2.25
–2.50
–2.75
–3.00
–3.25
–3.50
–3.75
VOUT
Fig. 5.92
0000
1111
1110
1101
1100
0011
1010
1001
1000
0111
0110
0101
0100
0011
2)
0010
= (10 kW)ÿ(–0.1 mA) = –1 V; Vout(D )
3
= (10 kW) (–0.2 mA)
= –2 V
The first binary input code is 0000, which produces
an output voltage of 0 V.
The next input code is 0001 (decimal 1), which
produces an output voltage of –0.25 V.
The next input code is 0010 (decimal 2), which
produces an output voltage of –0.5 V.
The next input code is 0011 (decimal 3), which
produces an output voltage of –0.75 V.
Each successive binary code increases the output
voltage by –0.25 V. So, for this particular straight
binary sequences on the input, the output is a stair
step waveform going from 0 V to –3.75 in –0.25 V
steps as shown in Fig. 5.79. If the steps are very small
the output approximates a straight line.
Vout(D
0001
Linear Integrated Circuits
0000
14
Solution for Problem 7
15
Supplementary Problems
CHAPTER 6
+V
Solution:
V ( Vsat )
= sat
and Vctr =
n
VUT VLT
= Vref 1 1 2
n
10 kW
–V
75 kW
R
nR
(a) The ratio of nR to R or n and Vref
determines VUT, VLT, VH, and Vctr
+Vo and Ei
VH = 12 V – 8 V = 4 V and Vctr =
12 V 8 V
2
= 10 V
(ii) n =
Vo
+
Ei
(i) VH = VUT – VLT
–
8.82 V = Vref
Example 6.50 Design the circuit for Fig. 6.63(a) to
have VUT = 12 V and VLT = 8 V. Assume that ±Vsat =
±15 V.
Vo
+Vsat
VUT = 12 V
Vctr = 10 V
VH = 4 V
VLT = 8 V
Vsat ( Vsat )
VH
=
15 V ( 15 V)
4
Ei
= 7.5
Vref = 8.82 V
t
0
10 V
Vctr
=
= 8.82 V
1 1/ n
1 1/ 7.15
(iv) Select R = 10 k W and nR = 75 k W.
(iii) Vref =
The relationship between Ei and V O shown in
Figs 6.63 (b) and (c).
Example 6.51 Design the circuit for Fig. 64(a) to
have VUT = 12 and VLT = 8 V. Assume that ±Vsat =
±15 V. What are the requirements of voltage level
detector with hysteresis?
–Vsat
–Vo
(b) Vo and Ei vs. time
+Vo
Vo vs. Ei
+Vsat
Solution:
(i) VH = 12 V – 8 V = 4 V
Vctr =
(ii) n =
=
12 V 8 V
= 10 V
2
Vref
8.82 V
0
( Vsat ) ( Vsat )
–1
VH
15 V ( 15 V)
– 1 = 6.5
4V
n 1
6.5 1
(Vctr) =
(10) = 11.53 V
n
6.5
(iv) Choose R = 10 k W; therefore, resistor nR =
6.5 ´ 10 = 65 k W
(iii) Vref =
The relationship between Ei and VO are shown in
Fig. 6.64 (b) and (c).
Vctr
10 V
VUT
12 V
VLT
8V
Ei
–Vsat
–Vo
VH = 4 V
(c) Vo vs. Ei
Fig. 6.63 Non-inverting voltage-level detector with hysteresis. Center voltage Vctr and
hysteresis voltage V H cannot be adjusted independently since both depend on the ratio n
16
Linear Integrated Circuits
The requirements of a voltage level detector are
(3) the setting of VH and Vctr should not interact.
(4) The centre voltage Vctr should equal or be
simply be related to an external reference
voltage Vref.
(1) an adjustable resistor to set the value of VH
(2) a separate adjustable resistor to set the value
of Vctr.
+V
Ei
–
Vo
+
–V
65 kW
10 kW
11.53 V = Vref
R
nR
(a) The ratio of nR to R or n and Vref
determines VUT, VLT, VH, and Vctr
+Vo
+Vsat
Vo
Ei
Vo vs. Ei
+Vsat
VUT = 12 V
VH = 4 V
VLT = 8 V
5
Ei
VctrVref
Vctr =
10 V V
t
0
–Vsat
0
VLT =
8V
Vref =
11.53 V
Ei
VUT =
12 V
–Vsat
–Vo
(b) Vo and Ei vs. time
VH = 4 V
(c) Vo vs. Ei
Fig. 6.64 Inverting voltage-level detector with hysteresis. Center voltage V ctr and hysteresis
voltage VH cannot be adjusted independently since both depend on n
Supplementary Problems
CHAPTER 8
Illustrate typicalÿ power amplifier
Problem 1
heatsinks.
Solution:
(a) Silicone
greese
Case
Be 0 washer
Chassis
(b)
Fin-type
heat sink
17
sink that can accommodate a TO-3 package (d)
Diagram showing the mounting of a TO-3 or
TO-66 transistor package on a heat sink with an
insulating washer
Problem 2 A transistor with VCE = 25 V and IC 1 A
has a junction-to-case thermal impedance of
1°C/W. Select a heatsink which will keep the junction
temperature from exceeding 90°C when the ambient
temperature is 25°C. (The NC-421, NC = 423 and
NC-441 all have qC < 1.6°C/W).
P D = VCE IC = 25 V ´ 1A = 25 W
Solution:
q CA = qCS + qSA =
=
Tj TA
– q jc
PD
90o C 25o C
– 1°C/W
25 W
= 1.6°C/W
As all three transistors have qC < 1.6°C/W , choose
the smallest and least expensive of the three, NC421’s.
(c)
Problem 3 Draw the pin configuration and a
practical application of the TDA2822.
Solution:
6 sheet
metal screws
8 +In (1)
Output 1 1
7 –In (1)
V+ 2
Power
transistor
TDA 2522
Insulator
Output 2 3
6 +In (2)
GND 4
5 –In (2)
Clearance
holes
Top view
Chassis or
heat sink
+6 V
Clearance
holes
Insulating
bushing
2
L/H
input
Socket
Screws or rivets
(not in
mounting kit)
0V
(d)
Fig. 8.40 (a) Method of mounting transistors
that are encased in a metal TO-5 package.
Mounting the transistors case close to the chassis using a beryllium oxide insulating washer
(b) Using a separate heat sink pressed on to
the transistor (c)Typical power transistor heat
R/H
input
0V
47 k
7
+
Volume
+ 8
–
100 m
47 k
10 m
+
470 m
1
+
100 n 4R7
L/H SPKR
4R0 to 32R
0V
TDA
2822
6
+
Volume
+ 5
–
470 m
3
+
100 n 4R7
R/H SPKR
4R0 to 32R
0V
10 m
4
0V
Fig. 8.41 Pin configuration of the TDA2822
dual amplifier IC
18
Linear Integrated Circuits
Problem 4 Draw the pin configuration of low power
IC-TBA820M. Give one application.
5
10
Input 1
6
9
Input 2
Feedback 1
7
8
Feedback 2
Solution: See Fig. 8.45.
Top view
C1
100 n
8
Vin
+
R1
56 R
+
7
RV1 3
5
TBA820M
100 k
Volume
2
+
6
4
1
+
14
7
100 n
100 n
–
2
8
k
+
2R7
V–
+
CS
470 p
R3
1R0
C6
220 n
C4
47 m
V+
C2
100 n
C7
100 n
C5
220 p
C3
100 m
R2
120 R
100 k
2k0
V+ (see text)
1
SPKR
(see
text)
100
3,4,5
10,11,12
LM1877
0
k
+
100 n
8
13
–
2R7
510R
0V
Comp
Gain
Input
GND
8
TBA
820M
4
5
1
100
100 k
Reflection
Bootsloep
V+
Out
Fig. 8.42 Pin configuration of IC-TBA829M
and a low power audio amplifier circuit
Fig. 8.43 Pin configuration of IC-LM1877 and
one application each of the IC using a singleended and a dual power supply
Problem 5 Draw the pin configuration and one
application each of LM1877 dual 2 W amplifier IC
using a single-ended and a dual power supply.
Problem 6 Draw the pin configuration of the
National Semiconductor LM2879T dual 8 W audio
power amplifier IC and give one application each of
the IC using a single ended and a dual power supply.
Solution: See Fig. 8.46.
Solution: See Fig. 8.47.
50 m
V+
14
7
100 n
470 m
+
–
2
100 n
8
Input
50 m 1M0
+
1M0
Input
+
1
2R7
LM1877
8R0
100 n
GND
0V
8
470 m
+
13
–
2R7
510R
100 k
510 R
8R0
50 m
+
+28 V
11
100 n
5
100 k
–
Input 1
4
+
50 m 1M0
+
13 OUT 2
OUT 1 2
3
12
LM1877
5
11
1M0
GND
Input 2
Input 1 6
Top view
50 m
+
+
3,0
TAB
8
7
9 Input 2
8 Feedback 2
LM2879T
10
100 n
10
Feedback 1 7
1
470 m
+
2R7
14 V+
Bios 1
4
100 n
2
100 n
GND
V+
OUTPUT 2
GND
INPUT 2
FEEDBACK 2
NC
FEEDBACK 1
INPUT 1
GND
OUTPUT 1
BIAS
Top view
+
+
3,4,5
10,11,12
0
100 n
50 m
11
10
9
8
7
6
5
4
3
2
1
100 k
510 R
+
–
0V
470 m
+
2R7
510R
100 n
100 k
8R0
100 n
8R0
19
Supplementary Problems
+21 V
V+
470 n
11
5
BIAS
generator
8
Input
+
10
2
7
Feedback
1m0
OUT
22 k
150 R
+
6
1
+
1
Bias
2
1
4
Input
+
–
Signal input
Feedback
82 R
+
7
5
TDA1514A
3 2
0 –
8
220 p
880 R
OUT
470 k
+
3, 9
GND
+
+14 V
5
100 n
Input 1
100 k
Input 2
4m7
100 n
+
–
+
–14 V
1
100 k
Metal
mounting
basis
(V–)
100 n
2
4
LM1877
3,9
TAB
2R7
8R0
+
–
3m3
2R7
1. –INPUT
2. SOAR
3. MUTE
4. V–
5. OUTPUT
6. V+
7. BOOTSTRAP
8. 0 V
9. +INPUT
Fig. 8.45 Pin configuration of the super-fi
audio amplifier IC-TDA1514A. An application of
the IC using split supplies
0V
13
510R
0V
Bottom view
100 n
8
7
22 n
–21 V
100 k
11
3R3
SPKR
4R0
470 n
4m7
220m
4
–
2k0
22 k
47m
8R0
100 n
100 k
Fig. 8.44 Pin configuration and simple equivalent circuit of the dual 8 W audio power
amplifier IC-2879T. The IC usage with a single
ended and a dual power supply
Problem 7 Give the pin configuration of the superfi audio amplifier IC-TDA1514A designed for use
with split supplies. Also give one practical application.
Solution: See Fig. 8.48.
Problem 8 Give the pin configuration of the 9.5 W
audio IC-TDA-1020 with one practical application.
Solution: See Fig. 8.49.
Problem 9 What type of protectionÿis provided to
MOSFETs and why?
Solution: The very thin layer of S i O 2, silicon
dioxide, between gate and channel is very susceptible
to high voltages and is very easily punctured, even
by static electricity resulting from the transistor
sliding around in a plastic bag. A large electrostatic
discharge may also result from a person who picks
up the transistor from its case and brushes the gate
lead against some grounded object. In a relatively
dry atmosphere, a static potential of 300 V is not
uncommon on a person who has high resistance soles
on his shoes.
As a result MOSFETs are protected by a shorting
ring, Fig. 8.50 (a), that is wrapped around all four
terminals during shipping and must remain in place
until after the device is soldered into position. The
MOSFET should never be inserted into or removed
from a circuit with the power on. The JFET is not
subject to these restrictions.
20
Linear Integrated Circuits
GND
1
P.A. OUTPUT
2
V+
3
BOOTSTRAP
4
RIPPLE REJECT
5
P.A. INPUT
6
PREAMP OUTPUT
7
PREAMP INPUT
GND
8
9
Top view
+14.4 V
Signal
input
RV1
10 k
100 n
+
8
1m0
330 k
5
100 n
3
4
TDA1020
6
9
C3
+ 100 m
2
+
1
100 n
7
C2
3n3
C1
150 n
4R7
C4
2000 m
SPKR
2R0
0V
Fig. 8.46 Pin configuration of the IC-TDA1020
and on practical application, for use in automobiles
Some MOSFETs have a built-in gate protection,
a system built into the device to get around the
problem of a high voltage on the gate causing a
puncturing of the oxide layer, thus removing the need
for the listed precautions.
The symbol in Fig. 8.50 (c) shows that between
each gate and the source is placed a back-to-back or
front-to-front pair of diodes, which are built right into
the p-type substrate (one pair on each side of the
MOSFET proper).
These diodes are designed so that if either gate
exceeds +10 V typically with respect to the source,
the upper diode will conduct and the lower diode will
break down (Zener effect) providing a shunt path for
excessive charge from gate to source. Likewise, if the
gate voltage exceeds –10 V, the lower diode conducts
and the upper diode breaks down. The normal
application of signal voltages will not be affected.
These diodes also guard against in-circuit transients.
Problem 10 With the help of a simplified digram
describe the operation of the IC-PAO4 (Apex
Microtechnology) power operational amplifier.
Solution: The PAO4 is an example of a highvoltage, high-current hybrid IC power operational
amplifier. It can operate with supply voltages up to
200 V and is capable of a peak current swing of 20 A.
It has a dc open-loop gain of 102 dB (typ) and 94 dB
(min). It offers a gain bandwidth product of 2 MHz
and a full power bandwidth of 90 kHz when producing
an output voltage swing of 180 V peak-to-peak. This
is an FET input operational amplifier, so along with
these very impressive power output characteristics
is an input bias current of 10 pA (typ), 50 pA (max)
and an input impedance of 1011 W (typ) in parallel
with 13 pF (typ).
A simplified schematic of the PAO4 is given in
Fig. 8.51. The input stage consists of the Q1 – Q2
PMOS differential amplifier stage that is biased by a
current source comprised of Q 5, R 5 and D 1. The
differential amplifier drives an npn current mirror
active load that is comprised of Q3 and Q4. The second
stage uses Q6 as a common-source amplifier stage
with a current source active load. The last stage uses
Q8 and Q9 in the form of a complementary NMOSPMOS class AB source-follower push-pull output
stage. Transistor Q7, in conjunction with resistors R7
and R8, generates a voltage drop that is used to bias
the Q 8 , Q 9 push-pull output stage for class AB
operation to minimize crossover distortion.
There are two separate sets of positive and
negative supply voltage connections, ± VBOOST and
± VS. The operational amplifier can be operated with
+V BOOST = V S and – V BOOST = – V S. Under these
conditions, the peak output voltage swing is about
5 V less than supply voltage under no load conditions,
and about 10 V less that the supply voltage for a
load current of 20 A. For a larger output voltage swing
and a greater power conversion efficiency, the boost
voltage can be raised by as much 20 V above the
supply voltage.
A boost voltage that is 5 V above the supply
voltage is enough to cause the output transistor to
be driven into saturation and results in a substantial
improvement in the output voltage swing and in
power conversion efficiency. With this value of boost
voltage, the peak output voltage swing is only 2 V
less than the supply voltage under no load
conditions, and 5 V less for a 20 A load current.
21
Supplementary Problems
Oxide
Gate 1 insulation
internal
P
P
N
Gate 2
internal
Drain 1
source 2
N
Source 1
N
Channel 1
(N)
Source
terminal
P
Drain 2
N
Channel 2
(N)
P
N
Drain
terminal
P
Unit No. 1
Unit No. 2
Gate-protection
diodes
Gate-protection
diodes
(a)
(b)
2
3
2
3
1. Drain
2. Gate
3. Gate 1
4. Source
(substrate and case)
4
1
(c)
4
1
(d)
Fig. 8.47 (a) Shorting spring for MOSFETs that do not contain the integrated protection (b) Dual
gate protected n-channel depletion type MOSFET, cross-sectional view (c) Symbol of the dual gate
protected MOSFET (d) Showing how a dual gate may be operated as a single gate protected MOSFET
by joining gates 1 and 2
Problem 11 Determine the ideal maximum peak
output voltage and current for the circuit shown in
Fig. 8.52.
Solution:
is
The ideal maximum peak output voltage
V O(peak) » VCEQ » VCC = 20 V
The ideal maximum peak current is
IO(peak) » IC(sat) »
20 V
VCC
=
= 1.25 A
RL
16 8
The actual maximum values of peak voltage and
current are slightly smaller.
Problem 12 Find the maximum ac output power and
the dc input power of the amplifier in Fig. 8.53. Also
determine the input resistance assuming bac = 50
and r e¢ = 6 W.
Solution:
The maximum peak output voltage is
20 V
VCC
=
= 10 V
2
2
The maximum peak output current is
V O(peak) » VCEQ =
IO(peak) » IC(sat) =
VCEQ
10 V
=
= 1.25 A
RL
8
8
The ac output power is
P O = 0.25 IC(sat) VCC
= 0.25 (1.25 A) (20 V) = 6.25 W
The dc input power is
P DC =
I C ( sat )VCC
8
= 7.96 W
=
(1.25 A) (20 V)
8
The input resistance is
R in = bac (re¢ + RL ) = 50 (6 W + 8 W)
= 700 W
22
Linear Integrated Circuits
+VBOOST
+V6
R5
D1
IB
Q8
Q5
IA
R7
R1
Q7
R2
Output
Noninverting
input
Inverting
input
Q1
Q2
Q3
Q4
R8
Q6
Q9
RCOMP
CCOMP
R3
R4
R6
–VBOOST
Fig. 8.48
–V5
Simplified schematic of the PAO4 power operational amplifier
+20 V
VCC
+20 V
R1
470 W
C1
Q1
D1
Q1
10 mF
Vout
D1
D2
D2
Q2
Vs
R1
100 W
R2
470 W
R6
16 W
Vin
For Example 8.57
10 mF
C2
Q2
10 mF
R2
100 W
–20 V
Fig. 8.49
C3 V
out
Fig. 8.50
For Example 8.58
RL
8W
Supplementary Problems
Problem 2 In Fig. 9.5, R = 1 kW and mR = 99 kW.
Find the current IL through the emitter diode of the
opto-coupler.
CHAPTER 9
Problem 1 Discuss a current amplifier.
Solution: There is no point in converting a current
to an equal current but a circuit that converts a small
current to a large current can be very useful. The
circuit of Fig. 9.67 is a current multiplier or current
amplifier (technically a current-to-current converter).
The signal current source Isc is effectively shortcircuited by the input terminals of the op-amp. All of
Isc flows through mR, and the voltage across it is
mR I sc . Resistor mR is known as a multiplying
resistor and m is a multiplier. Since R and mR are in
parallel, the voltage across R is also mRIsc. Therefore,
the current through R must be Isc. Both currents add
to form the load current IL. IL is an amplified version
of Isc and is found from
IL = (1 + m) Isc
(9.36)
Solution:
m = 99 kW/1 kW = 99
IL = (1+99) (10 mA) = 1.0 mA
Problem 3 Explain the working of a light-column
voltmeter.
Solution: A light-column voltmeter displays a
column of light whose height is proportional to
voltage. Manufacturers of audio and medical
equipment may replace analog meter panels with lightcolumn voltmeters because they are easier to read
at a distance.
A light-column voltmeter is shown in Fig. 9.68.
Rcal is adjusted so that 1 mA flows through the equal
resistor divider network R 1 to R 10. Ten separate
reference voltages are established in 1-V steps from
1 V to 10 V.
When Ei = 0 V or less than 1 V, the outputs of all
op-amps are at –Vsat. The silicon diodes protect the
light-emitting diodes against excessive reverse bias
voltage. When Ei is increased to a value between 1
and 2 V, only the output of op-amp 1 goes positive to
light LED 1. The op-amp’s output current is
automatically limited by the op-amp to its short-circuit
The load does not determine load current. Only
the multiplier m and Isc determine the load current.
For variable current gain, the mR and R can be
replaced by a single 100 kW potentiometer. The wiper
goes to the emitting diode, one end to the ground
and the other end to the (–) input. The optical coupler
isolates the op-amp circuit from any high voltage
load. DP is an ordinary silicon diode that protects
the emitting diode against a reverse bias voltage.
R = 1 kW
321
mISC
IL = (1 + m)ISC
0V
99 kW
ISC
mR
321
2
0V
3
7
–
741
6
+
4
–V
Fig. 9.51
To
high
voltage
DP
+V
Signal
current
source ISC
100 mA
23
Current amplifier with optical coupler load
Optical
coupler
load
24
Linear Integrated Circuits
+15 V = +V
Rcal
0 – 10 kW
+V
–
220 W
#10
Vref10 = 10 V
+
R10 = 1 kW
LED 10
–V
+V
–
220 W
#9
Vref9 = 9 V
+
LED 9
R9 = 1 kW
–V
+V
321
R3 to R8
all 1 kW
–
220 W
#2
Vref2 = 2 V
+
R2 = 1 kW
LED 2
–V
+V
2
R1 = 1 kW
Vref1 = 1 V
7
–
220 W
#1
3
6
+
+
4
LED 1
Ei
–
–V
Fig. 9.52 Light-column voltmeter. Reference voltages to each op-amp are in steps of 1 V. As Ei
is increased from 1 V to 10 V, LED 1 through LED 10 light in sequence. R1 to R10 are 1% resistors.
The op-amps are 741 8-pin mini-DIPs
value, approximately 20 to 25 mA. The 220 W output
resistances divert heat away from the op-amp.
As Ei is increased, the LEDs light in numerical
order. This circuit can also be built using two and
one-half LM324 quad op-amps. Some manufacturers
have designed IC packages for this particular
applications, such as National Semiconductors
LM3914.
25
Supplementary Problems
CHAPTER 10
Ground
Problem 1 Give a typical application of the LM386.
1
8
C
NC
Solution: A typical application of the LM386 as a
power amplifier in a radio receiver is shown in
Fig. 10.29. The detected AM signal is fed to the
inverting input through the volume control
potentiometer R 1 and resistor R 2, C1 is the input
coupling capacitor and C 2 is the power supply
decoupling capacitor. R2 and C3 filter out any residual
RF or IF signal that may be on the output of the
detector. R 3 and C 5 provide additional filtering
before the audio signal is applied to the speaker
through the coupling capacitor C7.
Square
wave out
Triangle
wave out
Fig. 10.30
the NE566
V+
NE566
R
4
5
Modulation
input
Outline and pin configuration of
Solution: The NE566 is a general purpose generator
that produces excellent simultaneous square and
triangle output (up to 1 MHz) that can be frequency
+9 V
C4
C1
C2
0.1 mF
1 mF
R2
R1
10 W
1.0 W
Volume
control
Fig. 10.29
10 mF
6
2
C3
0.0022 mF
1
–
8
3
47 W
7
+
C7
R3
5
LM386
4
C5
10 mF
220 mF
C6
0.047 mF
The LM386 as an audio power amplifier
modulated (FM) or frequency shift keyed (FSK) via a
voltage control input terminal. Figure 10.30 shows
the ICs outline and pin configuration. Figure 10.31
Problem 2 Give the pin configuration and functional
block diagram of the IC-NE 566. Explain briefly.
V+
R
6
Modulation
input
vc
5
8
Current
source
Schmitt
trigger
Buffer
amplifier
Buffer
amplifier
NE566
1
7
C
0V
Fig. 10.31
Functional block diagram of the NE566
Out
3
Out
4
26
Linear Integrated Circuits
shows its functional block diagram plus a few
essential external components.
In essence, the NE566 is a VCO with buffered
output; the VCO section is made up of a pair of
voltage-controlled current sources that linearly
charge or discharge an external timing capacitor, and
a Schmitt trigger that flips the current sources when
the capacitor voltage reaches preset levels. A linear
triangle wave is generated across the capacitor, and
a high-quality square wave is generated at the
Schmitt output; these waveforms are fed to the
outside world via simple buffer amplifiers.
Problem 3 Discuss a simple fixed frequency
application of the NE566.
Solution: The NE566's operating frequency is set
by an external resistor R and capacitor C, and by the
voltage Vc, applied to its control terminal and is
roughly equal to 2 (V+ – V)/RC.V+. R must be in the
range 2–20 kW; C can have any value, and Vc must be
between 75 and 100 per cent of the supply voltage
value. Frequency can be varied over a 10 :1 range via
R, and can be varied or modulated over a similar range
via Vc. Thus the Fig. 10.46 circuit acts as a fixedfrequency FM waveform generator; it operates at
about 5 kHz with R and C values of 4 k and 10 nF. The
1 nF capacitor between pins 5 and 6 enhances circuit
stability.
V+ (10 to 24 V)
R
(2 k0 to
20 k)
R1
1 k5
Out
6
1n0
C1
8
3
VC
NE566
5
Out
4
Mod
input
7
R2
10 k
1
C
0V
Fig. 10.32
tion circuit
Simple
fixed-frequency
applica-
27
Supplementary Problems
CHAPTER 11
+V = +10 V
Problem 1. Explain the false lock in phase locked
loops. How can it be alleviated?
Solution: The PLL could lock to twice the
frequency of the input signal, three times the
frequency of the input signal or any other multiple.
Alternatively, it could lock to a submultiple of the
frequency of the input signal (i.e., one-half, one-third,
or some other submultiple). This false lock will occur
whenever the free-running frequency of the VCO is
closer to a multiple or submultiple of the input
signal’s frequency rather than to its actual frequency.
False lock can only be alleviated by somehow
guaranteeing that the free-running frequency of the
oscillator is closer to the actual input frequency than
it is to some multiple or submultiple thereof. This
requires a prior knowledge of the input signal and is
a limitation on how much the input signal’s frequency
can vary.
Problem 2. A PLL is locked onto an incoming
signal with a frequency of 1 MHz at a phase angle of
50°. The VCO signal is at a phase angle of 20°. The
peak amplitude of the incoming signal is 0.5 V and
that of the VCO output signal is 0.7 V.
(a) What is the VCO frequency?
(b) What is the value of the control voltage
being fed back to the VCO at this point?
Solution:
(a) Since the PLL is in lock
fi = fo = 1 MHz
(b) qe = qi – qo = 50° – 20° = 30°
VV
Vc = i o cos qe
2
(0.5 V s 0.7 V )
cos 30°
2
= (0.175 V) cos 30° = 0.152 V
=
Problem 3. In the circuit in Fig. 11.42, determine
the free-running frequency fout, the lock range fL,
and the capture range fC.
R1
12 kW
10
C3
8
0.001 mF
2
Input
+ C2
– 10 mF
NE565
7
Demodulated
output
6
Reference
output
4
3
VCO output
5
9
C1
1
0.01 mF
–V = –10 V
Fig. 11.42
For Problem 3
Solution:
f out »
1.2 Hz
4 R1C1
(11.47)
12
.
Hz
4 (12 s 103) ( 0.01 s 106)
= 2.5 kHz
=
fL = ±
=
8 f out
Hz
V
(11.48)
8 ( 2.5 s 103)
= ± 1 kHz
20
fC = ±
1/ 2
fL
3
!
(2Q ) (3.6) (10 ) ( C2 ) "
Hz
(11.49)
where C2 is in farads.
fC = ±
=
1/ 2
(10) 3
6 !
3
( 2Q ) ( 3.6 s 10 ) (10 s 10 ) !
"
± 66.49 Hz
28
Linear Integrated Circuits
fout, fL and fC are illustrated in Fig. 11.43.
Lock range
Lock range fL
Capture
range
Capture range
fC
fC
fOUT
1.5 k
2.433 k 2.5 k 2.566 k
Frequency (Hz)
Fig. 11.43
1.0
kHz
3.5 k
Fig. 11.45
Solution for Problem 3
Problem 4. In the circuit in Fig. 11.43, determine
the free running frequency fout, the lock range fL
and the capture range fC.
Solution:
f out »
1.2
4 R1C1
=±
fC = ±
R1 = 5 k W, VT = 26 mV, ISO = 10–10 A
Find the output voltage vo corresponding to the
input voltage vS = (i) 1 mV, (ii) 10 mV ; (iii) 100 mV
and (iv) 1 V.
C
iC
+
vs > 0
–
8 f out
Hz
V
8 s 3 s 103
= ± 2 kHz
12
( 2Q )
1/ 2
= ± 106 Hz
fout, fL and fC are illustrated in Fig. 11.44.
+6 V
+
C3
10
Input
R1
C2
–
5 mF
Vj1
=0
6
LM 565
Demad
o/p
Ref o/p
9
C1
1
0.01 mF
–6 V
Fig. 11.44
For Problem 4
5
VCO
output
+
vo
–
Solution:
v o = –VT ln
vs
I so R1
(11.50)
= – (26 ´ 10–3) ln
(ii) vo = –(26 ´ 10–3) ln
4¢
3
+
For Problem 5
0.001 mF
7
E
VCB – B– VBE
–
(i) vo = –(26 ´ 10–3) ln
0.001
2
T
+
Fig. 11.46
(2) (10) 3
!
( 3.6) (103) (5) (106) !"
R1
10 k
Solution for Problem 4
+
= 3 kHz
5.0 kHz
Problem 5. The log amplifier shown in Fig. 11.46
has the following circuit parameters.
12
.
=
(4) (10 s 103) (.01 s 106)
fL = ±
2.894 3.106 kHz
kHz
3 kHz
Frequency, Hz
10
10
vs
1010 s 5 s 103
103
= –0.197 V
s 5 s 103
10
103
= –0.2575 V
s 5 s 103
10
(iii) vo = –(26 ´ 10–3) ln
102
= –0.3174 V
10 s 5 s 103
(iv) vo = – (26 ´ 10–3) ln
1
= – 0.377 V
1010 s 5 s 103
10
Thus, the output voltage is a compressed version
of the wide input voltage.
Supplementary Problems
29
Problem 6. If you have at your disposal a
logarithmic amplifier and an exponential amplifier,
devise a circuit that will produce the quotient of two
members.
Problem 8. Show that the op-amp circuit of Fig. 11.49
uses the analog multiplier to perform division.
Solution: x/y = eIn x–In y. Thus, if the divisor and the
dividend are each fed to a logarithmic amplifier, the
two resulting signals are fed to a difference amplifier,
and the difference is fed to an exponential amplifier,
the result is identical to division. This is shown in
Fig. 11.47.
vovss
vs
v
= P =
vR
vR
R
Solution:
Since
i S = iP
vo = –
and
vd = 0
vs
vss
(11.52)
Logarithmic amplifier
V1
–k(ln V1)
R
R
–
V1
V2
C(ln V1 – ln V2)
+
V2
–k(ln V2)
Exponential amplifier
R
R1
Logarithmic amplifier
Fig. 11.47
For Problem 6
Problem 7. The analog multiplier of Fig. 11.48 has
the characteristic vP = v1 v2. Determine the output vo
for the op-amp circuit.
Solution:
Since
i S = iP
vo =
iS
vs
vs
Fig. 11.49
X
iP
–
v1
v2
+
vs
+
–
Fig. 11.48
vP
+
vo
–
For Problem 7
X
–
(11.51)
R vP
R
R
R
+
This is shown in Fig. 11.77
iS
vSS
iP
and vd = 0
vp
v1v2
vs
v2
=–
=
=– 0
R
R
R
R
\
This is shown in Fig. 11.49
For Problem 8
vo
30
Linear Integrated Circuits
CHAPTER 13
Solution:
Problem 1. For the Wien bridge oscillator circuit
of Fig. 13.51, determine (a) the oscillation frequency,
and (b) the value of Rf required.
R = 15 kW, C = 0.02 mF, and Ri = 10 kW
R =
The largest value of f0 requires the smallest value
of R and the smallest value of f0 requires the largest
value of R.
Solution:
(a) f0 =
1
1
=
Hz
2Q RC
2Q (15 k8) ( 0.02 NF)
= 530.5 Hz
(b) To sachieve a gain of 3, the value of Rf must
be
R f = 2Ri = 2(10 kW) = 20 kW
Rf
10 kW
–
vo
+
1
2 Q f 0C
Rmin =
1
= 15.915 kW
2Q (1 kHz) ( 0.01 NF)
Rmax =
1
= 159.15 kW
2Q (100 Hz) (0.01 NF)
Thus, the resistances must be adjustable from
15.915 kW to 159.15 kW in order to tune the oscillator
over the required range. It is assumed that the
resistances are aligned so that their values are equal.
Problem 3. Design a phase-shift oscillator to
produce oscillations at 1 kHz. The capacitor values
are selected as C = 0.01 mF.
15 kW
Rf
0.02 mF
0.01 mF
0.01 mF
0.01 mF 12 kW
–
0.02 mF
15 kW
vo
+
R
Fig. 13.51
R
Rc
For Problem 2
Problem 2. A variable Wien bridge oscillator of a
form similar to that of Fig. 13.52 is to be designed to
produce an output sinusoid that can be adjusted from
100 Hz to 1 kHz. The two capacitor values are
selected as C = 0.0 mF. Determine the required range
in the resistances.
C
For Problem 4
Solution:
R =
1
=
2 Q 6 f 0C
2Q
1
= 6497 W
6 (1 kHz) (0.01 NF)
The value of R f is then determined as
R f = 29R = 29 ´ 6497 = 188.4 kW
R2
R
Fig. 13.53
None of the resistance values are standard so
some adjustments will be required.
+
–
Problem 4. What is the frequency of the output
signal in Fig. 13.54?
C
R
C
R1
Solution:
The feedback fraction is
b=
Fig. 13.52
For Problem 3
18 k8
= 0.9
20 k8
Supplementary Problems
= 0.693(1 kW + 3 kW)(0.02 mF)
= 55.44 ms
(b) The low-state time interval is
1 kW
+15 V
2
7
–
318
3
+
4
0.1 mF
6
TL = 0.693 RB C = 0.693 (3 kW)(0.02 mF)
= 41.58 ms
vout
(c) The period is
–15 V
T = TH + TL = 55.44 mS + 41.58 ms
= 97.02 ms
2 kW
18 kW
Fig. 13.54
(d) The frequency is
f=
For Problem 5
1 C
T = 2RC ln
= 2 (1 kW)(0.1 mF)
1 C
ln
1 0.9
= 589 ms
1 0.9
1
1
=
= 10.31 kHz
T
97.02 s 10 6
(e) The duty cycle is
D =
54.44 Ns
TH
´ 100% =
´ 100% = 57.14%
T
97.02 Ns
Problem 6. In a Wien bridge oscillator C1 = C2 =
C. The minimum and maximum values of C1 are 90 pF
and 900 pF respectively. R1 = R2 = R = 100 kW.
The frequency is
f=
31
1
= 1.7 kHz
589 Ns
Problem 5. Consider the 555 astable circuit of
Fig. 13.55. Determine (a) high state time interval,
(b) low-state time interval (c) period (d) frequency,
and (e) duty cycle.
R A = 1 kW, RB = 3 kW, and C = 0.02 mF
Solution:
(a) Determine the range of the operating
frequency of the oscillator.
(b) Determine the value of R3, if R4 = 10 kW, so
that oscillations can be maintained.
Solution:
(a) f0 =
(a) The high-state time interval is
T H = 0.693 (RA + RB)C
1
2Q RC
f0(max) =
1
2Q RC min
+5 V
=
1 kW
RA
8
f0(min) =
4
7
3 kW
RB
555
3
Output
=
6
2
1
0.02 mF
Fig. 13.55
For Problem 6
1
2Q RC max
1
= 1.768 kHz
2Q 100 k8 s 900 s 1012
The range of f0 is from 1.768 kHz to 17.68 kHz.
5
C
0.01 mF
1
= 17.68 kHz
2Q s 100 k8 s 90 s 1012
(b)
R3
£ 1 , R3 = 2R4 = 2 ´ 10 kW = 20 kW
3
R 3 R4
32
Linear Integrated Circuits
Wien bridge
f0 =
R1
=
R2
C1
A
R3
1
2Q RC 6
1
2Q s 200 s 103 100 s 10 12 6
= 3.248 kHz
Problem 9. Design a phase-shift oscillator to
oscillate at 100 Hz.
R4
C2
Solution:
Let
C = 0.1 mF
Fig. 13.56
For Problem 6
Problem 7. In a Wien bridge oscillator, if the value
of R is 100 kW, and the frequency of oscillation is
10 kHz, find value of capacitor C.
f0 =
1
2Q RC 6
R =
1
2Q f 0 C 6
=
Solution:
1
= 6.49 kW
2Q (100) (107) 6
Use
R = 6.5 kW
To prevent loading of the amplifier by the RC
network, R1 ³ 10 R
f0 =
1
2Q RC
C =
1
2Q R f 0
C =
1
2Q s 100 k8 s 10 kHz
\
R 1 = 65 kW
R f = 29 R1
R f = 29 ´ 65 kW = 1885 kW
Since
= 159 pF
Problem 8. In an RC phase-shift oscillator if R1 =
R2 = R3 = R = 20 kW, and C1 = C2 = C3 = 100 pF, find
the frequency of the oscillator.
Problem 10. For the 555 monostable circuit of
Fig. 13.60, determine the pulse width.
+5 V
Solution:
2 kW
Rf
R1
8
Input
Amplifier
4
2
7
5
6
R
15 kW
C
0.22 mF
0.01 mF
1885 kW
–
65 kW
vo
+
3
Rcomp
0.01 mF
Output
0.1
C
vf
C
R
6.5 kW
Fig. 13.57
0.1
R
6.5 kW
0.1
C
R
6.5 kW
Fig. 13.60
Feedback
network
RC phase-shift oscillator
Solution:
For Problem 12
In the given circuit
R = 15 kW and C = 0.22 mF
Supplementary Problems
+5.5 V
+VCC
Ri
Ci
8
4
R
3
R2
4.7 kW
555
THRESH
OUT
C
TRIG
Output
vo(t)
Fig. 13.61
VCC
DISCH
6
5
1
RESET
vC(t)
555
0.01 mF
R1
2.2 kW
7
2
Trigger
input
33
CONT
GND
Cext
0.022 mF
C1
0.01 mF
For Problem 13
T P = 1.1RC
= 1.1(15 ´ 103) (0.22 ´ 10–6)
= 0.003635
= 3.63 ms
Problem 11. Design a monostable 555 timer circuit
of the form shown in Fig. 13.61 to produce an output
pulse 1ms wide.
Solution:
T P = 1ms = 1.1RC
RC = 9.1 ´ 10–4
There are many choices of R and C that would
satisfy the constraint. In the range of reasonable
choices select:
C = 0.01 mF, R = 91 kW
If the trigger circuit shown on the left-hand side
of Fig. 13.61 is used, the values of Ci and Ri should
selected. These values are not critical, but the product
R iC i should typically be much smaller than T P .
Reasonable choices might be
C i = 0.001 mF and Ri = 10 kW.
Problem 12. A 555 timer configured to run in the
astable mode is shown in Fig. 13.64. Determine the
frequency of the output and the duty cycle.
Fig. 13.63
For Problem 15
Solution:
fr =
=
1.44
( R1 2 R2) Cext
144
.
(2.2 k8 9.4 k8 ( 0.022 NF)
= 5.64 kHz
Duty cycle =
=
R1 R2 R1 2 R2 2.2
2.2
100%
k8 4.7 k8 100% = 59.5%
k8 9.4 k8 Problem 13. Give the pin configuration of CD 4046
phase-locked loop IC. Explain briefly.
Solution: The tendency to lose lock is a major
weakness of the exclusive OR type phase detector.
Within the CD 4046 is a second phase detector. It
shares the input and feedback signals with the f1
(exclusive OR) detector, but has its own fII, output
(Pin 13). It consists of digital logic with flip-flops for
memory and a three-state output driver.
34
Linear Integrated Circuits
CHAPTER 14
Problem 1. Illustrate the frequency response of a
(a) practical low-pass filter (b) practical high-pass
filter.
Solution:
See Fig. 14.58
Gain
Stop band
Pass band
–3 dB
The curves of Fig. 14.59 may be readily used. We
interpret the cut-off frequency to be fc = 800 Hz. The
actual frequency f = 2 kHz corresponds to a normalized frequency f/fc = 2000/800 = 2.5. At an abscissa of
2.5 on the normalized frequency scale, we drop down
to determine the response curves that will achieve
the required attenuation. The response of a two-pole
function is down by only about 16 dB at this frequency, so it is inadequate. However, a three-pole
response is down by about 23 dB, so it more than
meets the specifications. Hence the minimum number of poles required in the Butterworth filter is three.
Note:
f–3 dB
Gain
f
Stop band
Pass band
–3 dB
f–3 dB
f
Fig. 14.58 Frequency response (a) low-pass
filter and (b) high-pass filter
Problem 2. A low-pass filter is desired for a given
application. The specifications are as follows:
(1) Relative attenuation £ 3 dB for f £ 800 Hz
(2) Relative attenuation ³ 23 dB for f ³ 2 kHz
Specify the minimum number of poles for a
Butterworth filter that will satisfy the requirements.
Solution: Requirement (1) specifies passband in
which the response drops no more than 3 dB.
Requirement (2) specifics a stopband in which the
response is required to be at or below a certain level.
The region between (1) and (2) can be interpreted as a
transition band. The specifications are not very
demanding since a very wide transition band is
provided.
(1) The relative amplitude response curve for any
three-pole Butterworth filter will meet the
specifications as given for any frequencies having
the same ratios as those given. For example, if the
frequency of specification (1) had been 5 kHz and
the frequency of specification (2) had been
12.5 kHz, a three-pole Butterworth filter would
again be the correct solution, since 12.5 kHz/5 kHz
= 2.5 is the same normalized frequency as
determined in the problem.
(2) The utility of the normalized frequency concept is
that the various results apply to any frequency
combination having the same relative ratios.
Problem 3. A high-pass filter is required for a given
application. The specifications are as follows:
(1) Relative attenuation
(2) Relative attenuation
£ 3 dB for f ³ 500 Hz
³ 46 dB for f £ 12.5 Hz
Specify the minimum number of poles for a
Butterworth filter that will satisfy the requirements.
Solution: The manner in which the specifications
are given suggests that the 3 dB cut-off frequency
can be established at 500 Hz. For a high-pass filter
the frequency of 125 Hz corresponds to 500 Hz
inverted normalized frequency of fc/f = 500/125 = 4.
At a normalized frequency of 4, the smallest number
of poles satisfying the specification is four. The
attenuation at this point is slightly greater than
48 dB, so the specification is met with reserve.
Supplementary Problems
0
–10
1
–20
–23
–30
4
–40
Gain (dB)
–20 dB/decade
2
3
–40
5
–50
6
–60
–60
–70
–80
–80
–100
–90
–120
–100
–110
–120
Fig. 14.59
1
Roll off rate comparison
1
2 2.5 3 4 5 6 7 8 910
f/f0
20
30 40
60 80100
50 70
35
36
Linear Integrated Circuits
CHAPTER 15
Problem 1. Design a voltage regulator using LM723
for 5 V, 100 mA power supply. Given Vin = 10 V.
Assume Vsense = 0.65 V.
Solution: The reference voltage V REF must be
reduced to 5 V for the non-inverting input of the
error amplifier by means of a voltage divider.
Assume I0 = 1 mA
R1 =
VR Vo
7.15 V 5 V
=
Io
1 mA
= 2.15 kW (use 2.2 kW)
R2 =
5V
Vo
=
= 5 kW (use 5.1 kW)
1 mA
Io
R 3 = R1 || R2 = 2.15 kW || 5 kW = 1.5 kW
R CL =
0.65 V
Rsense
=
= 6.5 W (use 6.8 W)
Im
100 mA
PD (max) = Vin (I0 + IQ) = 10 V (100 mA + 3 mA )
= 1.03 W
from 1 to 40 V. The mA 78S40 draws a maximum
quiescent current of 2.5 mA at Vin = 5 V and 3.5 mA, at
Vin = 40 V, with typical values being 1.8 mA and
2.3 mA respectively. The regulator is supplied in a 16pin DIP that can dissipate 1.5 W in the plastic version
and 1 W in the hermetically sealed version. The device
is supplied in a commercial version with an operating
temperature of 0 to 70°C and a military version with a
temperature range of – 55 to 125°C. The device can
supply up to 1.5 A without external transistors.
The m A 78S40 consists of a temperature
compensated voltage reference, a duty-cycle
controllable oscillator with an active current limit
circuit, high-gain comparator, high-current highvoltage output switch, a power switching diode and
an uncommitted op-amp. The block diagram and the
pin configuration of the IC are given in Fig. 15.50.
Noninv. Inv.
input input
9
10
Ipk
Driver Switch
sense collector collector
14
15
16
Timing
capacitor Vcc
12
13
Ipk
CT
Oscillator
Vin
V
+
VC
VREF
R1
VO
CL
R3
V–
1.25 V
reference
INV
Comp.
100 pF
C1
Fig. 15.49
Q2
Q1
Comp.
Vo
CS
R2
S Q
RCL
723
NI
Cref
Gnd.
11
8
Ref
output
R
170
–
Op
Amp.
+
D1
7
6
5
4
3
Inv. Noninv.
Vcc Output Switch
input input Op Amp.
emitter
2
Diode
anode
1
Diode
cathode
for Problem 1
Problem 2. Explain in detail the operation of
switching voltage regulator IC-mA 78S40.
Solution: m A 78S40 is a universal switching
regulator subsystem. It is a versatile pulse-width
modulated switching regulator capable of line and
load voltage regulation of 80 dB (0.01%). It has an
input voltage range from 2.5 to 40 V and can control
output voltage limited by the external components
used. As a step-down or step-up regulator with no
external switching transistors, it can supply voltages
Diode cathode 1
16 Switch collector
Diode anode 2
15 Driver collector
14 Ipk sense
Switch emitter 3
13 Vcc
Op amp output 4
Vcc Op Amp 5
12 Timing capacitor
11 Ground
Comparator
Inv. input
9 Comparator
Non-inv. input
Op Non-inv. 6
Amp Inv. input 7
10
Reference 8
(Top view)
Fig. 15.50 mA 78S40 universal switching
regulator (a) block diagram, and (b) pin
configuration
Supplementary Problems
The initial switching frequency is set by the timing
capacitor CT, connected between pins 12 and ground
pin 11. The initial duty cycle is 6 : 1. The switching
frequency and duty cycle can be modified by the
current limit circuitry, I pk sense pin 14, and the
comparator pins 9 and 10. The oscillator can be set
Vin
25 V
100
10
11
between 100 Hz and 100 kHz. Ipk, pin 14, is used to
vary the duty cycle and thus ton in the regulator. The
lower limit of tON or tOFF is 10 ms.
The output transistors can block 40 volts and
supply up to 1.5 A. Q2 is the driver for Q1 × Q1 and Q2
can be connected as a darlington pair or Q2 can be
RSC
0.33
470
pF
CT
9
12
13
VCC
Ipk
CT
Oscillator
8
7
14
15
S Q
Q4
R
170
–
Op
Amp.
+
6
D1
5
4
3
2
1
1N5822
L
R2
R1
16
Q1
Comp.
1.25 V
reference
Vout
–220 mH 5.0 V/500 mA
3.6 K
1.2 K
470
Fig. 15.51
220 V dc
Transistor
switching
array
Load
Transistor
drive
Reference
voltage
Fig. 15.52
+
C0
Step-down voltage regulator with mA 78S40
Line
rectification
filtering an
isolation or
battery
37
Pulse width
modulator
Negative feedback
Generalized block diagram of a buck converter
38
Linear Integrated Circuits
Table 15.1
Datasheet of m A78S40 (Fairchild Semiconductors)
Calculation
ton
toff
Step-Down
Ipk(switch)
RSC
L
CO
Vout VF Vin(min)
Vin(min) Vsat
Vout VF
Vin(min) Vsat
1
tmin
1
tmin
1
tmin
45
´ 10–5 ´ tON
45
´ 10–5 ´ tON
45
´ 10–5 ´ tON
2Iout(max)
t t
2I out(max) on off t t
2I out on off 0.33
I pk(switch)
0.33
I pk (switch)
0.33
I pk (switch)
Vin(min) Vsat I
t on(max)
pk (switch) Vin(min) Vsat I
t on(max)
pk (switch) (V0 + V d)/I pk
´ toff
I pk (switch) ( ton toff )
8Vripple( pp )
used with an external resistor to provide increased
base drive to Q1 as is necessary in the step-up supply.
QCE (sat), of Q1 is 1.1 V typically and 1.3 V maximum
at IC = 1 A. The b of Q1 is 70 with IC = 1 A and VCE =
5 V, so for VCE = 1 V at IC = 1 A, a value of b (Q1) = 20
may be used for calculations.
The AND gate output is connected to the flip-flop
input to turn Q1 off when V0 > VR. It is part of the
regulator circuitry. The diode will block 40 V and drop
1.5 V in the forward bias case with forward current IF
= 1 A. The typical VD is 1.25 V at 1 A. The reference
voltage is temperature compensated and is equal to
1.25 V typically.
The comparator is a high-gain amplifier used as
an error amplifier for regulation. The uncommitted
op-amp is used in inverting configuration or used
as a driver for an auxiliary series-pass regulator.
Problem 3. Draw the generalized block diagram
of a buck converter and illustrate the charge and
discharge cycles.
Solution:
Inverting
Vout VF
Vin(min) Vsat Vout
(ton + toff)max
CT
Step-Up
See Figs 15.51 through 15.53.
Problem 4. How will you read the data sheet
(Table 15.1) of mA 78S40? Design a step-down voltage
regulator using mA 78S40 given that Input voltage =
=
toff
I out ton
Vripple
=
toff
I out ton
Vripple
Vload
0V
I
On
Ein
–
+
+
PWM
–
+
–
+
Off
Load
–
(a) Charge cycle
Vload
0V
Off
–
+
+
PWM
–
+
On
Load
–
(b) Discharge cycle
Fig. 15.53 (a) Charge, and
cycles of a buck converter
(b)
discharge
12 V dc ; Output voltage = 5 V ; Output current
maximum 0.5 A. Maximum output ripple is 2%.
Solution: From Table 15.1 for step-down mode: The
voltage drop across the diode VD = 1.25 V.
The output saturation voltage ; VS = 1.1 V, VREF =
1.245 V; IBias (comparator) = 35 mA and ID (divider
current) through R1 – R2 = 0.1 mA.
39
Supplementary Problems
Ipeak = 2 Iout(max) = 2 ´ 0.5 ´ 10–3 = 1 A
0.33
0.33
=
=
1
I peak
Short-circuit resistance, RSC =
0.33
C0 =
Next, calculate the values of resistors used in the
sampling network. The non inverting terminal is
connected to the reference voltage. Therefore,
W
Vo VD
5 125
.
Ton
=
=
= 1.06
Vin Vout VS
12 11
. 0.5
Toff
1245
.
s 103
R2
´ Vout; 1.2 =
R1 R2
R1 (12.45 s 103 )
V R2 =
1
= 50 ms
20 s 103
R 1 = 36 kW
The efficiency of the switching is given by
Ton + Toff , but Ton = 1.06 Toff
Toff = 24.2 ms and Ton = 25.8 ms
C T = (45 ´ 10–3) Toff
= (45 ´ 10–5) (24.2 ´ 10–6) = 0.0109 mF
The load inductor,
L =
1245
.
= 12.45 kW
01
. s 103
R2 =
The switching regulator has maximum efficiency
when operating at 20 kHz
TD =
I pk ( Ton Toff )
50 s 106
=
= 125 mF
8 Vripple
8 Vripple
h =
hÿ % =
Vout VD
5 1.25
´ Toff =
´ 24.2 ´ 10–6
I peak
1
Vin Vs Vo
Vout
s
Vin
Vin Vout
12 11
. 125
.
s 5
´ 100 = 81%
12
5 125
.
Problem 5. Illustrate the use of the CA723CT IC
as switching regulator:
= 151.25 mH
The value of output capacitor,
Solution: See Fig. 15.54
VIN = 25 V ± 20%
R9
3.3 k
R10
2.2 MW
R1
5.6 k
R2
4.7 k
Q1
BEL 6109
4
3
+
2
–
8
6
CA 723CT
5
9
1
R5
10 W
10
D
2N 1482
R8
0.6 W, 1W
Q2
BC 148
C2
22 KPF
L = 4 mH
7
C4
330 PF
R6
0.75 W R7
0.6 W
C1
47 KPF
C3
250 mF
12 V
Vo
5 V, 1 A
R3
1.8 k
100 W
R4
3.3 k
Fig. 15.54
Circuit of a switching regulator using CA723CT
40
Linear Integrated Circuits
CHAPTER 16
Problem 1. Discuss the need for an isolation
transformer. How does it operate?
Solution: Isolation transformers provide dc isolation between input and output for the protection
of human life of sensitive equipment in those applications where hazardous power-line leakage or
high-voltage transients are possible. The principal
areas of applications for isolation amplifiers are in
medical instrumentation, power plant instrumentation, industrial processing and automated testing.
In some ways, the isolation amplifier can be viewed
as an elaborate op-amp instrumentation amplifier.
The difference is that an isolation amplifier has an
input stage, an output stage and a power-supply
section that are all electrically isolated from each
other. The transformer-coupled device is the one most
commonly used. The circuit is in IC form, but the
miniature multiple-winding, toroid transformer is not
fully integrated.
As shown in Fig. 16.37, there are three isolated
),
independent grounds for the input signal (
the output signal (
) and the power supply (
).
An external dc supply voltage, VDC is applied to
the oscillator. The oscillator converts the dc power
to ac at a relatively high frequency. The ac output of
the oscillator is coupled by the transformer to the
input power supply (rectifiers and filters) and to the
output power supply (rectifiers and filters) where it
is rectified and filtered to produce dual-polarity dc
voltages (+ ve and – ve) for the input and output
stages.
The oscillator output is also coupled to the
modulator where it is combined with the input signal
from the input op-amp A1. The modulator varies the
amplitude of the relatively high oscillator frequency
with the lower-frequency input signal. To couple the
lower-frequency input signal without modulation
would require a prohibitively large transformer.
The modulated signal is coupled to the
demodulator in the output stage. The demodulator
recovers the original input signal from the higher
oscillator frequency. The demodulated input signal
is then applied to output op-amp, A2, which is part of
a feedback loop that forces the signal at the inverting
input of A1 to equal the original input signal at the
non-inverting input.
The isolation function is an unseen process. You
apply a dc voltage, put a signal in and you get an
amplified signal out. A representative device is the
Burr–Brown 3656KG. It has a few more input and
output pins to provide for gain adjustments, offset
adjustments, isolated dc voltage outputs, and other
functions.
Problem 2. Explain the operation of an ECG system
with the help of a block diagram.
Solution: The human heart produces an electrical
signal that can be picked up by electrodes in contact
with the skin. When the heart signal is displayed on
a chart recorder, or on a video monitor, it is called
Input stage
Output stage
Input
demodulator
Oscillator
Modulator
Output
demodulator
–
–
A1
+
Output
A2
+
Input
Output
Rectifiers
and filters
Vin
Rectifiers
and filters
Power
Fig. 16.37
+
VDC
–
A transformer coupled isolation amplifier
Power
41
Supplementary Problems
an electrocardiograph (ECG). Typically, the heart
signal picked up by the electrode is about 1 mV and
has significant frequency components, from less than
1 Hz to about 100 Hz.
As indicated in the block diagram in Fig. 16.38, an
ECG system has at least three electrodes—a rightarm electrode (RA), a left-arm electrode (LA), and a
right-leg electrode (RL) that is the common terminal.
The isolation amplifier provides for differential
inputs from the electrodes, provides a high CMR to
eliminate the relatively high common-mode noise
voltages associated with heart signals and provides
electrical isolation for protection of the patient. The
low-pass filter rejects frequencies above those
contained in the heart signal. The post-amplifier
Solution:
The voltage gain of the input stage is
A v1 =
RF1
22 k8
+1=
+ 1 = 10 + 1 = 11
2.2 k8
Ri1
The voltage gain of the output stage is
A v2 =
RF2
47 k8
+1=
+1
10 k8
R i2
= 4.7 + 1 = 5.7
The total voltage gain of the isolation amplifier is
Av (tot) = Av1 Av2 = (11) (5.7)
= 62.7
Note: The triangle with a split down the middle is one way
of representing an isolation amplifier by indicating that the
input voltages are separated by transformer coupling.
Power supply
Video monitor
RA
LA
Isolation
amplifier
Low-pass
filter
Postamplifier
RL
Electrodes
Amplifier circuit board
Chart recorder
Fig. 16.38
Block diagram of an ECG system
provides most of the amplification in the system and
drives a video and/or a chart recorder.
The inputs from electrode sensors are connected
to the amplifiers through a shielded cable to prevent
noise pick-up. The input differential signal is amplified
by the fixed gain of the 3656KG isolation amplifier.
The low-pass filter is an active filter. The postamplifier is an inverting amplifier with an adjustable
voltage gain. The inverting input also serves as a
summing point for the signal voltage. A dc voltage is
used for adding an adjustable dc level to the output
for adjusting the vertical position of the display.
Problem 3. Determine the total voltage gain of the
3656 KG isolation amplifier in Fig. 16.39.
Ri2
10 kW
Rf2
10 kW
Vin
7
Rf1
10
22 kW
14
6
Ri1
2.2 kW
Input
47 kW
Output
15
16
12
0.47 mF
19
20
0.47
mF
0.47
mF
+15 V
Fig. 16.39
For Problem 3
Vout
42
Linear Integrated Circuits
Problem 4. Calculate the differential voltage gain
of the instrumentation amplifier in Fig. 16.40 with
the following resistance values.
(–)
=
2 R 3
R 1
R2
= 141
Input
–
R1
Gain R3
R 7
" R 5
8) (15 k8)
8 1!" (3.3 k8) !"
R6
–
1 ! (2 ) (33 k
(2.2 k )
R4
A1
Solution: R3 = 33 kW, R1 = 2.2 kW, R5 = 3.3 kW and
R7 = 15 kW.
Av =
+
A3
+
E0
–
R5
A2
+
(+)
AV =
R7
CMR
ADJ
LM 2 R3 + 1OP LM R6 OP
N R1 Q N R4 Q
Provided that: R2 = R3
R4 = R5
R6 = R7
Fig. 16.40
amplifier
For
Example
4—instrumentation