Spartan-II™ 200 PCI
Development Board
User’s Guide
Version 1.0
April 2002
PN# DS-MANUAL-SPARTANII-200PCI
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Table of Contents
1
OVERVIEW ....................................................................................................................1
2
THE SPARTAN-II DEVELOPMENT BOARD ...................................................................1
3
SPARTAN-II DEVELOPMENT BOARD FEATURES ........................................................2
3.1
SDRAM M EMORY ....................................................................................................2
3.2
CLOCK G ENERATION .................................................................................................4
3.3
R ESET C IRCUIT ........................................................................................................4
3.4
USER 7-S EGMENT D ISPLAY........................................................................................5
3.4.1
7-Segment Display Signal Description..................................................................5
3.5
USER LED...............................................................................................................6
3.6
USER PUSH B UTTON SWITCH (SW5) ...........................................................................6
3.6.1
User Push Button Switch Signal Assignment ........................................................6
3.7
PROGRAM SWITCH (SW2) .........................................................................................6
3.8
USER DIP SWITCH (SW4) .........................................................................................6
3.8.1
3.8.2
3.9
User DIP Switch Interface ...................................................................................7
User DIP Switch Signal Assignments ...................................................................7
RS232 PORT...........................................................................................................7
3.9.1
3.9.2
3.10
RS232 Interface..................................................................................................7
RS232 Signal Descriptions ..................................................................................8
JTAG PORT ............................................................................................................8
3.10.1
3.10.2
3.10.3
3.10.4
3.11
JTAG Connector .............................................................................................8
JTAG Signal Descriptions ................................................................................8
JTAG Chain ...................................................................................................9
JTAG Chain Jumper Settings ..........................................................................9
SLAVE PARALLEL /SLAVE SERIAL PORT....................................................................... 10
3.11.1
Slave Parallel ............................................................................................... 10
3.12
SLAVE SERIAL PORT ............................................................................................... 11
3.13
BANK I/O VOLTAGE ................................................................................................. 11
3.13.1
Bank I/O Voltage Jumper Settings ................................................................. 11
3.14
ISP PROM ........................................................................................................... 12
3.15
PCI INTERFACE ...................................................................................................... 12
3.15.1
3.16
VOLTAGE R EGULATORS ........................................................................................... 14
3.16.1
3.17
PCI Interface Signal Descriptions ................................................................... 12
Voltage Regulators Jumper Settings .............................................................. 14
SPARTAN-II CONFIGURATION M ODE S ELECT ............................................................... 14
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i
3.18
P160 EXPANSION MODULE ...................................................................................... 15
3.18.1
4
Expansion Module Signal Assignments .......................................................... 15
DESIGN DOWNLOAD.................................................................................................. 18
4.1
4.1.1
4.1.2
JTAG INTERFACE ................................................................................................... 18
Configuring the Spartan-II FPGA ....................................................................... 18
Programming the XC18V02 ISP PROM.............................................................. 18
4.2
SLAVE SERIAL INTERFACE ........................................................................................ 19
4.3
SLAVE PARALLEL .................................................................................................... 19
REVISION HISTORY............................................................................................................ 20
APPENDIX A - SPARTAN-II 200 PCI BOARD SCHEMATICS ............................................... 21
April 1, 2002
ii
Figures
FIGURE 1 – S PARTAN-II DEVELOPMENT B OARD .............................................................................1
FIGURE 2 - S PARTAN-II 200 PCI DEVELOPMENT B OARD BLOCK D IAGRAM ........................................2
FIGURE 3 – SDRAM INTERFACE.................................................................................................3
FIGURE 4 – R ESET C IRCUIT .......................................................................................................5
FIGURE 5 - 7-S EGMENT LED DISPLAY INTERFACE .........................................................................5
FIGURE 6 – USER DIP SWITCH INTERFACE...................................................................................7
FIGURE 7 – RS232 INTERFACE ..................................................................................................8
FIGURE 8 – JTAG CONNECTOR..................................................................................................8
FIGURE 9 – S PARTAN-II DEVELOPMENT B OARD JTAG CHAIN..........................................................9
FIGURE 10 – SLAVE PARALLEL /SLAVE SERIAL CONNECTOR .......................................................... 10
FIGURE 11 – SLAVE PARALLEL MODE C ONFIGURATION ................................................................ 10
FIGURE 12 – SLAVE SERIAL MODE C ONFIGURATION .................................................................... 11
FIGURE 13 – ISP PROM INTERFACE ........................................................................................ 12
FIGURE 14 – S PARTAN-II DEVELOPMENT BOARD VOLTAGE R EGULATORS ....................................... 14
FIGURE 15 – D OWNLOAD SETUP............................................................................................... 18
April 1, 2002
iii
Tables
TABLE 1 – SDRAM INTERFACE S IGNAL DESCRIPTION ....................................................................3
TABLE 2 - S PARTAN-II DEVELOPMENT BOARD MASTER CLOCKS ......................................................4
TABLE 3 - 7-S EGMENT D ISPLAY SIGNAL D ESCRIPTIONS ..................................................................6
TABLE 4 - USER P USH BUTTON SWITCH S IGNAL ASSIGNMENTS .......................................................6
TABLE 5 - USER DIP SWITCH S IGNAL ASSIGNMENTS ......................................................................7
TABLE 6 - RS232 S IGNAL D ESCRIPTIONS .....................................................................................8
TABLE 7 - JTAG SIGNAL D ESCRIPTIONS ......................................................................................9
TABLE 8 - JTAG CHAIN J UMPER S ETTINGS ..................................................................................9
TABLE 9 - BANK I/O VOLTAGE J UMPER S ETTINGS ........................................................................ 11
TABLE 10 – PCI INTERFACE S IGNAL D ESCRIPTIONS ..................................................................... 12
TABLE 11 - VOLTAGE R EGULATORS J UMPER S ETTINGS ................................................................ 14
TABLE 12 - S PARTAN-II CONFIGURATION M ODE S ELECT............................................................... 15
TABLE 13 – JX1 USER I/O CONNECTOR .................................................................................... 16
TABLE 14 – JX2 USER I/O CONNECTOR .................................................................................... 17
April 1, 2002
iv
1
Overview
The Spartan-II 200 PCI Development Kit provides a complete solution for developing designs and
applications based on the Xilinx Spartan-II FPGA family. The kit bundles an expandable SpartanII based system board with a power supply, user guide and reference designs. Also available
from Memec Design, optional P160 expansion modules enable further application specific
prototyping and testing. Xilinx ISE software and a JTAG cable are available as kit options.
The Spartan-II system board utilizes the 200,000 gate Xilinx Spartan-II device (XC2S2006FG456C) in the 456 fine-pitch ball grid array package. The high gate density and large number
of user I/Os allows complete system solutions to be implemented in the low cost FPGA. The
system board includes two clock sources, a 32-bit PCI edge connector, 8MB SDRAM memory, an
RS-232 port, LED displays, switches and additional user support circuits. The board supports the
Memec Design P160 expansion module standard, which allows application-specific expansion
modules to be easily added.
The Spartan-II FPGA family has the advanced features needed to fit the most demanding, high
volume applications. The Spartan-II 200 PCI Development Kit provides an excellent platform to
explore these features so that you can quickly and effectively meet your time-to-market
requirements.
2
The Spartan-II Development Board
The Spartan-II Development Board provides the FPGA, PCI edge connector, support circuits and
the P160 expansion slot for a complete system-level design. Figure 1 shows a picture of the
board and its features.
Figure 1 – Spartan-II Development Board
April 1, 2002
1
3
Spartan-II Development Board Features
User
Switches
User
LEDs
RS232
Port
80-Pin Connector
User
7-Segment
Display (2)
80-Pin Connector
A high-level block diagram of the Spartan-II 200 PCI development board is shown in Figure 2 followed
by a brief description of each sub-section.
P160 Module
ISP PROM
(XC18V02)
JTAG Port
Spartan-II FPGA
XC2S200
(FG456)
SlaveSerial/
Slave Parallel
SDRAM
2Mx32
Clock Generator
(100 & 24Mhz)
Reset
Circuit
32-bit
PCI Interface
2.5V
Regulator
3.3V
Regulator
Voltage
Regulators
Figure 2 - Spartan-II 200 PCI Development Board Block Diagram
3.1 SDRAM Memory
The Spartan-II 200 PCI development board provides 8MB of SDRAM memory. This memory is
implemented using the Toshiba TC59S6432CFT 2Mx32 SDRAM (or a compatible) device. A
high-level block diagram of the SDRAM interface is shown below followed by a table describing
the SDRAM memory interface signals.
April 1, 2002
2
OSC
100Mhz
Data[31:0]
clk_in
Addr[10:0]
BS[1:0]
reset
DQM[3:0]
CSn
Spartan-II
FPGA
RASn
2M x 32 SDRAM
(TC59S6432CFT)
CASn
WEn
CLKE
CLK
Figure 3 – SDRAM Interface
Table 1 – SDRAM Interface Signal Description
Signal Name
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
April 1, 2002
Description
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
FPGA Pin #
M18
L18
L20
J21
J22
K21
K22
L21
L22
M22
M19
T18
W22
R18
P18
V20
U19
U20
T19
P22
P21
R22
T21
U22
U21
V22
V21
SDRAM Pin #
25
26
27
60
61
62
63
64
65
66
24
2
4
5
7
8
10
11
13
74
76
77
79
80
82
83
85
3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
BS0
BS1
DQM0
DQM1
DQM2
DQM3
CSn
RASn
CASn
WEn
CLK
CKE
Data 16
Data 17
Data 18
Data 19
Data 20
Data 21
Data 22
Data 23
Data 24
Data 25
Data 26
Data 27
Data 28
Data 29
Data 30
Data 31
Bank Select 0
Bank Select 1
Write Mask
Write Mask
Write Mask
Write Mask
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Clock
Clock Enable
J20
J19
H19
G20
G19
F20
F19
E20
C22
D21
D22
E21
E22
F21
F22
G21
N20
M20
T20
N21
K19
H21
N19
P20
P19
R19
N18
N22
31
33
34
36
37
39
40
42
45
47
48
50
51
53
54
56
22
23
16
71
28
59
20
19
18
17
68
67
3.2 Clock Generation
The Spartan-II development board provides three master clock inputs to the Spartan-II FPGA.
The following table provides a brief description of these clock signals.
Table 2 - Spartan-II Development Board Master Clocks
Signal Name
CLK.CAN2
CLK.CAN1
User Clock
Spartan-II Pin #
Y11
W12
A11
Direction
Input
Input
Input
Description
On-board 100 MHz Oscillator
On-board 24 MHz Oscillator
User Clock Input via JP30
The Spartan-II development board provides two on-board oscillators running at 100Mhz
(CLK.CAN1) and 24Mhz (CLK.CAN2). The 100Mhz oscillator is enabled when the JP24 jumper is
open, while leaving the JP32 jumper open will enable the 24Mhz oscillator. In addition to these
oscillators, a jumper is provides (JP30) for a User supplied clock input to the FPGA.
JP30 is provided as an external clock input jumper, connecting to the global clock pin on A11 of
the FPGA. Pin 1 of JP30 connects to A11 and pin 2 of JP30 connects to ground. The PCI clock
from the PCI edge connector connects to the global clock pin on C11 of the FPGA.
3.3 Reset Circuit
The Spartan-II development board uses the TI TPS3125 voltage supervisory device to monitor
the Spartan-II FPGA core voltage (2.5V). This circuit asserts a reset signal (RESETn_FPGA, Pin
April 1, 2002
4
B10) to the Spartan-II device when the 2.5V core voltage falls below its minimum specifications
(V). The reset signal to the FPGA is a fixed 100ms active low pulse. In addition to monitoring the
core voltage, this circuit can be used to generate a reset pulse by activating the Master Reset
(MRn) signal to the TPS3125 device via the on-board push-button switch (SW3). The following
figure shows the reset circuit on the Spartan-II development board.
TPS3125
2.5V
VDD
FPGA_RESETn
RESETn
SW3
MRn
Figure 4 – Reset Circuit
3.4 User 7-Segment Display
The Spartan-II development board utilizes two common-cathode 7-segment LED displays that
can be used during the test and debugging phase of a design. The user can turn a given segment
on by driving the associated signal high. The following figure shows the user 7-segment display
interface to the Spartan-II FPGA.
DISPLAY.1F
DISPLAY.1G
DISPLAY.1E
DISPLAY.1D
A1
A2
DISPLAY.1C
DISPLAY.1B
DISPLAY.1A
F2
B2 F1
G1
G2
B1
DISPLAY.2F
DISPLAY.2G
E2
C1
C 2 E1
DISPLAY.2E
DISPLAY.2D
DISPLAY.2C
D2
D1
DISPLAY.2B
DISPLAY.2A
Figure 5 - 7-Segment LED Display Interface
3.4.1 7-Segment Display Signal Description
The following table shows the 7-Segment LED display pin descriptions.
April 1, 2002
5
Table 3 - 7-Segment Display Signal Descriptions
Signal Name
DISPLAY.1A
DISPLAY.1B
DISPLAY.1C
DISPLAY.1D
DISPLAY.1E
DISPLAY.1F
DISPLAY.1G
DISPLAY.2A
DISPLAY.2B
DISPLAY.2C
DISPLAY.2D
DISPLAY.2E
DISPLAY.2F
DISPLAY.2G
Spartan-II Pin #
E10
E9
E8
E6
E7
F11
E11
D6
C5
D5
C7
D7
C6
A8
Description
7-Segment LED Display1, Segment A
7-Segment LED Display1, Segment B
7-Segment LED Display1, Segment C
7-Segment LED Display1, Segment D
7-Segment LED Display1, Segment E
7-Segment LED Display1, Segment F
7-Segment LED Display1, Segment G
7-Segment LED Display2, Segment A
7-Segment LED Display2, Segment B
7-Segment LED Display2, Segment C
7-Segment LED Display2, Segment D
7-Segment LED Display2, Segment E
7-Segment LED Display2, Segment F
7-Segment LED Display2, Segment G
3.5 User LED
The Spartan-II development board provides a single user LED. Pin A10 of the Spartan-II FPGA is
used to drive this active low signal.
3.6
User Push Button Switch (SW5)
The Spartan-II development board design provides a user push button switch input to the
Spartan-II FPGA. The push button switch can be used to generate an active low signal.
3.6.1
User Push Button Switch Signal Assignment
The following table shows the pin assignment for the user push button switch.
Table 4 - User Push Button Switch Signal Assignments
Signal Name
PUSH.USER1
3.7
Spartan-II Pin #
B1
Description
User Push Button Switch Input 1 (SW5)
Program Switch (SW2)
The Spartan-II development board provides a push button switch for initiating the configuration of
the Spartan-II FPGA. This switch is used when the XC18V02 ISP PROM configures the SpartanII FPGA. After programming of the XC18V02 ISP PROM, this switch can assert the PROGn
signal. Upon activation of the PROGn signal, the XC18V02 ISP PROM initiates the configuration
of the Spartan-II FPGA.
3.8 User DIP Switch (SW4)
The Spartan-II development board provides 8 user switch inputs. These switches can be statically
set to a low or high logic level.
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6
3.8.1 User DIP Switch Interface
The following figure shows the user DIP Switch interface to the Spartan-II FPGA.
SW4
Switch
DIP8
DIP7
DIP6
DIP5
DIP4
DIP3
DIP2
DIP1
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
Figure 6 – User DIP Switch Interface
3.8.2 User DIP Switch Signal Assignments
The following table shows the user switch pin assignments.
Table 5 - User DIP Switch Signal Assignments
Signal Name
DIP8
DIP7
DIP6
DIP5
DIP4
DIP3
DIP2
DIP1
3.9
Spartan-II Pin #
E4
F3
E3
F5
G5
F4
C1
D2
Description
User Switch Input 8
User Switch Input 7
User Switch Input 6
User Switch Input 5
User Switch Input 4
User Switch Input 3
User Switch Input 2
User Switch Input 1
RS232 Port
The Spartan-II development board provides an RS232 port that can be driven by the Spartan-II
FPGA. A subset of the RS232 signals is used on the Spartan-II development board to implement
this interface (RD and TD signals).
3.9.1 RS232 Interface
The Spartan-II development board provides a DB-9 connection for a simple RS232 port. This
board utilizes the TI MAX3221 RS232 driver for driving the RD and TD signals. The user provides
the RS232 UART code, which resides in the Spartan-II FPGA.
April 1, 2002
7
JDR1
Connector
RXD
TXD
Din
RS232
Drivers
MAX3221
Rout
Dout
Rin
RD
TD
2
3
Figure 7 – RS232 Interface
3.9.2 RS232 Signal Descriptions
The following table shows the RS232 signals and their pin assignments to the Spartan-II FPGA.
Table 6 - RS232 Signal Descriptions
Signal Name
RXD
TXD
Spartan-II Pin #
B9
A9
Description
Received Data, RD
Transmit Data, TD
3.10 JTAG Port
The Spartan-II development board design provides a JTAG port that can be used to configure
and/or program various devices on the board and JTAG devices located on the P160 module.
3.10.1 JTAG Connector
The Spartan-II development board provides a JTAG connector that can be used to program the
on-board ISP PROM, configure the Spartan-II FPGA, and program and/or configure JTAG
devices located on the P160 module. The following figure shows the pin assignments for the
JTAG connector on the Spartan-II development board.
J2
JTAG
Connector
3.3V
GND
TCK
TDO
TDI
TMS
1
2
3
4
5
6
7
Figure 8 – JTAG Connector
3.10.2 JTAG Signal Descriptions
The following table provides a brief description of the JTAG signals and their pin assignments to
the Spartan-II FPGA.
April 1, 2002
8
Table 7 - JTAG Signal Descriptions
Signal Name
TDI
TCK
TMS
TDO
Description
JTAG Data Input
JTAG Clock Input
JTAG Test Mode Input
JTAG Data Output
3.10.3 JTAG Chain
The following figure shows the JTAG chain on the Spartan-II development board. If any of the
devices in the chain are not populated, its associated jumper must be closed in order to maintain
the chain integrity. If the P160 module is not present, then jumper JP25 must be closed in order
to connect the P160 module TDI pin to its TDO pin.
TDI
TMS
TCK
TDI
Jumper
Jumper
Jumper
JP22
JP17
JP25
XC18V02
ISP
TDO
PROM
TDI
Spartan-II
TDO
FPGA
TDI
TMS
TMS
TMS
TCK
TCK
TCK
P160
Module
TDO
TDO
Figure 9 – Spartan-II Development Board JTAG Chain
3.10.4 JTAG Chain Jumper Settings
The following table shows the JTAG chain jumper setting on the Spartan-II development board.
Table 8 - JTAG Chain Jumper Settings
Jumper
JP22
JP17
JP25
April 1, 2002
Setting
Open
Closed
Open
Closed
Open
Closed
Description
XC18V02 ISP PROM is present
XC18V02 ISP PROM is not present
Spartan-II FPGA is present
Spartan-II FPGA is not present
P160 module is present
P160 module is not present
9
3.11 Slave Parallel/Slave Serial Port
In addition to the JTAG mode, the Spartan-II FPGA on the Spartan-II development board can be
configured using the Slave Serial or the Slave Parallel mode of configuration. The following figure
shows the connector pin assignments for the Slave Serial/Slave Parallel port.
J3
Slave Parallel/Slave Serial
Connector
CSn
D0
1
2
3
4
DONE
D1
CCLK
D2
5
6
7
8
9
10
11
12
13
14
15
16
INITn
D3
PROGRAMn
D4
D5
RD/Wn
D6
DOUT/BUSY
D7
Figure 10 – Slave Parallel/Slave Serial Connector
3.11.1 Slave Parallel
In the Slave Parallel configuration mode, a byte of configuration data is loaded into the Spartan-II
FPGA during each CCLK clock cycle. In this mode, an external source drives the CCLK clock and
the data bus containing the configuration data. The following figure shows the Slave Parallel
configuration mode interface to the Spartan-II FPGA. The JP12 jumper must be installed in
position 1-2 for this mode of configuration.
D[0:7]
D[0:7]
DONE
DONE
CCLK
CCLK
INITn
INIT_B
PROGRAMn
Spartan-II
PROG_B FPGA
RD/Wn
RDWR_B
DOUT/BUSY
BUSY
CSn
CS_B
Figure 11 – Slave Parallel Mode Configuration
April 1, 2002
10
3.12 Slave Serial Port
In the Slave Serial configuration mode, a bit of configuration data is loaded into the FPGA during
each CCLK clock cycle. In this mode, an external source places the most significant bit of each
byte on the DIN pin first and then drives the CCLK clock to store data into the FPGA. The
following figure shows the Slave Serial configuration mode interface to the Spartan-II FPGA. The
JP12 jumper must be installed in position 1-2 for this mode of configuration.
D0
DIN
DONE
DONE
CCLK
CCLK
INITn
INIT_B
Spartan-IIE
FPGA
PROGRAMn
PROG_B
Figure 12 – Slave Serial Mode Configuration
3.13 Bank I/O Voltage
The Spartan-II development board allows the Spartan-II I/O pins to be configured for 2.5V or 3.3V
operation. All Spartan-II user I/O pins are grouped in 8 different banks. Each bank of I/O pins on
the board can be configured to operate in the 2.5V or the 3.3V mode.
3.13.1 Bank I/O Voltage Jumper Settings
The following table shows the jumper settings for the Spartan-II bank I/O voltage (VCCO)
selection. Each bank can be set to 2.5V or 3.3V.
Table 9 - Bank I/O Voltage Jumper Settings
Bank #
Jumper
I/O Voltage
JP35
0
1-2
Closed
Open
2-3
Open
Closed
3.3V
2.5V
JP26
1
2
3
4
1-2
Closed
Open
2-3
Open
Closed
FIXED
FIXED
JP19
1-2
Closed
Open
2-3
Open
Closed
3.3V
2.5V
3.3V
3.3V
3.3V
2.5V
JP34
5
6
7
April 1, 2002
1-2
Closed
Open
2-3
Open
Closed
FIXED
FIXED
3.3V
2.5V
3.3V
3.3V
11
3.14 ISP PROM
The Spartan-II development board utilizes the Xilinx XC18V02 ISP PROM, allowing FPGA
designers to quickly download revisions of a design and verify the design changes in order to
meet the final system-level design requirements. The XC18V02 ISP PROM uses two interfaces to
accomplish the configuration of the Spartan-II FPGA.
The JTAG port on the XC18V02 device is used to program the PROM with the design bit file.
Once the XC18V02 has been programmed, the user can configure the Spartan-II device in the
Master Serial mode. The configuration of the Spartan-II device is initiated by asserting the
PROGn signal. Upon activation of the PROGn signal (by pressing the SW2 switch), the XC18V02
device will use its FPGA Configuration Port to configure the Spartan-II FPGA.
XC18V02 ISP PROM
TDI
TMS
JTAG
Port
TCK
TDO
Spartan-II FPGA
D0
D0
CE
DONE
CCLK
CCLK
RESET/OE
INIT_B
CF
PROG_B
Figure 13 – ISP PROM Interface
3.15 PCI Interface
The Spartan-II 200 PCI development board provides a 32-bit PCI interface edge connector for
prototyping PCI-based designs. The Xilinx PCI32 core can be used to implement this interface.
3.15.1 PCI Interface Signal Descriptions
The following table shows the PCI interface signals and their assignments to the Spartan-II
FPGA.
Table 10 – PCI Interface Signal Descriptions
FPGA Pin #
JE1 Signal
Name
+12V
M3
April 1, 2002
TDI
+5V
INITAn
JE1 Pin #
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
JE1 Signal
Name
-12V
FPGA Pin #
GND
TDO
+5V
+5V
12
+5V
E2
RSTn
L5
GNTn
GND
G4
AD30
H5
F1
AD28
AD26
GND
AD24
IDSEL
G1
L6
H2
H1
J2
J1
M6
M1
L4
P2
K5
K3
P4
AD22
AD20
GND
AD18
AD16
FRAMEn
GND
TRDYn
GND
STOPn
GND
PAR
AD15
P5
AD13
AD11
GND
AD09
P1
C/BE0n
T1
T2
AD06
AD04
GND
AD02
AD00
R5
T5
+5V
+5V
April 1, 2002
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
GND
PCI.CLK
GND
REQn
C11
K2
AD31
AD29
GND
AD27
AD25
E1
G3
C/BE3n
AD23
GND
AD21
AD19
N2
H3
AD17
C/BE2n
GND
IRDYn
J3
N3
DEVSELn
GND
L1
PERRn
N5
SERRn
M4
C/BE1n
AD14
GND
AD12
AD10
GND
N4
K1
AD08
AD07
P3
R2
AD05
AD03
GND
AD01
R4
U1
F2
H4
J4
J5
L3
K4
R1
V1
+5V
+5V
13
3.16 Voltage Regulators
The following figure shows the voltage regulators that are used on the Spartan-II development
board to provide various on-board voltage sources. As shown in the figure, JP1 connector is used
to provide the main 5.0V voltage to the board. This voltage source is provided to all on-board
regulators to generate the 2.5V, and 3.3V voltages.
3.3V
2.5V
3.3V
Reg
2.5V
Reg
JP6
Jumper
JP9
Jumper
JP7
3.3V
Connector
JP10
2.5V
Connector
JP1
5.0V
Connector
Figure 14 – Spartan-II Development Board Voltage Regulators
For any one of the on-board voltages (2.5V, and 3.3V), if the current provided by the on-board
regulator is not sufficient for some applications, the user can directly drive the voltage source and
bypass the on-board regulators. This can be accomplished by removing jumpers JP6 and JP9 for
3.3V and 2.5V voltages respectively.
3.16.1 Voltage Regulators Jumper Settings
The following table shows the jumper setting for the 3.3V and 2.5V supply voltages on the
Spartan-II PCI development board.
Table 11 - Voltage Regulators Jumper Settings
Jumper
JP6
Jumper
Setting
Open
3.3V Source
JP9
Closed
Open
External 3.3V supply via JP7
connector
On-board 3.3V regulator
NA
Closed
NA
2.5V Source
NA
NA
External 2.5V supply via JP10
connector
On-board 2.5V regulator
3.17 Spartan-II Configuration Mode Select
The following table shows the Spartan-II Configuration Mode Select jumper settings.
April 1, 2002
14
Table 12 - Spartan-II Configuration Mode Select
Mode
Master Serial
Master Serial
Slave Serial
Slave Serial
Slave Parallel
Slave Parallel
JTAG
JTAG
PC Pull-up
No
Yes
No
Yes
No
Yes
No
Yes
1-2 (M0)
Closed
Closed
Open
Open
Closed
Closed
Open
Open
J1
3-4 (M1)
Closed
Closed
Open
Open
Open
Open
Closed
Closed
5-6 (M2)
Closed
Open
Open
Closed
Open
Closed
Open
Closed
3.18 P160 Expansi on Module
A versatile expansion slot is implemented on the Spartan-II board, allowing application specific
cards or modules to be easily interfaced with the Spartan-II FPGA. The P160 Expansion Slot is
made up of two 80-pin connectors yielding 110 user I/O signals to an add-on module.
3.18.1 Expansion Module Signal Assignments
The following tables show the Spartan-II pin assignments to the P160 Expansion Module
connectors (JX1 & JX2) located on the Spartan-II development board.
April 1, 2002
15
Table 13 – JX1 User I/O Connector
FPGA
Pin #
NA
NA
NA
NA
NA
NA
E16
NA
E15
NA
E14
NA
F12
NA
C10
NA
D10
NA
B8
NA
A7
NA
B7
NA
B6
NA
A5
NA
B5
NA
A4
NA
B4
NA
A3
NA
B3
NA
April 1, 2002
I/O Connector
Signal Name
TCK
GND
TMS
Vin
TDI
GND
TDO
3.3V
LIOA9
GND
LIOA11
2.5V
LIOA13
GND
LIOA15
Vin
LIOA17
GND
LIOA19
3.3V
LIOA21
GND
LIOA23
2.5V
LIOA25
GND
LIOA27
Vin
LIOA29
GND
LIOA31
3.3V
LIOA33
GND
LIOA35
2.5V
LIOA37
GND
LIOA39
Vin
JX1 Pin #
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
I/O
Connector
Signal
Name
FPGA.BITSTREAM
SM.DOUT/BUSY
FPGA.CCLK
DONE
INITn
PROGRAMn
NC
LIOB8
LIOB9
LIOB10
LIOB11
LIOB12
LIOB13
LIOB14
LIOB15
LIOB16
LIOB17
LIOB18
LIOB19
LIOB20
LIOB21
LIOB22
LIOB23
LIOB24
LIOB25
LIOB26
LIOB27
LIOB28
LIOB29
LIOB30
LIOB31
LIOB32
LIOB33
LIOB34
LIOB35
LIOB36
LIOB37
LIOB38
LIOB39
LIOB40
FPGA
Pin #
B19
A19
B18
A18
B17
A17
A16
B15
A15
B14
A14
B13
A13
B12
C18
D17
C17
D16
C16
D15
C15
D14
C14
D13
C13
E13
C12
D12
E12
C9
D9
C8
D8
16
Table 14 – JX2 User I/O Connector
FPGA
Pin #
V14
Y14
W13
Y18
Y13
Y17
V13
Y16
Y12
Y15
V12
AB20
V11
AA19
W11
AB18
V10
AB17
Y10
AA15
W10
AA14
Y9
AA13
W9
AA12
Y8
AB10
W8
AB9
Y7
AB8
W7
AA7
Y6
AA6
W6
AA5
W5
AA4
April 1, 2002
I/O
Connector
Signal
Name
RIOA1
RIOA2
RIOA3
RIOA4
RIOA5
RIOA6
RIOA7
RIOA8
RIOA9
RIOA10
RIOA11
RIOA12
RIOA13
RIOA14
RIOA15
RIOA16
RIOA17
RIOA18
RIOA19
RIOA20
RIOA21
RIOA22
RIOA23
RIOA24
RIOA25
RIOA26
RIOA27
RIOA28
RIOA29
RIOA30
RIOA31
RIOA32
RIOA33
RIOA34
RIOA35
RIOA36
RIOA37
RIOA38
RIOA39
RIOA40
JX2 Pin #
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
I/O
Connector Signal
Name
FPGA
Pin #
GND
RIOB2
Vin
RIOB4
GND
RIOB6
3.3V
RIOB8
GND
RIOB10
2.5V
RIOB12
GND
RIOB14
Vin
RIOB16
GND
RIOB18
3.3V
RIOB20
GND
RIOB22
2.5V
RIOB24
GND
RIOB26
Vin
RIOB28
GND
RIOB30
3.3V
RIOB32
GND
RIOB34
2.5V
RIOB36
GND
RIOB38
Vin
RIOB40
NA
W18
NA
W17
NA
W16
NA
W15
NA
W14
NA
AA20
NA
AA18
NA
AA17
NA
AB16
NA
AB15
NA
AB14
NA
AB13
NA
AB11
NA
AA10
NA
AA9
NA
AA8
NA
AB6
NA
AB5
NA
AB4
NA
AB3
17
4
Design Download
The Spartan-II development board supports multiple methods of configuring the Spartan-II FPGA.
The JTAG port on the Spartan-II development board can be used to directly configure the
Spartan-II FPGA, or to program the on-board XC18V02 ISP PROM. Once the ISP PROM is
programmed, it can be used to configure the Spartan-II FPGA. The Slave Parallel/Slave Serial
port on this development board can also be used to configure the Spartan-II FPGA. The following
figure shows the setup for all Spartan-II FPGA configuration modes that are support ed on the
Spartan-II development board.
AC/DC
Adapter
PC
JTAG
Cable
Spartan-II™
Development
Board
JP1
Parallel
Port
J2
J3
Slave Serial/Slave Parallel
Figure 15 – Download Setup
4.1 JTAG Interface
The J2 JTAG connector on the Spartan-II development board can be used to configure the
Spartan-II or to program the on-board XC18V02 ISP PROM. The Memec Design JTAG cable is
connected to the Spartan-II development board via J2 at one end and to the PC parallel port at
the other end.
4.1.1
Configuring the Spartan-II FPGA
When the JTAG port is used to configure the Spartan-II FPGA, the following steps must be taken:
• Using Table 13 set the Configuration Mode of the Spartan-II FPGA to JTAG Mode.
• Install the JP25 jumper if the P160 module is not present
• Install JP12 in position 2-3.
• Use the Xilinx JTAG programmer (iMPACT) utility to load the design bit file into the
Spartan-II FPGA. You will need to associate the ISP PROM with either a dummy .mcs
file, or a .bsd file to allow the JTAG programming software to pass data through the ISP
PROM.
4.1.2 Programming the XC18V02 ISP PROM
When the JTAG port is used to program the ISP PROM, the following steps must be taken:
• Using Table 13 set the Configuration Mode of the Spartan-II FPGA to Master Serial
Mode.
• Install the JP25 jumper if the P160 module is not present
• Install JP12 in position 2-3.
April 1, 2002
18
•
•
4.2
Use the Xilinx JTAG programmer utility (iMPACT) to load the design mcs file into the ISP
PROM. You will need to associate the FPGA with either a dummy .bit file or a .bsd file to
allow the JTAG programming software to pass data through the FPGA.
Upon programming of the 18V02 ISP PROM, the on-board PROGn push button switch
(SW2) is used to initiate the Spartan-II FPGA configuration.
Slave Serial Interface
In this mode, an external source provides the configuration bit stream and the configuration clock
(CCLK) to the Spartan-II FPGA. Refer to Table 13 for setting up the Configuration Mode pins.
The JP12 jumper must be installed in position 1-2 for this mode of configuration.
4.3 Slave Parallel
In this mode, an external source provides the configuration bit stream and the configuration clock
(CCLK) to the Spartan-II FPGA. Refer to Table 13 for setting up the Configuration Mode pins.
The JP12 jumper must be installed (position 1-2) for this mode of configuration.
April 1, 2002
19
Revision History
V1.0
Initial Release
April 1, 2002
4/1/02
20
Appendix A - Spartan-II 200 PCI Board Schematics
April 1, 2002
21
10
VOLTAGE
9
8
INPUT JACK
7
6
5
REGULATION
4
LED
3
2
1
GROUND TEST LOOPS
TEST LOOP
5V
5VJACK
JP1
1
2
Barrel Jack SMT
H
JP2
R1
750
2
5VJACK
3
H
Test Point Loop - Black
5V
JP3
5V
JP4
1X2
Header
SPDT Slide 6A
1
2
JP5
Test Point Loop - Red
DS1
LST670-HK
STANDALONE
ON/OFF SWITCH
1X2
SPARTAN-II PCI : DS-BD-2S200PCI
VIN
(5V)
SW1
1
Test Point Loop - Black
5VJACK
G
G
3.3V
5V
U1
JP6
2
1
2
3
4
5
1
1X2
3.3V
JP7
1X2
Header
C1
2.2u
1
2
+ C2
150u
TPS75533KTT
EN
IN
GND
OUTPUT
FB/PG
5A
HS
6HS3
TP1
R2
330
JP8
Test Point Loop - Red
Pmax = (Tj-Ta)/Rth = (125 - 50) / 25°C/W = 3W
1X2
3.3V
DS2
LST670-HK
I = P/V = 3/(5-3.3) = 3/1.7 = 1765mA
3.3V
NE1
SHUNT-LO-CL
BRACKET
3.3V
F
F
Pmax = (Tj-Ta)/Rth = (125 - 50) / 30°C/W = 2.5W
5V
2.5V
I = P/V = 2.5/(5-2.5) = =2.5/2.5 = 1A
U2
REG1117FA-2.5 DDPAK
R3
130
JP9
2.5V
JP10
1X2
Header
2
1
2
1
1
1X2
VOUT
HS
GND
C3
2.2u
1X2
VIN
NE20 PCI Bracket - rectangle
2.5V
2
4 HS2
TP2
JP11
C4
2.2u
DS3
LST670-HK
2.5V
3
Test Point Loop - Red
2.5V
E
E
NE13 SHUNT-LO-CL
RUBBER FEET
NE9
Little Rubber Feet
NE10 Little Rubber Feet
D
D
NE11 Little Rubber Feet
NE12 Little Rubber Feet
MOUNTING HOLES
C
C
NE2
Mounting Hole (.125)
NE3
Mounting Hole (.125)
NE7
Mounting Hole (.125)
NE14 Mounting Hole (.125)
B
B
Spartan II PCI 32 Development Board
A
A
POWER
MemecBoard
<OrgAddr1>
<OrgAddr2>
<OrgAddr3>
<OrgAddr4>
10
9
8
7
6
5
4
3
2
Last Modified
Wednesday, January 23, 2002
Rev
Size
1
C
Designer
Sheet
Jim Elliott
1 of 8
1
8
7
6
LIO.A31
DISPLAY.2F
DISPLAY.2A
LIO.A29
LIO.A27
G
DISPLAY.2E
DISPLAY.2D
LIO.B40
B5
C6
D6
A5
B6
D7
C7
D8
C11
PCI.CLK
XC2S200
IO
IO*1*
IO*1*
IO
IO_VREF_0*3*
IO
IO*1*
IO
IO_VREF_0
IO
IO
IO
*2*IO
*1*IO
IO
IO
IO
IO_VREF_0
IO
IO*1*
IO*1*
IO
IO
IO
*1*IO
*2*IO
IO
IO
IO_VREF_0
IO
*2*IO
IO
GCLKPAD3
IO
*1*IO
E8
B7
A7
E9
C8
B8
D9
A8
DISPLAY.1C
LIO.A25
LIO.A23
DISPLAY.1B
LIO.B39
LIO.A21
LIO.B38
DISPLAY.2G
D10
C9
E10
B9
A9
C10
F11
B10
LIO.A19
LIO.B37
DISPLAY.1A
RXD
TXD
LIO.A17
DISPLAY.1F
FPGA.RESETn
A10
E11
LED.USER
DISPLAY.1G
D11
C12
D12
B12
A13
E12
B13
C13
LIO.B34
LIO.B35
LIO.B21
LIO.B20
LIO.B36
LIO.B19
LIO.B32
D13
A14
B14
C14
F12
A15
E13
B15
LIO.B31
LIO.B18
LIO.B17
LIO.B30
LIO.A15
LIO.B16
LIO.B33
LIO.B15
C15
LIO.B28
2
1
JP30
A11
IO
IO*1*
IO
IO
IO*2*
IO
IO_VREF_1
IO
U5B
XC2S200
IO
IO_VREF_1
IO
IO
IO
*1*IO
*1*IO
IO
IO
IO*2*
IO*1*
IO
IO
IO*1*
IO*2*
IO
IO_VREF_1
IO
IO
*1*IO
IO
*3*IO_VREF_1
IO
*1*IO
IO
*1*IO
IO_WRITE
IO_CS
GCLKPAD2
K17
J17
H17
G17
L16
K16
Bank 1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
U5A
A16
E14
D14
C16
D15
A17
E15
B17
A18
D16
C17
E16
B18
A19
D17
C18
LIO.B14
LIO.A13
LIO.B29
LIO.B26
LIO.B27
LIO.B13
LIO.A11
LIO.B12
SM.DOUT/BUSY
FPGA.BITSTREAM
MEM.D24
MEM.D25
MEM.D23
MEM.D26
MEM.D27
MEM.D28
LIO.B11
LIO.B25
LIO.B24
LIO.A9
LIO.B10
LIO.B9
LIO.B23
LIO.B22
MEM.D21
MEM.D29
MEM.D22
MEM.D30
MEM.D20
MEM.D19
B19
A20
C19
LIO.B8
Bank 2
U5C
C21
D20
C22
D21
E20
D22
E21
E22
F18
F20
F21
F19
F22
G19
G20
G18
G21
H18
MEM.D31
SM.RDWRn
SM.CSn
XC2S200
IO_DOUT_BUSY
IO_DIN_D0
IO*1*
IO*1*
IO
IO_VREF_2*3*
IO
IO*1*
H22
H20
H19
H21
J19
J22
J18
J20
IO_D1
IO_D2
IO
*2*IO
*1*IO
IO
IO
*1*IO
IO
IO
IO_VREF_2
IO
IO*1*
IO*1*
IO
IO
*2*IO
IO
IO
IO_VREF_2
IO_D3
*2*IO
IO
IO
IO
IO_VREF_2
*1*IO
IO
IO_IRDY
SM.D1
SM.D2
MEM.D18
MEM.DQM3
MEM.D17
MEM.A4
K18
J21
K22
K21
K20
K19
L22
L21
L18
L17
L20
Bank 3
M22
M18
M20
M19
M17
N22
N21
N20
MEM.A9
MEM.A0
MEM.BS1
MEM.A10
MEM.D16
MEM.CLKE
MEM.DQM1
MEM.BS0
MEM.A3
MEM.A6
MEM.A5
SM.D3
MEM.DQM2
MEM.A8
MEM.A7
MEM.CLK
MEM.D8
MEM.CSn
MEM.D9
MEM.RASn
MEM.CASn
MEM.D10
MEM.D3
N18
P22
N19
P21
P20
P19
R22
P18
SM.D5
SM.D6
R21
T22
MEM.A1
IO_TRDY
IO*1*
IO
IO
IO*2*
IO_D4
IO_VREF_3
IO
XC2S200
IO_VREF_3
IO
IO
IO
*1*IO
*1*IO
IO
IO_VREF_3
IO
IO*2*
IO*1*
IO
IO
IO*1*
IO*2*
IO
IO
IO
*1*IO
IO
*3*IO_VREF_3
IO
*1*IO
*1*IO
IO_D5
IO_D6
H
U5D
IO_D7
IO_INIT
R19
U22
R18
T21
V22
T19
T20
U21
MEM.WEn
MEM.D12
MEM.D2
MEM.D11
MEM.D14
MEM.D7
MEM.DQM0
MEM.D13
W22
T18
V21
U19
U20
W21
AA22
V20
MEM.D1
MEM.D0
MEM.D15
MEM.D5
MEM.D6
SM.D4
3.3V
R7
330
G
MEM.D4
Y21
V19
SM.D7
INITn
MEM.A2
1X2
*#* See Chart on Core Power Symbol.
*#* See Chart on Core Power Symbol.
*#* See Chart on Core Power Symbol.
BANK 5 - P160 RIGHT HEADER
BANK 4 - P160 HEADERS
1
3.3V
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
Bank 0
2
3.3V
G13
G12
F16
F15
F14
F13
G11
G10
F10
F9
F8
F7
LIO.A39
LIO.A37
LIO.A35
DISPLAY.1D
LIO.A33
DISPLAY.1E
C5
D5
B3
A3
B4
E6
A4
E7
3
BANK 3 - SDRAM
VBANK1
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
H
4
BANK 2 - SDRAM
VBANK0
DISPLAY.2B
DISPLAY.2C
5
BANK 1 - P160 LEFT HEADER
T17
R17
P17
N17
N16
M16
9
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
10
BANK 0 - USER IO & PCI CLK
*#* See Chart on Core Power Symbol.
BANK 6 - PCI
VBANK4
BANK 7 - PCI
VBANK5
3.3V
3.3V
W18
AA20
Y18
V17
AA19
AB20
W17
AA18
RIO.B2
RIO.B12
RIO.A4
RIO.A14
RIO.A12
RIO.B4
RIO.B14
E
V16
Y17
AB19
AB18
W16
AA17
Y16
V15
RIO.A6
RIO.A16
RIO.B6
RIO.B16
RIO.A8
AB17
RIO.A18
W12
CLK.CAN1
IO
IO
IO*1*
IO*1*
IO
IO_VREF_4*3*
IO
IO*1*
IO_VREF_4
IO
IO
IO
*2*IO
*1*IO
IO
IO
IO
IO
IO_VREF_4
IO
IO*1*
IO*1*
IO
IO
*1*IO
*2*IO
IO
IO
IO_VREF_4
IO
*2*IO
IO
IO
IO
IO*1*
IO
GCLKPAD0
AB16
Y15
AA15
AB15
W15
Y14
V14
AA14
RIO.B18
RIO.A10
RIO.A20
RIO.B20
RIO.B8
RIO.A2
RIO.A1
RIO.A22
W14
AB14
V13
Y13
AA13
AB13
W13
AA12
RIO.B10
RIO.B22
RIO.A7
RIO.A5
RIO.A24
RIO.B24
RIO.A3
RIO.A26
Y12
V12
U12
U11
AB11
W11
AA10
V11
Y10
AB10
W10
RIO.B26
RIO.A15
RIO.B28
RIO.A13
RIO.A19
RIO.A28
RIO.A21
AA9
V10
Y9
AB9
W9
AB8
V9
AA8
RIO.B30
RIO.A17
RIO.A23
RIO.A30
RIO.A25
RIO.A32
RIO.B32
RIO.A9
RIO.A11
Y11
CLK.CAN2
*#* See Chart on Core Power Symbol.
IO*1*
IO
IO
IO*2*
IO
IO_VREF_5
IO
IO
IO*2*
IO*1*
IO
IO
IO*1*
IO*2*
IO
IO
IO
IO_VREF_5
IO
IO
IO
*1*IO
*1*IO
IO
IO_VREF_5
IO
IO
*1*IO
IO
*3*IO_VREF_5
IO
*1*IO
GCLKPAD1
*1*IO
Y8
W8
W7
AA7
AB6
AA6
V8
AB5
W3
Y2
V4
V3
W2
Y1
U4
V2
RIO.A27
RIO.A29
RIO.A33
RIO.A34
RIO.B34
RIO.A36
RIO.B36
AA5
Y7
W6
AB4
AA4
Y6
V7
AB3
RIO.A38
RIO.A31
RIO.A37
RIO.B38
RIO.A40
RIO.A35
AD00
AD01
AD02
AD03
RIO.B40
W5
RIO.A39
AD04
AD05
*#* See Chart on Core Power Symbol.
W1
T4
T3
U2
T5
V1
R5
U1
T2
R4
L7
K7
K6
H6
G6
J6
N7
M7
T6
R6
P6
N6
U5F
XC2S200
Bank 6
U5G
XC2S200
IO
IO
IO*1*
IO*1*
IO
IO_VREF_6*3*
IO
IO*1*
IO
IO
IO
*2*IO
*1*IO
IO
IO
*1*IO
IO
IO
IO_VREF_6
IO
IO*1*
IO*1*
IO
IO
*2*IO
IO
IO
IO_VREF_6
IO
*2*IO
IO
IO
IO
IO_VREF_6
*1*IO
IO_TRDY
T1
R2
P3
P5
R1
P4
P2
N5
P1
N4
N3
N2
M5
N1
M4
M3
M6
M1
AD06
AD07
AD08
AD09
AD10
AD11
PAR
PERRn
IRDYn
STOPn
GNTn
DEVSELn
IDSEL
REQn
AD12
AD13
C/BE0n
C/BE1n
C/BE2n
C/BE3n
SERRn
INTAn
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
FRAMEn
TRDYn
AD22
AD23
L3
L4
L5
L1
L6
K2
K4
K3
H2
H3
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
R8
3.3k
Pull-ups
Master-serial
Slave Serial
Slave Parallel
Boundary-scan
0
1
W20
B22
Y19
DONE
M0
M1
M2
No
Yes
No
Yes
No
Yes
No
Yes
012
B
Configuration
PROGRAMn
FPGA.CCLK
2
TCK
TDO.PROM.to.TDI.FPGA
TDO.FPGA.to.TDI.EXP
TMS
1
3
5
Mode
J1
C4
B20
A21
D3
V6
Y5
2X3
U5I
XC2S200
M0
M1
M2
TCK
TDI
TDO
TMS
(Driven by VCCO_2)
PWDN
STATUS
IO_VREF_7
IO
IO
*1*IO
IO
*3*IO_VREF_7
IO
*1*IO
*1*IO
IO
IO
IO
E2
F3
G5
F4
E3
D2
F5
C1
E4
B1
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
E
RSTn
DIP7
DIP4
DIP3
DIP6
DIP1
DIP5
DIP2
DIP8
PUSH.USER1
VCCINT = 2.5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Notes:
2s200
2s150
2s100
*1*
IO
IO
NC
*2*
IO
NC
NC
*3*
VREF
IO
IO
Core Power
U5J
XC2S200
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D18
G22
E19
L19
M21
R20
Y22
U18
AB21
AA16
AB12
AA11
AB7
AA3
AA1
U3
R3
M2
L2
G2
D1
C2
W19
W4
D19
D4
C
B
L13
L12
L11
L10
L9
K14
K13
K12
K11
K10
K9
J14
J13
J12
J11
J10
J9
C20
C3
B21
B2
A22
A2
A6
B11
A12
B16
E17
2
4
6
Indicates jumper installed ('0')
Indicates jumper removed ('1')
AB2
U5
Y4
PROGRAM
CCLK (Driven by VCCO_2)
DONE(Driven by VCCO_3)
IO
IO_VREF_7
IO
IO
IO
*1*IO
*1*IO
IO
D
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
AB22
AB1
AA21
AA2
Y20
Y3
P14
P13
P12
P11
P10
P9
N14
N13
N12
N11
N10
N9
M14
M13
M12
M11
M10
M9
L14
3.3V
R12
3.3k
U5H
XC2S200
G1
H4
F1
F2
H5
G3
G4
E1
2.5V
3.3V
R10
3.3k
Bank 7
*#* See Chart on Core Power Symbol.
POWER BLOCK
R9
3.3k
IO
IO
IO*2*
IO*1*
IO
IO
IO*1*
IO*2*
*#* See Chart on Core Power Symbol.
CONFIGURATION BLOCK
C
IO_IRDY
IO
IO*1*
IO
IO
IO*2*
IO
IO_VREF_7
K1
K5
J1
J3
J2
J5
H1
J4
E5
E18
F6
F17
G7
G8
G9
G14
G15
G16
H7
H16
J7
J16
P7
P16
R7
R16
T7
T8
T9
T14
T15
T16
U6
U17
V5
V18
D
Bank 5
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
VCCO_7
XC2S200
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
VCCO_6
U5E
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_5
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
VCCO_4
Bank 4
U10
U9
U8
U7
T11
T10
F
U16
U15
U14
U13
T13
T12
F
NE4
SHUNT-LO-CL
NE5
SHUNT-LO-CL
NE6
SHUNT-LO-CL
FPGA JTAG BYPASS
A
Spartan II PCI 32 Development Board
JP17
TDO.PROM.to.TDI.FPGA
2
1
MemecBoard
Populate when the FPGA is depopulated/disabled to maintain JTAG chain integrity
10
9
8
7
6
5
4
A
FPGA
TDO.FPGA.to.TDI.EXP
1X2 RA
3
<OrgAddr1>
<OrgAddr2>
<OrgAddr3>
<OrgAddr4>
2
Last Modified
Wednesday, January 23, 2002
Rev
Size
1
C
Designer
Sheet
Jim Elliott
2 of 8
1
10
9
8
7
XC18 PROM
6
5
4
PROGRAM PUSHBUTTON
3
2
1
FPGA POWER SELECT
PROGRAMMING DONE LED
3.3V
2.5V
3.3V
H
H
JP35
1X3
3
R13
3.3k
2
3.3V
1
3.3V
3.3V
A
PROGRAMn
B
3.3V
VBANK0
R14
330
SW2
Tl1105SP
C11
CAP-1009-X7R-2020-0603-006
17
35
38
8
16
26
36
G
R15
10
13
15
21
43
PROGRAMn
0
1%
3
5
7
31
DONE
FPGA.CCLK
TDI
TMS
TCK
TDO
11
12
F
A'
B'
3
Q2
JP26
1X3
3
DONE
40
29
42
27
9
25
14
19
G
DS5
34
33
D0/DATA
D1
U6
D2
D3
XC18V02VQ44C
CF
D4
OE/RESET
D5
CE
D6
CEO
D7
CLK
GND
GND
GND
GND
TDI.PORT.to.TDI.PROM
TMS
TCK
TDO.PROM.to.TDI.FPGA
2
LST670-HK
FPGA.BITSTREAM
1
R1
1
DONE
VBANK1
3.3V
R2
PROM JTAG BYPASS
23
22
6
18
28
41
JTAG
VCC
VCC
VCC
1
VCCO
VCCO
VCCO
VCCO
44
BCR133
JP19
1X3
3
2
C12
CAP-1009-X7R-2020-0603-006
F
2
2
INITn
3
JP12
1
1
1X3
VBANK4
JP22
PROM (Default): 2-3
SelectMAP/Slave Serial : 1-2
1
TDI.PORT.to.TDI.PROM
2
TDO.PROM.to.TDI.FPGA
1X2 RA
Populate when the XC18 PROM is
depopulated/disabled to maintain JTAG chain
integrity
NE19 SHUNT-LO-CL
JP34
1X3
3
2
E
E
1
VBANK5
CLOCK
JTAG CHAIN DIAGRAM
TDO.EXP.to.TDO.PORT
PROM
FPGA
EXP SOCKET
D
D
3.3V
JP32
2
TDI.PORT.to.TDI.PROM
TDI
TDO
TDO.PROM.to.TDI.FPGA
TDI
TDO
TDO.FPGA.to.TDI.EXP
TDI
TDO
3.3V
Y5
1
1
EN
JP24
VCC
4
2
1X2
Y4
1
1
EN
VCC
4
1X2
2
GND OUT
24MHz
3
2
CLK.CAN1
GND OUT
100MHz
3
CLK.CAN2
NE18 SHUNT-LO-CL
C
JP22
JP17
JP25
C
NE15 SHUNT-LO-CL
NE16 SHUNT-LO-CL
NE17 SHUNT-LO-CL
JTAG PORT
SELECTMAP PORT
FPGA RESET CIRCUIT
2.5V
B
2.5V
2.5V
2.5V
B
3.3V
C80
.1u
J2
1
VCC 2
GND
3
NC 4
TCK 5
TDO
6
TDI
7
TMS
JTAG7 RA
J3
SM.CSn
TCK
TDO.EXP.to.TDO.PORT
TDI.PORT.to.TDI.PROM
TMS
DONE
FPGA.CCLK
INITn
PROGRAMn
SM.RDWRn
SM.DOUT/BUSY
1
3
5
7
9
11
13
15
CSn
DIN/D0
DONE
D1
CCLK
D2
INITn
D3
PROGRAMn
D4
NC
D5
RDWRn
D6
DOUT/BUSY
D7
2
4
6
8
10
12
14
16
FPGA.BITSTREAM
SM.D1
SM.D2
SM.D3
SM.D4
SM.D5
SM.D6
SM.D7
R16
3.3k
1%
R69
10k
1%
A
B
U11
1
2
3
FPGA.RESETn
SelectMAP RA
RESET
GND
MR
TPS3823
SW3
VDD
WDI
5
Tl1105SP
4
A'
B'
Spartan II PCI 32 Development Board
A
A
FPGA PERIPHERALS
MemecBoard
NE8
10
9
8
7
6
5
4
<OrgAddr1>
<OrgAddr2>
<OrgAddr3>
<OrgAddr4>
TL1105 CAP - RED
3
2
Last Modified
Wednesday, January 23, 2002
Rev
Size
1
C
Designer
Sheet
Jim Elliott
3 of 8
1
10
9
8
7
6
5
4
3
2
1
H
H
G
G
-12V HEADER
+12V HEADER
JE1
JP37
1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
2
1X2
INTAn
F
POWER MANAGEMENT NOT
SUPPORTED
C97
CAP-0479-X7R-2020-0603-006
C81
CAP-0479-X7R-2020-0603-006
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
RSTn
AD30
AD28
AD26
C83
CAP-0109-X7R-2020-0603-006
AD24
IDSEL
AD22
AD20
E
C85
CAP-0109-X7R-2020-0603-006
AD18
AD16
FRAMEn
TRDYn
C87
CAP-0109-X7R-2020-0603-006
STOPn
CACHE NOT
SUPPORTED
C89
CAP-0109-X7R-2020-0603-006
PAR
AD15
AD13
AD11
D
C92
CAP-0109-X7R-2020-0603-006
AD09
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
C/BE0n
AD06
AD04
C93
CAP-0109-X7R-2020-0603-006
-12V
TCK
GND
TDO
+5V
+5V
INTB
INTD
PRSNT1
RSVD
PRSNT2
JP36
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
2
1
1X2
R23
AD02
AD00
C95
CAP-0479-X7R-2020-0603-006
+3.3Vaux
RST
+5V (I/O)
GNT
GND
PME
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME
GND
TRDY
GND
STOP
+3.3V
SDONE
SBO
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD09
RSVD
GND
CLK
GND
REQ
+5V (I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2
GND
IRDY
+3.3V
DEVSEL
GND
LOCK
PERR
+3.3V
SERR
+3.3V
C/BE1
AD14
GND
AD12
AD10
GND
C/BE0
+3.3V
AD06
AD04
GND
AD02
AD0
+5V (I/O)
REQ64
+5V
+5V
AD08
AD07
+3.3V
AD05
AD03
GND
AD01
+5V (I/O)
ACK64
+5V
+5V
0
PRSNT1# and PRSNT2# identify the power
requirements of this card to the platform
R26
GNTn
POWER MANAGEMENT NOT
SUPPORTED
PCI32
TRST
+12V
TMS
TDI
+5V
INTA
INTC
+5V
RSVD
+5V (I/O)
RSVD
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
F
0
PCI.CLK
REQn
AD31
AD29
C82
CAP-0479-X7R-2020-0603-006
AD27
AD25
C/BE3n
AD23
C84
CAP-0109-X7R-2020-0603-006
AD21
AD19
E
AD17
C/BE2n
C86
CAP-0109-X7R-2020-0603-006
IRDYn
DEVSELn
LOCKING NOT
SUPPORTED
C88
CAP-0109-X7R-2020-0603-006
PERRn
SERRn
C90
CAP-0109-X7R-2020-0603-006
C/BE1n
AD14
C91
CAP-0109-X7R-2020-0603-006
AD12
AD10
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
D
AD08
AD07
AD05
AD03
C100
CAP-0109-X7R-2020-0603-006
AD01
C102
CAP-0479-X7R-2020-0603-006
C
C
5V
5V
B
B
Spartan II PCI 32 Development Board
A
A
PCI 32 BIT EDGE
MemecBoard
<OrgAddr1>
<OrgAddr2>
<OrgAddr3>
<OrgAddr4>
10
9
8
7
6
5
4
3
2
Last Modified
Wednesday, January 23, 2002
Rev
Size
1
C
Designer
Sheet
Jim Elliott
4 of 8
1
5
4
3
2
1
EXP SOCKET
D
D
2.5V
5V
3.3V
3.3V
5V
2.5V
JX1
TCK
TMS
TDO.FPGA.to.TDI.EXP
TDO.EXP.to.TDO.PORT
LIO.A9
LIO.A11
LIO.A13
LIO.A15
LIO.A17
C
LIO.A19
LIO.A21
LIO.A23
LIO.A25
LIO.A27
LIO.A29
LIO.A31
LIO.A33
LIO.A35
LIO.A37
LIO.A39
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
TCK
GND
TMS
VIN
TDI
GND
TDO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
P160 Left Header MB
DIN
DOUT
CCLK
DONE
INITn
PROGRAMn
NC
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
JX2
FPGA.BITSTREAM
SM.DOUT/BUSY
RIO.A1
RIO.A2
RIO.A3
RIO.A4
RIO.A5
RIO.A6
RIO.A7
RIO.A8
RIO.A9
RIO.A10
RIO.A11
RIO.A12
RIO.A13
RIO.A14
RIO.A15
RIO.A16
RIO.A17
RIO.A18
RIO.A19
RIO.A20
RIO.A21
RIO.A22
RIO.A23
RIO.A24
RIO.A25
RIO.A26
RIO.A27
RIO.A28
RIO.A29
RIO.A30
RIO.A31
RIO.A32
RIO.A33
RIO.A34
RIO.A35
RIO.A36
RIO.A37
RIO.A38
RIO.A39
RIO.A40
FPGA.CCLK
DONE
INITn
PROGRAMn
LIO.B8
LIO.B9
LIO.B10
LIO.B11
LIO.B12
LIO.B13
LIO.B14
LIO.B15
LIO.B16
LIO.B17
LIO.B18
LIO.B19
LIO.B20
LIO.B21
LIO.B22
LIO.B23
LIO.B24
LIO.B25
LIO.B26
LIO.B27
LIO.B28
LIO.B29
LIO.B30
LIO.B31
LIO.B32
LIO.B33
LIO.B34
LIO.B35
LIO.B36
LIO.B37
LIO.B38
LIO.B39
LIO.B40
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P160 Right Header MB
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
GND
IO
3.3V
IO
GND
IO
2.5V
IO
GND
IO
VIN
IO
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
RIO.B2
RIO.B4
RIO.B6
RIO.B8
RIO.B10
RIO.B12
RIO.B14
RIO.B16
RIO.B18
C
RIO.B20
RIO.B22
RIO.B24
RIO.B26
RIO.B28
RIO.B30
RIO.B32
RIO.B34
RIO.B36
RIO.B38
RIO.B40
B
B
JTAG BYPASS
A
A
JP25
1
TDO.FPGA.to.TDI.EXP
2
TDO.EXP.to.TDO.PORT
1X2 RA
Spartan II PCI 32 Development Board
EXP SOCKET
NE21 SHUNT-LO-CL
MemecBoard
Suite 540, 1212 31st Ave. NE
Calgary, Alberta
Canada
T2E 7S8
5
4
3
2
1
Last Modified
Wednesday, January 23, 2002
Rev
Size
1
C
Designer
Sheet
Jim Elliott
5 of 8
5
4
3
DIP SWITCH
2
1
SERIAL PORT
3.3V
3.3V
C13
.1u
R34
3.3k
1%
D
R41
3.3k
1%
R35
3.3k
1%
R38
3.3k
1%
R36
3.3k
1%
R39
3.3k
1%
R37
3.3k
1%
1
U10
1
2
3
4
5
6
7
8
C14
.1u
R40
3.3k
1%
C15
.1u
SW4
1
2
3
4
5
6
7
8
DIP1
DIP2
DIP3
DIP4
DIP5
DIP6
DIP7
DIP8
JDR1
3.3V
16
15
14
13
12
11
10
9
6
EN
C1+
V+
C1C2+
C2VRIN
MAX3221
FORCEOFF
VCC
GND
DOUT
FORCEON
DIN
INVALID
ROUT
16
15
14
13
12
11
10
9
2
7
3
8
4
C16
.1u
9
C17
.1u
5
SWDIP08
DCD
D
DSR
RD
RTS
USE STANDARD STRAIGHT-THRU
CABLE WHEN CONNECTING TO A PC
TD
CTS
DTR
RI
GND
DB9 RA
TXD
RXD
LEDs
SEVEN SEGMENT DISPLAYS
C
VBANK0
PUSHBUTTONS
DISPLAY.2A
DISPLAY.2B
DISPLAY.2C
DISPLAY.2D
DISPLAY.2E
DISPLAY.2F
DISPLAY.2G
C
3.3V
DISPLAY.1A
DISPLAY.1B
DISPLAY.1C
DISPLAY.1D
DISPLAY.1E
DISPLAY.1F
DISPLAY.1G
R42
3.3k
1%
R44
330
1%
A
R45
330
1%
R46
330
1%
R47
330
1%
R48
330
1%
R49
330
1%
R50
330
1%
R51
330
1%
B
R52
330
1%
SW5
Tl1105SP
DS7
R54
330
1%
R55
330
1%
R56
330
1%
R58
330
1%
R57
330
1%
A'
R59
330
1%
B'
LST670-HK
5
9
10
1
2
4
6
7
LED.USER
5
9
10
1
2
4
6
7
DD1
D
E
F
G
DP
8
3
RED CC
B
CC
RED CC
C
A
B
C
CC
D
3
B
E
F
G
DP
8
A
B
PUSH.USER1
DD2
a
f
b
g
e
c
d
A
A
Spartan II PCI 32 Development Board
USER IO
MemecBoard
Suite 540, 1212 31st Ave. NE
Calgary, Alberta
Canada
T2E 7S8
5
4
3
2
1
Last Modified
Wednesday, January 23, 2002
Rev
Size
1
C
Designer
Sheet
Jim Elliott
6 of 8
5
4
3
2
1
D
D
R72 11
C
R73 11
MEM.DQM0
MEM.DQM1
MEM.DQM2
MEM.DQM3
MEM.WEn
MEM.CSn
R70 11
MEM.BS0
MEM.BS1
MEM.CLK
MEM.CLKE
16
71
28
59
17
20
22
23
68
67
U8
TC59S6432CFT-60
DQM0
DQM1
DQM2
DQM3
WE
CS
BS0
BS1
CLK
CKE
NC
NC
NC
NC
NC
NC
NC
44
58
72
86
GND
GND
GND
GND
14
21
30
57
69
70
73
CAS
RAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
2
4
5
7
8
10
11
13
74
76
77
79
80
82
83
85
31
33
34
36
37
39
40
42
45
47
48
50
51
53
54
56
MEM.D0
MEM.D1
MEM.D2
MEM.D3
MEM.D4
MEM.D5
MEM.D6
MEM.D7
MEM.D8
MEM.D9
MEM.D10
MEM.D11
MEM.D12
MEM.D13
MEM.D14
MEM.D15
MEM.D16
MEM.D17
MEM.D18
MEM.D19
MEM.D20
MEM.D21
MEM.D22
MEM.D23
MEM.D24
MEM.D25
MEM.D26
MEM.D27
MEM.D28
MEM.D29
MEM.D30
MEM.D31
C
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
18
19
MEM.CASn
MEM.RASn
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
6
12
32
38
46
52
78
84
25
26
27
60
61
62
63
64
65
66
24
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCC
VCC
VCC
VCC
R71 11
MEM.A0
MEM.A1
MEM.A2
MEM.A3
MEM.A4
MEM.A5
MEM.A6
MEM.A7
MEM.A8
MEM.A9
MEM.A10
3
9
35
41
49
55
75
81
3.3V
1
15
29
43
3.3V
B
B
A
A
Spartan II PCI 32 Development Board
SDRAM
MemecBoard
Suite 540, 1212 31st Ave. NE
Calgary, Alberta
Canada
T2E 7S8
5
4
3
2
1
Last Modified
Wednesday, January 23, 2002
Rev
Size
1
C
Designer
Sheet
Jim Elliott
7 of 8
10
9
8
7
FPGA Core Decoupling
6
FPGA IO Decoupling
3.3V
2.5V
5
2.5V
2.5V
4
3
2
1
Memory
Decoupling
3.3V
3.3V
2.5V
3.3V
3.3V
3.3V
3.3V
H
H
C22
.1u
C18
C19
C20
C23
.1u
C24
.1u
C21
C103
CAP-0223-X7R-2020-0402-006
CAP-0223-X7R-2020-0402-006
CAP-0223-X7R-2020-0402-006
C104
CAP-1009-X7R-2020-0603-006
3.3V
2.5V
2.5V
2.5V
3.3V
G
C33
.1u
C30
CAP-1009-X7R-2020-0603-006
C31
CAP-0223-X7R-2020-0402-006
C34
.1u
3.3V
CAP-0223-X7R-2020-0402-006
G
C35
.1u
C108
VBANK0
C40
.1u
CAP-1506-TAN-2020-7343-010
C109
C110
CAP-1009-X7R-2020-0603-006
CAP-1009-X7R-2020-0603-006
CAP-1009-X7R-2020-0603-006
VBANK0
2.5V
F
+ C43
3.3V
CAP-0223-X7R-2020-0402-006
VBANK0
2.5V
3.3V
C32
CAP-1009-X7R-2020-0603-006
2.5V
CAP-1009-X7R-2020-0603-006
3.3V
C107
CAP-0223-X7R-2020-0402-006
C106
CAP-1009-X7R-2020-0603-006
2.5V
3.3V
C29
C105
CAP-0223-X7R-2020-0402-006
+ C44
CAP-1506-TAN-2020-7343-010
C41
.1u
3.3V
C42
.1u
3.3V
3.3V
3.3V
F
+ C45
CAP-1506-TAN-2020-7343-010
C111
CAP-1009-X7R-2020-0603-006
VBANK1
VBANK1
C112
C113
CAP-1009-X7R-2020-0603-006
C114
CAP-1009-X7R-2020-0603-006
CAP-1009-X7R-2020-0603-006
VBANK1
Bulk Capacitance
C50
.1u
C51
.1u
C52
.1u
E
E
VBANK4
VBANK4
C57
.1u
VBANK4
C58
.1u
C59
.1u
2.5V
D
VBANK5
VBANK5
C65
.1u
+ C68
CAP-1506-TAN-2020-7343-010
VBANK5
C66
.1u
D
C67
.1u
Bulk Capacitance
C
C
3.3V
3.3V
3.3V
3.3V
+ C72
CAP-1506-TAN-2020-7343-010
C116
.1u
C117
.1u
C118
.1u
Bulk Capacitance
B
B
3.3V
3.3V
3.3V
5V
C119
.1u
C120
.1u
C121
.1u
+ C115
CAP-1506-TAN-2020-7343-010
Bulk Capacitance
A
Spartan II PCI 32 Development Board
A
DECOUPLING
MemecBoard
<OrgAddr1>
<OrgAddr2>
<OrgAddr3>
<OrgAddr4>
10
9
8
7
6
5
4
3
2
Last Modified
Wednesday, January 23, 2002
Rev
Size
1
C
Designer
Sheet
Jim Elliott
8 of 8
1