FAKULTA ELEKTROTECHNIKY A KOMUNIKAČNÍCH TECHNOLOGIÍ
VYSOKÉ UČENÍ TECHNICKÉ V BRNĚ
Electronic Devices
Garant předmětu:
Doc. Ing. Jaroslav Boušek, CSc.
Autoři textu:
Doc. Ing. Jaroslav Boušek, CSc.
RNDr. Michal Horák, CSc.
Brno
2.11. 2006
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Contents
1
ELECTRONIC DEVICES IN BACHELOR STUDY ....................................................9
2
SEMICONDUCTOR FUNDAMENTALS ....................................................................10
2.1 THE ELECTRONS IN FREE ATOMS.................................................................................... 10
2.2 THE ELECTRONS IN SOLIDS ............................................................................................ 10
2.3 BAND STRUCTURE OF SOLIDS ........................................................................................ 11
2.3.1
Band structures in different types of solids ............................................... 12
2.4 PREPARATION OF SEMICONDUCTOR MATERIALS ............................................................ 12
2.4.1
Intrinsic semiconductors ........................................................................... 13
2.4.2
Doped semiconductors .............................................................................. 14
2.4.3
Degenerately doped semiconductors......................................................... 15
2.4.4
Control question and example for capture 2.4 .......................................... 16
2.5 CARRIER DENSITY ......................................................................................................... 16
2.5.1
Density of states ........................................................................................ 16
2.5.2
The Fermi-Dirac distribution function ...................................................... 17
2.5.3
Filling of bands ......................................................................................... 18
2.5.4
Calculation of carrier densities................................................................. 19
2.5.5
Calculation of Fermi energy level ............................................................. 21
2.5.6
Generation and recombination processes ................................................. 23
2.6 TRANSPORT OF CARRIERS .............................................................................................. 26
2.6.1
Carrier drift ............................................................................................... 27
2.6.2
Carrier diffusion ........................................................................................ 29
2.6.3
Control questions and examples ............................................................... 31
3
PN JUNCTION ................................................................................................................31
3.1 STRUCTURE AND PRINCIPLE OF OPERATION ................................................................... 31
3.1.1
Built in potential ........................................................................................ 33
3.2 ELECTROSTATIC ANALYSIS OF A PN JUNCTION ............................................................. 34
3.2.1
The full-depletion approximation .............................................................. 34
3.2.2
Full depletion analysis .............................................................................. 35
3.3 FORWARD AND REVERSE BIAS ....................................................................................... 37
3.3.1
Forward bias ............................................................................................. 38
3.3.2
Reverse bias ............................................................................................... 39
3.4 IDEAL DIODE CURRENT .................................................................................................. 41
3.5 STATIC AND DYNAMIC RESISTANCE OF PN JUNCTION .................................................... 45
3.6 JUNCTION CAPACITANCE ............................................................................................... 45
3.7 DIFFUSION CAPACITANCE .............................................................................................. 47
3.8 DYNAMIC CHARACTERISTICS OF PN JUNCTION ............................................................. 48
3.8.1
Turn on process ......................................................................................... 48
3.8.2
Reverse recovery ....................................................................................... 49
3.9 REVERSE BIAS BREAKDOWN .......................................................................................... 50
3.9.1
Avalanche breakdown ............................................................................... 51
3.9.2
Zener breakdown ....................................................................................... 52
3.9.3
Second breakdown..................................................................................... 54
3.9.4
Surface breakdown .................................................................................... 55
3.10 METAL-SEMICONDUCTOR JUNCTION ............................................................................ 56
3.10.1 Ohmic contact for semiconductor devices................................................. 59
3.10.2 Control questions and examples for Chapter 3.10 .................................... 59
Electronic Devices
4
3
SEMICONDUCTOR DIODES ...................................................................................... 61
4.1 POINT-CONTACT DIODES ................................................................................................ 61
4.2 PLANAR DIODES ............................................................................................................. 62
4.2.1
Examples for Chapter 4.2 .......................................................................... 64
4.3 PIN DIODES 65
4.4 ZENER DIODES ............................................................................................................... 65
4.4.1
Examples for Chapter 4.4 .......................................................................... 66
4.5 VARICAP OR VARACTOR DIODES .................................................................................... 66
4.5.1
Examples for capture 4.5 ........................................................................... 68
4.6 TUNNEL (ESAKI) DIODE ................................................................................................. 68
4.7 RECTIFIER DIODES ......................................................................................................... 69
4.7.1
Line-frequency diodes ................................................................................ 69
4.7.2
Fast recovery diodes .................................................................................. 70
4.7.3
Schottky diodes .......................................................................................... 71
4.7.4
Avalanche diodes ....................................................................................... 71
4.8 LEDS AND PHOTOTIODES .............................................................................................. 72
4.8.1
Light-emitting diodes and lasers................................................................ 72
4.8.2
Photodiodes ............................................................................................... 72
4.9 I-V CHARACTERISTICS OF DIODE .................................................................................... 73
4.10 DIODE SUBSTITUTE CIRCUIT ........................................................................................... 75
5
BIPOLAR JUNCTION TRANSISTOR ........................................................................ 75
5.1 STRUCTURE OF BIPOLAR TRANSISTOR ............................................................................ 75
5.2 OPERATION OF BIPOLAR TRANSISTOR ............................................................................ 78
5.2.1
Modes of operation .................................................................................... 78
5.2.2
Two types of bipolar junction transistor .................................................... 79
5.3 TECHNOLOGY OF BIPOLAR TRANSISTORS ....................................................................... 80
5.4 USE OF BJT83
5.4.1
BJT as electronic amplifier ........................................................................ 83
5.4.2
BJT as electronic switch ............................................................................ 85
5.4.3
Current gain in BJT structure .................................................................... 85
5.5 CHARACTERISTIC CURVES OF BJT ................................................................................. 86
5.5.1
Early effect ................................................................................................. 88
5.6 OPERATION OF BJT AMPLIFIER ...................................................................................... 89
5.6.1
Operation point of BJT amplifier............................................................... 89
5.6.2
Voltage gain of the BJT amplifier .............................................................. 96
5.6.3
Power gain of BJT amplifiers .................................................................... 97
5.6.4
Control questions and examples for Chapter 5.6 ...................................... 99
5.7 OPERATION OF BJT AS CONSTANT CURRENT SOURCE .................................................. 100
5.8 BJT AS ELECTRONIC SWITCH ....................................................................................... 101
5.8.1
Darlington transistor ............................................................................... 102
5.8.2
Design rules for BHT switch .................................................................... 103
5.9 VOLTAGE BREAKDOWN OF BJT STRUCTURE ............................................................... 105
5.10 CONTROL QUESTIONS FOR BIPOLAR JUNCTION TRANSISTOR ....................................... 107
6
FIELD-EFFECT TRANSISTORS .............................................................................. 108
6.1 JUNCTION FIELD EFFECT TRANSISTOR (J-FET) ........................................................... 109
6.1.1
Output characteristics of JFET................................................................ 109
6.1.2
The transfer characteristic....................................................................... 112
6.2 INSULATED GATE FIELD EFFECT TRANSISTOR (IGFET) .............................................. 116
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6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Operation of IGFET ................................................................................ 117
Enhancement and depletion mode........................................................... 119
Characteristic curves for E-IGFET ......................................................... 120
Characteristic curves for D-IGFET ........................................................ 120
Available terminals by IGFET devices .................................................... 121
6.3 CONTROL QUESTIONS FOR FIELD-EFFECT TRANSISTORS ............................................. 122
7
BIPOLAR SWITCHING DEVICES............................................................................122
7.1 THYRISTOR 123
7.1.1
Operation of thyristor.............................................................................. 123
7.1.2
Thyristor switching .................................................................................. 124
7.1.3
Applications ............................................................................................. 125
7.1.4
Triac ........................................................................................................ 125
7.1.5
Diac ......................................................................................................... 126
8
RESULTS AND EXAMPLES ......................................................................................128
8.1 EXAMPLES FOR SEMICONDUCTOR DIODES ................................................................... 128
8.1.1
Solution Chapter 4.2.1 ............................................................................ 128
8.1.2
Solution Chapter 4.4.1 ............................................................................ 129
8.2 EXAMPLES FOR BIPOLAR JUNCTION TRANSISTOR ....................................................... 131
8.2.1
Solution Chapter 5.6.4 ............................................................................ 131
8.2.2
Examples for BJT as electronic switch.................................................... 134
8.2.3
Example for Operation of BJT as constant current source ..................... 135
8.3 EXAMPLES FOR FIELD-EFFECT TRANSISTORS.............................................................. 135
8.3.1
Example for Operating point of JFET..................................................... 135
8.3.2
Example for Operating point of MOSFET .............................................. 137
8.3.3
Example for JFET as analogue switch .................................................... 138
9
REFERENCES ...............................................................................................................139
Electronic Devices
5
Seznam obrázků
FIG. 2.1:
THEORETICAL BAND MODEL OF IV. ELEMENTS UNIT IN DEPEND ON THE GRID
11
FIG. 2.2:
ELECTRON AND HOLE GENERATION FOR INTRINSIC SEMICONDUCTOR ................ 13
FIG. 2.3:
SI CRYSTAL LATTICE WITH ONE ATOM OF DONOR AND BAND MODEL FOR N TYPE
14
FIG 2.4:
SI CRYSTAL LATTICE WITH ONE ATOM OF ACCEPTOR AND BAND MODEL FOR P
TYPE
15
FIG 2.5:
GENERAL ENERGY DEPEND OF GC(E) AND GV(E) ................................................ 17
FIG. 2.6:
ENERGY DEPEND OF FERMI-DIRAC FUNCTION A) T → 0 K, B) GENERAL DEPEND
17
FIG. 2.7:
BAND FILLING OF BANDS FOR INTRINSIC SEMICONDUCTOR AND BOTH DOPED PTYPE AND N-TYPE .............................................................................................................. 18
FIG. 2.8:
THERMAL DEPENDENCE OF INTRINSIC CARRIERS DENSITY FOR GAAS, SI AND GE
21
FIG. 2.9:
A) THE LEVEL OF FERMI ENERGY IN SILICON IN DEPENDENCE ON
CONCENTRATION OF IMPURITIES. B) TEMPERATURE DEPENDENCE OF FERMI ENERGY IS
TAKEN IN MARKED POINTS FOR BOTH N-TYPE AND P-TYPE. ............................................... 22
TEMPERATURE DEPENDENCE OF CARRIERS DENSITY FOR N-TYPE
FIG. 2.10:
SEMICONDUCTOR IN LINEAR SCALE A 1/T SCALE FOR TEMPERATURE. ............................... 22
FIG. 2.11:
THE CARRIER MOTION IN THE SEMICONDUCTOR IN THE PRESENCE OF AN
ELECTRIC FIELD. ................................................................................................................ 27
FIG. 2.12:
DRIFT CURRENT OF HOLES THROUGH P-TYPE SEMICONDUCTOR ......................... 27
FIG. 2.13:
ELECTRICAL FIELD DEPENDENCE OF MOBILITY FOR ELECTRONS AND HOLES IN
SILICON BY TEMPERATURE 300 K. ..................................................................................... 28
FIG. 2.14:
THE MOBILITY OF ELECTRONS AND HOLES IN SILICON AT ROOM TEMPERATURE IN
DEPENDENCE ON DENSITY OF DONOR AND ACCEPTOR IMPURITIES (BY TEMPERATURE 300
K).
29
FIG. 2.15:
THE SCHEME OF THE DIFFUSION PROCESS AND CORRESPONDING CURRENT
DENSITY FOR ELECTRONS AND HOLES. ............................................................................... 30
FIG. 3.1:
ASYMMETRIC PN JUNCTION............................................................................... 32
FIG. 3.2:
ABRUPT PN JUNCTION IN FORWARD AND REVERSE BIAS: A) CONFIGURATION; B)
SPACE CHARGE; C) ELECTRIC FIELD; D) JUNCTION POTENTIAL .......................................... 38
FIG. 3.3:
CARRIER TRANSPORT OVER THE ENERGETIC BARRIER IN CASE OF FORWARD (A)
AND REVERSE (B) BIAS. ...................................................................................................... 41
FIG. 3.4:
MINORITY CARRIER DENSITY IN CASE OF FORWARD BIAS (A) AND REVERSE BIAS
(B).
42
FIG. 3.5:
I-V CHARACTERISTIC OF IDEAL PN JUNCTION IN LINEAR (A) AND
SEMILOGARITHMIC (B) SCALE ............................................................................................ 44
FIG. 3.6:
VOLTAGE DEPENDENCE OF JUNCTION CAPACITY (OR BARRIER CAPACITY). ........ 47
VOLTAGE OVERSHOOT AS CONSEQUENCE OF RAPID GROW OF CURRENT DURING
FIG. 3.7:
SWITCH ON. (A) DIODE FORWARD VOLTAGE /DOTTED LINE IS SUPPOSED POWER LOSS/. (B)
ESTIMATION OF FORWARD RECOVERY TIME TRR ................................................................. 49
FIG. 3.8:
DEFINITIONS OF THE RECOVERY CHARACTERISTICS ........................................... 50
FIG. 3.9:
PRINCIPLE OF AVALANCHE MULTIPLICATION ..................................................... 51
FIG. 3.10:
BREAKDOWN VOLTAGE VERSUS DOPING DENSITY OF AN ABRUPT ONE-SIDED PN
JUNCTION (A) AND LINEARLY GRADED JUNCTION (B). ........................................................ 52
SPACING
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FIG. 3.11:
PRINCIPLE OF ZENER BREAKDOWN VISUALIZED BY MEANS OF BAND DIAGRAM. A)
PN JUNCTION IN THERMAL EQUILIBRIUM. B) THE SAME JUNCTION WITH REVERSE BIAS AND
VALUE OF REVERSE VOLTAGE CORRESPONDING TO ZENER BREAKDOWN. ......................... 53
FIG. 3.12:
THERMAL STABILITY OF THE PN JUNCTION ....................................................... 55
FIG. 3.13:
SCHOTTKY BARRIER. (A) BAND DIAGRAM OF METAL AND SEMICONDUCTOR. (B)
BAND DIAGRAM OF METAL-SEMICONDUCTOR JUNCTION IN THERMAL EQUILIBRIUM. ........ 56
FIG. 3.14:
METAL-SEMICONDUCTOR JUNCTION. BAND DIAGRAMS .................................... 58
FIG. 3.15:
BAND DIAGRAM OF METAL-SEMICONDUCTOR JUNCTION.. (A) BY FORWARD BIAS.
(B) BY REVERSE BIAS. (C) I-V CHARACTERISTIC. .............................................................. 59
FIG. 3.16:
CONTACT SYSTEM METAL-SEMICONDUCTOR. (A) RECTIFYING BY LOW DOPING
LEVEL. (B) OHMIC (WITH TUNNEL TRANSITION) BY HEAVILY DOPED SEMICONDUCTOR. .... 59
FIG. 4.1:
SEMICONDUCTOR (A) OF GERMANIUM POINT CONTACT DIODE. (B) GERMANIUM
POINT CONTACT DIODE WITH GOLD WIRE (C) PLANAR SILICON DIODE ............................... 62
FIG. 4.2:
TECHNOLOGIES FOR PLANAR DIODES. (A) ALLOYED JUNCTION. (B) DIFFUSION
MESA TECHNOLOGY. (C) DIFFUSION PLANAR TECHNOLOGY. (D) EPITAXIAL PLANAR
TECHNOLOGY. (E) SCHOTTKY DIODE MADE BY EPITAXIAL PLANAR TECHNOLOGY. ON
PICTURES (A-D) THERE IS NOT DRAWN AN ALUMINUM CONTACT LAYER. IN PICTURE (E) THE
ALUMINUM LAYER IS A PART OF THE DIODE STRUCTURE. .................................................. 63
FIG. 4.3:
DOPANTS DENSITY DEPENDENCE OF BREAKDOWN VOLTAGE BY PN JUNCTION.. 65
FIG. 4.4:
CONNECTION OF VARICAP DIODE TO RESONANT RC CIRCUIT. ........................... 67
FIG. 4.5:
CHARACTERISTIC CURVE OF A TUNNEL DIODE COMPARED TO THAT OF A
STANDARD PN JUNCTION. ................................................................................................. 69
PRINCIPAL SCHEMES OF LINE FREQUENCY RECTIFIERS. (A) HALF WAVE
FIG. 4.6:
RECTIFIER. (B) FULL WAVE RECTIFIER WITH CENTER TAPPED TRANSFORMER. (C) FULL
WAVE RECTIFIER WITH A BRIDGE RECTIFIER. ..................................................................... 70
FIG. 4.7:
I-V CHRACTERISTICS PHOTOVOLTAIC AND PHOTOCONDUCTIVE MODES ............ 73
FIG. 4.8:
I-V CHARACTERISTICS OF SEMICONDUCTOR DIODE WITH DIFFERENT SCALES. (A)
LOW VOLTAGE AND LOW CURRENT SCALE. (B) COARSE SCALE FOR VOLTAGE. (C) COARSE
SCALE FOR BOTH VOLTAGE AND CURRENT. (D) DIFFERENT SCALES FOR CURRENT AND
VOLTAGE.
73
FIG. 5.1:
PNP BIPOLAR JUNCTION TRANSISTOR. (A) THE CURRENT THROUGH BASE REGION.
(B) IN FORWARD ACTIVE BIAS MODE OPERATION THE COLLECTOR TAKES OVER A GREAT
PART OF THE EMITTER CURRENT. ....................................................................................... 76
FIG. 5.2:
NORMAL MODE OPERATION OF THE BJT............................................................ 77
FIG. 5.3:
COMMON EMITTER CONFIGURATION FOR NPN AND PNP TYPES OF BJT IN
NORMAL (ACTIVE FORWARD) MODE OPERATION ............................................................... 80
DIFFUSION TRANSISTORS. (A) ALLOY JUNCTION TRANSISTOR. (B) DIFFUSED BASE
FIG. 5.4:
TRANSISTOR. (C) DIFFUSED MESA TRANSISTOR. (D) DIFFUSED PLANAR TRANSISTOR. (E)
EPITAXIAL PLANAR TRANSISTOR. (F) EPITAXIAL PLANAR TRANSISTOR IN INTEGRATED
CIRCUIT 81
FIG. 5.5:
DIFFUSED PLANAR TRANSISTOR TECHNOLOGY PROCESS FOR NPN TYPE
TRANSISTOR. (A) OXIDATION. (B) SELECTIVE ETCHING. (C) DIFFUSION OF BASE. (D)
SHAPING THE MASK FOR EMITTER DIFFUSION. (E) DIFFUSION OF EMITTER. (F) SHAPING THE
MASK FOR THE CONTACTS. (G) DEPOSITION OF METAL CONTACTS .................................... 83
FIG. 5.6:
BJT AS AMPLIFER. CONFIGURATIONS : (A) COMMON EMITTER (CE) (B) COMMON
BASE (CB) (C) COMMON COLLECTOR (CC) ....................................................................... 84
FIG. 5.7:
BT CONNECTION................................................................................................ 84
FIG. 5.8:
BIPOLAR JUNCTION TRANSISTOR: CHARACTERISTICS IN COMMON EMITTER
CONFIGURATION ................................................................................................................ 86
FIG. 5.9:
EARLY EFFECT. DETERMINATION OF EARLY VOLTAGE. ..................................... 88
Electronic Devices
FIG. 5.10:
FIG. 5.11:
7
OPERATING POINT OF BJT: THE SIMPLEST FIXED-BIAS CIRCUIT ........................ 90
BJT OPERATING POINT: COLLECTOR FEEDBACK (OR VOLTAGE OR PARALLEL
FEEDBACK) 90
FIG. 5.12:
BJT OPERATING POINT: VOLTAGE DIVIDER (RB1,RB2)..................................... 91
FIG. 5.13:
BIPOLAR TRANSISTOR AS AN AMPLIFIER (CE CONFIGURATION). ........................ 91
FIG. 5.14:
DETERMINATION OF EMITTER-COLLECTOR VOLTAGE BY MEANS OF LOAD LINE.
(A) AMPLIFIER (B) SWITCH. ............................................................................................... 97
FIG. 5.15:
BJT AS CONSTANT CURRENT SOURCE. (A) (B) WITH NEGATIVE FEEDBACK ON RE
100
FIG. 5.16:
BJT AS CONSTANT CURRENT SOURCE: CURRENT MIRROR. ............................... 100
FIG. 5.17:
BIPOLAR TRANSISTOR AS A SWITCH (RESISTIVE LOAD) .................................... 102
FIG. 5.18:
PRINCIPLE SCHEME OF DARLINGTON TRANSISTOR ........................................... 103
FIG. 5.19:
BJT SWITCH WITH SCHOTTKY DESATURATION DIODE. ..................................... 105
FIG. 5.20:
DIFFERENT CIRCUITS TO INCREASE THE BREAKDOWN VOLTAGE OF BJT. ......... 106
FIG. 5.21:
DIFFERENT CIRCUITS TO INCREASE THE BREAKDOWN VOLTAGE OF BJT .......... 106
FIG. 5.22:
SAFE OPERATING AREA IN OUTPUT CE CHARACTERISTICS .............................. 107
FIG. 6.1:
THE JUNCTION FIELD-EFFECT TRANSISTOR (JFET) ......................................... 109
FIG. 6.2:
JFET: CHANNEL SHAPES IN ACTIVE MODE ....................................................... 110
FIG. 6.3:
JFET: CHANNEL SHAPES IN ACTIVE MODE ....................................................... 111
OUTPUT CHARACTERISTICS OF N-CHANNEL JFET ........................................... 112
FIG. 6.4:
FIG. 6.5:
OUTPUT CHARACTERISTICS OF N-CHANNEL JFET ........................................... 113
FIG. 6.6:
IGFET/MOSFET TRANSISTORS, STRUCTURES AND TYPES .............................. 116
FIG. 6.7:
ENHANCED -MOSFET WITH N-CHANNEL: CHARGE ACCUMULATION BENEATH
THE GATE 117
ENHANCED -MOSFET WITH N-CHANNEL: THE GATE ACTION.......................... 118
FIG. 6.8:
FIG. 6.9:
ENHANCED -MOSFET WITH N-CHANNEL: SATURATION MODE ....................... 119
FIG. 6.10:
E-MOSFET WITH N-CHANNEL: OUTPUT AND TRANSFER CHARACTERISTICS ... 120
FIG. 6.11:
D-MOSFET WITH N-CHANNEL: OUTPUT AND TRANSFER CHARACTERISTICS ... 121
FIG. 6.12:
MOSFET WITH THE BULK (SUBSTRATE) ELECTRODE ...................................... 121
BIPOLAR SWITCHING DEVICES. (A) THYRISTOR. (B) TRIAC. (C) DIAC ............... 122
FIG. 7.1:
FIG. 7.2:
THYRISTOR. (A) THE STRUCTURE. (B) THE SUBSTITUTE SCHEME ..................... 123
FIG. 7.3:
THYRISTOR. SWITCHING CHARACTERISTIC. ..................................................... 124
FIG. 7.4:
THYRISTOR. PHASE ANGLE TRIGGERED CONTROL ............................................ 125
FIG. 7.5:
DIAC. (A) STRUCTURE. (B) V-I CHARACTERISTIC. ............................................ 127
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Seznam tabulek
TAB. 1:
THE WORK FUNCTION OF SELECTED METALS AND BARRIER HEIGHT IN CASE OF
DIFFERENT SEMI-CONDUCTIVE MATERIALS ....................................................................... 56
TAB. 2:
BIPOLAR JUNCTION TRANSISTOR: MODES OF OPERATION .................................. 79
Electronic Devices
9
1 Electronic devices in bachelor study
From the invention of the transistor at Bell Labs in 1947 the semiconductor technology
have seen tremendous development. On that way high-density microprocessors developed by
the mid of 1980s were only a further milestone aimed in fact to up to day technology which
struggle with physical limits in many technological steps. Surely, silicon and its compounds
using in semiconductor technology are to time the best explored material the mankind know.
This course will focus on practical knowledge of semiconductor technology and on
operation and use of semiconductor devices. The first part is addressed to semiconductor
physics and to basic knowledge concerning the semiconductors. In the second part some
phenomena of semiconductor physics are discussed namely PN junctions, diode and transistor
fundamentals, bipolar and unipolar devices and its operation in different operational
conditions. Basic physical models of the operation of semiconductor devices such as diodes,
MOS transistors, and bipolar junction transistors will be presented including the analysis and
design of important circuits which utilize these devices.
The subject Electronic Devices is established in second semester of bachelor study.
Because of that there is a certain overlap with other subjects dealing with theory of circuits,
electronics, physics and material science. On the other hand the subject Electronic Devices in
many aspects brings the knowledge acquired in these subjects together.
In following chapter atomic and electronic structure of materials is dealt shortly to
define energetic band structure of materials. With help of energy bands diagrams the charge
density in semiconductor is computed and charge transport in semiconductors is explained.
Third chapter aims to explain the operation of semiconductor junctions. Charge build up
in the depletion zone in PN junction is dealt thoroughly and junction parameters as built in
voltage, junction width, barrier and diffusion capacitances and dynamic resistance are
derived. Breakdown mechanisms and dynamic properties of PN junction are discussed to
understand the operation of diodes in different circuits.
In following chapter manufacture processes for different diode types are discussed
shortly. Examples of different diode circuits are given.
In fifth chapter the bipolar junction transistor is dealt. Its operation is explained and the
basic knowledge about transistor circuits as amplifiers, electronic switchers and constant
current sources is given. Computation of transistor circuits is explained using examples of
typical transistor circuits.
Similarly operation of both unipolar transistor types, JFET and IGFET is explained in
next chapter. The depletion and enhanced IGFET types are discussed and computation of
transistor circuits is explained using both graphic and numerical methods.
In seventh chapter is explained operation of bipolar switches with emphasis on thyristor
and triac devices. The turn on mechanisms of thyristor are dealt thoroughly. Power control
using thyristor and triac circuits is discussed and dynamic properties of different types of
thyristors are shortly dealt.
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FEKT Vysokého učení technického v Brně
2 Semiconductor fundamentals
Aim of this chapter is to explain basic definitions from material and semiconductor
science. Atomic and electronic structure of materials is dealt shortly to define energetic band
structure of materials. Coming out from energy band structure charge density in
semiconductor is computed and charge transport in semiconductors is explained.
To understand the fundamental concepts of semiconductors modern physics must be
applied to solid materials. We need to know how many fixed and mobile charges are present
in the material and we need to understand the transport of the mobile carriers through the
semiconductor
In this chapter we start from the atomic structure of semiconductors and explain the
concepts of energy bands, energy band gaps and the density of states in an energy band. We
also show how the current in an almost filled band can more easily be analyzed using the
concept of holes. Next, we discuss the probability that energy levels within an energy band
are occupied. We will use this probability density to find the density of electrons and holes in
a band
Two carrier transport mechanisms will be considered. The drift of carriers in an electric
field and the diffusion of carriers due to a carrier density gradient will be discussed.
Recombination mechanisms and the continuity equations are then combined into the diffusion
equation. Finally, we present the drift-diffusion model, which combines all the essential
elements discussed in this chapter
2.1 The electrons in free atoms
The electrons in free atoms can be found in only certain discrete energy states. These
sharp energy states are associated with the orbits or shells of electrons in an atom. The Bohr
model successfully predicted the energies for the hydrogen atom, Nevertheless there are some
significant failures. The precise details of spectra and charge distribution must be left to
quantum mechanical calculations, as with the Schrodinger equation. Despite this imperfection
the Bohr model gives us a basic conceptual model of electrons orbits and energies.
2.2 The electrons in solids
According the Bohr model electrons of a single free-standing atom occupy atomic
orbitals, which form a discrete set of energy levels. If several atoms are brought together into
a molecule, their atomic orbitals split. Reason for this behavior is that the electron energy
levels can not to be the same - Pauli exclusion principle does not allow it. Consequently we
obtain a set of energy levels ordered so closely that an energy band is formed instead of
original discrete energy levels. This produces a number of molecular orbitals proportional to
the number of atoms. Energy bands are thus the collection of the individual energy levels of
electrons surrounding each atom. When a large number of atoms (of order 1020 or more) are
brought together to form a solid, the number of orbitals becomes exceedingly large, and the
difference in energy between them becomes very small.
Electronic Devices
Fig. 2.1:
11
Theoretical band model of IV. elements unit in depend on the grid spacing
Any solid has a large number of bands, but, as we will see further, only few lie at
energies which are significant for electronic properties of solids. As seen from Fig. 2.1 bands
widths and positions depends upon the properties of the atomic orbitals of atoms from which
the solid is composed and upon the distances and angles in crystalline structure of solid.
Moreover, allowed bands may overlap, producing a single large band.
2.3 Band structure of solids
The energy band model is very important feature for semiconductor devices science. To
describe semiconductors behavior a simplified energy band diagram is used usually. There are
the valence band and conduction band separated by an energy gap between them.
For band diagram following parameters are important:
EV
Energy of the valence band edge indicated by a horizontal line
EV
Energy of the conduction band edge indicated by a horizontal line
EG
Energy gap between valence and conduction band EG and
Evac Vacuum level
The uppermost occupied band in an insulator or semiconductor is called the valence
band by analogy to the valence electrons of individual atoms. The lowermost unoccupied
band is called the conduction band because only when electrons are excited to the conduction
band the current can flow in these materials. Energy interval between conduction and valence
bands is called forbidden band gap. Forbidden band gap strongly influence the electrical and
optical properties of the material. Electrons can transfer from one band to the other by means
of carrier generation and recombination processes.
Electrons at energy bands under the valence band are tightly bound to the atom and are
not allowed to freely move in the material. It means that only the valence electrons (the
electrons in the outer shell) are of interest for electronic devices. Because there are two
electrons with opposite spin on each energy level and the band is formed by splitting of one or
more atomic energy levels the minimum number of states in a band equals twice the number
of atoms in the material. For material properties such electrical and thermal conductivity is
important how the energy levels in bands are occupied.
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FEKT Vysokého učení technického v Brně
The difference between insulators and semiconductors is that the forbidden band gap
between the valence band and conduction band is larger in an insulator. Because one of the
main mechanisms for electrons to be excited to the conduction band is due to thermal energy,
the conductivity of semiconductors and insulators is strongly dependent on the temperature of
the material. Owing to the large bandgap the probability of electron excitation is much less in
case of insulator so that fewer carriers of electric charge are found there and the electrical
conductivity is less. Semiconductors on the other hand contain (relatively) small number of
thermally excited charge carriers. Consequently they have an "almost-empty" conduction
band and an "almost-full" valence band. With this feature they differ from both metals and
insulators.
Metals contain a band that is partly empty and partly filled regardless of temperature.
Therefore they have very high conductivity.
2.3.1
Band structures in different types of solids
Although electronic band structures are usually associated with crystalline materials,
quasi-crystalline and amorphous solids may also exhibit band structures. However, the
periodic nature and symmetrical properties of crystalline materials makes it much easier to
examine the band structures of these materials theoretically. As a result, virtually all of the
existing theoretical work on the electronic band structure of solids has focused on crystalline
materials. In semiconductor industry practically all production is made using mono-crystalline
or crystalline materials.
a) An important feature of an energy band diagram, which is not included on the
simplified diagram, is whether the conduction band minimum and the valence band maximum
occur at the same value for the wavenumber. If so, is called direct. If not, the energy bandgap
is called indirect. This distinction is of interest for optoelectronic devices as LED and laser
diode. Direct bandgap materials provide much more efficient absorption and emission of
light. Mostly used semiconductor silicon and also germanium have indirect energy bandgap.
Gallium arsenide and other semiconductors of AIIIBV group have a direct bandgap.
b) The energy bandgap of semiconductors tends to decrease as the temperature is
increased. By elevated temperature the inter-atomic distances increase as consequence of
increase of the atomic vibrations. This effect cause linear expansion of a material. By
increased inter atomic distances decreases the average potential seen by the electrons in the
material, which in turn reduces the size of the energy bandgap. (The temperature dependence
of the energy bandgap, Eg, has been experimentally determined.)
c) A direct modulation of the inter-atomic distance caused by compressive or tensile
stress can also bring an increase or decrease of the energy bandgap.
d) The energy bandgap of semiconductors tends to decrease by high doping densities.
The average distance between two impurities is very small in this case, impurities therefore
interact each to other forming an energy band rather than a discreet level. The effect starts by
doping density higher then 1018 cm-3.
2.4 Preparation of semiconductor materials
The level of chemical purity needed is extremely high because the presence of
impurities even in very small proportions can have large effects on the properties of the
material. A high degree of crystalline perfection is also required, since faults in crystal
structure (such as dislocations, twins, and stacking faults) change the properties of the
Electronic Devices
13
material. Crystalline faults are a major cause of defective semiconductor devices. The larger
the crystal, the more difficult it is to achieve the necessary perfection. Current mass
production processes use crystal ingots between four and twelve inches (300 mm) in diameter
which are grown as cylinders and sliced into wafers.
Because of the required level of chemical purity, and the perfection of the crystal
structure which are needed to make semiconductor devices, special methods have been
developed to produce the initial semiconductor material. A technique for achieving high
purity semiconductors includes growing the crystal using a special process called Czochralski
process. An additional step that can be used to further increase purity is zone refining. In zone
refining part of a solid crystal is melted. The impurities tend to concentrate in the melted
region, while the desired material recrystallizes leaving the solid material more pure and with
fewer crystalline faults.
2.4.1
Intrinsic semiconductors
Intrinsic semiconductor (or i-type semiconductor), is a pure semiconductor without any
significant structure defects and dopant species. The presence and type of charge carriers is
then determined by the material itself. In thermal equilibrium the amount of free electrons
depends on the bandgap and on the temperature.
n = p = ni
( 2.1 )
When electron is excited to move freely in the semiconductor lattice than by atom of
free electron origin there remain a vacant place in the chemical bond between semiconductor
atoms. Such vacant place can be filled by an electron from neighboring atom, the vacant place
with positive charge displaces, new vacant place can be filed again.... etc., finally resulting in
hopping of valence electrons from one bonds to the other and in moving of the positive
charge. This moving positive charge is called hole to differ from electron motion in
conductivity band.
Fig. 2.2:
Electron and hole generation for intrinsic semiconductor
Holes behave as particles with the same properties as the electrons would have except
that they carry a positive charge. However it is important to understand that the charge
movement is done by displacement of electrons which are the only real charged particles
available in a semiconductor. Because the mechanism of charge movement is more complex
in this case, holes have allways lower mobility then electrons. The concepts of holes was
introduced in semiconductors science because it is easier to keep track of holes, rather than
keeping track of the actual electrons in almost full valence band.
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FEKT Vysokého učení technického v Brně
In case of intrinsic semiconductors the amount of electrons and holes is roughly equal
and depends on the bandgap and on the temperature. Intrinsic semiconductors conductivity is
therefore given by present crystal defects and by thermal excitation.
2.4.2
Doped semiconductors
An N-type semiconductor is obtained by adding an impurity of valence-five elements
to the semiconductor in order to increase the number of free electrons. Atoms of the doping
material give away weakly-bound outer electrons. This type of doping agent is labeled as
donor material since it gives away (donates) one of its electrons.
Fig. 2.3:
Si crystal lattice with one atom of donor and band model for N type
To understand how n-type doping is accomplished, consider the case of silicon (Si). Si
atoms have four valence electrons, each of which is covalently bonded with one of four
adjacent Si atoms. If an atom with five valence electrons (P, As or Sb) is incorporated into the
crystal lattice in place of a Si atom, then that atom will have four covalent bonds and one
unbonded electron. This extra electron is only weakly bound to the atom and can easily be
excited into the conduction band.
At normal temperatures, virtually all such electrons are excited into the conduction
band. Since excitation of these electrons does not result in the formation of a hole, the number
of electrons in such a material far exceeds the number of holes. In this case the electrons are
labeled as the majority carriers and the holes as the minority carriers. Note that each movable
electron within the semiconductor is never far from an immobile positive dopant ion, and the
N-doped material normally has a net electric charge of zero.
A P-type semiconductor is obtained in the same process as N-type only the doping
species is a trivalent atom (B, In, Al). The result is that one electron is missing from one of
the four covalent bonds normal for the silicon lattice. As a consequence, when trivalent atom
is added, it takes away (accepts) weakly-bound outer electrons from neighboring
semiconductor atoms to complete the fourth bond. Such dopants are therefore called
acceptors. When the dopant atom accepts an electron, one bond electron from the
neighboring atom is lost. This process result in the formation of another bond with missing
electron. This vacant bond is called hole and because of one missing electron it has positive
charge.
Electronic Devices
Fig 2.4:
15
Si crystal lattice with one atom of acceptor and band model for P type
Each hole is associated with a nearby negative-charged dopant ion, and the
semiconductor remains electrically neutral as a whole. When a sufficiently large number of
acceptor atoms are added, the holes greatly outnumber the thermally-excited electrons. The
holes are then the majority carriers, while electrons are the minority carriers in P-type
materials.
In general, an increase in doping concentration cause an increase in conductivity due to
the higher concentration of carriers available for conduction. By doped semiconductors the
carrier concentration is determined by the concentration of dopant introduced to an intrinsic
semiconductor. In addition the dopant indirectly affects also other electrical properties.
Doping a semiconductor crystal introduces allowed energy states within the band gap
but very close to the energy band that corresponds with the dopant type. Donor impurities
create states near the conduction band while acceptors create states near the valence band (see
the Fig. 2.3 and Fig 2.4). The gap between these energy states and the nearest energy band is
usually referred to as dopant-site bonding energy or EB and is relatively small. For example,
the EB for boron in silicon bulk is 45 meV, compared with silicon's band gap of about 1.12
eV. Because EB is so small, it takes little energy to ionize the dopant atoms and create free
carriers in the conduction or valence bands. Usually the thermal energy available at room
temperature is sufficient to ionize most of the dopant atoms.
2.4.3
Degenerately doped semiconductors
Degenerately (very highly) doped semiconductors have conductivity levels comparable
to metals and are often used in modern integrated circuits as a replacement for metal. Often
superscript plus and minus symbols are used to denote relative doping concentration in
semiconductors. For example, n+ denotes an n-type semiconductor with a high (often
degenerate) doping concentration. Similarly, p− would indicate a very lightly doped p-type
material. It is useful to note that even degenerate levels of doping imply low concentrations of
impurities with respect to the base semiconductor. In crystalline intrinsic silicon, there are
approximately 5×1022 atoms/cm³. Doping concentration for silicon semiconductors range
from 1013 cm-3 up to 1018 cm-3. Doping concentration above about 1018 cm-3 is considered
degenerate at room temperature.
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FEKT Vysokého učení technického v Brně
2.4.4
Control question and example for capture 2.4
1.
a) What are doped semiconductors? b) Why we use them?
2.
What are intrinsic semiconductors?
3.
a) What are doped semiconductors? b) Explain how they are produced
4.
Explain the origin of the electron conductivity of solids
5.
Explain the origin of hole conductivity of solids
2.5 Carrier density
To calculate the density of carriers in a semiconductor we need to know the number of
available states at each energy and we also need to know the probability that at a given energy
the state at is occupied by an electron. The number of electrons at each energy level will be
then obtained by multiplying the number of states with the probability that a state is occupied
by an electron.
It is obvious that the number of energy levels is very large and depends on the volume
of the semiconductor. Therefore is very convenient to calculate the number of states per unit
energy and per unit volume. This parameter is called density of states.
2.5.1
Density of states
For given energy level density of states in a semiconductor equals the number of states
per unit volume.
Density of energy states in a band is not uniform. It approaches zero at the band
boundaries, and is generally greatest near the middle of a band.
For energy close to the lower edge of the conduction band the density of states is
gC (E) =
mn* 2mn* (E − E C )
π 2h3
= konst. E − E C , E ≥ EC
( 2.2 )
And likewise for energy close to upper edge of the valence band:
gV ( E ) =
m *p 2m *p (EV − E )
π h
2
3
= konst. EV − E , E ≤ EV
( 2.3 )
Here gV(E) gC(E) are density of states in conduction and valence bands respectively, m*
and m* are effective mass for electrons and holes and h is Dirac constant.
Electronic Devices
Fig 2.5:
17
General energy depend of gC(E) and gV(E)
Shape of both functions is seen on the Fig 5. It is obvious that for the narrow energy
range from E to E + dE the number of allowed energy levels per unit volume of the material
is g(E) dE.
2.5.2
The Fermi-Dirac distribution function
Although the number of states in all energy bands is effectively infinite, in an uncharged
material the number of electrons is equal only to the number of protons in the atoms of the
material. Therefore not all of the states which can be occupied by electrons are filled at any
time. The likelihood of any particular state being filled at any temperature is given by the
Fermi-Dirac distribution function:
f (E) =
1
E − E 
F
1 + exp 
 kT 

( 2.4 )

where:
k
is Boltzmann´s constant
T
is the temperature,
EF
is the Fermi energy (or 'Fermi level').
The Fermi-Dirac distribution function is visualized on Fig 2.6. Regardless of the
temperature, f(EF) = 1/2. At T=0, the distribution is a simple step function. At nonzero
temperatures, the step "smooths out", so that an appreciable number of states below the Fermi
level are empty, and some states above the Fermi level are filled. In condition of thermal
equilibrium the Fermi function therefore gives the probability that an energy level at energy E
is occupied by an electron. The system is thus characterized by its temperature, T, and its
Fermi energy, EF.
Fig. 2.6:
Energy depend of Fermi-Dirac function a) T → 0 K, b) general depend
18
FEKT Vysokého učení technického v Brně
Note:
a) Electrons are Fermions, the half-integer spin particles, which obey the Pauli
exclusion principle.
The Pauli exclusion principle postulates that only one Fermion can occupy a single
quantum state. The states with the lowest energy are filled first, followed by the next higher
ones. At absolute zero temperature (T = 0 K), the energy levels are all filled up to a maximum
energy, which we call the Fermi level. No states above the Fermi level are filled.
b) For energies more than a few times kT below the Fermi energy the Fermi function
has a value of one.
c) If the energy equals the Fermi energy Fermi function equals 1/2. Finally, it decreases
exponentially for energies which are a few times kT larger than the Fermi energy.
d) Near the absolute zero at T = 0 K the Fermi function is a step function.
e) At finite temperatures the transition is more gradual and by high temperatures the
slope of the curve is less and less giving thus high probability of high energy states.
2.5.3
Filling of bands
n ( E ) = f ( E ) gV E
( 2.5 )
Where gC(E) is the density of states in the valence band.
Probability of having a hole occupied state equals the probability that a particular state
is not filled by electron because holes correspond to empty states in the valence band. Using
[1- f(E)] for hole instead f(E) the hole density per given energy, p(E), equals:
p( E ) = [1 − f ( E )]gV ( E )
( 2.6 )
Where gV(E) is the density of states in the valence band.
Graphic visualization of band filling of bands for intrinsic semiconductor and both
doped p-type and n-type respectively is visualized on Fig 2.7.
Fig. 2.7:
type
Band filling of bands for intrinsic semiconductor and both doped p-type and n-
Electronic Devices
2.5.4
19
Calculation of carrier densities
The density of carriers can be obtained by integrating the density of carriers per unit
energy over all possible energy states within a given band. The integral is taken from the
bottom of the conduction band Ec, to the top of the conduction band for electrons in the
conduction band and, similar way, from the upper energy of the valence band EV to the
bottom of valence band for holes in valence band.
Eroof
n = ∫ f (E )g C (E )dE
( 2.7 )
EC
Where gC(E) is the density of states in the conduction band and f(E) is the Fermi
function.
For holes, using [1-/f(E)] for probability of occupancy, we get:
p=
EV
∫ [1− f (E )]g V (E )dE
( 2.8 )
Ebottom
After substitution for density of states and FD distribution function we obtain:
n=
p=
m∗n 2mn∗
π h
2
3
m∗p 2m∗p
π h
2
3
Eroof
∫
EC
E - EC dE
1+exp[(E - E F ) / kT ]
exp[(E - E F ) / kT ] EV - E dE
EV
∫
Ebottom
1+exp[(E - E F ) / kT ]
( 2.9 )
( 2.10 )
And after integration the result is:
n = N C exp[−( EC − E F ) / kT ]
( 2.11 )
p = N V exp[−( E F − EC ) / kT ]
( 2.12 )
where NC is the effective density of states in the conduction band and NV is the
effective density of states in the valence band.
The effective density of states NC , NV are as follows:
 2π m∗ kT 
n

NC = 2
2
h




3/ 2
 2π m∗ kT 
n

NV = 2 
2
h




3/ 2
= konst ⋅ T 3 / 2
( 2.13 )
= konst ⋅ T 3 / 2
( 2.14 )
Note that the effective density of states is temperature dependent.
Equations (( 2.11 )( 2.12 )) are not much convenient for practical computation. In case
of intrinsic semiconductor we can substitute EF = Ei and n = p = ni . We obtain:
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FEKT Vysokého učení technického v Brně
ni = N C exp[−( EC − Ei ) / kT ]
( 2.15 )
ni = N V exp[−( Ei − EC ) / kT ]
( 2.16 )
and:
N C exp(− EC / kT = ni exp(− Ei / kT )
( 2.17 )
N V exp( EV / kT ) = ni exp( Ei / kT )
( 2.18 )
Using the equations ( 2.17 ) and ( 2.11 ) densities of carriers as a function of the
intrinsic density and the intrinsic Fermi energy Ei can be derived:
n = ni exp[( E F − Ei ) / kT ]
( 2.19 )
p = ni exp[(Ei − E F ) / kT ]
( 2.20 )
Equations ( 2.19 ) and ( 2.20 ) can be used to find the electron and hole density in a
semiconductor (in thermal equilibrium.) Value of intrinsic concentration is usually, as
important semiconductor parameter, known. Of course to computation we need the level of
Fermi energy.
By multiplying the expressions for the electron and hole densities in a non-degenerate
semiconductor, as in equations ( 2.19 ) and ( 2.20 ) one obtains:
n ⋅ p = n i2
( 2.21 )
For any non-degenerate semiconductor the product of the electron and hole density
equals the square of the intrinsic carrier density. This important property is referred to as the
mass action law.
However it is valid only for non-degenerate semiconductors in thermal equilibrium.
From this relation it is possible to find the hole density if the electron density is known or vice
versa.
The value of intrinsic density can be estimated from product of equations ( 2.11 ) and (
2.12 ) :
ni2 = N C N V exp[−( E C − EV ) / kT ] = N C N V exp(− E G / kT )
( 2.22 )
And after square root:
n = N C N V exp(− E G / 2kT ) = konst ⋅ T 3 / 2 ⋅ exp(− E G / 2kT )
( 2.23 )
Intrinsic density depends on temperature and semiconductor bandgap EG. For silicon by
room temperature intrinsic density is about ni = 1,45.1010 cm-3.
Electronic Devices
Fig. 2.8:
21
Thermal dependence of intrinsic carriers density for GaAs, Si and Ge
2.5.5
Calculation of Fermi energy level
In case of intrinsic semiconductor we can find the intrinsic Fermi energy using the
above equations ( 2.11 ) and ( 2.19 ) for the intrinsic electron and hole density:
N C exp[(E F − EC ) / kT ] = N V exp[( EV − E F ) / kT ]
( 2.24 )
From this equation we can obtain EF easily. After substitution for NV and NC we get:
E + E kT  N
E F = C V + ln V
2
2  NC
*
 EC + EV kT  m p 
 =
+
ln
2
2  mn* 

3/ 2
( 2.25 )
The intrinsic Fermi energy is half way between the conduction and valence band edge
(midgap energy). The intrinsic Fermi energy can also be expressed as a function of the
effective masses of the electrons and holes in the semiconductor.
By doped (extrinsic) semiconductor we can suppose that carriers density equals the
density of impurities. So for electrons (n = ND) we get:
N D = ni exp[( E F − Ei ) / kT ]
( 2.26 )
The position of Fermi energy EF in respect to intrinsic energy Ei is:
E F − Ei = kT ln( N D / ni )
( 2.27 )
And similarly for holes
Ei − E F = kT ln( N A / ni )
( 2.28 )
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FEKT Vysokého učení technického v Brně
Position of Fermi energy in semiconductor bandgap depends on concentration (density)
of impurities.
The dependence of Fermi level for silicon is visualized on Fig. 2.9. By low
concentration the change is very rapid (the same as logarithm does). By high density of
impurities the dependence in semilogarithmic plot is almost linear. When the distance of
Fermi energy from the edge of valence or conductivity band is less then about 3KT, the
semiconductor is regarded as degenerated.
Fig. 2.9: a) The level of Fermi energy in Silicon in dependence on concentration of
impurities. b) Temperature dependence of Fermi energy is taken in marked points for both Ntype and P-type.
T1 and T2 correspond with carriers activation from impurities and from semiconductor
lattice respectively (see also Fig. 2.10) . The level of intrinsic energy Ei grows with
temperature (see equ. ( 2.25 )). The bangap energy diminish with temperature with coefficient
approximately 10-4 eVK-1.
Fig. 2.10: Temperature dependence of carriers density for N-type semiconductor in linear
scale a 1/T scale for temperature.
Electronic Devices
2.5.6
23
Generation and recombination processes
Carrier generation and recombination result from interaction between electrons and
other carriers, or with the lattice of the material, or with optical photons. As the electron
moves from one energy band to another, the energy which is gained or lost in this process
take different forms. The form of energy transformed during electron transition distinguishes
various types of generation and recombination.
2.5.6.1 Generation of free carriers
In thermal equilibrium electrons can gain energy for transition from valence to
conductivity band only from thermal vibrations of the semiconductor lattice. The number of
generated carriers is therefore very low. In addition to thermal generation there are other
mechanism described as follows.
Carriers can be generated by illuminating the semiconductor with light. The energy of
the incoming photons is used to bring an electron from a lower energy level to a higher energy
level. If the photon energy is large enough, an electron raised from the valence band into an
empty conduction band state, and one electron-hole pair is generated. The photon energy
needs to be larger than the bandgap energy to satisfy this condition. The excess energy, Eph –
EG, is added to the electron and the hole in the form of kinetic energy. As the energy of the
photon is given off to the electron, the photon does not exist any longer.
Because of light absorption the light intensity in a semiconductor decreases with
distance from surface. The calculation of the generation rate of carriers therefore requires first
a calculation of the optical power within the structure from which the generation rate can then
be obtained.
Note:
After impact to the semiconductor photons are mostly absorbed generating a pair of free
carriers. Absorption is the active process in photodiodes, solar cells, and other semiconductor
photodetectors. Nevertheless a photon can also stimulate a recombination event, resulting in a
generated photon with similar properties to the original photon responsible for the event.
Original photon is not absorbed by such interaction. This process results in stimulated
emission which is basic mechanism for laser action in laser diodes.
Carrier generation or ionization due to a high-energy beam consisting of charged
particles is similar except that the available energy can be much larger than the bandgap
energy so that multiple electron-hole pairs can be formed. The high-energy particle gradually
loses its energy and eventually stops. This generation mechanism is used in semiconductorbased nuclear particle counters. As the number of ionized electron-hole pairs varies with the
energy of the particle, one can also use such detector to measure the particle energy.
Finally, there is a generation process called impact ionization, the generation
mechanism that is the counterpart of Auger recombination. Impact ionization is caused by an
electron (hole) with an energy, which is much larger (smaller) than the conduction (valence)
band edge. The excess energy is given off to generate an electron-hole pair through a band-toband transition. This generation process causes avalanche multiplication in semiconductor
diodes under high reverse bias: As one carrier accelerates in the electric field it gains energy.
The kinetic energy is given off to an electron in the valence band, thereby creating an
electron-hole pair. The resulting two electrons can create two more electrons which generate
four more causing an avalanche multiplication effect. Electrons as well as holes contribute to
avalanche multiplication.
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FEKT Vysokého učení technického v Brně
2.5.6.2 Recombination of free carriers
Recombination of electrons and holes is a process by which both carriers annihilate
each other: As a result of this process electrons ends to occupy the empty state associated with
a hole. This process proceeds through one or multiple steps. The energy difference between
the initial and final state of the electron is released several ways:
a) Radiative recombination - electron energy is emitted in the form of a photon.
b) Non-radiative recombination - electron energy is given to one or more phonons.
c) Auger recombination - electron energy is transformed to kinetic energy of another
electron.
Band-to-band recombination occurs when an electron moves from its conduction
band state into the empty valence band state associated with the hole. The recombination rate
depends on the density of available electrons and holes. Both carrier types need to be
available in the recombination process. Therefore, the rate is expected to be proportional to
the product of n and p. Also, in thermal equilibrium, the recombination rate must equal the
generation rate since there is no net recombination or generation.
Note:
Band-to-band transition mechanism is typically also for a radiative transition in direct
bandgap semiconductors. During radiative recombination a photon is emitted with the
wavelength corresponding to the energy released. This effect is called spontaneous emission
an it is the basis of LEDs operation. Because the photon carries relatively little momentum,
radiative recombination is significant only in direct bandgap materials.
Trap-assisted recombination occurs when an electron falls into a "trap", an energy
level within the bandgap caused by the presence of a foreign atom or a structural defect. Once
the trap is filled it cannot accept another electron. The electron occupying the trap, in a second
step, moves into an empty valence band state, thereby completing the recombination process.
One can envision this process as a two-step transition of an electron from the conduction band
to the valence band. The impurity state can absorb differences in momentum between the
carriers, and so this process is the dominant generation and recombination process in silicon
and other indirect bandgap materials. The energy is exchanged in the form of lattice vibration,
or phonon, exchanging thermal energy with the material. This process is referred as ShockleyRead-Hall (SRH) recombination.
Auger recombination involves three particles: an electron and a hole, which recombine
and third particle which overtake the resulting energy excess without moving to another
energy band. After the interaction, the third carrier normally loses its excess energy to thermal
vibrations. The involvement of a third particle affects the recombination rate so that we need
to treat Auger recombination differently from band-to-band recombination. The density of the
electrons or holes, which can receive the released energy from the electron-hole annihilation
is very important. Practically Auger recombination takes place only by very high densities of
carriers. Moreover, the Auger generation process is not easily produced, because the third
particle would have to begin the process in the unstable high-energy state.
Recombination at surfaces and interfaces can have a significant impact on the
behavior of semiconductor devices. This is because surfaces and interfaces typically contain a
large number of recombination centers because of the abrupt termination of the
semiconductor crystal, which leaves a large number of electrically active states. In addition,
Electronic Devices
25
the surfaces and interfaces are more likely to contain impurities since they are exposed during
the device fabrication process.
2.5.6.3 Thermal equilibrium
Each of previoulsy described recombination mechanisms can be reversed leading to
carrier generation rather than recombination. A single expression will be used to describe
recombination as well as generation for each of the above mechanisms.
In addition, there are generation mechanisms, which do not have an associated
recombination mechanism, such as generation of carriers by light absorption or by a highenergy electron or particle beam. These processes are referred to as ionization processes.
Impact ionization, which is the generation mechanism associated with Auger recombination,
also belongs to this category.
To denote the carriers density in thermal equilibrium we will use “0” index for both
holes and electrons. Then we will have for thermal equilibrium condition:
p 0 n0 = ni2
( 2.29 )
n = n0 + ∆n
( 2.30 )
p = p 0 + ∆p
( 2.31 )
When the difference is positive we talk about an injection of carriers. When the
difference is negative the process is called extraction.
A simple model for the recombination-generation mechanisms states that the
recombination-generation rate is proportional to the excess carrier density. It acknowledges
the fact that no net recombination takes place if the carrier density equals the thermal
equilibrium value.
Example 2.1:
For silicon with donor density ND = 1014 cm-3 we will have injection of electrons and
holes ∆n = ∆p = 109 cm-3. For this semiconductor material n0 ≈ ND = 1014 cm-3 a p0 ≈
ni2/ND ≈ 106 cm-3. Then n = n0 + ∆n ≈ n0 ≈ 1014 cm-3
Solution
p = p0 + ∆p ≈ ∆p = 109 cm-3
When we compare n.p product in equilibrium and under carriers injection we see that
the injection of majority carriers cause practically no change while injection of minority
carriers brings the semiconductor far from thermal equilibrium.
n0 p0 = ni2 = 1014 106 cm-3 = 1020 cm-3
np = 1014 109 cm-3 = 1023 cm-3
26
FEKT Vysokého učení technického v Brně
Conclusion: Minority carriers influence thermal equilibrium.
Based on considerations above it is obvious that the resulting expression for the
recombination or generation of electrons in a p-type semiconductor can be written as:
∂n p
∂t
∂n n
∂t
=−
G−R
=−
G−R
∆n p
τn
∆nn
τp
( 2.32 )
( 2.33 )
where the parameter τ can be interpreted as the average time after which an excess
minority carrier recombines.
For each of the different recombination mechanisms the recombination rate can be
simplified to this form when applied to minority carriers in a "quasi-neutral" semiconductor.
The above expressions are therefore only valid under these conditions.
Because of recombination processes the lifetime of minority carriers is much shorter
than lifetime of majority carriers. In medium quality silicon the lifetime of minority carriers is
about 1 µs. In case of structurally and chemically pure materials the lifetime can be about 1
ms, but when some structural defects or impurities (traps) are present the lifetime can be as
short as 1 ns.
Note:
1. The recombination rates of the majority carriers equals that of the minority carriers
since in steady state recombination involves an equal number of holes and electrons.
Therefore, the recombination rate of the majority carriers depends on the excess-minoritycarrier-density as the minority carriers limit the recombination rate.
2. Recombination in a depletion region and in situations where the hole and electron
density are close to each other cannot be described with the simple model and the more
elaborate expressions for the individual recombination mechanisms must be used.
2.6 Transport of carriers
Electric current is caused by motion of free carriers. In principle there are two transport
mechanisms of carriers in semiconductor:
1. The motion of carriers can be caused by an electric field. The transport mechanism is
called as carrier drift.
2. When the motion is caused by difference in carriers concentration we describe the
mechanism as carrier diffusion. This carrier transport mechanism is due to random motion of
the carriers in consequence of the thermal energy in semiconductor lattice.
When neglecting generation and recombination phenomena the total current in a
semiconductor equals the sum of the drift and the diffusion current for both holes and
electrons.
Electronic Devices
2.6.1
27
Carrier drift
In the absence of electric field, the carriers exhibit random motion depending on their
thermal energy. In an electric field the random motion still exists but in addition, there is a
motion caused by electrostatic force. The carriers first accelerate until they are moderate due
to collisions and lattice vibrations. Consequently they reach a constant average velocity, v.
Holes move in the direction of the applied field because of their positive charge. Electrons
move in the opposite direction.
The carrier motion in the semiconductor in the presence of an electric field is visualized
in Fig. 2.11.
Because of thermal motion the carriers constantly change direction and velocity due to
scattering and do not exactly follow a path along the electric field lines.
Fig. 2.11: The carrier motion in the semiconductor in the presence of an electric field.
a) macroscale; b) microscale
A typical drift velocity in semiconductors is not much higher than about 104 cm/s. This
is much less than the typical thermal velocity at room temperature which reach up to 107 cm/s.
Fig. 2.12: Drift current of holes through p-type semiconductor
Investigating motion of carriers caused by an electric field we can consider the average
velocity, vd of the carriers. Then, for example, considering the area A with uniform current
flow (see Fig. 2.12) for holes the drift current is given as:
I p , drift = qpv d A
( 2.34 )
Where p is the hole density in the semiconductor.
And the hole current density:
J p , drift = qpv d
( 2.35 )
28
FEKT Vysokého učení technického v Brně
By low electric field intensity, the velocity vd is proportional to the applied electric
field. Velocity to field ratio is called mobility, µ. The drift velocity for holes can be now
described as:
vd = µ p E
( 2.36 )
Where µp is hole mobility.
Then the drift current density for electrons and holes respectively is:
J p , drift = qµ p pE
( 2.37 )
J n ,drift = qµ n nE
( 2.38 )
Here µp is electron mobility.
The linear relationship between the applied field and the average carrier velocity is valid
only for relatively low electric field - see the Fig. 2.13. In high electric field the carriers are
decelerate due to collisions and lattice vibrations.
Fig. 2.13: Electrical field dependence of mobility for electrons and holes in silicon by
temperature 300 K.
Because the motion of the hole is in fact the hopping of electrons between valence
bonds the mechanism of hole motion is more complicated and because of that the holes have
always lesser mobility then electrons. In case of silicon the difference is considerable. For
electrons the mobility is µn = 1300 cm2V-1s-1 while for holes the mobility is µp=490 cm2V-1s-1.
The scattering mechanisms are as follows:
1. At high electric fields the velocity of carriers saturates because of scattering with
semiconductor lattice.
2. Additional scattering occurs at the surface of a semiconductor due to surface or
interface scattering mechanisms.
3. Efficient scattering centers are impurities in the semiconductor lattice. Ionized donors
and acceptors are here typical example. Larger impurity concentrations result in a lower
mobility. The mobility of electrons and holes in silicon at room temperature in dependence on
density of donor and acceptor impurities is shown in Fig. 2.14.
Electronic Devices
29
Fig. 2.14: The mobility of electrons and holes in silicon at room temperature in dependence
on density of donor and acceptor impurities (by temperature 300 K).
Electrical conductivity of semiconductors is given by sum of both electron and hole
current:
J drift = J p ,drift + J n, drift = q ( µ n n + µ p p ) E
( 2.39 )
Here the electrical conductivity is:
σ = q( µ n n + µ p p)
( 2.40 )
In case of doped (extrinsic) semiconductors the density of majority carriers is given by
dopant density while density of minority carriers several order lesser. It means that the
minority carriers have practically no influence on electrical conductivity of extrinsic
semiconductor. Consequently, the electrical conductivity for N-type and P-type
semiconductor respectively is:
σ = qµ n N D
( 2.41 )
σ = qµ p N A
( 2.42 )
2.6.2
Carrier diffusion
Carrier diffusion is based on random motion of the carriers which is due to the thermal
energy in the semiconuctor lattice. When the distribution of carrier density is not uniform this
random motion cause the net flow of carriers from regions where the density is high to
regions where the density is low.
Diffusion of carriers is controlled by the gradient of the carrier density. For example
such gradient can be consequence of different doping density or in the case of a thermal
gradient in the semiconductor device.
In material with a uniform distribution of carrier density this process does not yield a
net flow as the carriers replace each other during its random motion.
Diffusion process and corresponding density of electrical current is schematically
visualized on the Fig. 2.15.
30
FEKT Vysokého učení technického v Brně
Fig. 2.15: The scheme of the diffusion process and corresponding current density for
electrons and holes.
For the particle density, c, the diffusion process is expressed by the first Fick law:
 ∂c ∂c ∂c 
J = − D , ,  = − Dgrad ⋅ c
 ∂x ∂y ∂z 
( 2.43 )
Where D [m2s-1] is diffusion coefficient.
Considering the gradient of carrier density the diffusion current density for electrons
and holes respectively is:
J n ,dif = qDn
dn
dx
J p , dif = − qD p
( 2.44 )
dp
dx
( 2.45 )
Where Dn is diffusion coefficient for electrons and Dp is diffusion coefficient for holes.
The total current density is obtained by adding the diffusion current and the drift current
for both electrons and holes:
J X = qE X ( µ p p + µ n n) + q ( Dn
dn
dp
− Dp )
dx
dx
( 2.46 )
Despite that diffusion is caused by thermal energy and the carriers drift is caused by an
electric field
diffusion and drift mechanism are related. Apparent reason there is that the same
particles and the same scattering mechanisms are involved. Between diffusion coefficient and
mobility is a well known relationship, often referred to as the Einstein relation:
Dn
µn
=
Dp
µp
=
kT
= UT
q
( 2.47 )
Here Kt/q is e thermal voltage UT. For temperature of 300 K the value of UT is
approximately 26 mV.
Formula ( 2.45) is useful for some considerations in theory of semiconductors; see
further.
Electronic Devices
2.6.3
31
Control questions and examples
1.
Two pieces of the same semiconductor (silicon) one of them is p-type and one of
them is n-type, contain impurities with constant (homogeneous) concentrations
ND = NA. Which of the pieces has greater resistance? Explain.
2.
Explain how the Fermi level position depends on the type of semiconductor and
on the impurity concentration.
3.
Explain how the Fermi level position depends on temperature.
4.
a) Draw a typical graph of the temperature dependence of carrier concentration
(both electrons and holes) in n type semiconductor with ND >> ni. Choose
appropriate temperature interval to demonstrate the effect of all possible
activation energies.
5.
Explain the effect of impurity atoms and lattice imperfections at semiconductors.
3 PN Junction
Aim of this chapter is to explain operation of semiconductor junctions. Charge build up
in the depletion zone in PN junction is explained thoroughly. Junction parameters as built in
voltage, junction width, barrier and diffusion capacitances and dynamic resistance are
derived. Breakdown mechanisms and dynamic properties of PN junction are dealt.
The PN junction is a basic part of all semiconductor electronic devices. One junction
device – diode - can be used as a rectifier, as a voltage dependent capacitor and as current
dependent resistor. In addition, they can be used as optoelectronic receivers, solar cells, light
emitting diodes or laser diodes. PN junction can be also used as an isolation structure. Bipolar
Junction Transistors (BJTs) which are used as amplifier and switch have two junctions.
Devices with more than two PN junctions are used in power electronics. Most known among
them are tyristor and triac. PN Junction can be also found in Field-Effects-Transistors which
are not only in integrated circuits in each PC but also in LCD displays, mobile phones etc.
3.1 Structure and principle of operation
A PN junction consists of two semiconductor regions with opposite doping type - Ptype with an acceptor density NA, and N-type with a donor density ND. To simplify the
investigation we will assume that both regions are doped uniformly and that the transition
between regions P and N is abrupt. Such structure is caled an abrupt PN junction (see Fig.
3.1a). Usually one side is higher-doped than the other. We will find later that in such a case
the device characteristics are determines mostly by the low-doped region.
In thermal equilibrium no external voltage is applied between the n-type and p-type
material. The processes involved can be shortly summarized as follows:
1. Because of very high gradient of carrier density (see Fig. 3.1b). the diffusion of
carriers must take place. Both electrons and holes which are close to the metallurgical
junction diffuse across the junction into the opposite part of the junction where they change to
32
FEKT Vysokého učení technického v Brně
minority carriers. This way a thermal equilibrium is disturbed (by injection of minority
carriers) and as consequence very strong recombination takes place.
Fig. 3.1:
Asymmetric PN junction
Electronic Devices
33
2. Carriers which diffuse to the opposite part of the junction leave behind the ionized
dopants namely positive donor ions in N-type and negative acceptor ions in P-type.
Consequently a narrow region around the metallurgical junction is depleted of mobile
carriers. Thus in thermal equilibrium there is positive charge of ionised donors in P-type
region and negative charge of ionized acceptors in N-type region (see Fig. 3.1c). Both charges
have the same absolute value so the junction region is electrically neutral.
3. The charge due to the ionized donors and acceptors causes an electric field (see Fig.
3.1d). which in turn causes a drift of carriers in the opposite direction.
4. The diffusion of carriers continues until the drift current balances the diffusion
current, thereby reaching thermal equilibrium.
5. Near the metallurgical junction is a narrow region where no carriers are present (as a
consequence of carriers diffusion) but only ionized donors and acceptors. We call this region
the depletion region. (In Fig. 3.1) the depletion region begins at x = -xp and reach up to x =
xn.)
6. Because of built in charge there is a built-in potential across the depletion region (see
Fig. 3.1e). Sometime this potential difference is called Diffusion Potential.
7. In P-type semiconductor the Fermi level is near the valence band while in N-type
semiconductor the Fermi level is near the conductivity band. On the other hand there is an
important law in thermodynamic which predict that in thermal equilibrium the Fermi energy
must have the same level in whole material volume. To fulfil both requirements the band
diagram must be bent near the metallurgical junction (see the Fig. 3.1f). The energy
difference is given by built in (diffusion) potential ∆E = q.UD.
3.1.1
Built in potential
In thermal equilibrium the diffusion of carriers is balanced by the drift current because
of electric field in the depletion region:
J = Jn = J p = 0
( 3.1 )
For electron and hole current density we obtain:
J n = J n, drift + J n, dif = qµ n nE + qDn
dn
=0
dx
J p = J p ,drift + J p ,dif = qµ p pE − qD p
dp
=0
dx
( 3.2 )
( 3.3 )
Further we use the Einstein relation:
 qD   dn 
 D   1   dn 
 kT   1   dn 
E =  − n    = − n      = −      
 q   n   dx 
 qµ n   dx 
 µ n   n   dx 
( 3.4 )
And now we can compute the built in potential as:
+∞
kT
U D = − ∫ Edx =
q
−∞
+∞
n ( +∞ )
kT
dn kT
n ( +∞ )
 1   dn 
∫−∞ n   dx dx = q n ∫−∞ n = q [ln n] n( −∞)
( )
The limits for integration are:
( 3.5 )
34
FEKT Vysokého učení technického v Brně
ni2
NA
( 3.6 )
n(+∞) = n n = N D
( 3.7 )
n(−∞) = n p =
Finally we obtain the built in potential (or diffusion potential) as:
UD =
kT
kT  nn 
ln nn − ln n p =
ln 
q
q  n p 
(
)
( 3.8 )
And using the equations 3.6 and 3.7 we obtain:
UD =
kT  N D N A 
ln

q  ni2 
( 3.9 )
Example 3.1:
By room temperature (T = 300 K) is thermal voltage UT = kT/q ≅ 0,026 V . Consider a
PN junction in silicon (ni = 1016 m-3 = 1010 cm-3). P region is acceptor doped to the
density NA = 1021 m-3 = 1015 cm-3 while N region is donor doped to the density ND = 1021
m-3 = 1015 cm-3.
Using the equ. ( 3.9 ) we can compute built in potential:
 1015 ⋅ 1015 

U D = 0,026 ⋅ ln
20
 10

( 3.10 )
Owing to logarithmic dependence on density of impurities for most silicon PN junctions
the built in potential UD does not much differ from about 0,6 V.
3.2 Electrostatic analysis of a PN junction
The electrostatic analysis of a PN junction provides knowledge about the charge density
and the electric field in the depletion region. It is also required to obtain the capacitancevoltage characteristics of the PN junction.
3.2.1
The full-depletion approximation
To simplify the solution we will make the assumption that the depletion region is fully
depleted and that the adjacent neutral regions contain no charge.
1. Full depletion approximation (which is used in all following considerations) assumes
that the depletion region around the metallurgical junction has well-defined edges. It also
assumes that the transition between the depleted and the quasi-neutral region is abrupt.
Electronic Devices
35
2.We define the quasi-neutral region as the region adjacent to the depletion region
where the electric field is small and the free carrier density is close to the net doping density.
3. Coordinates x for depletion region boundary which are derived from the depletion
layer width in the p-type region and from the depletion region width in the n-type region
respectively are xp and xn . In metallurgical junction x = 0. We obtain following relations:
1.
2.
3.
for -xp ≤ x ≤ 0
NA >> np or pp
for 0 ≤ x ≤ xn
ND >> nn or pn
for x < -xp a x > xn
⇒
⇒
ρ = -qNA
ρ = qND
ρ = 0
Now we can start the electrostatic analysis using an abrupt charge density profile.
3.2.2
Full depletion analysis
To the general analysis we need Poisson's equation:
dE ρ
=
dx ε
where ρ is the charge density. Charge density is a function of the electron density, the hole
density and the donor and acceptor densities. To solve the equation, we have to express the
Charge density by means of electron and hole density, n and p. Considering full depletion
approximation we obtain:
dE
ρ
= − NA
for -xp ≤ x ≤ 0
( 3.11 )
dx
ε
dE ρ
= ND
dx ε
for
E=0
for x ≤ -xp a x ≤ xn
0 ≤ x ≤ xn
( 3.12 )
( 3.13 )
The electric field is obtained by integrating equation ( 3.11 ),( 3.12 ),( 3.13 ):
E (x ) = ∫
− qN A
E( x ) = ∫
qN D
dx =
ε
ε
dx =
− qN A
ε
qN D
ε
x + C1
x + C2
for
-xp ≤ x ≤ 0
( 3.14 )
for
0 ≤ x ≤ xn
( 3.15 )
The boundary conditions are that the electric field is zero at both edges of the depletion
region: E(-xp) = E(xn) = 0 (see equ.( 3.13 )).
After substitution we get:
C1 =
x p (− qN A )
ε
( 3.16 )
36
FEKT Vysokého učení technického v Brně
C2 = −
x n (qN D )
( 3.17 )
ε
And finally for electric field in depletion region:
E (x ) = −
qN A
ε
E (x ) = −
(x
qN D
ε
p
+ x)
(xn − x )
for
-xp ≤ x ≤ 0
( 3.18 )
for
0 ≤ x ≤ xn
( 3.19 )
For x = 0 the electric field must be continuous. From this condition follows:
−
qN A
xp = −
ε
qN D
xn
ε
( 3.20 )
Equation ( 3.20 ) expresses the condition of charge neutrality. The net charge on both
sides of PN junction must be the same except the polarity. Equation ( 3.20 ) can be rewritten:
xp
xn
=
ND
NA
( 3.21 )
From this relation follows that the depletion layer extends to the less doped region. Less
doped region is often labelled as high resistance region or also as base.
To compute the function for potential dependence we will use the relation between the
potential and the electrical field:
dV
= −E
dx
( 3.22 )
Using equations ( 3.14 ) we obtain:
x
V ( x ) = − ∫ E( x )dx =
−x
x
V (x) = − ∫ E(x)d x =
xn
qND
ε
∫ (x
x
qN A
ε
p
+ x )d x =
−xp
x
∫ (x
n
− x)dx = −
xn
qN A
( x p + x) 2 + C 3 for -xp ≤ x ≤ 0
2ε
qND
(xn − x) 2 + C4 for 0 ≤ x ≤ xn
2ε
( 3.23 )
( 3.24 )
The boundary conditions here are again that the electric field is zero at both edges of PN
junction and that the potential difference between both edges is UD. When we set V(-xp) = 0
then V(xn) = UD. Consequently we obtain the relations for potential in P and N region
respectively.
V ( x) =
qN A
(x p + x )2
2ε
V ( x) = −
for -xp ≤ x ≤ 0
qN D
( x n − x) 2 + U D
2ε
for 0 ≤ x ≤ xn
( 3.25 )
( 3.26 )
Electronic Devices
37
Now we can compute the width of depletion region. For x=0 the potential must be
continuous:
qN A
(x p )2 = qN D ( xn − x) 2 + U D
2ε
2ε
( 3.27 )
From equation ( 3.21 ) we can derive:
xp =
ND
xn
NA
After substitution xp in equation ( 3.27 ) we obtain quadratic equation for unknown xn :
2
qN D2 x n2 qN D
qN A  N D 

.x n  =
=
( xn ) 2 + U D
2ε  N A 
2εN A
2ε
( 3.28 )
Solution of equation (3.28) is
 2ε U D

NA
xn = 
⋅

N D (N A + N D )
 q
1/ 2
( 3.29 )
After substitution of xn back to equation (3.21) we obtain for xp :
 2ε U D

ND
xp = 
⋅

N A (N A + N D )
 q
1/ 2
( 3.30 )
The total width w of the junction equals the sum of both xn and xp . Using relations ((
3.27 ) and ( 3.30 )) and after some computation we get:
 2ε U D (N A + N D ) 
w=
⋅

q
NAND 

1/ 2
( 3.31 )
In case of unsymmetrical PN junction we can simplify the relation ( 3.31 ) considerably.
For example having P+N junction where NA >> ND the relation ( 3.31 ) is:
 2ε U D 1 
w≈ xn ≈
⋅

q
ND 

1/ 2
( 3.32 )
3.3 Forward and reverse bias
In thermal equilibrium there exists a balance between the drift and diffusion current. For
example, for electrons this steady state can be interpreted following way. The electrons which
had migrated across junction from the N to the P region in the process of forming the
depletion layer reached equilibrium. Other electrons from the N region cannot migrate
because they are repelled by the negative ions in the P region and attracted by the positive
ions in the N region.
38
FEKT Vysokého učení technického v Brně
3.3.1
Forward bias
When the positive voltage is applied to the P-doped region, the potential across junction
decreases because external voltage has opposite orientation to the built in potential. The total
potential across the junction equals in this case the built-in potential minus the applied
voltage. An applied voltage in the forward direction therefore assists electrons in overcoming
the coulomb barrier of the space charge in depletion region. Holes in the P-type region and the
electrons in the N-type region are pushed towards the junction. The electrons which pass the
junction barrier (by diffusion process) enter the P-type region; holes are moving (by diffusion
process) from the P-type region through the junction to N-type region. This makes an electric
current possible:
Fig. 3.2: Abrupt PN junction in forward and reverse bias: a) Configuration; b) Space
charge; c) Electric field; d) Junction potential
Electronic Devices
39
After passing through the junction both majority carriers electrons and holes become
minority carriers and thermal equilibrium in adjacent parts of the junction (quasi-neutral
region) is disturbed. Because of that in quasi-neutral region the minority electron and holes
recombine with majority carriers.
Consequently forward bias case of PN junction can be summarized as:
1. Owing to lower potential barrier the majority carriers diffuse through the junction.
2. After passing through the junction both majority carriers electrons and holes become
minority carriers and thermal equilibrium in adjacent parts of the junction (quasi-neutral
region) is disturbed. Consequently in quasi-neutral region the minority electrons and holes
recombine with majority carriers.
3. Recombination depends on the carrier lifetime and on the distance of the terminal
contact. (... one part of carriers recombine, other part reach the contact; see also bipolar
transistor.)
4. Diffusion of majority carriers reduces the width of the depletion zone.
5. Difference between the Fermi energy in the N-type and P-type quasi-neutral regions
is proportional to difference of the applied voltage and built in potential.
Dependence of space charge, electric field and junction potential for an abrupt PN
junction in forward bias is visualized on the Fig. 3.2. with dotted lines
3.3.2
Reverse bias
The junction is reverse-biased if a negative voltage is applied to the P-type region. By
reverse bias the potential across the junction increases because the external voltage has the
same orientation as the built in potential. Because of that the potential barrier increases.
Reverse bias case of PN junction can be summarized as:
1. Owing to higher potential barrier the diffusion of majority carriers is impeded.
2. There is only drift current of minority carriers originated in quasi-neutral regions by
thermal generation
3. Because of minority carriers extraction the quasi-neutral regions are depleted and the
width of the depletion zone grows.
4. Difference between the Fermi energy in the n-type and p-type quasi-neutral regions is
proportional to the sum of applied voltage and built in potential.
Dependence of space charge, electric field and junction potential for an abrupt PN
junction in reverse bias is visualized on the Fig. 3.2. with dashed lines
Note: The contact to the P-type region is called the anode and the contact to the N-type
region is called the cathode.
To compute the width of biased PN junction we can used the previously derived
formulas, only instead of UD we must use (UD – U):
1. By forward bias - external voltage cause reduction of junction potential
2. By reverse bias - external voltage junction potential grows.
40
FEKT Vysokého učení technického v Brně
Consequently we can write previously derived equations for N-type and P-type regions
respectively:
 2ε

ND
x p =  (U D −U )

N A (N A + N D )
q
V ( x) =
1/ 2
( 3.33 )
qN A
(x p + x )2
2ε
E ( x) = −
qN A
ε
(x
p
( 3.34 )
+ x)
( 3.35 )
 2ε

NA
x n =  (U D −U )

N D (N A + N D ) 
q
V ( x) = (U D − U ) −
E ( x) = −
qN D
ε
1/ 2
qN D
( x n − x )2
2ε
(xn − x )
( 3.36 )
( 3.37 )
( 3.38 )
Then the total width of the junction is:
 2ε
(N + N D )
w =  (U D −U ) A

NAND 
q
1/ 2
( 3.39 )
Electronic Devices
Fig. 3.3:
bias.
41
Carrier transport over the energetic barrier in case of forward (a) and reverse (b)
By abrupt PN junction the width of the junction is roughly proportional to the square
root of applied voltage. This relation is important because the width of the junction influence
the junction capacitance and breakdown voltage, see next chapters.
Carrier transport over the energetic barrier which is caused by built in potential in
depletion layer can be visualized by means of band diagram. On the Fig. 3.3. there are band
diagrams for both forward and reverse bias. All phenomena described in this chapter can be
observe easily.
3.4 Ideal diode current
The current in a PN diode is due to carrier recombination or generation within the PN
diode structure. Under forward bias, the diode current is due to recombination. This
recombination can occur within the quasi-neutral regions, within the depletion region or at the
metal-semiconductor contacts. Under reverse bias the current is due to generation. By all
considerations the minority carrier density has a key role. On the Fig. 3.4. there is visualized
the minority carrier density in case of both forward and reverse bias. In case of forward bias
(dotted line) there is the injection of minority carriers resulting in excess of minority carriers.
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FEKT Vysokého učení technického v Brně
In case of reverse bias (dashed line) the extraction of minority carriers takes place resulting in
depletion of quasi-neutral regions.
Fig. 3.4:
Minority carrier density in case of forward bias (a) and reverse bias (b).
To find the relation for PN junction current as a function of junction voltage we need to
make following assumptions
1. There is no external source of carrier generation (for example light).
2. We consider an abrupt PN junction and full depletion approximation.
3. There is no generation and recombination in depletion layer.
4. We consider low injection of minority carriers.
5. Electric field equals zero beyond the depletion region.
6. ND and NA are constant.
After some computation we obtain:
Electronic Devices
43
D
  qU  
Dp
−1
I = q A n n p 0 +
pn 0 exp
L

L
k
T

 
n
p


( 3.40 )
where the meaning of variables is:
A
area of the junction [m2 ]
Dn ,Dp ,
diffusion coefficient for electrons and holes respectively [m2s-1]
(note that Dn = µn kT/q and Dp = µp kT/q )
Ln, Lp
diffusion length of minority carriers [m]
Diffusion length (Ln, Lp )of minority carriers is a mean distance to which the minority
carriers with lifetime τ n, τ p can diffuse in P-type and N-type semiconductor respectively
before they recombine. For electrons and holes respectively the diffusion length is defined as:
Ln = Dnτ n
( 3.41 )
L p = D pτ p
( 3.42 )
Now we can substitute for Dn/Ln and Dn/Ln :
Dn
=
Ln
Dn
Dp
Dp
Lp
=
τn
τp
=
µ n kT 1
q τn
( 3.43 )
=
µ p kT 1
q τp
( 3.44 )
It is obvious that this term in equation ( 3.40 ) is material dependent. Here most
important is the minority carrier lifetime (τ n, τ p), which can differ in many orders, typically
from about 1 ms in case of very clean semiconductor materials up to 1 ns in case of bad
structure or intentional doping by impurities with high recombination rate.
For minority carrier densities np0 and pn0 we can write (using the mass action law):
n p0 =
ni2
NA
( 3.45 )
pn0 =
ni2
ND
( 3.46 )
Now, from equation ( 3.40 ) we can extract an important parameter – saturation current
I0:
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FEKT Vysokého učení technického v Brně
 D 1 Dp 1  2
ni
I 0 = q A n
+
L N

L
N
p
D 
 n A
( 3.47 )
In case of PN junction with unsymmetrical doping (P+N for example, where NA >> ND)
we can use more simple relation:
 Dp 1  2
 ni
q A
 Lp N D 
( 3.48 )
From equation ( 2.31 ) is easy to deduce that the saturation current:
- grows when Junction area A is growing
- decrease when increasing the dopant density (ND in this case)
- grows exponentially with the temperature T
- diminish more than exponentially with the bandgap energy EG (see EG dependence of
ni).
For silicone diodes the saturation current is usually in range from 10-12A up to 10-8A
(depends on junction area A and junction technology). It doubles by the temperature
difference 6K. In case of germanium, the saturation current range from 10-6A up to 10-4A in
(depends on junction area A and junction technology). It doubles by the temperature
difference of 10K about.
Substituting to ( 3.40 ) for kT/q = UT (thermal voltage) we obtain well known
Shockleys equation:


U
I = I 0  exp
− 1
UT


( 3.49 )
I-V characteristic of ideal PN junction based on Shockleys equation is visualized on the
Fig. 3.5.
Fig. 3.5:
I-V characteristic of ideal PN junction in linear (a) and semilogarithmic (b) scale
Electronic Devices
45
By reverse bias and the reverse voltage larger then some UT the reverse current is
almost constant:
I ≈ I0
( 3.50 )
In forward bias and forward voltage larger then some UT the forward current grows
exponentially with the forward voltage:

U 
I ≈ I 0  exp

UT 

( 3.51 )
3.5 Static and dynamic resistance of PN junction
Static and dynamic resistances of PN junction have the same meaning as in case of
other devices. To derive static and dynamic resistance we compute at first the junction
voltage:

 I 
I 
U = U T ln 1 +  ≈ U T ln 
I0 

 I0 
( 3.52 )
(Second relation in equation (3.52) is valid for I >> I0.)
From equation ( 3.52 ) it is seen that the static resistance is nonlinear function of
junction voltage or current. For practical use the static resistance is not much important.
On the other hand the dynamic resistance of the junction (which is the junction
resistance for voltage and current with small amplitude) is very useful in considerations about
semiconductor circuits. To obtain the dynamic resistance we must compute first derivative of
the junction voltage:
Rd =
UT
UT
U
dU
=
=
≈ T
U
dI
I + I0
I
I 0 exp
UT
( 3.53 )
(The last relation in equation ( 3.53 ) is again valid for I >> I0.)
For I=U=0 both static and dynamic resistances have the same value:
R0 = Rd 0 =
UT
I0
( 3.54 )
In case of silicon diode the value of R0 range from 106 Ω up to 1010 Ω, for germanium
diode the value of R0 is from about 102 Ω up to 105 Ω.
Note:
Dynamic resistance of PN junction is very important parameter in semiconductor
cuircuit theory. We will use it not only for diodes but also for bipolar transistors.
3.6 Junction capacitance
The capacitance versus applied voltage is by definition the change in charge for a
change in applied voltage:
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FEKT Vysokého učení technického v Brně
Cj =
dQ
dU
( 3.55 )
The space charge can be computed easily using
Q = q Ax n N D = qAx p N A
( 3.56 )
Here the absolute value sign is added in the definition of space charge so that either the
positive or the negative charge can be used in the calculation, as they are equal in magnitude.
The width xn or xp in N-type or P-type regions respectively we obtain from euations (
3.39 ):
 2ε

NA
x n =  (U D −U )

N D (N A + N D )
q
1/ 2
 2ε

ND
, x p =  (U D −U )

N A (N A + N D )
q
1/ 2
After substitution to ( 3.56 ) we get the space charge in both N-type and P-type regions
respectively:
 2ε

NAND
Q = qA (U D − U )

N D (N A + N D )
q
1/ 2
( 3.57 )
The capacitance of the junction we obtain by means of first derivative:
NAND 
dQ
qA  2ε
1
Cj =
=


d (U D −U )
2  q (U D − U ) N A + N D ) 
1/ 2
( 3.58 )
The junction capacitance is frequently expressed as a function of the zero bias (U = 0V)
capacitance Cj0:
q
NAND 
1
C j = ε A

 2ε (U D −U )( N A + N D ) 
1/ 2
=
C j0
1−
U
UD
( 3.59 )
A comparison with equation which provides the depletion layer width, w, as a function
of voltage, reveals that the expression for the junction capacitance, Cj, is similar to that of a
parallel plate capacitor:
Cj = ε
A
w
( 3.60 )
Electronic Devices
47
The only difference is that the depletion layer width and hence the capacitance is
voltage dependent. The distance between the added negative and positive charge equals the
depletion layer width:
 2ε
(N + N D ) 
w =  (U D −U ) A

NAND 
q
1/ 2
Voltage dependence of junction capacitance is given on the Fig. 3.6.
The barrier capacitance of the PN junction depends:
- on the junction Area A
- on dopant density NA and ND
- on external voltage ~U-1/2
Fig. 3.6:
Voltage dependence of junction capacity (or barrier capacity).
Note:
1. A capacitance versus voltage measurement can be used to obtain the built-in voltage
and the doping density of a one-sided PN diode.
2. A capacitance-voltage measurement also provides the doping density profile of onesided PN diodes. Both the doping density and the corresponding depth can be obtained at each
voltage, yielding a doping density profile.
3. A linearly graded junction has a doping profile, which depends linearly on the
distance from the interface. The capacitance of a linearly graded junction is less dependent
(~U-1/3) on external voltage.
3.7 Diffusion capacitance
In case of forward bias majority carriers diffuse through the junction. After passing
through the junction both majority electrons and holes become minority carriers and thermal
equilibrium in adjacent parts of the junction (quasi-neutral region) is disturbed. Consequently
in quasi-neutral region the minority electrons and holes recombine with majority carriers.
Recombination rate is given by the lifetime of minority carriers and because of that only a
part of minority carriers can recombine. The rest is accumulated in quasineutral regions of the
junction as exces minority carriers. The charge of excess minority carriers grows linearly
with the junction current. On the other hand the junction current exponentially depends on the
junction voltage.
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FEKT Vysokého učení technického v Brně
Because any variation of the charge within a PN junction with an applied voltage
variation yields a capacitance the voltage dependent accumulation of minority carriers is
in principle capacitance which must be added to the circuit model of a PN junction. To differ
from barrier capacitance, which is more important by reverse bias, we will call this
capacitance as diffusion capacitance.
To estimate the diffusion capacitance we will consider an unsymetrical P+N junction,
through which flows a current I. Because the junction is unsymmetrical diffusion current of
holes from P-type region will be much larger then the diffusion current of electrons from Ntype region. In such case only accumulation of holes in N-type region will be significant. The
accumulated charge is:
Qap = Iτ p = qA∆p n L p = qAL p p n exp(q
U
)
kT
( 3.61 )
Difussion capacitance will be then computed by first derivative; see the equation (3.60):
q2
I
 qU  q
CD =
=
AL p p n exp
Ip =
τp
=
dU
kT
UT
 kT  kT
d Qa p
( 3.62 )
Total capacity of PN junction is given by the sum of barrier and diffusion capacity:
C = C j + CD
( 3.63 )
3.8 Dynamic characteristics of PN junction
For diodes operating on high frequencies and for diodes in switching converters and of
course in high power circuits turn-on and reverse recovery processes are very important.
3.8.1
Turn on process
During the turn-on of the diode under a high value of forward current a voltage
overshoot arises because of low conductivity caused by depletion region in PN junction.
During continuous conduction, the resistance of this region is reduced by the injection of the
minority carriers. However, during high-speed turn-on, the current may raise much faster then
the diffusion of the minority carriers injected from the junction. In the case of PIN structure
the level of the voltage overshoot is strictly related to the resistivity and thickness of the N
region. An elevated forward voltage overshoot in the diode can be a serious problem in power
circuits. An example of voltage overshoot by different rates dIF/dt is visualized on the Fig.
3.7.
Electronic Devices
49
Fig. 3.7: Voltage overshoot as consequence of rapid grow of current during switch on. (a)
Diode forward voltage /dotted line is supposed power loss/. (b) Estimation of forward
recovery time trr
3.8.2
Reverse recovery
Reverse recovery takes place during the transition from the conduction state to the
blocking state. This is due to the excess of carriers stored in the base that must be removed
before the diode will be able to block the voltage, and this requires a finite time proportional
to the “volume” of the region and the density of recombination centers. The removal of the
stored charge occurs by means of the flow of a large reverse current and by the
recombination. Once the carriers are removed by the combined action of recombination and
sweep-out by negative diode current, the depletion layer acquires a substantial amount of
space. After then the diode is able to block the reverse voltage.
The transition time from the conduction to the blocking state is labeled as reverse
recovery time (trr) of the diode. This can be divided into the time of “storage” (ts) needed to
remove the carriers before the PN junction regains the voltage blocking capability, and the
time, tr, during which the diode voltage goes negative with a rate of change dVR/dt.
Obviously, increased injection, to reduce the forward voltage drop, implies more charge that
needs to be removed from the intrinsic region before the diode will be able to block voltage.
This will, therefore, adversely affect the reverse recovery time.
As long as an excess of carriers are at the end of the drift region, the junctions must be
still forward biased. The voltage will changed from its conduction value only because of the
voltage drop caused by the reverse current and the ohmic contacts.
However, once the excess of carriers is no longer present at the end of ts, the junction
becomes reverse biased. At this point, the diode voltage goes negative with a rate of change
dVR/dt proportional to dIREC/dt. As a further consequence, if the reverse recovery dIREC/dt is
large, the peak reverse voltage is also high, causing failures when exceeding the blocking
voltage capability which can cause damage to the switching rectifier. Moreover a high level of
dVR/dt generates significant radiated and conducted noise.
On the other hand if the rate of change is too low then the reverse recovery time will
increase. Consequently the power dissipated in the rectifier during transition from the
conducting to the blocking state increases.
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FEKT Vysokého učení technického v Brně
Fig. 3.8:
Definitions of the recovery characteristics
The removal of stored charge in the intrinsic region occurs by means of the flow of a
large reverse current during time ts. At the end of this time the junction becomes reverse
biased.
The reverse current at this point is defined as the peak reverse recovery current, IRRM.
The value of IRRM is proportional to the rate of change of forward current through zero
crossing dIF/dt.
IRRM = (dIF/dt) . ts
The reverse current then decreases by recombination at a rate of dIR/dt in time tr. The
amount of reverse recovery charge is given by
QRR = (IRRM .trr)/2
Where trr = ts + tr
Some rectifier datasheets may define a softness factor S where
S = (ts/tr)
The diode voltage now goes negative at a rate proportional to dIR/dt. During this diode
recovery this change in current will result in a reverse voltage overshoot due to the parasitic
inductance LLS in the transformer secondary. The peak reverse voltage VRRM is then given by:
VRRM = LLS dIR/dt
Moreover a high level of dVR/dt generates a noise immunity problem as well, because
of the emission of a radio frequency. These and many other factors limit the optimization of
diode performance. Low on-state voltage, faster switching times and larger breakdown
voltages may not in fact co-exist easily without proper design and an advanced manufacturing
technique.
3.9 Reverse bias breakdown
When the diode is reverse-biased (p-region negative with respect to the n-region) the
only current which flows through the junction is the reverse saturation current, resulting from
thermally generated minority carriers which are extracted from quasineutral regions by means
of electric field.
Electronic Devices
51
The width of the depletion region grows with higher voltage but only with square root.
Because of that the electric field grows as the reverse voltage increases. When the electric
field increases beyond a critical level a PN junction will experience a rapid grows of current
in the reverse direction. The maximum reverse bias voltage is therefore limited by junction
breakdown.
Junction breakdown is characterized by the rapid increase of the current under reverse
bias. When this process is taking place very small changes in voltage can cause very large
changes in current. The corresponding applied voltage is referred to as the breakdown
voltage.
If we include the effect of breakdown in the I-V curve for the diode we would see rapid
grow of current in reverse part of I-V characteristic.
The breakdown process depends upon the applied electric field, so by changing the
width of the junction very different diodes can be formed with breakdown voltage from about
4 volts to more than one thousand volts.
There are four mechanisms which can cause reverse bias breakdown of the PN junction:
Non-destructive breakdowns are avalanche multiplication and quantum mechanical
tunneling of carriers through the bandgap. These breakdowns can be repeated arbitrarily.
Moreover, there are devices which work on principle of avalanche or tunnel breakdown,
Zener diode for example.
Destructive breakdowns are thermal breakdown (second breakdown) and surface
breakdown.
The breakdown voltage is a key parameter of power devices. The breakdown of logic
devices is equally important when the device dimensions are reduced without reducing the
applied voltages, thereby increasing the internal electric field.
3.9.1
Avalanche breakdown
Avalanche breakdown is caused by impact ionization of electron-hole pairs. If we make
the reverse bias greater, the same current flows, but the carriers pick up more energy as they
move in higher electric field. When applying a high electric field, carriers gain kinetic energy,
they collide with a semiconductor lattice and thus create an additional electron-hole pair
through a process called impact ionization. The current now consists of five electrons and two
holes. These newly originated carriers also contribute to ionization. Such process is called
avalanche multiplication because through a succession of impacts create more and more
current. The avalanche breakdown process is visualized on the Fig. 3.9.
Fig. 3.9:
Principle of avalanche multiplication
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FEKT Vysokého učení technického v Brně
Avalanche breakdown can be characterised by the multiplication factor M, which is
commonly expressed as a function of the applied voltage and the breakdown voltage.
Assuming that the ionization coefficients of electrons and holes are the same, the
multiplication factor M, can be calculated from the following empirical relation:
s
M= =−
r
1
 u 
1−  R 
U

 ( BR ) 
n
( 3.64 )
Fig. 3.10: Breakdown voltage versus doping density of an abrupt one-sided PN junction (a)
and linearly graded junction (b).
The electric field depends on the width of the junction and therefore the resulting
breakdown voltage is inversely proportional to the doping density (neglecting the weak
doping dependence of the electric field at breakdown). The resulting breakdown voltages for
silicon and germanium PN junctions as a function of the doping density are on the Fig. 3.10
below, plotted for an abrupt one-sided junction (a) and for linearly graded junction (b).
The process of avalanching itself is not destructive. Diodes in breakdown regime are
used as voltage references because the voltage across them is more or less independent of the
diode current. A series current limiting resistor must be always used to limit the breakdown
current.
Thermal dependence of avalanche breakdown voltage:
By elevated temperature vibrations of semiconductor lattice are more intensive. These
vibrations impede the free motion of carriers in electric field in depletion layer. To reach the
energy needed for impact ionisation the electric field must be higher and this mean that the
breakdown takes place by higher junction voltage.
Thermal coefficient of breakdown voltage in case of avalanche breakdown is positive.
3.9.2
Zener breakdown
Highly doped p-n junctions are very narrow. Here the dominant breakdown mechanism
is tunnel transition of electrons through the bandgap. After the inventor this type of
breakdown is frequently called as Zener breakdown.
Electronic Devices
53
The Zener effect comes from direct field generation of extra carriers, rather than as a
result of impact ionization. For tunnel transition of electrons two conditions must be fulfiled:
1. PN junction must be very narrow.
2. There must be free states on one site of the junction on the same energy level as the
occupied states on the other site of the junction.
Fig. 3.11: Principle of Zener breakdown visualized by means of band diagram. a) PN
junction in thermal equilibrium. b) The same junction with reverse bias and value of reverse
voltage corresponding to Zener breakdown.
Note:
Electron tunnel transition can take place not only in reverse but also in case of forward
polarisation of the PN junction (in case of tunnel diode for example).
Zener breakdown is visualized by means of band diagram on the Fig. 3.11. A tunnel
transition of electrons from occupied states in valence band in P-type region to free states in
conductivity band in N-type region is here indicated with arrow.
Thermal dependence of breakdown voltage:
The probability of tunnel transition depends on the bandgap energy. Because with
growing temperature the bandgap energy diminish probability of the tunnel transition will be
higher by elevated temperature. This means that in case of Zener breakdown the breakdown
voltage diminish with growing temperature.
Thermal coefficient of breakdown voltage in case of tunnel breakdown is negative.
A Zener breakdown exists only by heavily doped PN junctions, where very narrow
depletion region gives a possibility of tunnel transition of electrons from the valence band of
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FEKT Vysokého učení technického v Brně
the P-type material to the conduction band of the N-type material. To have only tunnel
transition without influence of avalanche multiplication the breakdown voltage should fulfil
the condition:.
qUBr < 4 EG .
The avalanche multiplication prevails from the breakdown voltage which corresponds
with condition:
qUBr > 6 EG
Between this limits both avalanche and tunneling processes take place. Because the
thermal coeficient of breakdown voltage is positive in case of avalanche breakdown and
negative in case of tunnel transition the thermal dependence is balanced in this range and the
breakdown voltage is almost independent on the temperatrure. This effect is used for
production of reference diodes for voltage stabilisers.
Zener diode exhibits almost the same properties as the diode with avalanche breakdown
mechanism, except having a greatly reduced breakdown voltage. In fact there is not possible
to differ both diodes by looking at the diode I-V curve. The breakdown voltage of both
avalanche and Zener breakdown can be controlled quite accurately in the doping process.
Tolerances to within 0.1% are available, nevertheless the most widely used tolerances are
from 1% to 5%.
3.9.3
Second breakdown
Because most electronic devices have breakdown voltage larger then about 6 V we can
consider that by most of electronic devices the main breakdown mechanism is avalanche
breakdown. Thermal coefficient of breakdown voltage is positive in this case and moreover it
grows with the breakdown voltage value. The dependence of thermal coefficient of
breakdown voltage is on the Fig. 3.12. Consequently by elevated temperature most of
electronic devices will have higher breakdown voltage.
Unfortunately this is useful only when there is no current passing through the PN
junction. By current load, the value of the power which cause the thermal load can be
estimating as:
Pj = u R i R
( 3.65 )
This power produces heat and because of that the device must be cooled. The power
which can dissipate to device environment is given by a simple formula:
Pa −
Tj − Ta
Rth
( 3.66 )
where Tj is junction temperature, Ta is ambient temperature and Rth is thermal resistance
between the junction and environment.
By elevated temperature the saturation current grows and this again brings larger power
and more heat ... etc., till the temperature of semiconductor reach the value by which the
semiconductor is melted in junction area and the device is irreversible destroyed.
When there are some defects or impurities in junction or junction is not truly planar or
when the distributions of dopants is not strictly uniform the current density will be much
Electronic Devices
55
higher in some points. Because of that the temperature here will be much higher, the current
density will grow mainly in this points.. etc till the temperature reach the melting point of the
semiconductor (or the melting point of the eutectic alloy of contact material and
semiconductor) and the device fails by thermal (second) breakdown.
When the junction has a good geometry no defects and uniformly distributed dopants
the breakdown occurs at whole junction area and the current density is distributed uniformly.
In such case the tolerance against thermal breakdown is much higher. This property is
essential by power devices.
For analysis of device cooling there is important that the saturation current grows
exponentially with temperature while the dissipated heat depends on temperature linearly. It
means that always exist a temperature by which is not possible to take away the heat
originated in the device as consequence of power load. The situation is visualized on the Fig.
3.12. By low temperature (after switching the device on) the device is warming up until the
steady state (represented by point 1) is reached. Hear the originated and dissipated heats are
balanced. By temperature higher the Tkr (point 2) the heat originated in device is not possible
to take away. In such situation the thermal breakdown is to expect.
Fig. 3.12: Thermal stability of the PN junction
3.9.4
Surface breakdown
In the surface of semiconductor there are always some defects and impurities which
behave as recombination centres or only change the resistance of material. Consequently the
electric field is not distributed uniformly. On some spots, where the electric field is high, a
local surface breakdown can take place. From this spots the surface breakdown expands and
the device is irreversibly destroyed. Surface breakdown come into being only by high voltage
devices.
To inhibit the surface breakdown a passivation layer with very low but well defined
conductivity is deposited on the high voltage device surface. Passivation layer is highly
uniform so the conductivity is distributed uniformly. This way also the electric field is
distributed uniformly and there are no more the spots with the high electric field.
Note:
1. Passivation layer also serves as protection layer for semiconductor surface and
termination of free bonds on the semiconductor surface.
2. To reliable surface breakdown diagnostic the voltage higher than 100 V about should
be used. By low voltage (which is used by digital multi-meters for example) the surface
breakdown can not be detected.
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FEKT Vysokého učení technického v Brně
3.10 Metal-Semiconductor Junction
Metal-to-semiconductor (M-S) junctions are of great importance since they are present
in every semiconductor device.
To construct an energy band diagram of metal semiconductor junction we first consider
the energy band diagram of the metal and the semiconductor which is visualized on the Fig.
3.13a. where both diagrams are aligned using the same vacuum level.
Fig. 3.13: Schottky barrier. (a) Band diagram of metal and semiconductor. (b) Band diagram
of metal-semiconductor junction in thermal equilibrium.
Here ΦM and ΦS are the work function of the metal and semiconductor respectively, and
χ is the electron affinity given by the difference between energy of vacuum level and energy
of the bottom of the conductivity band. The work function of selected metals as measured in
vacuum can be found in Table 1.
Tab. 1:
The work function of selected metals and barrier height in case of different semiconductive materials
(Note that barrier heights reported in the literature can vary widely due to different
surface cleaning procedures)
Electronic Devices
57
As the metal and semiconductor are brought together, the Fermi energies of the metal
and the semiconductor do not have same value. This means that the system is not in thermal
equilibrium. To reach thermal equilibrium electrons from the N-type semiconductor traverse
the junction. As they leave the semiconductor they left behind a positive charge, due to the
ionized donor atoms. This charge creates a negative field between the metal contact and
semiconductor and lowers the band edges of the semiconductor (see the Fig. 3.13b). Electrons
flow into the metal until equilibrium is reached between the diffusion of electrons from the
semiconductor into the metal and the drift of electrons caused by the field created by the
ionized impurity atoms. In thermal equilibrium the positive space charge of ionised donors is
balanced by negative charge of electrons in metal.
The built in potential is:
UD = ΦM − ΦS
( 3.67 )
The barrier height, φB, is defined by the potential difference between the Fermi energy
of the metal and the band edge where the majority carriers reside. From Fig. 3.13b it is seen
that for an N-type semiconductor the barrier height is obtained from:
ΦB = ΦM − χ
( 3.68 )
Where χ is electron affinity The measured barrier height for selected metalsemiconductor junctions is listed in Tab 1.
If a negative voltage is applied to the contact the Fermi energy of the metal is changed
with respect to the Fermi energy in the semiconductor. The potential across the semiconductor
now increases, yielding a larger depletion region and a larger electric field at the interface.
The barrier, which restricts the electrons to the metal, is unchanged so that that barrier,
independent of the applied voltage, limits the flow of electrons. The metal-semiconductor
junction with positive barrier height has therefore a pronounced rectifying behavior. A large
current exists under forward bias, while almost no current exists under reverse bias.
1. Streamlining:
(a) φM > φS
metal – N-type semiconductor (depletion layer rise)
(b) φM < φS
metal – P-type semiconductor (depletion layer rise)
2. Non-streamlining:
(c) φM < φS
metal – N-type semiconductor (enhancement layer rise)
(d) φM > φS
metal – P-type semiconductor (enhancement layer rise)
A metal-semiconductor junction results in an ohmic contact (contact with voltage
independent resistance) if the Schottky barrier height, φB, is zero or negative. In such case, the
carriers are free to flow in or out of the semiconductor so that there is a minimal resistance
across the contact. For an N-type semiconductor, this means that the workfunction of the
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Fig. 3.14: Metal-semiconductor junction. Band diagrams
metal must be close to or smaller than the electron affinity of the semiconductor. For a
P-type semiconductor this condition requires that the workfunction of the metal must be close
to or larger than the sum of the electron affinity and the bandgap energy.
An alternate and more practical contact is a tunnel contact. Such contacts do have a
positive barrier at the metal-semiconductor interface, but also have a high enough doping in
the semiconductor that there is only a thin barrier separating the metal from the
semiconductor. If the width of the depletion region at the metal-semiconductor interface is
very thin (in the order of few nm) carriers can readily tunnel across such barrier. The required
doping density for such contact is 1019 cm-3 or higher.
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Fig. 3.15: Band diagram of metal-semiconductor junction.. (a) By forward bias. (b) By
reverse bias. (c) I-V characteristic.
3.10.1 Ohmic contact for semiconductor devices
Fig. 3.16: Contact system metal-semiconductor. (a) Rectifying by low doping level. (b)
Ohmic (with tunnel transition) by heavily doped semiconductor.
Metal-semiconductor contacts are used in all semiconductor devices. However for a lot
of semiconductors there is no appropriate metal available to provide a low resistance ohmic
contact. Large mismatch between the Fermi energy of the metal and semiconductor can in
many cases result in a high-resistance rectifying contact.
This problem is usually solved by making a tunnel contact. Such contact consists of a
thin barrier (obtained by heavily doping of the semiconductor) through which carriers can
readily tunnel. Thin interfacial layers also affect contact formation therefore most metalsemiconductor contacts are annealed or alloyed after the initial deposition of the metal to
further improve(diminish) the contact resistivity.
3.10.2 Control questions and examples for Chapter 3.10
1.
Enumerate the types of breakdowns of semiconductor junctions and briefly
characterize the breakdowns.
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2.
a) What conditions should be satisfied for the avalanche breakdown of the pn
junction? b) For what devices is the avalanche breakdown typical? c) How the
avalanche breakdown depends on temperature?
3.
What means the surface breakdown of semiconductor junctions? b) At what
devices the surface breakdown occurs? c) Is it possible to increase the surface
breakdown resistance? If so, how?
4.
What means the temperature breakdown of semiconductor junctions? At what
devices the temperature breakdown occurs? Is it possible to increase the
temperature breakdown resistance? If so, how?
5.
a)What conditions should be satisfied for the tunneling breakdown of the pn
junction? For what devices is the tunneling breakdown typical? How the
tunneling breakdown depends on temperature?
6.
a) Draw how the energy band diagram of the pn junction (Si) will be changed if
the reverse voltage is applied (3 V). b) Draw the diffusion voltage and the reverse
voltage in the band diagram.
7.
a) Draw how the energy band diagram of the pn junction (Si) will be changed if
the reverse voltage is applied (0.6 V). b) Draw the diffusion voltage and the
reverse voltage in the band diagram.
8.
a) Draw how the energy band diagram of the pn junction (Si) will be changed if
the reverse voltage is applied (3 V). b) b) Draw the orientation of the diffusion
voltage and of the reverse voltage.
9.
a) Draw how the energy band diagram of the pn junction (Si) will be changed if
the reverse voltage is applied (0.6 V). b) Draw the orientation of the diffusion
voltage and of the reverse voltage.
10.
a) Draw how the energy band diagram of the pn junction (Si) will be changed if
the forward voltage is applied (0.6 V). b) Draw the orientation of the diffusion
voltage and of the forward voltage. c) Draw the diffusion voltage and the reverse
voltage in the band diagram.
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4 Semiconductor diodes
In this chapter we will go over the technology and use of semiconductor diodes.
Production of semiconductor diodes or any semiconductor devices begins with a wafer of
semiconductor material. For high production yields the uniformity of the wafers is
indispensable and therefore monocrystalline materials are used. In first step the single crystal
(called as boule) in shape of a cylinder is made. Then the cylinder is sliced into thin wafers
using a diamond annular saw. After cutting process the wafers have some saw marks that
must be removed. This is achieved using a combination of mechanical polishing and chemical
etching until the surface of the wafer is optically flat. To time 6 inch diameter wafers are
industrial standard.
The performance of a semiconductor device is determined primarily by the distribution
of charge carriers, both electrons and holes. A depletion layer is formed in case of both metalsemiconductor or PN junction devices, nevertheless the diodes differ between them by the
way how the junction is made.
Starting from the first bipolar transistor in 1948 semiconductor industry passed through
massive development. Many new processes were invented and after about 20 years it results
in epitaxial planar technology. To follow the issue of semiconductor diode technology we will
begin with point contact diode and alloy junction technology.
4.1 Point-contact diodes
Point contact diodes were first semiconductor devices that found large use in
electronics.
Cat's whisker or crystal diodes. The cat's whisker diode consists of a thin or
sharpened metal wire pressed against a semi conducting crystal. Cat's whisker diodes, usually
made from galena were used in early radio receivers. The wire formed the anode and the
crystal formed the cathode, so it was in principle Schottky diode. Nevertheless not all cat's
whisker diodes made after then were based on principle metal-semiconductor contact
phenomena.
In case of germanium point contact diode N-type semiconductor and a wolfram wire
are used. After pressing the wolfram wire against the semiconductor crystal a short forward
current pulse is forced. This way a crystal defects which behave as P-dopants are shaped in
close vicinity of contact. Thus the junction is in principle a miniature PN junction with very
low area. The capacitance of germanium point contact diode is about 1pF which gives a
possibility to use it as a rectifier for frequency up to 100 MHz.
Germanium point contact diode with gold wire has more reliable technology. Gold is
here alloyed with gallium (about 3%¨). During the forward current pulse gallium diffuse to
germanium N-crystal and thin PN junction is shaped in close vicinity to contact. The diode
has a bit larger capacitance (2 pF) but
reproducibility is much higher. Both type of germanium point contact diode have had
very large utilization in all kind of electronics between 1960 – 1980. To time these diodes are
not used in large scale.
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Fig. 4.1: Semiconductor (a) of germanium point contact diode. (b) Germanium point
contact diode with gold wire (c) Planar silicon diode
Microwave silicon point contact diode on the other hand is a Schottky diode. It is
made from P-type silicon and wolfram wire. Silicon is heavily doped which helps to obtain
high ultimate frequency but also brings very low reverse breakdown voltage. To suppress
parasitic inductance and capacity microwave diodes have not wire leads but only a contacts
on enclosure. The limit frequency is about 10 GHz. Microwave silicon diode must be used
carefully with respect to very low breakdown voltage.
4.2 Planar diodes
By all planar diodes diffusion of dopant is a basic process in device technology.
Diffusion is high temperature process by which the dopants diffuse from the
semiconductor surface into the semiconductor bulk. Temperature of diffusion is between 900O
C and 1100° C and whole diffusion process can take several hours. The resulting density
profile depends on temperature, on dopant species and on type and purity of semiconductor.
Diffusion process is extremely complicated and is not easy to compute the right process
model.
Planar technologies are schematically visualized on the Fig. 4.1.
Alloyed junction (a) was usually made on N-Type germanium crystal. Contact is made
with three valent metal (In or Al). PN junction is made by diffusion of metal atoms into the
semiconductor by elevated temperature. Advantage is quite simple technology, disadvantage
low reproducibility. Between 1960 - 1970 alloy junction technology was replaced by planar
diffusion technology.
Diffusion Mesa technology (b) is based on diffusion process made en masse for whole
wafer batch. To remove the defects on fracture edges the junction is etched at edges. The
name of the device comes out from the Mesa rock formation with very similar profile.
Diffusion Planar Technology (c). Diffusion is here controlled by a mask made from
silicon oxide. The oxide mask determines precisely the position of the junction. Advantage in
comparison with the Mesa technology is that the junction can be arbitrary small.
Disadvantage of both diffusion planar technology and diffusion mesa technology is that for
different types of diodes there is a need of differently doped substrates and moreover the
substrates must not have the defect and impurities.
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Fig. 4.2: Technologies for planar diodes. (a) Alloyed junction. (b) Diffusion Mesa
technology. (c) Diffusion Planar Technology. (d) Epitaxial Planar technology. (e) Schottky
diode made by Epitaxial Planar technology. On pictures (a-d) there is not drawn an aluminum
contact layer. In picture (e) the aluminum layer is a part of the diode structure.
Epitaxial Planar technology (d) The problem of high quality substrate of different
doping level is here solved by deposition of epitaxial layer on standard grade substrate
(wafer). Epitaxy is an ordered crystalline growth on a single-crystalline substrate. The lattice
structure and orientation or lattice symmetry of the epitaxial layer is identical to that of the
substrate on which the epitaxial layer is deposited. If the substrate is a single crystal, then the
epitaxial layer will also be a single crystal with the same crystallographic orientation.
Advantage of epitaxy is high growth rate of epitaxial layer which allows the formation of
films with thickness up to 100 µm. Using epitaxial planar technology all demands on the
defects and impurities free semiconductor can be satisfied. Moreover the epitaxial layer can
have arbitrary dopant density or dopant density profile. PN junctions made in epitaxial layer
can therefore have very large variety of properties. On the other hand substrates for epitaxy
need not to be extremely pure and they can be produced only in few types in very large scale
mass production, which make the production very cheap.
Schottky diode made by Epitaxial Planar technology(e). Aluminum contact layer is
at the same time the function part of the metal-semiconductor junction. Epitaxial planar
technology gives possibility of arbitrary doped high quality epitaxial layer for the junction.
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Note:
1. Thermal oxidation is one of the most basic deposition technologies in technology of
silicon semiconductors. It is simply oxidation of the silicon substrate surface in an oxygen
rich atmosphere. To speed up this process the temperature is raised to 800 O C – 1000O C. The
growth of the oxide film is controlled by diffusion of the oxygen into the silicon substrate.
When the thickness of the oxidized layer increases the diffusion of oxygen to the substrate
becomes more difficult. For films thicker than 100 nm the relationship between film thickness
and oxidation time is therefore parabolic. It means that the thickness of the oxide layer can be
controlled quite precisely.
2. Silicon oxide has excellent electric, chemical and mechanical properties. Its
coefficient of thermal expansion is not much different from that of silicon, which gives a
possibility of high temperature processing. In fact, existence of such oxide greatly contributes
to perfection of silicon based semiconductor technology. There is no other semiconductor
material with such “perfect” oxide.
3. The protection of the semiconductor devices by silicon dioxide coating gives a
possibility to work without sealing. Because of that cheap plastic encapsulation can be
used.
4. The protection of the semiconductor devices by silicon dioxide coating gives a
possibility to work without sealing. Because of that cheap plastic encapsulation can
be used.
4.2.1
Examples for Chapter 4.2
Example 4.1a:
Four identical silicon diodes with diffusion voltage UD = 0.7 V are in the circuit
with four resistors. Find the currents through each diode when UN = 24 V, the
resistance of all four resistors is 1 kΩ.
Example 4.2b:
Find the currents I and ID in the circuit. The diode is silicon with U D = 0.7 V ,
U N = 15 V , R1 = 10 kΩ , R2 = 20 kΩ , R3 = 20 kΩ .
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65
Example 4.3c:
Find the voltage on the diode and the current through the diode. The diffusion
voltage of the silicon diode is U D = 0.7 V , U N 1 = 15 V , U N 2 = 10 V ,
R1 = R2 = R3 = R4 = 10 kΩ .
Solution in Chapter 8.1.1
4.3 PIN diodes
A PIN diode has a central un-doped, or intrinsic, layer, forming a P-type / Intrinsic / Ntype structure. They are used as
1. Radio frequency switches because of very low capacitance.
2. Large volume ionizing radiation detectors and photo detectors because of large
volume junction
3. Rectifying diodes in power electronics, as their central layer can withstand high
voltage.
4.4 Zener diodes
Zener diodes use the PN junction reverse voltage breakdown to work as voltage
stabilizer or a voltage reference. Breakdown occurs at a precisely defined voltage which is
given by dopant density in less doped part of the junction ( see the Fig. 4.3) . Of course the
semiconductor material has influence on the breakdown process and affects the voltage value.
Zener diodes are made to conduct backwards.
Fig. 4.3:
Dopants density dependence of breakdown voltage by PN junction
Note:
1. Thermal dependence of breakdown voltage is given by mechanism of Zener (tunnel
transition) and avalanche breakdown. In case of silicon by breakdown voltage about 5 V the
thermal dependence of both mechanism is balanced and the breakdown voltage is practically
independent on the temperature.
2. For higher voltage reference circuits Zener and switching diodes are connected in
series and opposite directions to balance the temperature coefficient. Devices labeled as highvoltage Zener diodes are actually avalanche diodes.
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3. Two equivalent Zener diodes in series connected in reverse order can serve as a
transient absorber.
4.4.1
Examples for Chapter 4.4
Example 4.4:
Explain the principle of operation of the Zener diode voltage regulator.
Example 4.5:
There is given the Zener diode voltage regulator with the following parameters of
the diode: U Z = 7 V , rd ≈ 0 , I D min = 20 mA , I D max = 200 mA ; the series resistance
of the regulator is R = 200 Ω . The mean value of the input voltage is
U1 = 50 V with ripple ∆U1 = 5 V . Find the maximum and the minimum possible
resistance of the load R L , of the voltage across the load should be constant and
equal to 7 V.
Example 4.6:
Zener diode regulator design. The input voltage is U1 = 30 V , the output voltage
across the load R L = 300 Ω should be U 2 = 20 V . Use Zener diodes with
parameters rd = 2 Ω , U Z = 9.5 V . Discuss the power dissipated at all devices of
the regulator; consider the following three possibilities: regulator with load
resistance R L = 300 Ω , regulator with open output terminals, short-circuit at the
output.
Solution in Chapter 8.1.2
4.5 Varicap or varactor diodes
These diodes use the voltage dependence of PN junction capacitance to work as
voltage-controlled capacitors. Under reverse bias, the carriers in each region (holes in the P-
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67
type and electrons in the N-type) move away from the junction, leaving an area that is
depleted of carriers. Thus a region that is essentially an insulator has been created, and can be
compared to the classic parallel plate capacitor. The effective width of this depletion region
increases with reverse bias, and so the capacitance decreases. Thus the depletion layer
effectively creates a voltage dependent junction capacitance. Control voltage can be varied
between the forward conduction region and the reverse breakdown voltage.
Different junction profiles exhibit different Capacitance-Voltage characteristics:
1. Abrupt junction shows a small range of capacitance due to its diffusion profile. The
exponent in the equation (xyz) is ½ and as a consequence it offer high quality factor and Q
and low distortion.
2. Hyperabrupt junction allows a larger change in capacitance for the same range of
reverse bias. For this case the exponent in equation (XYZ) is close to 1.
3. Hyper-hyperabrupt capacitance diodes show a large change in capacitance for a
relatively small change in bias voltage. This is particularly useful in battery powered systems
where the available bias voltage is limited.
The varicap (or varactor) diode can be modeled as a variable capacitance (Cj ), in series
with a resistance (Rs):
The capacitance (Cj )depends upon the reverse bias voltage, the junction area, and the
doping densities of the semiconductor material ( 3.60 ).
The series resistance (Rs) exists as a consequence of the remaining undepleted
semiconductor bulk resistance, of the resistance between die and substrate, and of a small lead
component: Series resistance determines the performance of the device under RF conditions.
The quality factor under RF conditions is Q = (xxx)-1. přepsat
To maximize Q, Rs must be minimised. This is achieved by the use of an epitaxial
structure to minimize the amount of high resistivity material in series with the junction.
Example of connection of capacitance diode as variable capacitance is on the Fig. 4.4:
1. To allow voltage control diode must be separated from the circuit by capacitance.
2. The voltage source has usually very low internal resistance. It must be detached by a
resistor of about 100 kΩ to avoid a short circuit of the capacitance diode.
Fig. 4.4:
Connection of varicap diode to resonant RC circuit.
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Capacitance diodes replaced older designs with mechanically driven variable capacitors.
They not only need much lesser volume bur they are also cheap and more reliable.
4.5.1
Examples for capture 4.5
Example 4.7:
There is given the circuit with the diode operating as an analogue switch (as a voltage
controlled resistance).
a) Find the voltage transfer Au = u 2 / u1 .
b) Draw the approximate graph of the voltage transfer Au as the function of the dc
voltage U N .
4.6 Tunnel (Esaki) diode
In the tunnel diode the semiconductor materials are doped to the level of 1019cm-3. This
heavy doping produces an extremely narrow depletion zone where a tunnel transition of
electrons is possible also by forward bias. Because of that a tunnel diode exhibits an unusual
current-voltage characteristic curve when compared with that of an ordinary PN junction
diode. The characteristic curve for a tunnel diode with forward bias is illustrated in Fig. 4.5.
On this characteristic curve there are three important aspects:
1. The forward current increases even with a small applied forward bias and reach up to
peak forward current IP (point P).
2. Afterwards with an increasing forward bias forward current decreases to a minimum
valley current IV (point V)
3. With further increases in the bias voltage normal forward current (based on diffusion
of majority carriers) takes place.
The portion of the characteristic curve between points P (IP) and V (IV) is the region of
negative resistance.
Electronic Devices
Fig. 4.5:
69
Characteristic curve of a tunnel diode compared to that of a standard PN junction.
Note:
1. A region of negative resistance by heavily doped diode discovered in 1958 Leo
Esaki, a Japanese scientist.
2. Tunnel diode has a region of operation showing negative resistance caused by
quantum tunneling.
3. Negative resistance allows amplification of signals and very simple bistable circuits.
Tunnel diodes found their use mainly in microwave applications. These diodes are also the
type most resistant to nuclear radiation.
4. To time the transistors which can replace the tunnel diode in all applications are
available. Tunnel diode was used especially in period 1960- 1990.
4.7 Rectifier diodes
Diodes for use in rectifier circuits are to time made of doped silicon. Before the
development of silicon power rectifier diodes, cuprous oxide and later selenium was used.
The efficiency was low having much higher forward voltage drop and lower reverse bias
breakdown voltage. Large heat sinks were needed, much larger than a silicon diode of the
same current ratings would require.
4.7.1
Line-frequency diodes
Line frequency diodes are intended for rectifiers which convert line frequency AC
power to uncontrolled DC voltage. They can have blocking voltage more than 1000 V and
current ratings up to 1000 A. On the other hand line-frequency diodes have a larger trr, and are
designed to have a low forward voltage drop.
Half wave rectification is the simplest rectifier, which needs only a single diode. Here,
either the positive or negative half of the AC wave passes easily depending on diode
orientation (see Fig. 4.6a). Other half wave is blocked. Because only one half of the input
waveform reaches the output, half way rectification it is very inefficient if used for power
transfer.
A full wave rectifier, which is more efficient, converts both input waveform to one of
constant polarity (positive or negative) depending on connection of diodes in rectifier circuit.
For single phase AC the simplest rectifier topology is using a center tapped transformer (see
Fig. 4.6b). Here two diodes are needed in back-to-back connection (i.e. cathode-to-cathode
for positive voltage or anodes-to-anode for negative voltage).
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Fig. 4.6: Principal schemes of line frequency rectifiers. (a) Half wave rectifier. (b) Full
wave rectifier with center tapped transformer. (c) Full wave rectifier with a bridge rectifier.
When a center tapped transformer can not be used, four rectifiers connected to a bridge
are required to route the AC current. The arrangement of diodes in bridge rectifier is seen on
the Fig. 4.6. This arrangement needs in principle no transformer. A drawback is twice larger
voltage drop because of two diodes in series. By low output voltage this causes large power
loss on diodes.
Note:
Be careful when a bridge rectifier is used for power line rectification. In this case
both output taps are, through the bridge, connected to phase and zero lines alternatively in
each period of AC voltage. Because of that the circuit on the bridge output must not be
connected to the earth. And of course there is a danger of electrical accident (!!!) when
contacting any point of the circuit.
4.7.2
Fast recovery diodes
For use in power electronics and for switched mode power supplies (typically used in
Pulse Width Modulation mode) diodes which requires small reverse recovery time (trr ) are
needed. Diodes are here used not only as rectifier diodes but also as freewheeling and snubber
components. This type of diodes is labeled as fast-recovery diode.
Low forward voltages, short switching times and larger breakdown voltages may not in
fact co-exist easily without proper design and an advanced manufacturing technique. To
achieve the shorter recovery time and lower stored charge, a substantial reduction of the
lifetime of minority carriers and also improved control over its distribution in depletion laeyr
is required.
Lifetime Control. A reduction in the recovery time is made by fast recombination of
minority carriers. Lifetime control can be obtained by the introduction of recombination
centers into the N-type region which can be made by two processes - using thermal diffusion
of gold or platinum or bombarding the silicon wafer with high energy particles (electron
irradiation or proton or alpha particles).
The introduction of recombination centers leads to an undesirable increase in leakage
current. Here is a difference between the dopants. For equal forward conduction
characteristics, the leakage current of electron-irradiated and platinum-doped devices are
much lower than for the gold-doped device. Electron irradiated parts also tend to have
snappier recovery characteristics while using gold or platinum diffusion, and the diodes show
much softer recovery.
PIN structure. Almost all of the power semiconductor diodes manufactured today are
made up using the same type of PIN structure. By fast recovery diodes this structure allows to
bring the widest range of performances and characteristics, such as blocking voltage
capability, forward voltage drop and switching speed.
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71
-
The intrinsic-like layer is here made by low doped N region between regions N and P+.
N region has the function to absorb the depletion layer created at the moment of the reverse
polarization (reverse bias) of the PN junction. Therefore the dimension of this region will
determine the blocking voltage characteristics. On the other hand the N region brings a
significant resistance to the forward current during the conduction of the diode. As
consequence the forward voltage drop and on state power are increased. To overcome this
problem, the preferred solution is to provide very high injection efficiency and a very “thin”
base (the N region) physical dimension. The presence of N region causes that a PIN structure
rectifier requires a certain time before it change status form forward conductivity to voltage
blocking in the reverse direction and vice versa.
Recovery softness is particularly important by high power rectifiers. In fact, when the
slope of the recovery (tb , see Chap .3.8) is very fast, it will generate significant radiated and
conducted noise. The induced over-voltage may also cause damage to the diode or the
switching element if the breakdown voltage is exceeded. The softness is related to the
quantity of charges left in the N region after the full spread of the depletion zone in blocking
mode. To sustain the current demand of the external stray inductance, allowing the current to
return to zero in a smoother way, the charge left in the N region must not be too low. On the
other hand, by keeping tb at the minimum, the losses in the diode might be reduced. However,
in such case, a much higher noise level is generated that requires additional cost in snubbers
and filtering to maintain the noise under the standard limit.
4.7.3
Schottky diodes
Schottky diodes are created by bonding a metal (Pt or Al) to a N-type silicon. Their
advantages are very low forward voltage drop (around 0.3 V) and very high switching speed
(less then 0,1 ns). Schottky diodes are therefore ideal for the output stages of a switching
power supplies and are also used in very high frequency applications. The little reverse
recovery time which they exhibit is casused rather by their capacitance then minority carrier
recombination.
Design considerations with Schottky diodes are limited because of their reverse leakage
currents being many times higher then by PN junction diodes. Also temperature ratings are
lower - depending on the device it is between 125ºC and 160ºC while by PN junction the
permissible temperature is 150ºC to 200ºC. Very important is relatively low reverse bias
breakdown voltage, which is limited to value from 50V to 100 V (because of very thin
depletion layer).
4.7.4
Avalanche diodes
When a diode is reverse biased and the reverse bias voltage pulses can exceeds the
breakdown voltage a large reverse current will result. This large current may destroy the diode
by the thermal breakdown also in the case that the allowed power load is not exceeded. The
result depends on the junction technology.
Avalanche diodes are designed to break down at a well-defined reverse voltage without
being destroyed. These are electrically very similar to Zener diodes, and are often mistakenly
called Zener diodes, but they not only break down by a different mechanism (the avalanche
effect) but mainly they have quite different use.
Avalanche diodes can be also used to protect other semiconductor devices from highvoltage transients. Such diodes must have p-n junctions with a much larger of cross-sectional
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area than those of a normal diode, allowing them to conduct large currents to ground without
sustaining damage.
4.8 LEDs and Phototiodes
Light emitting diodes and photodiodes are based on generation and recombination
phenomena in in depletion zone and in quasi-neutral regions of PN junction. Here is only a
short summary of their basic properties.
4.8.1
Light-emitting diodes and lasers
Light-emitting diodes (LED) are formed from a direct band-gap semiconductors AIIIBVI,
such as gallium arsenide (GaAs) or indium phosphide (InP). After crossing the junction
carriers recombine by radiative recombination with the majority carriers Depending on the
material bandgap the wavelength of emiting light starts from the infrared area (GaA; 1,4 eV)
and reach up to blue (InP; 3,5 eV). The forward voltage of LED diodes depends on the
semiconductor material. So the voltage 1.2 V corresponds to red, 2.4 V to blue.
When an special LED-like structure is contained in a resonant cavity formed by
polishing the parallel end faces, a laser can be formed. Laser diodes are commonly used in
optical storage devices and for high speed optical communication .
4.8.2
Photodiodes
In case that the energy of light photon impacting on semiconductor is larger than the
energy bandgap of semiconductor light absorbed in the semiconductor generates electron-hole
pairs. When semiconductors are subjected to light the photogeneration allways takes place. To
prevent light generation semiconductor devices must be packaged in light blocking material.
On the other hand if they are packaged in materials that allow light to pass, their
photosensitivity can be utilized.
If the light is absorbed in the depletion region of the diode the electric field in the
depletion zone ensure that the electrons and holes are separated. When the junction is
shortciuted by external circuit then through this cuircuit will pass a current proportional to the
impacting lihgt power. By no load the open circuit voltage can be measured. In this cese the
dependence is nonlinear – roughly logarithmic.
To achieve effective operation the large depletion region is convenient. This is easily
assured by making the absorbing layer undoped (PIN structure). PIN fotodiode is often used
device. When the light photon is absorbed outside the depletion region the electron hole pair
can contribute to the photovoltaic effect only in the case that the point of generation is within
the diffudion length from the junction. (Diffusiion lentgth depends on minority carrier
lifetime - see the equqtion ( 3.41)
Photodiodes can be operated in two very different modes:
1. Photovoltaic mode (a solar cell mode). The illuminated photodiode generates a
voltage and current (depending on the load) which can be measured. However, the
dependence of voltage on the light power is rather nonlinear, and the dynamic range is quite
small. Also, the maximum speed is not achieved.
2. Photoconductive mode. The junction is in this case reverse biased. A measure of the
light power is the resulting photocurrent. In fact it is sufficient to keep the applied voltage
Electronic Devices
73
close to zero. In this regime the dependence of the photocurrent on the light power can be
very linear over six or more orders of magnitude of the light power. The magnitude of the
reverse voltage has nearly no influence on the photocurrent and only a weak influence on the
dark current (dark current is obtained without light). Higher voltage tends to make the
response much faster. Unfortunately also the powerloss is higher, which is of importance by
avalanche photodiodes.
The I-V chracteristics and both photovoltaic and photoconductive modes are visualized
on the Fig.4.7.
Fig. 4.7:
I-V chracteristics photovoltaic and photoconductive modes
4.9 I-V characteristics of diode
I-V characteristics of diode are used to be drawn with different scales. An example is on
the Fig. 4.8.
There are other types of diodes, which all share the basic function of allowing electrical
current to flow in only one direction, but with different methods of construction.
Fig. 4.8: I-V characteristics of semiconductor diode with different scales. (a) Low voltage
and low current scale. (b) Coarse scale for voltage. (c) Coarse scale for both voltage and
current. (d) Different scales for current and voltage.
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Example 4.8:
There is given a simple circuit with a silicon diode (UD = 0.7 V), a voltage supply UN =
4.5 V and a resistor R = 0.560 kΩ. The current-voltage characteristics of the diode is
known from the catalogue sheet.
a) Find the operating point of the diode, use the graphical solution.
b) Draw how the position of the diode operating point will be changed if the voltage UN
or the resistance R are changed.
Solution:
a) The circuit consists of a single loop; the equation of the loop is also the equation of the load line:
U N = RI + U
To draw the load line we find its intersections with the coordinate axes:
U = 0 ….. I = U N R ; I = 0 …. U = U N
The operating point P of the diode lies at the intersection of the load line with the diode
characteristics; its coordinates U ( P ), I ( P ) determine the current through the diode and the voltage
across the diode.
b) See the figures:
Electronic Devices
75
4.10 Diode substitute circuit
Diodes are referred to as non-linear circuit elements nevertheless for most applications
the non-linear region can be avoided and the device can be modeled by piece-wise linear
circuit elements. Qualitatively we can just think of an ideal diode has having two regions: a
conduction region of zero resistance and an infinite resistance non-conduction region. For
many circuit applications, this ideal diode model is an adequate representation of an actual
diode and simply requires that the circuit analysis be separated into two parts: forward current
and reverse current.
5 Bipolar Junction Transistor
Bipolar junction transistor is a complex semiconductor device. Aim of this chapter is to
explain its operation and give the basic knowledge of transistor circuits as amplifiers,
electronic switchers and constant current sources. Computation of transistor circuits is
explained using examples of typical transistor circuits.
The invention of the bipolar transistor in 1948 started a revolution in electronics. Soon
the design and manufacture of lightweight, inexpensive electronic devices were possible
resulting in today’s all purpose electronics and sophisticated computer technology.
A bipolar junction transistor (BJT) is a three-terminal device constructed of doped
semiconductor material. Bipolar transistors are so named because their operation involves
both electrons and holes.
Bipolar transistors work as current-controlled current regulators. It may be used in
amplifying or switching applications.
5.1 Structure of bipolar transistor
A Bipolar junction transistor (BJT) consists of three differently doped semiconductor
regions, the emitter region, the base region and the collector region. These regions are,
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FEKT Vysokého učení technického v Brně
respectively, P-type, N-type and P-type in case of a PNP transistor, and N-type, P-type and Ntype in case of a NPN transistor. Contacts on this regions are emitter (E), base (B) and
collector (C) respectively. Each BJT structure has following properties:
1. The base B is physically located between the emitter E and the collector C and is
made from lightly doped (high resistivity) material.
2. The base is very thin. The thickness should be much less then the diffusion length of
minority carriers in the base.
3. The heavy doping of the emitter region and light doping of the base region cause that
in case of forward bias many more carriers diffuse from the emitter into the base than that
from the base into the emitter.
4. The collector is in close vicinity of the emitter region, making it almost impossible
for the carriers injected from emitter into the base region to escape towards the base contact.
5. The base contact is usually far from the EB junction (more then few diffusion
lengths) to impede a collection of carriers injected from emitter.
On the Fig. 5.1 a there is a indication of emitter-base current in such structure for
emitter-base junction in case of PNP transistor. It is seen that before the current reach the
base contact it passes in close vicinity to base surface. When a PN junction is made in this
region the carriers must pass through this junction.
Now we consider the mostly used regime of bipolar transistor which is forward active
bias mode operation. This mode is obtained by forward biasing the base-emitter junction and
reverse biasing the base-collector junction. On the Fig. 5.1. this case is visualized for PNP
transistor.
Fig. 5.1: PNP bipolar junction transistor. (a) The current through base region. (b) In
forward active bias mode operation the collector takes over a great part of the emitter current.
Following considerations (ad.1–ad.6) are valid for PNP transistor. Using the NPN type
the role of electrons and holes interchanges:
1. In case of forward bias on EB junction large amount of holes is diffusing from the
emitter into the base. (Because of uneven doping level in base and emitter respectively there
is only a small amount of electrons which diffuse from the base into the emitter.) This carrier
diffusion is identical to that in a p-n junction. After passing the junction majority carriers
become minority carriers and recombine with time constant which is given by the lifetime of
minority carriers in base.
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77
2. When the BC junction is in diffusion length distance holes from emitter carriers can
reach the Base-Collector (BC) junction before they recombine in the base. Once the holes
arrive at the base-collector depletion region, they are swept through the depletion layer due to
the electric field. So the holes that diffuse from emitter contribute to the collector current.
3. When the voltage on the collector is more negative the force pulling the N-type
electrons and P-type holes apart increases. This widens the depletion zone between the
collector and base. However the consequently by magnitude of emitter current.
4. Magnitude of emitter-collector current is set by the chosen Emitter-Base voltage. The
current flow through the transistor is maintained by putting fresh carriers into the emitter by
means of external circuit and removing them from the collector after passing the depletion
zone of CB junction. Hence, a small change of the base voltage (or of the base current) can
translate to a large change in flow of holes between emitter and collector.
5. Most holes that get into the Base move straight on into the CB junction and electrical
field in the depletion layer draws them out of the base region to collector. (Because holes are
majority carriers in collector they are not subjected here to recombination.) On their way to
CB junction some of the holes recombine in base-emitter depletion layer and further on their
way across the base. This recombination needs some electron current from the base contact.
For most practical Bipolar Transistors only about 1% of the free carriers which try to cross the
Base region is catch in this way. Therefore for most transistors base current IB, is typically
around one hundred times smaller than the Emitter Current, IE.
6. Bipolar transistor can this way amplify the input base current into much larger
collector current. On the other hand we can also state that it works as the constant current
source which is controlled by base emitter voltage. We will learn further which interpretation
chose for different situation and circuits.
All currents in the BJT structure in case of normal mode operation are visualized in Fig.
5.2 for NPN type transistor. Mind that for PNP type function of electrons and holes
interchanges.
IB
backward hole injection B? E
hole component of the emitter
junction current
B
electron-hole
recombination
inside base
electron and hole
components of the
collector junction current
IE
n
emitter
p
base
E
electron injection E? B
electron component of the
emitter junction current
Fig. 5.2:
n
collector
IC
C
electron diffusion
across base
Normal mode operation of the BJT
electron extraction by the
strong electric field in the
collector junction
electron component of
the collector current
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Note:
EMITTER emits the electrons which pass through the device. The emitter current is
made by diffusion of majority carriers from the emitter to base because of large gradient of
carrier density.
COLLECTOR collects them after they have passed through the Base-Emitter junction.
By reverse bias PN Junction tends to extract minority carriers from quasi-neutral parts of the
junction. In or close to thermal equilibrium the density of the minority carriers is low and
there is only small current in the CB junction. However in case of forward bias of on of EB
junction the energetic barrier which inhibits the diffusion of carriers through the EB junction
lowers and the diffusion of majority carriers is possible. After passing through the junction
the majority carriers from emitter change to the minority carriers in the base and thus can be
extracted by reverse biased CB junction.
BASE Further we will see that early transistors were made by creation of emitter and
collector junctions as an alloy junction on both sides of tiny N-type semiconductor slice.
Whole semiconductor bulk was therefore electrically identical with the inner layer of BJT
sandwich structure which was also the mechanical support or BASE of the device.
COMMON BASE circuit. Because of very low current gain early transistors were used
the way that the semiconductor bulk (BASE) was grounded and separated power sources were
used for emitter (negative voltage ) and collector (positive voltage) circuits respectively. This
type circuit is labeled as COMMON BASE.
5.2 Operation of bipolar transistor
In typical operation, the emitter-base junction is forward biased and the base-collector
junction is reverse biased. This regime is used by A-class voltage amplifiers. Nevertheless
there are other applications of bipolar transistor, as a switch or B-class amplifier for example,
where the function of both junction changes.
5.2.1
Modes of operation
Different modes of BJT operation are given by reverse or forward polarization of
emitter and collector junctions (see Tab. 2):
Normal mode operation
In normal operation CB junction is reverse biased. The reason the emitter is heavily
doped is to increase the emitter injection efficiency. For high current gain, most of the carriers
injected into the EB junction must come from the emitter. Small changes in the voltage
applied across the BE terminals causes the diffusion current that flows from emitter to base
and is extracted by reverse polarized BC junction. The voltage dependence of emitter current
is exponential. Therefore small change of voltage between the base emitter causes the emitter
(=collector) current to change significantly. This effect can be used to amplify the input
voltage or current.
Saturation mode
The BJT enters saturation when the base current is increased to a point where the
external circuitry prevents the collector current from growing any larger. At this point, the CB
junction becomes forward biased. A residual voltage drop of approximately 100 mV to 300
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79
mV (depending on the amount of base and collector current and their ratio) then remains
between collector and emitter. This regime is used in transistor switching (ON state).
Cut-off regime
In the cut-off region the BE voltage is too small for any significant emitter current to
flow or the BE junction is biased reversely. In this state the collector current is very low. This
regime is used for transistor switching (OFF state).
Inverted operation
Interchanging the collector and the emitter makes the transistor leave the forward active
mode and start to operate in reverse mode. Because the internal structure of BJT is usually
optimized to forward-mode operation, interchanging the collector and the emitter makes the
current gain of reverse operation much smaller than in case of forward operation.
The lack of symmetry is primarily due to very different doping ratios of the emitter and
the collector. The emitter is heavily doped, while the collector is lightly doped, allowing a
large reverse bias voltage to be applied before the CB junction breaks. Moreover the area of
emitter is much smaller then that of collector. So in inverted operation the collector cannot
serve as emitter and vice versa emitter is not very good in extraction of minority carriers from
the base.
Tab. 2:
mode of operation
emitter-base junction
collector-base junction
active normal
(active forward)
forward biased
reverse biased
active inverse
(active reverse)
reverse biased
forward biased
saturation
forward biased
forward biased
cut-off
reverse biased
reverse biased
breakdown
forward biased
breakdown
Bipolar junction transistor: modes of operation
5.2.2
Two types of bipolar junction transistor
NPN is one of the two types of bipolar transistors, in which the letters "N" and "P" refer
to type of impurities ( and the majority charge carriers) inside the emiter collector and base
regions respectively. of the transistor. NPN transistors are commonly operated with the
emitter at ground and the collector connected to a positive voltage through an electric load. A
small current entering the base in common-emitter mode is amplified in the collector output.
The arrow in the NPN transistor symbol is on the emitter and points in the direction of
the conventional current flow when the device is in forward active mode. (It means that the
arrow always points against the direction of electron flow!!)
The other type of BJTs is PNP transistors, which consist of a layer of N-doped (often
doped with boron) semiconductor between two layers of P-doped (often with phosphor)
material. Since it reverses the roles of the free electrons and holes it works in a similar way,
but with the voltages and currents reversed. So, if we replaced the NPN transistor with a PNP
we could just reverse the polarities of the applied voltages and the directions of the current
arrows and it works !!!
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VCE
- +
VCE
IC
IE
n
p
n
emitter base collector
-
+
IC
IE
p
n
emitter base collector
IB
IB
-
+ VBE
C
VBC = - VCB
B
VCB
IB
+
+
VBE
VCB = - VBC
C
VBC
IB
IC
B
IC
VEC
-
IE
VCE = VCB + VBE
IE = IB + IC
-
VCE
+
p
IE
VEC = VEB + VBC
VBE
E
IE = IB + IC
VEB
E
Fig. 5.3: Common emitter configuration for NPN and PNP types of BJT in normal (active
forward) mode operation
Most bipolar transistors used today are NPN, since electrons mobility in silicon is
higher than holes mobility. Nevertheless fast to all NPN transistors the PNP counterparts are
made with comparable parameters. When changing the polarity of voltages and currents, as
suggested before, the function of the transistor in circuit would be mostly the same. And what
is important - there is great variety of complex circuits where both types NPN a PNP
transistors are used simultaneously.
5.3 Technology of bipolar transistors
The earliest transistor types were point contact types made from germanium and were
used rather for research and experiments then for a production of electronics. Their
performance was pure, the current gain was low and they were limited not only in reliability
but also in high frequency performance and power handling. After a few years, the point
contact transistor technology had been superseded by junction transistor technology.
By grown-junction transistors a single crystal of germanium was grown and doped at
the same time. The crystal was pulled slowly but continuously from a melt containing initially
N-type impurities, to which P-type impurities were later added and left for a short while, then
more N-type was added again. The result was an N-doped crystal with a thin P-type layer in
it. The crystal was then cut into small blocks each forming a single NPN transistor.
At the same time diffusion based technologies were developed. Resulting devices had
better performance starting already from the first type - alloy junction transistor, where the
diffusion areas were shaped on the interface between the semiconductor bulk and metal alloy
contact. Structures of diffusion transistors are schematicaly drawn in the Figure 5.6.
Alloy junction transistors (a) were first types. Both emitter and collector layers were
here made as an alloy junction on both sides of tiny N-type semiconductor slice. Two beads
of indium (three valence metal to form P-type region) were fused onto a thin N-type
germanium block, one on either side. High temperature used by alloying allows some indium
atoms to diffuse into the germanium. Thus two junctions are created and hierwith the PNP
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81
structure transistor. This process was easier to control and reproduce than in the grownjunction case, yielding a thinner base layer, which gave a better high-frequency response.
Diffused base transistors (b) were established between 1954 and 1955. Diffusion was
performed using the dopant species in gas phase. This gave a possibility of precise control of
diffusion process allowing thus creation of a very thin base region through the controlled
diffusion of impurities into the mono-crystalline germanium or silicon. The resultant diffused
base transistors performed at much higher frequencies than other transistor types of the day.
Moreover the dopants density in collector was lesser then that in the base giving much higher
breakdown voltage of CB junction
Diffused mesa transistor (c). Mesa transistor technology has similar aspects as the
mesa process used for production of PN junction diodes. Mesa technology brought further
improving of diffused base transistor resulting in much higher cut off frequency. Mesa
structure is used up to this day for some (special) high frequency transistor.
Fig. 5.4:
Diffusion transistors. (a) Alloy junction transistor. (b) Diffused base transistor. (c)
Diffused mesa transistor. (d) Diffused planar transistor. (e) Epitaxial planar
transistor. (f) Epitaxial planar transistor in integrated circuit
The use of diffusion was a first great breakthrough in semiconductor technology. Real
expansion of semiconductor industry however starts with implementation of planar process in
1960.
Diffused planar transistor (d) technology is in principle the same as for production of
PN junction planar diodes. Planar technology is based on the masking and passivating
properties of silicon dioxide. The oxide mask determines precisely the position of the
junction. The difference from PN Junction diode process is that here are two diffusion
processes as described below.
Epitaxial planar transistor (e). As well as in the case of PN junction diodes the
disadvantage of planar technology is that for different types of transistors there is a need of
differently doped substrates and moreover the substrates must not have the defect and
impurities. Therefore in modern technology the structure of the transistor is created in
epitaxial layer which is deposited on the standard grade wafer. In epitaxial layer both collector
and emitter junctions are formed by the same processes as in planar technology using silicon
oxide masking an diffusion of impurities from the top surface. Colector area is in this case
identical with the epitaxial layer. Therefore it can have arbitrary low concentration of dopants
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FEKT Vysokého učení technického v Brně
without influencing the serial resistance of colector circuit which is given by high
conductivity substrate. On the other hand substrate (wafer) having high conductivity need not
be extremely pure.
Epitaxial planar transistor in integrated circuit (f). BJT in integrated circuits must
have collector lead in the same level as base ant emitter. Buried N+ collector is here used to
ensure high collector conductance.
Diffused planar transistor technology process for NPN type transistor is schematically
vizualizeed on the Fig. 5.5. It includes seven basic steps:
(a) N-type wafer is oxidized by exposing to an oxygen carrier gas in a high temperature
furnace.
(b) Selective etching of the oxide using the photolithographic process.
(c) The wafer is exposed to a gas containing boron to create the transistor's base by high
temperature diffusion process. As the boron atoms diffused both vertically and horizontally,
the junction between the collector and the base moves laterally. Junction is therefore protected
from outside contaminants by the silicon oxide layer.
(d) To form the emitter another masking and etching process is performed to shape a
window into the regrown oxide on the base surface.
(e) Through this window emitter is created by phosphorus diffusion process (second
diffusion). This junction (like the base to collector junction) is protected from outside
contamination by the silicon oxide.
(f) After diffusing of the emitter, the silicon oxide layer is selectively etched to provide
areas for alloy contacts
(g) Metal (Al) layers are deposited on the etched areas and alloyed by elevated
temperature with semiconductor material to estabilish a reliable contact.
To contact areas for base and emitter gold or alluminum wire are bonded to provide
external leads. (Not seen on the Fig. 5.4) Collector lead is made by contacting onto the
semiconductor bulk.
Electronic Devices
Fig. 5.5:
83
Diffused planar transistor technology process for NPN type transistor. (a)
Oxidation. (b) Selective etching. (c) Diffusion of base. (d) Shaping the mask for
emitter diffusion. (e) Diffusion of emitter. (f) Shaping the mask for the contacts.
(g) Deposition of metal contacts
Note:
Planar technology fulfill automatically the requirements to doping levels in bipolar
transistor. Emitter is difussed into the base and therefore to change the type of conductivity
(N-type to P-type in case of NPN transistor) the N-dopants density in emitter must be much
higher then P-dopants density in the base. This results in high injection efficiency from
emitter to base. The same way - the base is diffused into the collector so the N-dopants
density in collector is much lesser than P-dopants density in the base resulting in wide
depletion zone in colector area with consequence of high breakdown voltage of CB junction.
5.4 Use of BJT
BJT is used in two basic configuration: as an amplifier and as a switch. Despite a
relative simple structure of BJT the operation of bipolar transistor can be quite complex
because of mutual dependence of transistors parameters and their dependence on temperature.
5.4.1
BJT as electronic amplifier
Bipolar junction transistor is in principle voltage-controlled current sources, but it is
better characterized as current-controlled current source, or current amplifier, due to the low
impedance at the base.
Basic property of BJT is that small voltage changes in the base-emitter junction will
produce large current changes in the collector and emitter, whereas small changes in the
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collector-emitter voltage have little effect on the base circuit. Because the transistor is a threeterminal device there are several posibilities how to connect it to the four-terminal circuit.
Any way the base is always part of the input circuit.
In case of amplifier BJT is used in normal (forward active) mode only. There are three
configurations of BJT amplifiers. The relationship between the voltages and currents in these
configurations is shown in Fig. 5.6:
npn-transistor
IC
B
IB
VCB
C
E
VBE
IE
E
E
IE
IC
IB
C
B
VCE
VBE
IE
VCE
IB
VCB
E
VBE
VCE
VCB
IC
B C
B
C
pnp-transistor
IC
B
IB
VBC
VEB
E
IE
C
E
IE
VEC
IC
C
B
VEC
VEB
IE
E
B
IB
VBC
IB
VBC
B
C
E
VEB
VEC
IC
C
Fig. 5.6: BJT as amplifer. Configurations : (a) Common emitter (CE) (b) Common base
(CB) (c) Common collector (CC)
Common emitter. Emitter is connected to ground and the load is connected between the
collector and power supply. The input voltage appears between the base and emitter, and the
output voltage appears between the collector and emitter. The emitter terminal is shared by (or
common to) the input and output. The voltage source at the base needs to supply only the
base current which is about two orders lesser then the output current. The output signal is a
voltage drop on the load in collector circuit. For example: a) Higher voltage on the base
brings larger collector current. b) On the load connected between the voltage power source
and the collector is then larger voltage drop. c) Consequently the collector voltage will be
lower – a change of input voltage is thus inverted. This means that Common emitter is an
inverting voltage amplifier circuit.
Fig. 5.7:
BT connection
Electronic Devices
85
Common collector. Here the collector is connected to voltage power supply and a load
is connected between the emitter and ground. Because the internal resistance of voltage
power supply is very low for the AC voltage, collector is for AC voltage shorted to the ground
through the voltage power supply. The voltage change applied to the base appears across the
load in emitter circuit. The voltage on the load is lesser than that in the base because of
voltage drop on the BE junction. For DC case the voltage drop is about 0,6 V (for 5 V base
voltage we get emitter voltage about 4.4 V). For AC case the voltage drop (few mV) is given
by dynamic resistance of emitter. This means that voltage gain is always less then one.
Because the AC ouput signal on emitter does not much differ from input signal on the base
this circuit is called emitter follower. Obviously it is non inverting amplifier. The input
impedance is high.
Note:
As dynamic ressistance of emitter diminish with the emitter current we can make the
AC voltage drop on the BE junction very low (the voltage gain close to one) by increasing the
steady state emitter current.
Common base. Base is grounded (or connected at a reference voltage) and the load is
connected between the collector and power supply. In NPN case emmiter must be more
negetive than base and vice versa. Control voltage is connected between the grounded base
and the emitter. The control voltage source must be able to supply both base and colector
current (!) which means that the input imedance is very low. The output signal is a voltage
drop on the load in collector circuit. For example: a) Higher voltage on the emiter tends to
close EB junction. b) This brings lesser collector current. c) On the load connected between
the voltage power source and the collector is lesser voltage drop. d) Consequently the
collector voltage will be higher - change of ouput voltage is thus in phase with change of
input voltage. Common base is a non-inverting voltage amplifier circuit.
Note:
Emitter follower is a current amplifier but has no voltage gain. Common base amplifier
has voltage gain but no current gain. Only common emitter amplifier has both current and
voltage gain.
5.4.2
BJT as electronic switch
In the case of a transistor switch the cuircuit configuration is similar to the amplifier
working with input signal of extremely large amplitude which force the transistor to very
rapid changes from saturation to off state and vice versa. Principally all cuircuit
configurations (CE,CB,CC) can be used also for the BJT switch. Nevertheless in most cases
CE configuration which gives the best switching condition is preffered.
5.4.3
Current gain in BJT structure
In previous chapter we treated the BJT as constant current source or as current
amplifier. Now we need to define foltage the current gain for different cuircuit configurations.
Comon emitter. The current gain is given by ratio IC/IB, and represented by β :
β=
IC
IB
Typically β is greater than 100.
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Comon Base. The current gain is given by ratio IC/IE and represented by α:
α=
IC
IE
This has values usually between 0.98 and 0.998 (IE is a bit larger then IC).
Further, α and β are related by the following relations:
β=
α=
iC
i
iC / i E
α
= C =
=
i B i E − iC (i E − iC ) / i E 1 − α
( 5.1 )
β
( 5.2 )
1+ β
5.5 Characteristic curves of BJT
The behaviour of a bipolar junction transistor described in previous chapters can be
summarized by the characteristic curves shown in Fig 5.8.
Collector potential is here reffered to the emitter (VCE) rather than to the base. Since the
precise collector voltage does not have much effect on the currents in BJT structure, moving
the place of reference is not very important. On the other hand this way is more convenient
from the practical view (by measuring for example).
Input characteristic
Voltage-current characteristic curve of the base-emitter junction has an exponential-like
shape similar to that of a normal PN Junction diode. Of course there is also similar edpenedce
on temperature. Input characteristic describes behaviour of a BJT by relating the base-emitter
voltage, VBE, to the base current, IB.
IC [mA]
VCE > 0.5 V
output
IC = f(VCE)||I
B =const.
IB [µ
µA]
current transfer
IC = f(IB)||V =const.
CE
IB [µ
µA]
VCE [V]
input
IB = f(VBE)||V
CE
IB
=const.
voltage transfer
VCB = f(VBE)||I =const.
VCE = 0
B
VCE > 5 V
VBE [mV]
Fig. 5.8:
Bipolar junction transistor: Characteristics in common emitter configuration
Electronic Devices
87
Ouput characteristic
The set of ouput characteristics is the most used part of transistors characteristics. It
contains a lot of detailed information useful to build any kind of electronic devices with BJT.
Each curve shows how the colletor current (IC) varies with the Collector-Emitter voltage (VCE)
for a specific fixed value of the base current IB.
1. When the Base-Collector junction is biased reversely the minority carriers are drawn
from the base and BJT operates as current controlled current source. The magnitude of the
current is given by diffusion of majority carriers from the emitter. This is set by the chosen
base-emitter voltage. However because of exponential dependence of base-emitter current on
voltage and temperature the base current is used preferently as the parameter of output
characteristics.
2. When the applied (VCE) level is larger then about one volt collector-base junction is
able to to remove free carriers from the base almost as quickly as emitter injects them. As we
decrease the collector potential up to the base potential (VCE = VBE) there is no bias on CB
junction. Nevertheless there is still the build in potential in depletion layer and the electrical
field which can extract the carriers from the base. Consequently the colector current does not
change significantly.
3. When the collector potential, VCE, further decreases (VCE < VBE) CB junction starts to
be forward polarized. In this case the junction voltage acts against the build in potential and
the extraction of carriers from the base becomes less efective. As consequence collector
current diminish and the transistor comes to saturation mode.
4. The precise voltage at which the CB junction stops to extract the carriers from the
base region depends on the temperature and the manufacturing details of the transisor mainly
on built in voltage which is given by dopants density. Transistors with low breakdown voltage
(higher dopants density) tend to have lower voltage in saturation mode.
Note:
1. If BJT works as amplifier VCE value should be at any operation state (given by output
signal amplitude) higher then at least one volt. On the other hand in case of transistor switch
the saturation mode gives the possibly lowest voltage drop on the transistor switch.
2. In reverse mode emitter and collector intechange their function of operation. In this
case it is emitor-base junction which extracts the carriers from the base. Because the density
of dopants is here much lager than in BC junction the built in potential is larger and the
saturation voltage is very low. Reverse mode is therfore used for switching in cuircuits which
works with low amplitude signals (measuring for example).
Current transfer characteristic
Because BJT is a current amplifying device the main characteristic parameter of a BJT
is its current gain value. This depends not only on BJT type but also on various factors as the
transistor's temperature, colector current, collector emiter voltage, etc.
Current transfer characteristic describe the dependence of collector current, IC, on the
base current, IB. From current transfer characteristic we can derive two parameters:
1. DC current gain, β, is determined as ratio IC/IB, and is called the static forwardcurrent transfer ratio.
2. Small Signal current gain, hfe , which is determined as ∆ IC/∆IB at given point of the
current transfer characteristic. This is similar to the β-value, but is defined in terms of small
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changes in the current levels. This parameter is used when considering the transistor's
operation in small signal amplifiers.
Note:
The difference between β and hfe by the same transistor at given temperature can be
much lesser then difference of the same parameters bettween two transistors of the same type
or by the same transistor by different temperature.
Voltage transfer characteristic
Current transfer characteristic describes the dependence of base- emitter voltage, VBE,
on the colector-emitter voltage, VCE. In first view this dependence is weak and can be
neglected. In more detailed consideration we will see that when the base is feeded from
constant current source there is a tendency to diminish base-emiter voltage when the colectoremiter voltage is raised. This effect hang together with change of charge gradient in base.
5.5.1
Early effect
As the applied collector-base voltage (VBC) varies, the collector-base depletion region
varies in width. This means a variation in the width of the base region of the BJT at the same
time. So an increase in the collector-base voltage causes not only increasing of the collectorbase depletion region width but also brings decreasing of the width of the base:
1. There is a lesser chance for recombination within the base region.
2. The charge gradient is increased across the base and because of that the current of
minority carries injected across the emitter junction increases.
Both factors increase the collector current of the bipolar junction transistor when higher
collector-base voltage is applied. This effect is called the "Early Effect" after its discoverer
James M. Early. On Fig. 5.9 is seen that the extended linear parts of output chactristics
encounter each other in one point intersection in the horizontal (voltage) axis. This point is
labeled as Early voltage.
CE output conductivity
Early voltage
IC
Q
IC(Q)
∆VCE
Early
voltage
0
VEarly
typical value
50 V ÷ 100 V
Fig. 5.9:
g out =
VCE(Q)
∆ IC
IB
VCE
 ∆IC 
IC (Q )
I (Q )

=
≈ C
lim 
 IB = const . VCE (Q ) + VEarly VEarly
∆VCE → 0  ∆VCE
Early effect. Determination of Early voltage.
In the forward active region the Early Effect modifies the collector current IC and the
forward common emitter current gain βF as follows:
Electronic Devices

89
v

β ef = β 1 + CB 
VE 

( 5.3 )
Where
VCB is the collector–base voltage
VE is the Early voltage (15 V to 150 V)
βF0 is forward common-emitter current gain when VCB = 0 V
Using Early voltage we can to compute collector dynamic resistance at given
workpoint:
RCE =
iC
I + α N iE
= CB 0
U E + u CE
U E + u CE
( 5.4 )
Note:
A particular voltage breakdown labeled as punchtrough breakdown exists in case of
alloy junction transistor where the colector is dopped almost to the same level as emitter.
When the BC voltage reaches a certain (device specific) value, the BC depletion region
boundary meets the BE depletion region boundary. In this state the transistor effectively has
no base which consequently results in the current breakdow.
5.6 Operation of BJT amplifier
Because BJT is in principle DC device, when applying an AC voltage input signal
between the base and emitter the carriers can flow only in that part of periode during which
the junction is forward biased. When that voltage is sufficiently high to overcome the baseemitter diode's forward voltage drop the transistor will be in the active mode. In other part the
transistor will remain in cutoff mode.
To keep the transistor in its active mode the entire time we must maintain the current
flow through the base during the entire input waveform cycle. This can be accomplished with
the aid of a DC bias voltage added to the input signal. By connecting a sufficient DC voltage
in series with the AC signal source, forward-bias can be maintained at all points throughout
the wave cycle.
For practical use the voltage source in series with the input voltage is not much
convenient. As we will see further, DC bias is set by means of resistors which act as current
source or voltage divider.
5.6.1
Operation point of BJT amplifier
The simplest circuit in common emitter (CE) configuration is demonstrated on the Fig.
5.10.
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FEKT Vysokého učení technického v Brně
RB
IB
VCC = R B IB + VBE
IC = β IB
RC
VCB
VBE ≈ 0 . 7 V
assumption: active normal mode:
+ VCC
V − VBE
⇒ IB = CC
RB
IE = IC + IB = β IB + IB = ( β + 1)IB
IC
VCC = RC IC + VCE
VCE
VCE = VCC − RC IC
⇒
VCB = VCE − VBE
VBE
IC
VCB = 0
PCmax
load line:
VCC = RCIC+ VCE
IE
VCC
RC
IB(P)
Q
IC(Q)
IB
IB = 0
VCE(Q)
VCC
VCE
Fig. 5.10: Operating point of BJT: The simplest fixed-bias circuit
The operation point depends on β and therefore is not much stable. We must always
consider the influence of temperature and of Early effect. Moreover β can differ between two
transistors of the same type. More better is the circuit on the Fig. 5.11. Here the operation
point is stabilized by means of negative feedback.
BJT operating point: collector feedback (or voltage or parallel feedback)
+ VCC
assumption: active normal mode: VBE ≈ 0 . 7 V
← IB + IC = ( β + 1)IB
VCC = RC (IB + IC ) + R B IB + VBE
RC
RB
IB
IB + IC
VCC − VBE
R B + ( β + 1)RC
IC = β IB , IE = IC + IB = ( β + 1)IB
IB =
IC
VCB
VCE
IB
VCC = RC ( β + 1)IB + R B IB + VBE
VCC = RC (IC + IB ) + VCE
⇒
VCE = VCC − RC (IC + IB )
VBE
∆I C > 0
R C ∆I C > 0
∆VCE < 0
∆ IB < 0
∆VBE < 0
∆I C < 0
IE Bias stability – the effect of RB:
• collector current increases
(e.g. if temperature increases)
• voltage drop across resistor RC increases
• voltage VCE decreases: VCC = RCIC+ VCE
const. increases
decreases
• voltage RBIB and VBE decrease: RBIB + VBE = VCE
decrease
decreases
• collector current decreases
Fig. 5.11: BJT operating point: Collector feedback (or voltage or parallel feedback)This
circuit works well in case of not large variance of β. In some application very low input
resistance due to feedback circuit may be a drawback.
Electronic Devices
91
When we use negative feedback on emitter resistor the operation point can be set quite
precisely – in fact it does not depend here on β. The scheme and the derivation of the
operation point is on the Fig. 5.12.
+ VCC
I
If β is great base current IB is small
and currents through resistors RB1, RB2
are approximately equal ⇒
RB 2
VRB 2 = VCC
RB1 + RB 2
RC
RB1
IC
VBC
IB
I - IB ≈ I
RB2
constant voltage in the emitter-base loop
independent on the transistor
VCE
assumption: active normal mode: VBE ≈ 0 . 7 V
V
− VBE
VRB 2 = VBE + R E IE ⇒ IE = RB 2
RE
I
IB = E , IC = IE − IB
β +1
VCC = RC IC + VCE + R E IE ⇒ VCE = VCC − RC IC − R E IE
VBE
IE
VRB2
RE
Fig. 5.12: BJT operating point: Voltage divider (RB1,RB2)
Now, when we learnt how set bias for the transistor operation point the problem is, that
connecting the AC input signal source directly in parallel with base-emitter circuit the AC
source will tend to change the operation point setting. Many times the AC source will act as
short-circuit for the base-emitter junction. Therefore, between the AC voltage source and the
voltage divider in the base-emitter circuit a coupling capacitor must be inserted. This coupling
capacitor acts here as a high-pass filter. For the same reason the capacitor is given between
collector and the load. The scheme of BJT amplifier with coupling capacitors is on the Fig.
5.13.
IC + ic
Bipolar transistor
as an amplifier
(CE configuration)
IB + iB
IC
IB
+ VCC
0
input
signal
RC
RB
IC + ic
iout
0
iout
iin
iin
0
IB + iB
VC+ vout
vin
CV
output
signal
vout
CV
0
vin
iE
VB + vin
IE
RE
VB
0
CE
VC
0
vout
RL
VB + vin
VC + vout
0
Fig. 5.13: Bipolar transistor as an amplifier (CE configuration).
Note:
0
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FEKT Vysokého učení technického v Brně
1. We have found that to reproduce entire input waveform faithfully DC bias voltage (or
current) must be used. The operation point is usually set at the level necessary to drive the
transistor between cut-off and saturation. This way, the AC input signal will be "centered"
between amplifier's high and low signal limit levels. This mode is called Class A operation
2. In Class B operation the transistor spends half its time in active mode and the other
half in cutoff mode. By itself, an amplifier operating in class B mode is not very useful. Class
B operation is dedicated for two amplifiers which operate in a pair, each amplifier handling
only half of the waveform. A special complementary NPN/PNP pairs are made for this
purpose.
3. Advantage of the class B amplifier over the class A design is greater output power
capability. With a class A design, the transistor dissipates a lot of energy because it never
stops conducting the bias current. Moreover this energy is dissipated also in the case that no
signal is processed. In a class B design, each transistor spends half the time in cutoff mode,
where it dissipates zero power. This gives each transistor a time to "rest" and cool while the
other transistor suplies the current to the load. Disipated power is thus proportional to output
power. Class A amplifiers are simpler in design, but tend to be limited to low-power signal
applications.
4. High-pass filter capacitor to couple the signal source to the amplifier means that the
amplifier can only amplify AC signals. A steady, DC voltage applied to the input would be
blocked by the coupling capacitor just as much as the voltage divider bias voltage is blocked
from the input source. Furthermore, since capacitive reactance is frequency-dependent, lowerfrequency AC signals will not be amplified as much as higher-frequency signals.
Example 5.1:
The figure shows an amplifier with bipolar transistor in common emitter configuration,
dc current and voltages are denoted by capital letters, small signal ac components by
small letters, respectively. Find: a) the operating point of the transistor, b) the input and
output resistance of the transistor c) the input resistance of the amplifier, d) the output
resistance, e) the voltage gain, f) the current gain. The transistor parameters are: the
current gain βdc ≈ βac = 200, the Early voltage UA = 55 V. The impedance of the
coupling capacitors can be neglected, RB = 500 kΩ, RC = 1 kΩ, UCC = 15 V.
Note: β dc =
IC
i
∆I
, β ac = C = C
IB
∆I B i B
It is necessary to strictly distinguish the symbols written by capital letters (dc
quantities) and by small letters (ac quantities).
Electronic Devices
93
Solution:
a) The operating point of the transistor:
The dc part of the circuit is drawn in the figure.
U BE ≈ 0.7 V … as the forward active mode as assumed for
the
amplifier
U CC = R B I B + U BE ⇒ I B =
U CC − U BE (15 − 0.7) V
=
= 28.6 µA
500 kΩ
RB
I C = β dc I B = 200 × 28.6 µA = 5.72 mA
I E = I C + I B = ( β dc + 1) I B = 5.75 mA
U CC = RC I C + U CE ⇒ U CE = U CC − RC I C = 15 V − 1 kΩ × 5.72 mA = 9.28 V
b) The input and output resistance of the transistor:
The input resistance of the transistor in the common emitter configuration (also called
the dynamic base resistance) is defined as follows:
 ∆U BE
rB = lim 
∆I B →0 ∆I B
rB =

 ∂U BE
u

= BE = 
iB
U CE =const.
 ∂I B

U

= T
U CE = sonst. I B
UT
25.9 V
=
= 905 Ω
I B 0.0286 mA
The output resistance of the transistor in the common emitter configuration can be
calculated in the following way:
 ∆U CE
rCE = lim 
∆I C →0 ∆I C
rCE =

 ∂U CE
u

= CE = 

iC
 I B =const.
 ∂I C
U CE + U A (9.28 + 55) V
=
= 11.2 kΩ
IC
5.72 mA

U +U A

= CE

IC
 I B =const.
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FEKT Vysokého učení technického v Brně
c) The input resistance of the amplifier:
The amplifier is redrawn in the
figure with only the small signal ac
currents and voltages. The input resistance
of the amplifier is defined in the following
way:
u 
Rin =  1 
 i1  output
open
The voltage supply UCC is
considered as ideal, thus its internal
resistance is zero and for a it can be
replaced by a short circuit for the ac
signal. This implies that the input voltage u1 falls also on the resistor RB. According to the
Kirchhoff’s law we can write the following equation for currents in the node B:
i1 = iB +
1
u1 u BE u1
1 

=
+
= u1 +
RB
rB
RB
 rB RB 
We have used the definition of the input resistance of the transistor (i.e. of the base
dynamic resistance) rB = u BE iB during the calculation. The input resistance of the amplifier
is:
Rin =
u1  1
1 

=  +
i1  rB R B 
−1
=
rB R B
U
25.9 V
= rB // R B ≈ rB = T =
= 905 Ω
rB + R B
I B 0.0286 mA
The resistance RB = 500 kΩ, the input resistance of the transistor was found to be
rB = 905 Ω ,
thus Rin = rB // R B ≈ rB = 905 Ω .
d) The output resistance of the amplifier:
The output resistance of the amplifier is
defined in the following way:
 u′ 
Rout =  2 
 i2′  input
short
The voltage u 2′ and the current i2′ are
small signal ac quantities applied to the output
terminal of the amplifier whereas the input
terminal is short circuited. The electronic circuit
for the calculation of the output resistance is
drawn in the figure.
As the dc voltage supply can be replaced
by a short circuit for an ac signal, the voltage u 2′
falls also on the resistor RC . According to the Kirchhoff’s law we can write the following
equation for currents in the node C:
Electronic Devices
i2′ = iC +
95
 1
u′2
u′
u′
1
= 2 + 2 = u′2 
+
RC rCE RC
 rCE RC




We have used the definition of the output resistance of the transistor rCE = uCE iC
during the calculation. The output resistance of the amplifier is:
Rout =
Rout
u 2′  1
1
= 
+
′
i2  rCE RC



−1
=
rCE RC
= rCE // RC
rCE + RC
As RC = 1 kΩ and rCE = 11.2 kΩ , the output resistance of the amplifier is
= rCE // RC ≈ RC = 1 kΩ .
e) The
amplifier:
voltage
gain
of
the
The voltage gain of the amplifier is
defined as the ratio of the output and
input voltages
Au =
u2
u1
The following relations are valid
for the bipolar transistor:
iC = β aciB +
1
rCE
uCE , i B =
u BE
rB
Observe that if the output resistance of the transistor rCE is considered, a more general
relation above replaces the usual relation iC = β ac i B . We can see in the figure that
iC = −
u2
, u BE = u1 , u CE = u 2
RC
We substitute for iC , iB, uBE, uCE into the first equation
−
u2
u
u
= β ac 1 + 2
RC
rB rCE
and calculate the voltage gain:
 1
1 
u
 = β ac 1
− u2 
+

rB
 RC rCE 
Au =
R // r
R
u2
= β ac C CE ≈ − β ac C = −220
u1
rB
rB
The sign – is meaningful: it denotes the opposite phase of the output voltage with
respect to the input voltage.
The base dynamic resistance is rB = U T I B , the emitter dynamic resistance
rE = U T I E . The emitter dc current is related to the base dc current by
I E = ( β dc + 1) I B ≈ β dc I B . The consequence of this relation between currents is the relation
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FEKT Vysokého učení technického v Brně
between the dynamic resistances: rE = rB β dc . As β dc ≈ β ac = β (the difference is less than
5%), the voltage gain of the amplifier can be written as
Au =
R
R
u2
≈ −β C = − C .
u1
rB
rE
f) The current gain of the amplifier:
The voltage gain of the amplifier is defined as the ratio of the output and input currents
Ai =
i2
i1
As the amplifier is unloaded, the output current is i2 = iC = −
u2
.
RC
By means of the relations derived above we can write for the input current
i1 =
u1
u1
u
=
≈ 1.
Rin rB // R B rB
The current gain is:
u2
RC
R r
i
u r
r
= − 2 B = − Au B = β ac C B = β ac = 200
Ai = 2 =
u1
i1
u1 RC
RC
rB RC
rB
−
Observe that a useful relation between the current gain and voltage gain was derived
during the calculation.
5.6.2
Voltage gain of the BJT amplifier
The voltage gain of a common-emitter transistor amplifier is approximately given here:
AU =
∆U 2 ∆I C RC ∆I B β ⋅ RC β ⋅ RC RC
=
=
=
=
∆U 1
∆I B rB
∆I B rB
rB
rE
( 5.5 )
Where RC is the resistor connected in collector, rB = UT/IB is dynamic resistance of
based and rE = UT/IE is dynamic resistance of emitter
Similarly the voltage gain of a common-base transistor amplifier is:
AU =
∆U 2 ∆I C RC RC
=
=
∆U 1
∆I E rE
rE
( 5.6 )
Where RC is the resistor connected in emitter and rE is dynamic resistance of emitter
And finally for the common collector configuration:
AU =
∆U 2
∆I E RE
∆I B β ⋅ RE
RE
=
=
=
∆U 1 ∆I E RE + ∆I B rB ∆I B β ⋅ RE + ∆I B β ⋅ rE (RE + rE )
( 5.7 )
Where RE is the resistor connected in emitter and rE is dynamic resistance of emitter.
Note:
Electronic Devices
97
In order to maintain linear (no-distortion) operation of transistor amplifiers both
saturation or cut-off modes should be avoided. The actual collector-emitter voltage in respect
to current and voltage on the load resistor can be visualized by means of the load line. This is
demonstrated on the Fig. 5.15.
Fig. 5.14: Determination of emitter-collector voltage by means of load line. (a) Amplifier (b)
Switch.
At the lower-right corner of the load line the collector current is at zero, representing a
condition of cut-off, and emitter-collector voltage is at maximum. At the upper-left corner of
the line collector current is at a maximum, representing a condition of saturation, and emittercollector voltage is close to zero.
In case of amplifier the transistor operates somewhere in the in middle of the load line
(Fig. 5.15a). In case of the switch there are two operation points namely saturation (in left
part of the load line) and cut-off mode (in right part of the load line).
5.6.3
Power gain of BJT amplifiers
To estimate the power gain we must consider both current and voltage gain and,
naturally, also the input and output impedances. For low frequency domain we can use
resistance instead of impedance.
Configuration CE.
Input resistance for AC voltage:
RINP ≈ RB // rB ≈ rB ≈ UT / IB
For typical value of IB rB is:
rB ≈ UT / IB ≈ (25 mV/20 µA) ≈ 103 Ω
Output resistance for AC voltage:
ROUT ≈ (RC // rC) !!!
Here rC ≈ 104 Ω and RC ≈103 ÷104 Ω
To evaluate real voltage gain we must now include both input and output resistances:
AV ≈ ∆IC . (RC // rC) / ∆IB (RB // rB)
In case that RC << rC and RB >> rB we can write:
AV ≈ ∆IC . (RC // rC) / ∆IB (RB // rB) ≈ ∆IC . RC / ∆IB rB ≈ β RC / rB
Typically we obtain:
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FEKT Vysokého učení technického v Brně
AV ≈ β RC / rB = RC / rE ≈ 102
For current gain similarly:
AI ≈ β ≈ 102
Power gain is then:
AP ≈ AU . AI ≈ 102 . 102 ≈ 104
Configuration CB.
Input resistance for AC voltage:
RINP ≈ RE // rE ≈ rE
For typical value of IE the result is
rE ≈ UT / IE ≈ (25 mV/1 mA) ≈ 25 Ω
Output resistance for AC voltage:
ROUT ≈ (RC // rC) ......
It is practically the same as in case of CE configuration.
Similarly the voltage gain is
AV ≈ ∆IC . (RC // rC) / ∆IE .rE ≈ RC/rE ≈ 102
Current gain is lesser than one:
AI < 1 ≈ α
And finally the power gain is:
AP ≈ AU ≈ 102
Power gain is much lesser than in case of CE configuration, because of low current
gain.
Configuration CC.
Input resistance RI of single transistor for AC voltage:
RI =
∆u INP RE ∆I E R E (β + 1)∆I B
≅
=
= R E (β + 1) ≅ R E β
∆I B
∆I B
∆I B
For input resistance of CC amplifier we must consider RI in parallel with RB
RINP ≈ RB // β RE (!!)
Typically RB ≈ 104 Ω and β RE ≥ 102 . 102 Ω ≈ 104 Ω
Output resistance for AC voltage is very low. Typically:
ROUT ≈ (RE // rE) ≈ rE ≈ UT / IE ≈ (25 mV/2 mA) ≈ 10 Ω
In Chapter 5.6.2 we computed the voltage gain as:
AV =
RE
( RE + rE )
Electronic Devices
99
It means that AV < 1. Current gain is given:
AI ≈ β ≈ 102
Power gain magnitude is comparable with CB configuration:
AP ≈ AU . AI ≈ 102
It is again much lesser than for CE configuration, this time because of low voltage gain.
5.6.4
Control questions and examples for Chapter 5.6
Example 5.2a:
Find the operating point of the bipolar transistor.
U CC = 15 V, RB = 560 kΩ, RC = 2,2 kΩ, R E = 0,8 kΩ, β = 120
Example 5.3b:
Find the operating point of the bipolar transistor.
U CC = 15 V, R B1 = 22 kΩ, R B 2 = 5,6 kΩ, RC = 3,3 kΩ, R E = 1 kΩ, β = 220
Example 5.4c:
Find the operating point of the bipolar transistor.
U EE = 3.5 V, U CC = 10 V, R E = 1.2 kΩ, RC = 2.4 kΩ, R B = 0.56 kΩ, β = 60
Solution in Chapter 8.2.1
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FEKT Vysokého učení technického v Brně
5.7 Operation of BJT as constant current source
We know that when a transistor operates in active mode, collector current is equal to
base current multiplied by the ratio β (see Fig. 5.16a). This is in fact most simple constant
current source, but there is a drawback of strong dependence on temperature and on Early
effect. Moreover β can be different more than 30% between two transistors of the same type.
Fig. 5.15: BJT as constant current source. (a) (b) With negative feedback on RE
In circuit on the Fig. 5.16 the emitter current is given by voltage drop on the emitter
resistance RE. Because the voltage drop on the base-emitter junction does not much differ
when changing β or collector voltage or temperature or even by changing the transistor the
emitter voltage is in fact given by base voltage.
Despite very good performance the circuit on the Fig. 5.16b has a drawback of large
voltage drop on the emitter resistance. To attain low voltage capability in integrated circuits a
current source labeled as current mirror is used routinely. Principal scheme is on the Fig. 5.17.
Operation of this circuit is based on an idea that identical transistors with identical parameters
will have also the same value of β. The actual value of β is not important.
Fig. 5.16: BJT as constant current source: Current mirror.
1. The current IR is given by voltage drop on resistor R:
IR = (UR – UBE) / R
Electronic Devices
101
2. In order to over take the current IR transistor T1 must have some base current, IB1.
Because transistors are identical and UBE1 – UBE2 the same current will flow into the base T2.
So IB1 = IB2 and consequently:
IR = IC1 + 2 IB ; where IB1 = IB2 = IB
3. Because transistors are identical and β1 = β2 the collector current IC2 must have the
same magnitude as IC1.
4. Output current IC2 is thus given:
IC2 = IC1.= IR - 2 IB = [(UR – UBE) / R]- 2 IB.
According the Shockley equation two PN junctions will behave identically when they
will have the same dimensions, technology, and temperature. Because the transistors are
identical to satisfy this conditions we only need to maintain both transistors at exactly same
temperature. In integrated circuit the transistors are located very close to one another on a
single chip of silicon which facilitates heat transfer between them. Using discrete components
very good thermal contact must be ensured.
Note:
1. Despite that the BC junction of T1 in current mirror circuit is shorted there is still
built in voltage and the depletion zone in the BC junction which ensure the extraction of
minority carriers from base. Therefore, β1 is not much different from its value in forward
active operation.
2. In case of high collector voltage of T2 Early effect can take place and IC2 will be
larger than IC1.
5.8 BJT as electronic switch
Transistors switches are used in variety of electronic circuits and form the basis of all
modern computers. Transistor switches offer lower cost and substantial reliability over
conventional mechanical relays. Nevertheless unlike the mechanical relays transistor switch
can be destroyed easily.
Maximal design parameters must not be exceeded: the allowable current, power loss
and breakdown voltage. A short circuit on the output must be avoided otherwise it will result
in overheat and destroying of the transistor. Principle of BJT switch operation is demonstrated
on the Fig. 5.18
.
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FEKT Vysokého učení technického v Brně
Principle
+ VS
load RL
I
ON
VS/RL
Ideal switch:
ON-state: zero voltage drop on switch
OFF-state: zero current through switch
VL
IL
OFF
VS
IC
Electronic circuit
+ VS = VL + VCES
load RL
IB
U
VS/RL
ON
VL = RL IC
IB
IL ≡ IC = β IB
VCES
OFF
current and voltage in ON state
IB = 0
VCES
≤1V
load line
VS = RL IC + VCE
VS
VCE
Fig. 5.17: Bipolar transistor as a switch (resistive load)
Virtually any general purpose NPN or PNP transistor can be used as a switch. All that is
needed is to know the current gain β, so that we can compute the base current to achieve
saturation. Some times also allowable power dissipation of the transistor is important.
For example all transistors in a TO-92 case will have β in range 150 - 300, fast
switching transistors of the same size and similar parameters have β in range 20-50 because
here recombination centers are used to eliminate excess carriers accumulated in the base.
Many power transistors (usually in TO-220 cases) may have β no greater than 25.
Therefore, if a power transistor is used to turn on a high current load, it may be necessary to
use another lower current transistor switch to drive a transistor switch used in a high current
application.
5.8.1
Darlington transistor
Instead to use two transistors in the switch configuration for large current an integrated
pair of transistors can be used. Darlington transistors (named after the inventor, Sidney
Darlington) contain two transistors connected in an emitter-follower configuration and
sharing the same collector contact. This gives very high current gain β and takes up less space
than using two discrete transistors in the same configuration.
Principle scheme of Darlington transistor is on the Fig. 5.19.
Electronic Devices
103
Fig. 5.18: Principle scheme of Darlington transistor
A Darlington pair behaves like a single transistor with a very high current gain. Total
current gain is the product of the gains of the individual transistors (see Fig. 5.19):
β = (β 1 + β 2 + β 1 β 2 )
Darlington pairs are available as complete packages but can also be made up from two
transistors; one a low power type other a high power type. The maximum collector current
ICmax for the pair is the same as ICmax of high power transistor. Integrated devices have three
leads (B, C, E) which are equivalent to the leads of a standard individual transistor. A typical
integrated device has a current gain of 1000 or more.
Despite high current gain there are some drawbacks:
1. The base-emitter voltage of Darlington pair is higher because both base-emitter
junctions are connected in series. Therefore, to turn the Darlington transistor on the voltage
higher the 1,2 V is needed.
2. When a Darlington pair is fully conducting, there is a residual saturation voltage
about 0.6 V in case of very low collector current and more than one volt in case of high load.
This can lead to substantial power dissipation.
3. Due to the inability of the first transistor actively inhibit the current into the base of
the second device the switch of process is slow. Switch off process can be accelerated by a
resistor of a few hundred ohms between the second device's base and emitter.
5.8.2
Design rules for BHT switch
As mentioned before electronic switches operate only in cut off and saturation modes.
Despite that the transistor switch is very simple device there are some design rules that always
must be considered:
1. To ensure work in saturation mode we need to know the maximum load current in
turn on state and minimum β of the transistor. It is advisable to calculate about 30% more
current to guarantee that the transistor switch is always saturated.
2. To obtain low saturation voltage bipolar transistors can be operated in reverse
(inverted) mode. In this case collector serves as emitter and vice versa. It means that basecollector voltage or current can control the emitter-collector current. The current gain in this
mode is usually much lesser than in forward-active mode (for example, 2 instead of 100)
because bipolar transistors are designed with relative doping concentrations that maximize
gain in forward active mode.
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3. In order to operate in the cut-off mode in base–emitter junction there must be no bias
or better BE junction must be biased reversely. To insure the zero potential on the baseemitter junction after the control current switch-off a resistor connected across the BE
junction is used.
4. When the transistor switch is turned on about 0,3 volts is lost between collector and
emitter. The voltage drop is given by the saturation voltage of transistor and can be up to one
volt in case of very large collector current. Anyway we must insure that the maximum power
dissipation of the transistor is not exceeded. We can calculate the static power dissipation by
multiplying the collector current by saturation voltage.
5. Dynamic losses are given by the switch on and switch off process. Before the
transistor is getting completely to saturation or to off state mode there is a short time when
simultaneously the emitter-collector voltage and collector current values are far from zero.
Effectively in this time the transistor is in normal active mode and instantaneous power loss is
very high. The dynamic loss is proportional to switching frequency. Therefore, in high power
applications the optimal frequency usually does not exceed 30 kHz.
6. The worst case load is when BJT switch works with an inductive load. When the
current stops to flow through the inductive load there is a large voltage spike which depends
on the magnitude of inductance and on switch-off speed. The voltage spike is proportional to
inductance L and the rate of current change:
∆U L = L
∆I L
∆t
By inductance 1 mH and typical current change about 1A/µs the voltage spike will be:
∆U L ≈ 1mH
1A
≈ 103V
1µs
a) In case that a relay coil is switching to prevent the transistor from destroying it is
good practice to use a diode reverse biased in parallel with the relay coil.
b) In power converters such solution is not possible and moreover the voltage spikes
can be also generated as effect of leakage inductance. Switching transistor must be therefore
made to withstand the avalanche breakdown of CB junction. However in most cases this is
not sufficient and therefore a special circuits (RC or RLC) are used to overtake the inductive
current during the switch-off process.
7. To ensure low voltage in turn on state of the BJT switch saturation mode is used.
However this brings a problem of delayed switch-off which is caused by charge of excess
non-equilibrium carriers in CB junction which is in case of saturation forward biased. This
situation is similar to reverse recovery process in case of PN junction diode. There are two
solutions:
a) Ensure high recombination in the base. This is done, similarly to PN junction diode
by impurities with acts as recombination centers. Nevertheless, when the carriers are catch by
recombination in the base they cannot be extracted by BC junction. Therefore by fast
switching transistors the current gain is typically very low (between 20-50).
b) Ensure that BJT will not pass to saturation mode. This is done by Schottky diode
connected across the BC junction. Principle of BJT switch operation with desaturation diode
is demonstrated on the Fig. 5.20. As soon as the collector voltage drops below the base
voltage the Schottky diode over takes redundant base current. Because the forward drop is
Electronic Devices
105
very low by Schottky diode collector voltage is not much lower then base voltage and deep
saturation is thus avoided.
Fig. 5.19: BJT switch with Schottky desaturation diode.
5.9 Voltage breakdown of BJT structure
Voltage breakdown typically occurs in reverse polarized base-collector junction. The
breakdown mechanisms of BJTs are similar to that of PN diodes. In case of BJT the collector
doping is low to ensure a large breakdown voltage (and to suppress the Early effect).
Consequently the breakdown is dominated by avalanche multiplication.
In case of avalanche breakdown mechanism the large electric field in the base-collector
depletion region causes carrier multiplication due to impact ionization. This breakdown is not
destructive. However, the high voltage and rapidly increasing current cause large heat
dissipation in the device, which can result in second (thermal) breakdown.
The breakdown voltage of a BJT depends on the chosen circuit configuration:
1. In a common base mode the breakdown is given by the BC junction reverse
breakdown voltage (it resembles that of a PN diode).
2. In a common emitter configuration the avalanche breakdown of the base-collector
junction is further influenced by the current gain mechanism:
1. Carriers which are generated by impact ionization in BC junction are pulled back into
the base region.
2. Due to the current gain of the BJT this additional base current causes additional flow
of carriers from the emitter. These carriers pass through the base into the collector.
3. Larger flow in the base-collector junction causes an even larger generation of
electron-hole pairs. Then the base current increases again … etc.
(In fact the reason for increasing the emitter current is increasing of base-emitter
voltage. This voltage acts against the built in voltage in depletion layer of EB junction and as
a consequence the height of energetic barrier which blocks the diffusion of majority carriers
on EB junction diminish.)
To increase the breakdown voltage in CE configuration the leakage (avalanche) current
must be lead out of the base. There are three possibilities to do it - as demonstrated on the
Figure bb1. Corresponding V-I curves are visualized on the Figure bb2:
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a) Open base circuit is the worst case. The steady state current flowing through the base
is the leakage current, ICB0 , which is in principle reverse current of the CB junction. Due to
the current gain of the BJT the collector current is then ICE0 = β ICB0. On the Figure bb2 we
see that the breakdown voltage, U(BR)CE0, is much lower than the breakdown voltage of CB
junction (U(BR)CB0 ) with open emitter.
b) Simple and mostly used way to suppress the influence of the leakage current is by
connecting a resistor RBE with value lesser than about 100 Ω in parallel with the base. In this
case large part of ICB0 is led out of the base, the steady state current ICER is much lesser than
ICE0 and the breakdown voltage (U(BR)CER ) is much higher than (U(BR)CE0 ). Dependence of
breakdown voltage on the RBE value is visualized on inset in Figure bb1. When the RBE value
is more than 100 Ω about the breakdown voltage diminish drastically.
Fig. 5.20: Different circuits to increase the breakdown voltage of BJT.
b) When the base-emitter junction is shorted the influence of leakage current is very
low. Corresponding collector current is ICES . Breakdown increases to U(BR)CES. This is the
case of transistor switch where a transformer is used to feed the base current
d) In case of NPN transistor to completely cancel the influence of the leakage current
the base is connected to the negative potential. This help to suppress the diffusion of
electrons from the emitter, collector current diminish and breakdown voltage is higher (see
ICEU. and U(BR)CEU in Fig. 5.20).
Fig. 5.21: Different circuits to increase the breakdown voltage of BJT
Electronic Devices
107
Note:
In case of early transistors and special microwave transistrors the base width
modulation as consequence of Early effect can also result in an rapid increase of the collector
current with increased collector-emitter voltage. However, in case of punchthrough
breakdown (where the base completely vanish) the increase of current is not so abrupt as in
the case of avalanche breakdown.
Safe Operation Area (SOA)
To ensure safe operation of the transistor all the operation points should be within the
finite boudaries on the IC versus VCE plane not only in steady state but also during transitions
between operating points, which may occur during switching or for other reasons. This is
called Safe Operation Area (SOA). The boundaries of SOA are usually specified by the
manufacturer of the device for stated conditions of working. Fig 5.22 shows a typical safe
operating area.
IC
breakdown
VCB = 0
ICmax
maximum
collector
current
safe
operating
area
hyperbola of
maximum power
losses
PCmax= ICVCE
IB = 0
VCEmax maximum
collector-emitter
voltage
VCE
Fig. 5.22: Safe Operating Area in output CE characteristics
Note:
In case of PNP type reversing of the BE junction does not result in significant increase
of the breakdown voltage.
5.10 Control questions for Bipolar Junction Transistor
1.
What rules of the design and manufacturing of the bipolar transistor structure
should be kept to ensure the correct transistor operation?
2.
Two bipolar transistors are fully identical, only their base widths are different:
the base width of the T1 transistor is twice higher. What electrical parameters
of the transistors will be different? Explain.
3.
a) What means the second breakdown of the bipolar transistor? b) How can be
the second breakdown resistance increased?
4.
a) Draw an example of the following circuits: the amplifier with a bipolar
transistor, the switch with a bipolar transistor (both in common emitter
configuration). b) Explain the differences in the position of the operation point.
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5.
Explain how and why switching bipolar transistors differ from common use
bipolar transistors with similar parameters (as the breakdown voltage, the
maximum collector loss).
6.
a) Explain the Early effect. b) Define the Early voltage.
7.
What are the applications of the bipolar transistor in the reverse active mode?
Explain.
8.
Why the breakdown voltage of the closed bipolar transistor in common emitter
configuration depends on the particular electronic circuit? Explain.
9.
Enumerate at least three methods how to increase the speed of the turn-off
process of the bipolar transistor switch. Explain.
10.
a) Draw an example of the following circuits: the amplifier with a bipolar
transistor, the switch with a bipolar transistor (both in common emitter
configuration). b) Explain the differences in the position of the operation point.
11.
Characterize and explain main properties of the bipolar junction transistor in
inverse active mode.
12.
Two bipolar transistors are fully identical, only the impurity concentration in
collector is different; it is higher at transistor T1. What electrical parameters of
the transistors will be different? Explain.
13.
How the breakdown voltage of the closed bipolar transistor in common emitter
configuration can be increased?.
14.
Explain the relation between the Early voltage and the output resistance of the
transistor.
6 Field-Effect Transistors
In this chapter the operation of both unipolar transistor types, JFET and IGFET, is
explained. The depletion and enhanced IGFET types are discussed. Computation of transistor
circuits is explained using both graphic and numerical methods.
Field-Effect Transistors (FET) are labeled as unipolar devices because the controlled
current here does not have to cross a PN junction. There is a PN junction inside the transistor
only to provide non-conducting depletion region which is used to restrict the current through
the channel. In principle there are two types which differ in way by which the depletion zone
is controlled.
Junction Field-Effect Transistor (J-FET). Here the control voltage is applied across a
reverse-biased PN junction to control the width of depletion region. This way the cross
section of a conductive channel in semiconductor bulk is influenced.
Insulated Gate Field-Effect Transistor (IGFET). Depletion region is here controlled
by means of charge in Channel-Gate capacitance which is proportional to applied voltage.
Electronic Devices
109
Because the Gate is insulated there is no direct connection between the gate lead and the
semiconductor material itself.
6.1 Junction Field Effect Transistor (J-FET)
The structure of JFET is on the Fig. 6.1. A pair of metallic contacts labeled Source and
Drain are placed at each end of the channel which is made in semiconductor bulk. In an nchannel device, the channel is made of N-type semiconductor, so the charges free to move
along the channel are electrons. In this case the gate is made from P-type area. In an p-channel
device the charge is transported by holes and gate lead is connected to the N-type area. In
both cases between the conductive channel and Gate there is a PN junction. In operation of
JFET this junction is reverse polarized.
depletion layer of
the p+n-junction
n-channel JFET
G … gate
+D
p+
ID
n
channel between source
and drain
S…
source
n
D…
drain
p+
G-
VGS < 0
S
G … gate
depletion layer of
the n+p-junction
p-channel JFET
G … gate
-D
n+
S…
source
ID
channel between source
and drain
p
p
n+
D…
drain
VSD
G+
VGS > 0
G … gate
Fig. 6.1:
VDS
ID
ID
S
The Junction Field-Effect transistor (JFET)
When applying a voltage between S and D a current flows along the channel from one
contact to the other. In principle the structure is symmetrical but usually J-FET transistors are
made the way that Source is close to Gate and the power source voltage is connected to the
drain. Evidently, source and drain have similar function as emitter and collector of bipolar
junction transistor respectively.
6.1.1
Output characteristics of JFET
To explain the operation of J-FET we will consider the N-channel device. Here, when
the negative potential is connected to the gate the PN junction is reverse polarized and the
width of depletion layer increases. Consequently the cross section of the channel diminish and
this way the channel resistance is changed. The effective resistance between S and D will
depend upon the size and shape of the channel and the properties of the N-type material. In
any case here are three typical areas:
1. When the collector potential is close to zero J-FET operates as variable resistor.
Resistance value is controlled by Gate-Source voltage. Because of low current gain this mode
is not suitable for amplification, nevertheless there are a plenty of application as controllable
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resistor. This mode is labeled as active and in output characteristics it is seen as straight lines
in close to zero voltage area. On Fig. 6.2 there is visualized how the depletion zone changes
when increasing the Gate-Source voltage (Mind that VGS is negative in case of N-type
device.)
G
p+
S
channel between
source and drain
n
D
n
JFET:
the gate action
VDS = 0
VGS = 0
depletion layer of
the p+n-junction
p+
G
G
p+
S
D
n
channel
n
VDS = 0
VP < VGS < 0
the depletion layer widens,
the channel becomes narrower
p+
G
VDS = 0
VGS = VP < 0
G
p+
S
n
n
D
VP = pinch-off voltage
the depletion layer occupies the entire
channel, the channel is completely
depleted of electrons and disappeares
the corresponding voltage VGS =VP
is called pinch-off voltage
(or threshold volatge)
p+
G
Fig. 6.2:
JFET: Channel shapes in active mode
2. When we apply a positive voltage to Drain, the potential is distributed along the
channel and from the drain site the gate potential in respect to the channel grows. This means
higher potential on the PN junction near the drain and wider depletion layer in this area. The
voltage current dependence stops to be linear and characteristic curve bends.
3. After the Drain voltage achieves certain level the depletion layer is wide enough to
choke the channel. From this voltage level the current does not grow regardless of the Drain
voltage value. This operation is labeled as Saturation. J-FET here operates as a constant
current source.
This situation is visualized on the Fig. 6.3 together with both output (red) and transfer
(blue) characteristics.
Electronic Devices
111
VGS
VDS
G
ID
VGS3
VDS = VDSsat
= VGS - VP
p+
S
VGS2
n channel
VGS1
D
p+
VDSsat
G
VGS
? at VDS = VDSsat = VGS – VP the pinch-off of the channel
at the drain end occurs
? VDS = VDSsat is the boundary between the active
(linear, ohmic) mode and the saturation mode
ID
VDS
VGS3
G
p+
VDS > VDSsat
VGS2
VGS1
n channel
S
D
p+
G
Fig. 6.3:
VDS
VDSsat
VDS
? the depletion layers overlap
? channel length modulation occurs:
the effective channel length is reduced
? the current saturates
JFET: Channel shapes in active mode
4. By negative voltage on contrary the channel is wider from the Drain site. When The
Drain voltage is sufficiently high the channel can be "open" completely and the current grows
rapidly. Characteristic curves resemble to these of vacuum triode. Therefore this operation
mode is called triode mode. In fact it is an operation of the closed switch which opens in
case that the voltage of the signal which was switched off exceeds some permissible level.
5. When the gate voltage is high enough to close the channel the transistor is in Cut-Off
regime regardless on the Drain-Source voltage.
6. Naturally there is a maximal allowable value of Drain-Source voltage. When
exceeded, the current grows very rapidly by non destructive avalanche breakdown (mind
that it can result in thermal breakdown).
Output characteristics of N-channel JFET are demonstrated on Fig. 6.4. On inset there
are marked out respective modes: A (active), B (saturation), C (triode) and D (cut-off).
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Fig. 6.4:
Output characteristics of N-channel JFET
Note:
In fact there is possibility to obtain greater drain currents by applying a very small
forward-bias voltage between gate and source of JFET. Nevertheless this mode is not
recommended for risk of damaging PN junction between gate and substrate.
6.1.2
The transfer characteristic
The transfer characteristic for the JTET is useful for visualizing the current gain of the
device and identifying the region of linearity. The gain is proportional to the slope of the
transfer curve. The current value IDSS represents the value of the maximum current for the
device (when the Gate is shorted to ground). This value is routinely supplied by the
manufacturer. The Gate voltage at which the current reaches zero is called the "pinch
voltage", VP. Construction of the transfer characteristic and the meaning of respective
parameters is on the Fig. 6.5.
transfer
characteristics
output characteristics
linear (ohmic,
active) mode
for saturation mode
ID
IDSS
saturation mode
ID
VGS = 0
IDSS
VP<VGS<0
VP
VGS
0
VDSsat = VGS - VP
VDS
VGS=VP<0
Important quantities:
? VP ……. the pinch-off voltage (threshold voltage)
? IDSS …… the saturation current at VGS = 0
? VDSsat … the boundary between the linear and the saturation modes
Electronic Devices
Fig. 6.5:
113
Output characteristics of N-channel JFET
Example 6.1:
a) Find the operating point of the JFET. UDD = 24 V, RD = 6.2 kΩ, RS = 1.5 kΩ, RG =
1.0 MΩ, the transistor parameters IDSS = 10 mA, UP = − 4 V.
b) Draw the operation point in output characteristics.
c) Discuss and draw how is the position of the operation point
changed if:
(i) the resistance RS is increased/decreased;
(ii) the resistance RD is increased/decreased;
(iii) the voltage supply UDD is increased/decreased.
Solution
a) The reverse biased depletion layer of the p+n junction is below the gate of the JFET
and it separates the gate electrode from the conductive n-channel of the transistor. As a result
no dc current flows through the gate (more exactly: only the negligibly small reverse current
of the reverse biased p+n junction flows). The equation of the closed loop [gate – source –
resistor RG – gate] is:
U GS + RS I D = 0
Another relation between the voltage UGS and the current IG is
 U
I D = I DSS 1 − GS
UP




2
This equation can be considered or as the equation of the transfer characteristics in the
saturation mode or as the equation of the output characteristics in the saturation mode.
We substitute for ID in the first equation and obtain the quadratic equation for the
voltage UGS:
U GS
 U
+ RS I DSS 1 − GS
UP

2

 = 0

We write this equation in the standard form with coefficients a, b, c at the quadratic,
linear and absolute terms, respectively:
RS I DSS
U P2

R I
2
U GS
+ 1 − 2 S DSS
UP


U GS + RS I DSS = 0

The coefficients of the quadratic equation are:
a=
R S I DSS
U P2
=
1.5 kΩ × 10 mA
16 V
2
= 0.9375 V -1
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b =1− 2
R S I DSS
1.5 kΩ × 10 mA
=1− 2×
= 8.5
−4V
UP
c = R S I DSS = 1.5 kΩ × 10 mA = 15 V
Note: It is necessary to substitute the threshold voltage UP with the correct sign; if not,
the result will be erroneous. Also the units of the quantities should correspond each other:
[mA, kΩ, V] or [A,Ω, V]; the first possibility was applied in our calculation.
The quadratic equation can be solved by means of the well-known formula:
U GS =
− b ± b 2 − 4ac
2a
U GS =
− 8.5 ± 8.5 2 − 4 × 0.9375 × 15
V , U GS = −2.4 V or U GS = −6.67 V
2 × 0.9375
It is clear that only one of the two roots of the quadratic equation corresponds to the
reality of the electronic circuit. It correct root can be identified with the aid of the transfer
characteristics of the JFET: the voltage UGS should satisfy the relation U P ≤ U GS ≤ 0 . This
means that the correct value of the gate voltage UGS is
U GS = −2.4 V
If the gate voltage is known, the current ID can be calculated or by means of the
characteristics equation or by means of the loop equation; of course, both methods should
give the same result:
 U
I D = I DSS 1 − GS
UP

ID = −
2
2

− 2,4 V 

 = 10 mA × 1 −
 = 1.6 mA
−4V 


U GS
− 2 .4 V
=−
= 1.6 mA
RS
1.5 kΩ
We note again that it is necessary to substitute the voltage with correct sign.
As the last step we write the equation of the closed loop [voltage supply UDD – resistor
RD – drain – source – resistor RS – ground] and calculate the voltage UDS:
U DD = R D I D + U DS + R S I D
U DS = U DD − ( R D + R S ) I D
U DS = 24 V − (6.2 + 1.5) kΩ × 1.6 mA = 11.7 V
b) The equation of the closed loop [gate – source – resistor RG – gate] is also the
equation of the load line in the plane of the transfer characteristics:
U GS + RS I D = 0
The equation of the closed loop [voltage supply UDD – resistor RD – drain – source –
resistor RS – ground] is also the equation of the load line in the plane of the output
characteristics:
U DD = R D I D + U DS + R S I D
Electronic Devices
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c) As we can see in the equations of the load lines, the variation of the resistance RS
affects both the load line in the transfer characteristics and the load line in the output
characteristics. The variation of the resistance RD and of the voltage supply UDD affects only
the position of the load line in the output characteristics and the gate voltage UGS(P) of the
operating point remains unchanged.
6.2 Insulated Gate Field Effect Transistor (IGFET)
Similarly to JFET devices Insulated Gate Field Effect Transistor (IGFET) operate on
principle of controlling the transistor conductivity by means of a depletion layer. In contrary
to JFET a change in channel width is due to depletion region displacement rather than
depletion region expansion.
There exist four basic types of IGFET: N-channel, P-channel and both of them with
depletion and enhancement mode (see further). Structures and types of IGFET/MOSFET
transistors is on the Fig. 6.6.
Fig. 6.6:
IGFET/MOSFET transistors, structures and types
Source and Drain areas are made in substrate with opposite type of conductivity. Gate is
a metal plate separated from the substrate by a thin insulating barrier. The simplest way how
to make the barrier is from silicon dioxide which is also a very good insulator. Due to this
Metal (gate) - Oxide (barrier) - Semiconductor (channel) construction, the IGFET is
sometimes referred to as a MOSFET. There are other types of IGFET devices where for
example other materials as nitride or oxy-nitride are used as insulators. Therefore, "IGFET" is
the better descriptor for this general class of transistors.
IGFET devices are widely used in large-scale digital integrated circuits, further in
switching power applications and in all purpose electronic circuits, where their high input
impedance is utilized especially.
Electronic Devices
6.2.1
117
Operation of IGFET
Principle of IGFET operation is that a conducting channel is made or altered when a
potential difference is applied between gate and substrate. The operation of IGFET is similar
to that of JFET. Main difference is here that IGFET exhibits larger resistive input impedance
due to the thin layer of silicon dioxide that is used to insulate the gate from the semiconductor
channel. The consequent lack of an internal DC connection to the gate makes the device more
versatile than the JFET, but it also means that the insulating material of the gate can be easily
damaged by the internal discharge of static charge developed during normal handling. On the
other hand the insulated gate allows to use a controlling voltages of any polarity without
danger of forward-biasing a junction, as was with JFETs.
To explain the operation of IGFET device we will use a structure with P-substrate and
N-type channel. Between Source and Drain there are two PN junctions. By any voltage
polarity between Drain and Source one of these PN junctions will be polarized reversely.
Consequently the only current which can pass there is a reverse current of one of these
junctions.
To make the transistor conductive, a conductive channel originate between Source and
Drain as a consequence of charge accumulation in the gate insulation:
1. Positive gate voltage brings to gate insulation a positive charge. When increasing the
gate voltage first majority holes are repelled and the gate charge is compensated by negative
ions of ionized P-dopants which stay firmly in the semiconductor lattice. This situation is
visualized on the Fig. 6.7. Mind that removing of holes in fact means the capture of electrons
in thin layer beneath the gate.
Fig. 6.7:
Enhanced -MOSFET with n-channel: Charge accumulation beneath the gate
2. By certain gate voltage the charge of ionized dopants is not sufficient to compensate
the gate charge. In this case (minority) electrons from substrate must be attracted. Because
there is very low density of holes beneath the gate, very low density of electrons is sufficient
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FEKT Vysokého učení technického v Brně
to change the type of conductivity from P-type to N-type. An inverse, N-type channel is thus
created. The voltage by which this process starts is called threshold voltage.
3. Further increasing of gate voltage causes accumulation of larger charge in the gate
insulation and attracts more electrons. Consequently the conductance of the inverse N-type
channel is higher. This operation mode is labeled as active mode. IGFET operates here as
variable resistor (see Fig. 6.8).
Fig. 6.8:
Enhanced -MOSFET with n-channel: The gate action
Electronic Devices
Fig. 6.9:
119
Enhanced -MOSFET with n-channel: Saturation mode
4. If a larger potential difference is applied between the source and drain terminals the
shape of the depletion region becomes asymmetrical because of different distribution of gate
potential versus channel. If the potential difference is large enough, the depletion region
begins to close the channel and the IGFET passes into the saturation mode. This situation is
in principle the same as by JFET although the mechanism of depletion layer control is
different. Also in this case any increase of the drain-to-source voltage will lengthen the
depletion region, increasing the channel resistance proportionally with the applied drain-tosource voltage. This causes the value of drain current to remain fixed. In saturation mode, the
FET behaves as a constant-current source rather than as a resistor and can be used as a voltage
amplifier. The value of gate voltage determines the value of the constant current in the
channel.
This situation is demonstrated on the Fig. 6.9
5. Negative gate voltage causes a depletion region to expand in size. If the depletion
region completely closes the channel, the resistance of the channel becomes very large, and
the FET is effectively turned off. ¨
6. When Drain voltage is negative the channel is opening from the Drain site. Similarly
as in the case of JFET there is the same opening of channel mechanism as the in case of JFET.
Also this mode is in principle the same as by the JFET type and is also called triode mode.
Note:
1. For N-channel IGFETs, the conductive channel is made from minority electrons in Ptype layer beneath the gate. Therefore to build up the channel the gate polarity must be
positive. For saturation mode positive Drain voltage is needed. By negative Drain-Source
voltage the N-channel IGFET passes into the triode mode.
2. For P-channel IGFETs, all is reversed. The conductive channel is made from
minority holes in N-type layer beneath the gate. To create the channel gate polarity must be
negative. Saturation mode is by negative Drain voltage while the triode mode come into being
by positive voltage between Drain and Source.
6.2.2
Enhancement and depletion mode
Depending on the device design there are two modes of IGFET operation. In
enhancement mode a voltage applied to the gate increases the current flow from source to
drain. In depletion mode a voltage applied decreases the current flow from source to drain.
Enhancement type:
Below some threshold of positive gate-source voltage, the conductive channel is
completely blocked by the depletion region generated by the PN junction. As the gate-source
voltage reach the value of threshold voltage minority carriers are attracted from substrate to
make an inverse high conductivity channel beneath the gate.
Depletion type:
Depletion type has the capability of having its channel either depleted or enhanced.
Input voltage polarity determines which way the channel will be influenced. When there is
zero voltage applied between gate and source, the IGFET will conduct current between source
and drain, but not as much current as it would if it were enhanced by the proper gate voltage.
Note:
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FEKT Vysokého učení technického v Brně
1. Bipolar junction transistors and Enhancement-type IGFET are “normally-off”
devices: With no base current or no gate voltage they block any current from going through.
2. Junction field-effect transistor is “normally-on” device: By zero gate-to-source
voltage they allow maximum drain current.
3. Depletion-type IGFET is “normally on” devices but with a special feature that in case
of no Gate-to-Source voltage, their conduction level is somewhere between cutoff and full
saturation. Moreover it will tolerate applied gate-source voltages of any polarity.
6.2.3
Characteristic curves for E-IGFET
Output characteristic and transfer characteristic and its relation are demonstrated on the
Fig. 6.10
Fig. 6.10: E-MOSFET with n-channel: Output and transfer characteristics
6.2.4
Characteristic curves for D-IGFET
Output characteristic and transfer characteristic and its relation are demonstrated on the
Fig. 6.11.
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121
Fig. 6.11: D-MOSFET with n-channel: Output and transfer characteristics
6.2.5
Available terminals by IGFET devices
All types of IGFET devices have in principle four terminals, which are known as the
gate, drain, source and body/base/bulk which is in fact the substrate of the device. To simplify
the design, the substrate lead is internally connected to the source lead, especially in large
IGFETs. However, in a plenty of applications one would connect the source to the body
anyway because a difference between the voltages of the source and body will change the
threshold voltage. This is known as the body effect and is used primarily in digital circuits
and in high precision analog circuits. This results in different schematic symbols as seen from
the Fig. 6.12.
Fig. 6.12: MOSFET with the bulk (substrate) electrode
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6.3 Control questions for Field-Effect Transistors
1.
a) Draw the structure of the JFET with n-channel. b) Briefly explain its
principle of operation. c) Draw the output characteristics of the JFET.
2.
Define the active mode of FET. What is the typical application of FET in the
active mode?
3.
Give at least two applications of the CCD structure. What is the principle of its
operation?
4.
Draw a typical electronic circuit for setting of the operation point: a) of the
JFET with n-channel, b) of the IG-FET with induced n-channel.
5.
Draw the structure of the IGBT transistor and its equivalent circuit
6.
What are the requirements on the gate controlling electronic circuits of IGBT
and of IG-FET?
7.
Draw the output characteristics of FET transistor for both possible polarities
of the UDS voltage and describe the corresponding modes of operation.
7 Bipolar switching devices
Aim of this chapter is to explain operation of bipolar switches with emphasis on
thyristor and triac devices. The turn on mechanisms of thyristor are dealt thoroughly. Power
control using thyristor and triac circuits is discussed and dynamic properties of different types
of thyristors are shorly dealt.
Operation of bipolar switching devices is similar to that of bipolar junction transistors.
The main difference is that there are more layers with different doping types and levels.
Mostly used bipolar switching device is thyristor which has four-layer structure and
operates as one way switch. Therefore, for AC applications is more convenient TRIAC which
has five-layer structure and can switch in both direction. Finally DIAC has the three layer
structure which is similar to BJT. Its V-I characteristic features an area of negative resistance.
Therefore it is used mainly for pulse generation. Symbols used for bipolar switching devices
are on the Fig. 7.1.
Fig. 7.1:
Bipolar switching devices. (a) Thyristor. (b) Triac. (c) Diac
Electronic Devices
123
7.1 Thyristor
Thyristor is a solid-state semiconductor device with four layers of alternating N and Ptype material. It acts as a switch, conducting when its gate receives a current pulse, and
continues to conduct for as long as it is forward biased.
An earlier gas filled tube device called a Thyratron provided a similar electronic
switching capability, where a small control voltage could switch a large current. It is from a
combination of "thyratron" and "transistor" that the term "thyristor" is derived. Some time
thyristors are also called silicon controlled rectifiers (SCR).
The structure of thyristor is drawn on the Fig. 7.2a). The main terminals are labeled
anode (A) and cathode (C). The control terminal, called the gate (G) is attached to p-type
material near to the cathode. The operation of a thyristor can be understood in terms of a pair
of tightly coupled bipolar junction transistors arranged to cause the self-latching action (see
Fig. 7.2b).
7.1.1
Operation of thyristor
The thyristor has three PN junctions, usually labeled J1, J2, J3 (starting from the anode).
Considering different conditions thyristors can have three operational states:
Reverse blocking mode:
VAK is applied in the direction that would reverse the
junctions J1 and J3. In this mode the thyristor operates as a diode.
Forward blocking mode: VAK is applied in the direction where the thyristor can
conduct, but it has not yet been triggered into conduction. From this state the thyristor can
switch to the Forward conducting mode.
Forward conducting mode After the thyristor has been triggered into conduction it
will remain conducting until the forward current drops below a threshold value known as the
holding current IH.
Fig. 7.2:
Thyristor. (a) The structure. (b) The substitute scheme
In forward blocking mode anode of the thyristor is at a positive potential VAK with
respect to the cathode with no voltage applied at the gate. Junctions J1 and J3 are forward
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biased, while junction J2 is reverse biased and no conduction takes place. From this off state
thyristor can be forced into the forward conducting mode. There are four possibilities:
1. VAK is increased beyond the breakdown voltage VACBR of the thyristor, avalanche
breakdown of J2 takes place and thyristor starts conducting. This represents the switch on in
case of voltage spikes and is undesirable.
2. The ambient temperature is increased. In this case the breakdown voltage VACBR of
the thyristor decreases and avalanche breakdown of J2 takes place by considerably lower
voltage. The situation is similar as in the case of the high voltage VAK and represents
undesirable event.
3. In PN junction J2 there is a barrier capacity. When the rise time of the VAK is to short
a current pulse can pass through this barrier capacity into the gate layer. In fact this pulse can
deliver the charge which is needed to force the thyristor into the forward conducting mode. Of
course also this case is undesirable.
4. If a positive current IG is applied at the gate terminal with respect to the cathode,
the breakdown of the junction J2 occurs at a lower value of VAK. By selecting an appropriate
value of IG, the thyristor can be switched into the on state immediately. This is normal
operation of a thyristor. It must be noted that IG need not be applied after the avalanche
breakdown has occurred. Hence IG can be only a voltage pulse.
Gate pulses are characterized in terms of gate trigger voltage (VGT) and gate trigger
current (IGT). Gate trigger current varies inversely with gate pulse width in such a way that it
is evident that there is a minimum gate charge required to trigger the thyristor. Typical
thyristor switching characteristic is demonstrated on the Fig. 7.3.
Fig. 7.3:
Thyristor. Switching characteristic.
7.1.2
Thyristor switching
A conventional thyristor, once it has been switched on by the gate terminal it remains
latched in the on-state, providing the anode current has exceeded the latching current (IL). As
long as the anode remains positively biased, it cannot be switched off until the anode current
falls below the holding current (IH).
Electronic Devices
125
A thyristor can be switched off if the external circuit causes the anode to become
negatively biased. In some applications this is done by switching a second thyristor to
discharge a capacitor into the cathode of the first thyristor. This method is called forced
commutation.
After a thyristor has been switched off by forced commutation, a finite time delay must
have elapsed before the anode can be positively biased in the off-state. This minimum delay is
called the circuit commutated turn off time (tQ). Attempting to positively bias the anode
within this time causes the thyristor to be self-triggered by the remaining charge carriers
(holes and electrons) that have not yet recombined.
For applications with frequencies higher than the AC mains supply special thyristors
with lower values of tQ are required. Such fast thyristors use charge recombination centers
(gold or platinum for example) similarly to fast diodes and switching transistors.
7.1.3
Applications
Thyristors are mainly used in high currents and voltages application. Especially they are
used to control alternating currents, where the change of polarity of the current causes the
device to automatically switch off. Very convenient application for thyristors is to use them as
the control elements for phase angle triggered controllers. Principle of this control is
demonstrated on the Fig. 7.4.
The functional drawback of a thyristor is that it conducts in one direction only. Here the
solution is to use two thyristors in back to back connection. Mind that in this case the circuits
for gate pulse control must be electrically separated. The potential difference can here up to
several kV in medium power circuits.
Other problem associated with thyristors is that there is not the posibility to switch them
off. Therefore many derivatives of thyristors were suggested between them the GTO (Gate
Turn-off Thyristor) devices. Here is the possibility to switch of action by means of large
negative current pulse into the gate.
Fig. 7.4:
Thyristor. Phase angle triggered control
In high-frequency applications, thyristors had been replaced by other devices with
superior switching characteristics like MOSFETs and IGBTs.
7.1.4
Triac
A TRIAC, or TRIode for Alternating Current is a five layers structure. It is
approximately equivalent to two thyristors joined in inverse parallel and with their gates
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connected together. This results in a bidirectional electronic switch which can conduct current
in either direction after when it is triggered (= turned on). It can be triggered by either a
positive or a negative voltage being applied to its gate electrode.
Similarly to the thyristor, once triggered, TRIAC continues to conduct until the current
through it drops below a certain threshold value. This makes the TRIAC a very convenient
switch for AC circuits, allowing the control of very large power flows. Of course, phase angle
triggered control can be used also in case of TRIAC allowing thus to control the percentage of
current that flows through the TRIAC to the load.
Low power TRIACs are used in many applications such as light dimmers, speed
controls for electric fans and other electric motors, and in the modern computerized control
circuits of many household small and major appliances.
Because the TRIAC can conduct in both directions, reactive loads can cause it to fail to
turn off during the zero-voltage instants of the ac power cycle. When used with inductive
loads such as electric fans for example, care must be taken to assure that the TRIAC will turn
off correctly at the end of each half-cycle of the ac power. Therefore a snubber circuit is often
used to assist this turn off. Snubber circuits are also used to prevent premature triggering. For
higher-powered, more-demanding loads, two thyristors in inverse parallel may be used instead
of one TRIAC. Because each Thyristor will have an entire half-cycle of reverse polarity
voltage applied to it, turn-off of the SCRs is assured, no matter what the character of the load
(mind the electrical separation of control circuits).
Note:
Snubber circuit is in principle RC or RLC circuit which is connected parallel to
switching device. In case switching off it over takes the inductive current.
7.1.5
Diac
The DIAC, or DIode for Alternating Current, is a bidirectional three layer structure
conducting only after its breakdown voltage has been exceeded. When this occurs, its
resistance abruptly decreases, leading to a sharp decrease in the voltage drop and a sharp
increase in current flow. DIAC remains in conduction until the current flow through it drops
below a value characteristic for the device, called the holding current. Below this value, the
DIAC switches back to its high-resistance (non-conducting) state. The structure and I-V
characteristic are visualized on Fig. 7.5.
Electronic Devices
Fig. 7.5:
127
Diac. (a) Structure. (b) V-I characteristic.
The behavior is typically the same for both directions of current flow. Most DIACs have
a breakdown voltage around 30 V.
DIACs are typically used for triggering of TRIAC devices. Because of this common
usage, many TRIACs contain a built-in DIAC in series with the TRIAC's gate terminal.
DIACs are also called symmetrical trigger diodes due to the symmetry of their
characteristic curve. Because DIACs are bidirectional devices, their terminals are not labeled
as anode or cathode but as A1 and A2 or MT1 ("Main Terminal") and MT2.
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8 Results and examples
8.1 Examples for Semiconductor diodes
8.1.1
Solution Chapter 4.2.1
Example 4.1a
The voltage UN = 24 V is sufficiently high, thus it could be assumed that all four diodes
are forward biased and open with voltage drop UD = 0.7 V on each.
The voltage drops on resistors R1 , R2 , R3 , R4 are UN – UD, UN – 2UD, UN – 3UD, UN –
4UD and the currents IR1, IR2, IR3, IR4 though resistors can be found by means of the Ohm´s
law. Then the currents through diodes are:
I 4 = I R4 =
U N − 4U D
= 21,2 mA
R4
I 3 = I R3 + I 4 =
U N − 3U D
+ I 4 = 21,9 mA + 21,2 mA = 43,1 mA
R3
I 2 = I R2 + I 3 =
U N − 2U D
+ I 3 = 22,6 mA + 43,1 mA = 65,7 mA
R2
I 1 = I R1 + I 2 =
U N −UD
+ I 2 = 23,3 mA + 65,7 mA = 89,0 mA
R1
Example 4.2b
We write the following equation using the Kirchhoff’s law:
U N = R1I + U D + R3 I D
U N = R1I + R2 ( I − I D )
Their solution is: I = 0.73 mA , I D = 0.35 mA .
Example 4.3c
As UN1 > UN2 and the resistance of all resistors is the same the diode is forward biased,
thus the voltage drop across the diode is U = U D = 0.7 V
The current through the diode we calculate by means of the Thevenin law.
For better understanding we draw at first the circuit as it is usual in circuit theory and as
the next step we draw the Thevenin equivalent circuit and calculate the Thevenin equivalent
voltage supplies and resistances:
Electronic Devices
129
U Th12 = U N 1
R2
= 7.5 V , RTh12 = R1 // R2 = 5 kΩ
R1 + R2
U Th 34 = U N 2
R4
= 5 V , RTh 34 = R3 // R4 = 5 kΩ
R3 + R 4
The current I through the diode we find by means of the Thevenin equivalent circuit:
I=
U Th12 − U D − U Th 34
= 0.18 mA
RTh12 + RTh 34
8.1.2
Solution Chapter 4.4.1
Example 4.4
In the figure above we can see the voltage regulator without load (left) and with the
resistance load R L (right). The Zener diode is normally operated in its reverse biased
breakdown region, where the voltage across the device remains substantially constant as the
reverse current varies over a large range of current from I D min to I D max . This ability to
maintain a constant voltage U 2 across the output terminals, independent of current, is what
makes the Zener diode useful as a voltage reference.
The Zener diode also provides a significant reduction in ripple voltage at the load. Let
U 1 be the mean value of the input voltage and ∆U 1 its ripple. The output voltage is be
U 2 ± ∆U 2 where the ripple ∆U 2 is negligibly small, thus U 2 = const. Consider the regulator
with open output terminals. It is valid the relation U 1 = U D + RI D , which is in fact the
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equation of the load line. The operating point P of the Zener diode lies at the intersection of
the diode characteristics and the load line. The output voltage is the voltage U 2 , which
corresponds to the point P. If the input voltage drops to U 1 − ∆U 1 the load line moves up and
the new operating point P’ lies at the intersection of the new load line with the characteristics
and the new output voltage is U 2 − ∆U 2 . As the dynamic resistance rd of the Zener diode is
very small, the ripple ∆U 2 is also very small.
Example 4.5
The input voltage U 1 varies between the maximum value U 1max and the minimum value
U 1 min because of the input ripple:
U1max = U1 + ∆U1 = 55 V , U1min = U1 − ∆U1 = 45 V
Similarly the input current I varies between the maximum and minimum values:
I max =
U1max − U Z
U
− UZ
= 240 mA , I min = 1min
= 190 mA
R
R
Consider at first the maximum load resistance R L max . If the resistance is maximal, the
current through the load should be at its minimum I L min . This means that the current through
the diode is maximal (as the sum of the diode current I D and the load current I L is equal to a
given input current I). The maximal allowed current through the diode is I D max = 200 mA and
it is clear that this value will be achieved for U 1max = 55 V and I max = 240 mA . These
considerations imply the following conclusion:
I L min = I max − I D max = 40 mA , R L max =
UZ
= 175 Ω .
I L min
As the second step consider the minimum load resistance R L min . If the resistance is
minimal, the current through the load should be at its maximum I L max . This means that the
current through the diode is minimal; however, it cannot be less than I D min = 20 mA . This
minimum value will be achieved for U 1min = 45 V and I min = 190 mA . These considerations
imply:
I L max = I min − I D min = 170 mA , R L min =
UZ
I L max
= 41.2 Ω
Example 4.6
Regulator with load R L = 300 Ω :
As the Zener voltage is U Z = 9.5 V and the output voltage should be U 2 = 20 V , we use
two Zener diodes in series. In the circuit we can be
immediately seen:
IL =
U2
= 66,7 mA
RL
1
U D = U 2 = 10 V
2
Electronic Devices
U D = U Z + rd I D , I D =
131
UD −UZ
= 250 mA
rd
I = I D + I Z = 317 mA
R=
U1 − U 2
= 31,5 Ω
I
The power dissipated at the resistor R and at the Zener diode is:
PR = I (U1 − U 2 ) = 3,17 W , PD = I DU D = 2,5 W
Regulator without load (open terminals):
The total current flows through diodes, the power dissipated at the diodes reaches its
maximum. By means of the figure we obtain (the upperscript (0) indicates open terminals) :
U 1 = RI D( 0) + 2(U Z + rd I D( 0) )
I D( 0) =
U 1 − 2U Z
= 310 mA
R + 2rd
U D( 0) = U Z + rd I D( 0) = 10.1 V
PR( 0) = I D( 0) (U 1 − 2U D( 0) ) = 3.04 W
PD( 0) = I D( 0)U D( 0) = 3.13 W
Short-circuit at the output:
The output voltage is zero, U 2 = 0 , thus the
voltage across diodes must be also zero, U D = 0 ,
both diodes are closed,
I D = 0 . The short-circuit current is
I short =
U1
= 952 mA
R
and the power dissipation
PR short = U 1 I short = 28.6 W
8.2 Examples for Bipolar Junction Transistor
8.2.1
Solution Chapter 5.6.4
Example 5.2a
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U BE = 0.7 V
U CC = R B I B + U BE + R E I E
U CC = R B I B + U BE + R E ( β + 1) I B
IB =
U CC − U BE
= 21.8 µA
R B + ( β + 1) R E
I C = βI B = 2.61 mA
I E = I C + I B = ( β + 1) I B = 2.63 mA
U CC = RC I C + U CE + R E I E
U CE = U CC − RC I C − R E I E = 7.14 V
U CB = U CE − U BE = 6.44 V
Example 5.3b
We solve this example in two different ways.
(I) We assume that the base current IB is small if compared with the current which flows
through resistors RB1, RB2; thus it can be neglected and the voltage divider can be considered
as unloaded. This approximation is satisfactory if the current gain β is high. The current
through the unloaded voltage divider is U CC /( B1 + R B 2 ) = 0.543 mA .
U BE = 0.7 V
IB ≈ 0
U RB 2 = U CC
RB 2
= 3.04 V
R B1 + R B 2
U RB 2 = U BE + R E I E
IE =
U RB 2 − U BE
= 2.34 mA
RE
IE
= 10.6 µA
β +1
I C = I E − I B = 2.34 mA
IB =
U CC = RC I C + U CE + R E I E
U CE = U CC − RC I C − R E I E = 4.96 V
U CB = U CE − U BE = 4.26 V
II) We apply the Thevenin theorem to the voltage divider; it enables to avoid the
assmption of negligible base current. For better understanding we redraw the original circuit
in several steps to get the Thevenin equivalent circuit:
Electronic Devices
133
We calculate the Thevenin equivalents U Th , RTh the base current I B and other currents
and voltages in the circuit:
U Th = U CC
RTh =
RB 2
= 3.04 V
RB1 + RB 2
RB1RB 2
= 4.46 kΩ
RB1 + RB 2
UTh = RTh I B + U BE + RE I E
UTh = RTh I B + U BE + RE ( β + 1) I B
IB =
U Th − U BE
= 10.4 µA
RTh + ( β + 1) I B
IC = βI B = 2.29 mA
I E = IC + I B = 2.30 mA
U CE = U CC − RC IC − RE I E = 5.16 V
U CB = U CE − U BE = 4.46 V
Example 5.4c
U BE = 0.7 V
R E I E − U EE + R B I B + U BE = 0
R E ( β + 1) I B − U EE + R B I B + U BE = 0
IB =
U EE − U BE
= 38 µA
R B + ( β + 1) R E
I C = βI B = 2.28 mA
I E = I C + I B = ( β + 1) I B = 2.32 mA
U CC + R B I B − U CB − RC I C = 0
U CB = U CC + R B I B − RC I C = 4.55 V
U CE = U CB + U BE = 5.25 V
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8.2.2
Examples for BJT as electronic switch
Example 8.1:
The npn bipolar transistor should be used as a switch of a resistive load with rated
voltage of 24 V and resistance 60 Ω. The transistor parameters are: β = 35 ÷ 125 ,
U CBO = 70 V , I C max = 500 mA , U CES ≈ 1.5 V , PC max = 800 mW (without additional
cooling).
a) Design the switch circuit.
b) Find current I B necessary to turn the load ON.
c) Calculate the currents and voltages I B , I C , U BE , U CE in ON-state and in OFF-state a
draw graphs of these quantities as functions of time.
d) Is it necessary to apply the additional cooling to the transistor?
Solution:
a) See the figure.
b) The current through the load is
is equal to
U L / R L = 24 V / 60 Ω = 0.4 A = 400 mA and it
base
the collector current I C of the transistor. The
current depends on the current gain: I B = I C β : I B = 11.4 mA for β = 35 and I B = 3.2 mA for
β = 125 .
c)
ON-state, β = 35 :
U L 24 V
=
= 400 mA ,
60
RL
I
400 mA
IB = C =
= 11.4 mA ,
β
35
U CE = U CES ≈ 1.5 V
IC =
U BE ≈ 0.7 V ,
ON-state, β = 125 :
U L 24 V
=
= 400 mA ,
RL
60
I
400 mA
IB = C =
= 3.2 mA ,
β
125
U CE = U CES ≈ 1.5 V
IC =
OFF-state, β arbitrary:
U BE ≈ 0.7 V ,
Electronic Devices
135
I B = I C = 0 , U BE < 0 , U CE = U L + U CES = 24 V + 1.5 V = 25.5 V
The emitter-base junction should be closed by the voltage U BE , its exact value does not
follow from the text.
d) The power dissipated by the transistor is PC = I C U CES = 400 mA × 1.5 V = 600 mW is
less than the maximum allowed power PC max = 800 mW , thus no additional cooling is
necessary.
8.2.3
Example for Operation of BJT as constant current source
Example 8.2:
The bipolar transistor is used as a constant current source.
The Zener diode is used to ensure the stability of the
operating point of the transistor. Calculate the transistor
operating point and also the operating point of the Zener
diode.
UCC = 15 V, RB = 3.3 kΩ, RC = 1.2 kΩ, RE = 1.6 kΩ, UZ =
V, rd ≈ 0.
Solution:
U BE = 0.7 V
U Z = U BE + R E I E
IE =
U Z − U BE
= 2.69 mA
RE
IB =
IE
= 17.8 µA, I C = I E − I B = 2.67 mA
β +1
U CE = U CC − RC I C − R E I E = 7.5 V
I RB =
U CC − U Z
= 3.03 mA
RB
I D = I RB − I B = 3.01 mA
8.3 Examples for Field-Effect Transistors
8.3.1
Example for Operating point of JFET
Example 8.3:
Find the operating point of the JFET in the circuit in the
figure.
5
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FEKT Vysokého učení technického v Brně
UDD = 24 V, RS = 10 kΩ, RG = 1.,0 MΩ, the transistor parameters IDSS = 10 mA,
UP = − 4 V.
Solution:
The equation of the closed loop [gate – source – resistor RG – gate] together with the
equation of the transistor characteristics
 U
U GS + RS I D = 0 , I D = I DSS 1 − GS
UP




2
give the quadratic equation for the voltage UGS
 U
U GS + RS I DSS 1 − GS
UP

RS I DSS
U P2
2

 = 0


R I
2
U GS
+ 1 − 2 S DSS
UP


U GS + RS I DSS = 0

Its coefficients are:
a=
R S I DSS
U P2
= 6.25 V -1 , b = 1 − 2
R S I DSS
= 51 , c = RS I DSS = 100 V
UP
The solution if the quadratic equation is:
U GS =
− b ± b 2 − 4ac
2a
U GS =
− 8.5 ± 8.5 2 − 4 × 0.9375 × 15
V , U GS = −3.28 V or U GS = −4.88 V
2 × 0.9375
As the voltage UGS should satisfy the relation U P ≤ U GS ≤ 0 the correct value of the gate
voltage UGS is U GS = −3.28 V .
The current ID is be calculated by means of the characteristics equation or by means of
the loop equation:
ID
 U
= I DSS 1 − GS
UP

2

U
 = 0.33 mA , I D = − GS = 0.33 mA
RS

The voltage UDS is:
U DS = U DD − R S I D = 20.7 V
Example 8.4:
Find the operating point of the JFET in the circuit in the figure.
UDD = 24 V, RD = 1.2 kΩ, RG = 1,0 MΩ, the transistor
parameters IDSS = 10 mA,
Electronic Devices
137
UP = − 4 V.
Solution
The equation of the closed loop [gate – source – resistor RG – gate] together with the
equation of the transistor characteristics
U GS + RS I D = 0 , I D
 U
= I DSS 1 − GS
UP




2
now give U GS = 0 , I D = I DSS = 10 mA . The voltage UDS is
U DS = U DD − R D I D = 10 V
8.3.2
Example for Operating point of MOSFET
Example 8.5:
Find the operating point of the MOSFET.
UDD = 24 V, RD = 3.0 kΩ, RS = 0.82 kΩ, RG1 = 18 MΩ,
RG2 = 36 MΩ, the transistor parameters are K = 0.12
mA/V2, UP = 5 V.
Solution:
The calculation of the operating point of a MOSFET is
very similar to the solution of circuit with a JFET.
U RG 2 = U DD
RG 2
= 16 V
RG1 + RG 2
U RG 2 = U GS + RS I D ,
I D = K (U GS − U P )2
U GS + RS K (U GS − U P )2 − U RG 2 = 0
2
KRSU GS
+ (1 − 2 KRSU P )U GS + KRSU P2 − U RG 2 = 0
a = KR S = 0.0984 V -1 , b = 1 − 2 KR S U P = 0.016 , c = KR S U P2 − U RG 2 = −13.54 V
U GS =
− b ± b 2 − 4ac
= 11.65 V or − 11.81 V , U GS ≥ U P ⇒ U GS = 11.65 V
2a
I D = K (U GS − U P ) 2 = 5.31 mA
U DD = RD I D + U DS + RS I D
U DS = U DD − ( RD + RS ) I D = 3.73 V
138
FEKT Vysokého učení technického v Brně
8.3.3
Example for JFET as analogue switch
Example 8.6:
The JFET is used as an analogue switch (as a voltage controlled resistor), see the
circuit in the figure.
a) Explain the principle of the analogue switch operation.
b) Find the dynamic channel (output)
resistance of the transistor in the active
mode.
b) Find the voltage transfer Au = u 2 u1
of the circuit.
c) Find the voltage UGG for Au = 1 / 2 .
Solution:
a) The JFET operates in the active (linear,
ohmic) mode, the voltage UDS is small. The output
characteristics of the transistor are approximately
straight lines that corresponds to different dynamic
channel (output) resistance rd of the transistor; it can
be controlled by the voltage UGS. The transfer of the
small ac signal u1 from the input terminal to the
output terminal is controlled by the resistance rd.
b) The equation of the output characteristics in
the active mode is


U − U GS
 U DS
I D = I DSS 3
− 2  DS


UP
 U P





3/ 2
U
−  GS
 U
 P




3/ 2 
 


The dynamic channel resistance rd and conductance g d is defined as
 ∂I D
1
= g d = 
rd
 ∂U DS



U GS =const
As the transistor output characteristics are (with some approximation) straight lines it is
sufficient to calculate the derivative for U DS = 0 :
 ∂I D
g d = 
 ∂U DS



 3 − 2 3 1  U DS − U GS

=
I
DSS
U = 0
UP
UP
2 U P 
U DS =const.

GS




1/ 2 
I

= 3 DSS

UP
 U DS =0
 U
1 −  GS
  U P





1/ 2 



Electronic Devices
rd =
UP
3I DSS
139
1
U GS
UP
1−
c) We assume that both coupling capacitors have
negligible impedance. The JFET can be replaced by the
dynamic channel resistance rd for a small ac signal. The
small signal equivalent circuit of the analogue switch is
drawn in the figure. We can see that resistors rd, R2 act
as a voltage divider; thus, the voltage transfer is:
u2 = u1
R2
R2 + rd
⇒ Au =
d) It should be Au =
u2
R2
1
=
=
u1 R2 + rd 1 + rd
R2
r
1
1
= , thus d = 1 , rd = R2 . With the result of part b) we
r
2
R2
1+ d
R2
have:
R2 =
UP
3I DSS
1
1−
U GS
UP
⇒ U GS

UP
= U P 1 −
 3I
DSS R 2





2
As it flows no dc current through the resistor RG, the voltage supply UGG and the gate
voltage UGS are equal, U GG = U GS .
9 References