Middle-East Journal of Scientific Research 24 (3): 663-668, 2016
ISSN 1990-9233
© IDOSI Publications, 2016
DOI: 10.5829/idosi.mejsr.2016.24.03.23047
Capacitor Cascaded Multilevel Inverter with PWM Control Method
K. Gowthami and K. Balachander
Department of EEE, Karpagam Academy of Higher Education, Coimbatore-641021, India
Abstract: A capacitor cascaded multilevel inverter with PWM control with detailed modes of operation with
proper switching sequence is presented in this paper. It consists of a standard 3-leg inverter (one leg for each
phase) and H-bridge in series with each inverter leg [1]. It uses only a single DC power source to supply a
normal 3 phase inverter along with three full H-bridges supplied by capacitors. Capacitor cascaded
Multilevel based PWM control is used to produce a five-level phase voltage and more by adding H-bridges
in series. The inverter can be used in hybrid electric vehicles(HEV) and electric vehicles (EV)[1]. A simulation
model based on SIMULINK is developed.
Key words: Multilevel inverter
sequence
Capacitor
MATLAB
INTRODUCTION
H-Bridge
Modes of Operation
Switching
electric motor to drive the vehicle and electric vehicles
(EV). An EV includes rechargeable batteries and an
electric motor. The power inverter that drives the electric
motor is a key device of a HEV and EV [1-5].
A simulation is done based on MATLAB/SIMULINK
platforms. It makes the design and analysis of a hybrid
capacitor cascaded multilevel inverter with detailed modes
of operation with proper switching sequence.
Nowadays, increasing oil prices and environmental
concerns, hybrid electric vehicles (HEVs) and electric
vehicles (EVs) are gaining increased attention due to their
higher efficiencies and lower emissions associated with
the development of improved power electronics and motor
technologies.
In this paper, the proposed hybrid capacitor
cascaded multilevel inverter includes a normal 3-leg
inverter (one leg for each phase) and by adding
H-bridge in series with each inverter leg [1]. It uses
only a single DC power source to supply a normal
3-leg inverter along with three full H-bridges supplied
by capacitors. Traditionally, each H-bridge requires a
DC power source. Multilevel capacitor cascaded
carrier based PWM control method is used to
produce a five level phase voltage and more by adding
H-bridges in series with each leg. But in this paper
presents a capacitor cascaded H-bridge multilevel boost
inverter design which can be used for EV and HEV
applications implemented without the use of inductors is
proposed.
The inverter mostly used in hybrid electric vehicles
(HEV) with a smaller internal combustion engine of a
conventional vehicle with a battery pack and an
Topology of Proposed 3-phase Inverter: The proposed
topology of the three phase capacitor cascaded H-Bridge
multilevel inverter is shown in Fig 2.1. S1,1 represents the
switch 1 of the first phase in the main inverter bridge
where as S2,a1 represents the switch of first phase in the
capacitor bridge.
The inverter uses a normal three-leg inverter (one leg
for each phase) and an H-bridge with a capacitor as its DC
source in series with each phase leg [1].
Topology of Proposed 1-phase Inverter: The proposed
topology of the three phase capacitor cascaded H-Bridge
inverter is shown in Fig 2.2.
Operation of the Inverter: A simplified single phase
topology is shown in Fig 2.2. The output voltage í1 of this
leg of the bottom inverter (with respect to the ground) is
Corresponding Author: K. Gowthami, Department of EEE, Karpagam Academy of Higher Education,
Coimbatore -641021, India. Tel: +919524158586.
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Middle-East J. Sci. Res., 24 (3): 663-668, 2016
Table 2.1: Shows the switching sequence of the proposed single phase
inverter
S1
Fig. 2.1: Three-Phase H-Bridge multilevel boost inverter
S2
S3
S4
S5
S6
0V
0
1
1
0
1
0
V
+ dc
2
1
1
0
0
1
0
+Vdc
1
0
0
1
1
0
V
+ dc
2
1
1
0
0
1
0
0V
0
1
1
0
1
0
0V
0
1
1
0
1
0
V
− dc
2
1
1
0
0
0
1
-Vdc
0
1
1
0
0
1
V
− dc
2
1
1
0
0
0
1
0V
0
1
1
0
1
0
The output waveform is shown in Fig 2.3. When the
output voltage = 1 + 2=0, one can either set 1 =
V
V
V
V
+ dc and 2 = - d c or 1 = - d c and 2 = + dc . To
2
2
2
2
explain how the capacitor is kept charged, consider the
, the output voltage in Fig 2.3 is zero
interval 1
and the current i > 0. If S1 and S4 are closed (so that 2 =
V
V
+ dc ) and S6 is closed (so that 1 = − dc ), then the
2
2
capacitor is discharging [ic = -i < 0] and = 1 + 2 = 0.
On the other hand, if S2 and S3 are closed (so that 2 =
V d c ) and S is also closed (so that 1 = Vdc ), then the
5
+
Fig. 2.2: Single-Phase H-Bridge multilevel boost inverter
2
2
capacitor is charging [ic = i > 0] and = 1 + 2 = 0 [1-5].
Modes of Operation: The proposed single phase
cascaded inverter produces five levels of output voltage.
The corresponding five levels are: -Vdc, − Vdc , 0, V d c
2
2
and Vdc.
Mode for 0V: In this mode, switches S2,S3 and S5 are
switched on. Upper bridge i.e., S2 and S3 will produce the
output voltage of − Vdc while the lower bridge i.e. switch
Fig. 2.3: Overall output voltage and load current
either
V
+ dc
2
(S5 closed) or –
Vdc
2
2
(S6 closed). This leg is
S5 will produce output voltage of
connected in series with a full H-bridge, which, in turn, is
supplied by a capacitor voltage. If the capacitor is kept
charged to + Vdc , then the output voltage of the H-bridge + Vdc
2
Vdc
2
. Thus the net
output will be v1+v2=0. Fig 2.4 shows the mode for 0V.
Mode for
2
(S1 and S4 closed), 0 (S1 and S2 closed or S3 and S4 closed),
or − Vdc (S2 and S3 closed). [1-5].
Vdc
2
: In this mode, switches S1,S2 and S5 are
switched on. Upper bridge i.e., S1 and S2 will produce the
output voltage of 0V as they have zero potential
2
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Middle-East J. Sci. Res., 24 (3): 663-668, 2016
Fig 2.7: Mode for –
Fig 2.4: Mode for 0V
Vdc
2
Fig 2.8: Mode for –Vdc
Fig 2.5: Mode for
Vdc
2
Mode for Vdc: In this mode, switches S1,S4 and S5 are
switched on. Upper bridge i.e., S1 and S4 will produce the
output voltage of V d c while the lower bridge i.e. switch
2
S5 will produce output voltage of
Vdc
2
. Thus the net
output will be v1+v2=Vdc. Fig 2.6 shows the mode for Vdc.
Mode for
V
− dc
2
: In this mode, switches S1,S2 and S6 are
switched on. Upper bridge i.e. S1 and S2will produce the
output voltage of 0V as they have zero potential
difference while the lower bridge i.e. switch S6 will
produce output voltage of - V d c . Thus the net output
2
will be v1+v2=- V d c . Fig 2.7 shows the mode for 2
Fig 2.6: Mode for Vdc
2
be v1+v2=
. Fig 2.5 shows the mode for
Vdc
2
.
Mode for –Vdc: In this mode, switches S2,S3 and S6 are
switched on. Upper bridge i.e. S2 and S3 will produce the
output voltage of -Fig 2.8: Mode for –Vdc while the lower
bridge i.e. switch S6 will produce output voltage of -Fig
2.8: Mode for –Vdc. Thus the net output will be v1+v2=Vdc. Fig 2.8 shows the mode for - Vdc.
difference while the lower bridge i.e. switch S5 will
produce output voltage of V d c . Thus the net output will
Vdc
2
Vdc
2
.
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Middle-East J. Sci. Res., 24 (3): 663-668, 2016
Design of 1-Phase H-bridge Multi Level Inverter
Simulation Diagram: With 0 degree phase shift
Output Waveform:
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Middle-East J. Sci. Res., 24 (3): 663-668, 2016
Design of 3-Phase H-bridge Multi Level Inverter:
Output Waveform:
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Middle-East J. Sci. Res., 24 (3): 663-668, 2016
CONCLUSION
8.
A simulation model for the hybrid capacitor cascaded
multilevel inverter is developed in SIMULINK cosimulation platform. The inverter output is a five level
phase voltage and more by adding H-bridges in series..
The paper presents the main circuit model in simulation
results in detail with modes of operation with proper
switching sequence. The experiment results verified the
proposed hybrid cascaded multilevel inverter with a PWM
control method.
9.
10.
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