December 2010, Volume 4, No.12 (Serial No.37)
Journal of Energy and Power Engineering, ISSN 1934-8975, USA
Hard Switching Process Optimization for Selected
Transistor Suited for High Power and High Frequency
Operation
M. Frivaldský, P. Drgoňa and P. Špánik
Department of Mechatronics and Electronics, Faculty of Electrical Engineering, University of Zilina, Univerzitna 1, Zilina 01026,
Slovakia
Received: May 12, 2010 / Accepted: August 12, 2010 / Published: December 31, 2010.
Abstract: This paper deals with optimization of hard switching commutation mode for high-power, high-frequency consumer
applications for selected power transistor. The experimental investigation of suitable settings is outgoing from simulation analysis of
hard switching for different transistor structures. For these purposes, the simulation models of power semiconductor switches with high
level of validity have been used. After that, the experimental analysis for selected transistor was done with change of parameters that
are influencing commutation process of transistor. Target of such kind of analysis was to reach as low switching losses as possible,
achieving high power density and efficiency of power system, without utilization of improved switching techniques such as resonant
switching. The results confirm that this task is realizable through use of progressive semiconductor devices such as SiC diodes and/or
through latest families of MOSFET devices.
Key words: Transistor, commutation, losses, frequency, simulation, experimental analysis, converter.
1. Introduction
Current tendencies in the field of power electronic
devices could be characterized by continuous
improvement of electrical, mechanical, economical and
ecological parameters. If we take into account physical
phenomenon relative to mentioned requirements, then
approaching the aims is possible by increasing of
switching frequency along with elimination of power
losses. Naturally by increasing of switching frequency
generation of higher power loss comes to be significant.
Instead of turn-on and turn-off losses, also conduction
losses are very important in high-frequency high-power
applications. Nowadays a huge amount of effort is
produced to find the ways how to totally eliminate
almost all of the losses in power semiconductor devices
[1, 2]. One way is to utilize soft-switching, second way
Corresponding author: M. Frivaldský, Ph.D., research field:
power systems. E-mail: michal.frivaldsky@fel.uniza.sk.
is to utilize the progressive semiconductor structures.
The goal of every power semiconductor system design is
approach to the highest efficiency with respect to
maximum output power. DC/DC power supplies
encounter the power levels, somewhere from a few
watts for battery-operated portable equipment, several
hundred to several kilo-watts for home entertainment,
computer and office equipment. Synchronous
rectification is also becoming popular method to
improve (Switched–Mode Power Supplies) SMPS
efficiency. Motor drives can use from a tenth of a Watt
to few mega Watts [3, 4]. Almost all the SMPS are
nowadays being developed in cooperation with a power
factor control (PFC) input stage in order to meet the
international regulatory standards for harmonic content.
The negative feedbacks of such technical improvement
are additional switching losses that are generated during
commutation process of mentioned boost diode and
power transistor. Therefore this system needs perfect
Hard Switching Process Optimization for Selected Transistor Suited for High Power and High Frequency 37
Operation
specification of suitable components for given
application (boost diode, MOSFET or IGBT transistor)
that is by reason of optimalization of output power and
also financial costs [5].
In next chapters the investigation of hard switching
commutation mode of power transistor will be solved,
targeting high power density and efficiency of power
system.
2. Simulation Analysis
For proper selection of power semiconductor device
for HF/HP application we decide to investigate three
types of power transistors.
It can be seen that for investigation we assigned two
generations of unipolar MOSFET transistors
(fyInfineon), whose RDS (ON) is minimized due to
improvements in technology process. IGBT structure
is selected for competition, whereby we’ve tried to find
the fastest structure in current market. IGBT structure
generally has better performance in conduction mode,
but on the other side MOSFETs are faster in turn-off
process. Target of this chapter is to compare and
evaluate processes which are occurring during
switching of transistor by utilization of simulation
program (OrCAD 15.7 Pspice). The results from
simulation have been serving at selection of proper
structure that was consequentially given into
experimental analysis.
Because every commutation technique requests
specific behavior of main circuit, the simulation
analysis was adapted to requirement of realness and
authenticity of experimental testing circuit. Simulation
has been realized at constant supply voltage (325 V),
what is corresponding to the maximum value of
rectified voltage from 1-phase supply network. The
load is represented by resistive-inductive alternative, at
which maximum load current was 10 A. Gate resistor
of transistor was set to 33 Ω at which pulse front
steepness of transistor’s current was di/dt = 250 A/us.
As we were considering high-frequency application,
the simulation analysis was done at switching
frequency of 100 kHz. The schematic of simulation
testing circuit is shown on Fig. 1.
2.1 Simulation Results
Fig. 2 shows voltage and current waveforms during
Fig. 1 Schematics of test circuit during simulation analysis.
Table 1 Investigated transistors and their basic parameters.
Parameter /
transistor
UDS (V)
ID (A) 25 ℃
ID (A) 100 ℃
PTOT (W)
RDS (Ω) 25 ℃
RDS (Ω) 150 ℃
CISS (pF)
COSS (pF)
Tr (ns)
Tf (ns)
Qg (nC)
SPP20N
60C3
650
20
13
208
0.19
0.43
2400
780
5
12
87
IPW60R
165CP
650
21
13
192
0.15
0.4
2000
100
5
5
39
IXGH12N
60BD1
600
24
12
100
2.1²
860
100
20
120
32
2-UCE(SAT)
Fig. 2 Detail of voltage (dashed line) and current waveform
(solid line) during turn-on process SPP20N60C3,
IPW60R165CP, IXGH12N60BD1.
38
Hard Switching Process Optimization for Selected Transistor Suited for High Power and High Frequency
Operation
turn-on process. From figure, delayed increase of
current in the case of IGBT structure is visible. This is
caused due to dynamic process characterization of
charge carrier transport. In the case of MOSFETs we
can see faster slope of conduction when using
IPW60R165CP [6, 7]. The time difference is around
7ns and is caused by higher value of input capacitance
of SPP20N60C3. Interesting fact from this simulation
is fast grow of current after start of conduction (IGBT
transistor) which is caused by different character of
drop at bipolar segment of IGBT.
Waveforms of current and voltage during turn-off
process are shown on Fig. 3.
Likewise as in previous case, also during turn-off we
can study expressive differences at behaviour of various
transistor structures. In the case of IGBT the effect of
tail current could be seen even despite of HiperFast
structure choice [8, 9]. A similar behaviour difference
occurs at investigation of MOSFET structures, where
SPP20N60C3 due to higher value of Miller capacitance
and consequently its strong voltage dependency shows
itself as slower against IPW60R165CP.
Fig. 4 represents time-dependency of absorbed
energy during whole switching sequence (turn-on →
conduction → turn-off). Transistors were switching
with period of 10 μs, whereby duty cycle was set to
45%. The highest value of absorbed energy was
noticed at IGBT transistor what is suggested not to use
at even higher frequencies. Interesting is shape
similarity during turn-on for each transistor. A first
difference occurs during transition into conduction
mode. Highest difference happens during transition
from conduction mode into turn-off process.
3. Evaluation of Simulation Analysis
Results of simulation analysis are outgoing from
figures that are listed in previous chapter. The value of
total power loss PTOT is comprised of turn-on losses
(PON) and turn-off losses (POFF). During computation of
each part of losses next equations have been used Eq. (1).
Fig. 3 Detail of voltage (dashed line) and current waveform
(solid line) during turn-off process SPP20N60C3,
IPW60R165CP, IXGH12N60BD1
Fig. 4 Comparison of absorbed energy during whole
switching sequence at hard-switching commutation mode
SPP20N60C3, IPW60R165CP, IXGH12N60BD1.
POFF(ON ) =
TZ 2
1
1
⋅WOFF(ON ) = .∫ iP (t ) u P (t ) dt = ∑ I P [i].U P [i ]ΔT
T
T
i =TZ 1
(1)
where
iP(t) is time function of transistor’s current;
uP(t) is time function of transistor’s voltage;
TZ1
sequence of sample at the begin of
transistor’s turn-on/turn-off process;
TZ2
sequence of sample at the end of transistor’s
turn-on/turn-off process;
IP[i] is ith sample of transistor´s current;
UP[i] is ith sample of transistor´s voltage;
ΔT
is sampling time.
From Table 2 it can be seen that value PON is almost
the same for each transistor. Substantial differences
were identified at turn-off process what is reflected at
value of POFF. Despite of HiperFast IGBT utilization
the worst dynamic behaviour has been confirmed.
Hard Switching Process Optimization for Selected Transistor Suited for High Power and High Frequency 39
Operation
Table 2 Review of each power loss size, which are being
generated during hard–switching commutation mode.
SPP20N60C3
IPW60R165CP
IXGH12N60BD1
Pon (W)
22
19.5
19
Poff (W)
20.2
14
31.6
Ptot (W)
42.2
33.5
50.6
From Fig. 3 it can be seen that, after rapid current drop
a current tail is visible which has time duration around
500
ns. Turn-off losses of this device
(IXGH12N60BD1) are higher by 126% against
IPW60R165CP. Also CoolMOS of 5th generation
IPW60R165CP has lower turn-on losses by 43%
against SPP20N60C3. The result of this analysis is, that
in the case of SPP20N60C3 PON are almost the same as
its POFF. IXGH12N60BD1 has POFF by 66% higher that
PON. Generally lowest losses were discovered at usage
of IPW60R165CP whose POFF are by 40% lower than
PON. PTOT of IPW60R165CP was lower against other
devices by 26% (SPP20N60C3) and 51%
(IXGH12N60BD1). Thereby the final selection has
concentrated on IPW60R165CP, which was selected
for experimental analysis.
4. Experimental Analysis
Experimental analysis was realized similarly as
simulation analysis at full fart to real conditions that are
corresponding to selected application. The goal of
experimental analysis was to evaluate each part of
switching power loss. Principal schematics of main
circuit that was used for experimental analysis is shown
in Fig. 1. Investigation of hard-switching commutation
mode was done throughout change of parameters,
which are influencing amount of power losses.
Changing parameters were: load current (ILOAD), pulse
front steepness of transistor´s current (di/dt(ON)),
turn-off resistor (RG(OFF)), and null diode (DNULL). Just
at the change of last parameter the perspective device
of material engineering has been utilized, specifically
schottky diode based on SiC substrate [10-14].
Measurements were realized at these parameters of
main circuit:
• UIN=325 V;
• fSW=100 kHz;
• ILOAD=5 A, 10 A;
• di/dt(ON)=50 A/us, 100 A/us, 150 A/us, 250
A/us;
• RG(OFF) = 15 Ω, 51 Ω, 230 Ω, 470 Ω;
• DNULL = BYT12P-1000, SDT12S60.
4.1Experimental Results of Turn-on Process
Fig. 5 is showing current and voltage waveforms
from experimental analysis of IPW60R165CP turn-on
process. It can be seen that, by utilization of
BYT12P-1000 as null diode, a huge peak value occurs
as consequence of diode’s reverse recovery process. As
result a higher amount of switching losses come into
account. This effect should be eliminated by utilization
of diode with better dynamic performance. It can be
seen that by using SDT12S60 the reduction of turn-on
losses come into account (see Table 3). Another way of
power losses reduction is to increase the di/dt of
transistor’s current. It should be noted that critical
value, which is mostly posted in datasheet, can not be
exceeded. Numerical evaluation of power losses that
are generated during turn-on process at change of
strategic parameters are shown in Table 3.
The next two graphical interpretations have been
reached by polynomial approximation of power losses.
They are showing turn-on losses in dependency of
switching frequency and load current. Fig. 6 interprets
this dependency in the case of BYT12P-1000
utilization and Fig. 7 in the case of SDT12S60. Both
graphs are valid for di/dt(ON) = 250 A/us because of
Fig. 5 Turn-on process of IPW60R165CP that is showing
current and voltage waveforms for different di/dt (50 A/us,
100 A/us, 150 A/us, 250 A/us).
40 Hard Switching Process Optimization for Selected Transistor Suited for High Power and High Frequency
Operation
Table 3 Results of experimental analysis of turn-on process
during
hard
switching
commutation
mode
of
IPW60R165CP transistor.
Pon [W] BYT12P BYT12P SDT12S60 SDT12S60
di/dt
50 A/us
100 A/us
150 A/us
250 A/us
ILOAD=5 A
27.4
23.2
20.4
18.3
ILOAD=10 A ILOAD=5 A
61.3
12.8
50.9
9.1
44.8
6.3
41.8
4.4
ILOAD=10 A
23.6
16.5
13.2
9
most favourable results.
These graphs are helpful at design of main circuit
parameters, where the compromise between maximum
switching frequency and value of load current is
necessary. If we think about power converter, whose
input–output parameters are (typical for distributed
power systems):
• Input voltage: 230 VAC–rectified and PFC
compensated;
• Output voltage: 60 V;
• Output current: 25 A;
• Switching frequency: >100 kHz.
and allow maximum switching losses PON = 20 W, then
in the case of SDT12S60 we have to hold transistor in the
area between s fSW = 200 kHz-300 kHz a ILOAD = 11-8 A
(Fig. 6). By utilization of BYT12P-1000, the borders
have to be reduced to fSW = 30 kHz-50 kHz when to
consider ILOAD = 11-8 A (Fig. 7). In connection with this
reduction, the power density of converter will
expressively decrease whereby dimensions will increase.
4.2 Experimental Results of Turn-on Process
Fig. 8 shows current and voltage waveforms from
experimental analysis of IPW60R165CP turn-off
process. During measurements the parameter DNULL
didn’t have visible influence. Higher dependency
occurs at the changing of RG (OFF) value.
Numerical evaluation of power losses that are
generated during turn-off process at change of strategic
parameters are shown in Table 4.
Fig. 6 3-D graphical interpretation of turn-on losses in
dependency of switching frequency and load current (DNULL
= BYT12P-1000).
Fig. 8 Turn-off process of IPW60R165CP that is showing
current and voltage waveforms for different RG(OFF) (470 Ω,
240 Ω, 110 Ω, 33 Ω).
Table 4 Results of experimental analysis of turn-off
process during hard switching commutation mode of
IPW60R165CP transistor.
Fig. 7 3-D graphical interpretation of turn-on losses in
dependency of switching frequency and load current (DNULL
= SDT12S60).
Pvyp [W]
RG(OFF)
470 Ω
240 Ω
110 Ω
33 Ω
BYT12P
ILOAD=5 A
4.2
4.1
3.3
1.3
BYT12P
ILOAD=10 A
20.3
15.7
15.0
9.4
SDT12S60
ILOAD=5 A
4.0
3.4
2.6
1.6
SDT12S60
ILOAD=10 A
17.0
15.2
12.1
9.5
Hard Switching Process Optimization for Selected Transistor Suited for High Power and High Frequency 41
Operation
transistor structure.
5. Conclusions
Fig. 9 3-D graphical interpretation of turn-off losses in
dependency of switching frequency and load current (RG(OFF)
= 33 Ω).
Graphical interpretation of turn-off losses in
dependency on switching frequency and load current is
shown in Fig. 9. It was obtained by the same way as in
the case of turn-on process (polynomial approximation).
The only difference is that the parameter DNULL did not
play important role, therefore 3-D graphical
interpretation has been made just only for the best result
of RG(OFF) = 33 Ω utilization. The graph is again useable
at the design of converter’s main circuit parameters. But
in this situation, we have to choose opposite procedure
as in the case of turn-on process. Considering
conditions as in previous case (PON = max.20 W) and
respecting already specified boarders we have to move
in range of fSW = 30 kHz-50 kHz, ILOAD = 11-8 A if we
consider BYT12P-1000 as null diode. Then the value of
turn-off power loss will be around POFF = 10 W. When
we choose as null diode faster device, like SDT12S60,
then with respecting already chosen boarders (fSW = 200
kHz-300 kHz, ILOAD = 11-8 A) the turn-off power loss
will be around 13 W.
From bellow it is clear to say that by the impact of
worse dynamic characteristics of diode structure, the
transistor’s turn-on process is mainly influenced
[15-17]. This at the other side is indirectly influencing
turn-off processes in the way of frequency range
assignment and value of load current assignment, what
is defined by certain interval of power losses of power
The main idea of this paper was to show the
possibilities of the optimization of hard switching
commutation mode for selected application. The
simulation analysis confirmed that this way of
investigation is good process of proper device selection.
Next the set of measurements was done with selected
device, namely IPW60R165CP. These measurements
have served for creation of universal 3-D graphs, which
can be useful at the design and construction of
switch–mode power supply, whose parameters are a bit
similar to target application that was selected by us.
The future steps, will be investigation of behaviour of
this type of transistor (IPW60R165CP) in the various
commutation modes, mainly resonant techniques, to
see how could be switching losses perfectly eliminated.
Acknowledgment
The authors wish to give thanks to project VEGA
“Research of Topology and Control of Power
Electronic Supply System with Single-Phase HF Input
and Two-Phase Orthogonal Output for Two-Phase
SM/IM Electrical Motors”. Next to grant agency
APVV project no. 20-051705 and no. APVV-0535-07.
Also we would like to thank VMSP-P-0085-09 and
LPP-0366-09.
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