UNIT-1
Bipolar Junction Transistors
Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press
Figure 6.1 A simplified structure of the npn transistor.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford
University Press, Inc.
Figure 6.2 A simplified structure of the pnp transistor.
Microelectronic Circuits,
Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford
University Press, Inc.
Figure 6.7 Cross-section of an npn BJT.
Microelectronic Circuits,
Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford
University Press, Inc.
Schematic diagram of integrated-circuit BJT
From Muller and Kamins, “Device Electronics for Integrated Circuits”, 2ed., Wiley
 Isolation keeps neighboring BJTs from “talking” to one another.
 An “epitaxial layer” is a very pure, crystalline layer of semiconductor that has been added by
one of several different deposition techniques.
 SiO2 is an insulator; in this case, it serves to protect the surfaces of the semiconductor.
 The notation p and n refers to the type of semiconductor (dominant carriers are holes (p) or
electrons (n)).
 Superscripts „+‟ and „-‟ on n or p indicate very heavy doping (high conductivity) or very light
doping (low conductivity), respectively.
Direction of electron flow during forward-active biasing
Figure 6.3 Current flow in an npn transistor biased to operate in the active mode. (Reverse current components due to drift of thermally
generated minority carriers are not shown.)
Microelectronic Circuits,
Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford
University Press, Inc.
Figure 6.10 Current flow in a pnp transistor biased to operate in the active mode.
Microelectronic Circuits,
Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford
University Press, Inc.
Circuit Symbols
The arrow is at the emitter, and it points to the ntype region. In the npn, the emitter is n type; in the
pnp, the base is n-type.
+
vCB
+
vBE
-
n
+
p vCE
n
-
DC (large signal) model for active region…
Hambley 2ed., Prentice Hall 2000
DC (large signal) model for saturation region…
Hambley 2ed., Prentice Hall 2000
DC (large signal) model for cutoff region…
Hambley 2ed., Prentice Hall 2000
BJT Characteristic Curves: along the vCE axis
a) For any iB: vCE = 0 means CB junction is in forward bias because
vCB = -0.7 V. There is no net current flow, so iC ~ 0.
b) An increase in vCE causes the CB junction to be less and less
forward biased, and finally reverse-biased. When fully reversebiased, we are in forward-active mode and iC is ~ constant.
+
vCB
+
vBE
-
n
+
p vCE
n
-
active mode
Figure 5.27 Circuit whose operation is
to be analyzed graphically.
a)
saturation
b)
vCE = vCB + vBE = vCB + 0.7 V if
BE junction is “on”.
cut-off
Figure 5.29 Graphical construction for determining the dc collector current IC and the collector-to-emitter voltage VCE in the circuit of Fig. 5.27.
BJT Characteristic Curves: along the load line
c)
vCB+
active mode
-
b)
a)
saturation
cut-off
vCE = vCB + vBE
Follow the load line, along the direction shown by the arrow...
a) VCC is positive, reverse-biasing the BC junction if iC is small. If iB = iC = 0, vCE = VCC cutoff
b) Next we put the BE junction in forward bias, so vBE ~ 0.6 V. As iB increases, iC increases, lowering
vCE; we are in active mode: BE junction forward biased and CB junction reverse biased.
c) As iB increases further, iC increases and vCE decreases to the point that the BC junction becomes
forward biased. Now we are in saturation: BE junction forward bias and CB junction forward bias. In
saturation, vCE is typically ~ 0.2 V, which means vCB = -0.4 V (so CB is reverse-biased) if vBE is 0.6 V.
If we bias the BJT in the Active
Mode, we can use it as an amplifier.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
When used as a switch, the BJT is either in
Cutoff (vo high) or Saturation (vo low)
Figure 5.32 A simple circuit used to illustrate the different modes
of operation of the BJT.
To see how amplification works, let‟s
look at the Common Emitter…
KVL around input loop (dc only):
VBB iB RB
vBE
VBB
RB
vBE
RB
iB
0
Figure 5.27 Circuit whose operation is to be analyzed graphically.
We can think of either iB or vBE as an
input, so the graph shows the input
characteristics for this device.
Figure 5.28 Graphical construction for the determination of
the dc base current in the circuit of Fig. 5.27.
We are looking here at iC vs. vCE, because we can think
of these as the output current and output voltage.
active mode
KVL around output loop (dc only):
VCC
iC
saturation
iC RC
vCE
VC
RC
vCE
RC
0
cut-off
Figure 5.29 Graphical construction for determining the dc collector current IC and the collector-to-emitter voltage VCE in the circuit of Fig. 5.27.
7. Bottom Line: Current Gain: iC >> iB
6. …and a change in
collector current ic.
3. …which changes
the base current ib.
2. …changes the
BE voltage vbe…
1. Applying a signal vi…
4. The base current change
shows up here…
5. …with a corresponding
change in CE voltage vce…
Figure 5.30 Graphical determination of the signal components vbe, ib, ic, and vce when a signal component vi is superimposed on the dc voltage VBB
(see Fig. 5.27).
Base-Width Narrowing: the Early Effect
Robert F. Pierret, Semiconductor Device
Fundamentals, Prentice Hall, 1996
The intersection of the iC-vCE
curves is known as the “Early
Voltage” after James Early.
ic
+
Modeling the Early Effect
vce
With a resistance in parallel with the
current source, ic is the sum of gmvbe
and vce/ro, which more accurately
predicts the ic - vce behavior.
ic
+
vce
-
Figure 6.47 The hybrid- small-signal model, in its two versions, with the resistance ro included.
Microelectronic Circuits, Sixth Edition
Sedra/Smith
Copyright © 2010 by Oxford University Press, Inc.
Finding ac model parameters from
the characteristic curves
Output Resistance ro
We have already seen that the
slope of the iC – vCE curve gives ro.
slope = 1/r
Current Gain
We defined current gain as = IB/IC
when we looked at the dc BJT. For
ac, gain is = iC/ iB.
iB
Base Resistance r
slope = 1/r
ib
If we look at the change in ib with vbe
(ac component of the graph to the
left) we will find the inverse of r .
IB
Relationship to dc parameters
r
vbe
ib
VT
IB
slope = gm
Transconductance gm
If we look at the change in ic with vbe
(ac component of the graph to the
left) we will find gm.
Relationship to dc parameters
gm
ic
vbe
IC
VT
There are three terminals; since we need two for input and
two for output, there are three possible combinations, with
one “common” terminal in each case.
Pierret, “Semiconductor Device Fundamentals”, Prentice Hall, 1996
Common Emitter
Input resistance
Rib
Rin
r
moderate/small
RB r
Output resistance
Rout
RC ro
RC
large
Open Circuit Voltage gain
vo
vi
g m RC ro
large
Short Circuit Current gain
io
ii
g m Rin
large
Large voltage and current gain but Rin
and Ro not good for voltage amplifier.
Figure 5.60 (a) A common-emitter amplifier using the structure of Fig. 5.59. (b)
Equivalent circuit obtained by replacing the transistor with its hybrid- model.
Common Emitter with RE
Re increases Rin but reduces open
circuit voltage gain. Current gain and
output resistance are unchanged.
Input resistance
Rib
Open Circuit Voltage gain
1 re Re
Rin
RB Rib
increased
Rib greatly increased by resistance
reflection rule (Miller)
vo
vi
g m RC reduced
1 g m Re
Voltage gain reduced by ~ (1+gmRe);
Rib increased by this factor.
Figure 5.61 (a) A common-emitter amplifier with an emitter resistance Re. (b) Equivalent circuit obtained by replacing the transistor with its T
model.
Common Base
Input resistance
Rin
re
small
Output resistance
Rou
RC large
Open Circuit Voltage gain
vo
vi
g m RC large
Non-inverting version of
common emitter.
Figure 5.62 (a) A common-base amplifier using the structure of Fig. 5.59. (b)
Equivalent circuit obtained by replacing the transistor with its T model.
Short Circuit Current gain
io
ii
unity
Good for unity gain current buffer.
Common Collector
Figure 5.63 (a) An emitter-follower circuit based on the structure of Fig. 5.59. (b) Small-signal equivalent circuit of the emitter follower with the
transistor replaced by its T model augmented with ro. (c) The circuit in (b) redrawn to emphasize that ro is in parallel with RL. This simplifies the analysis
considerably.
Input resistance
Rin
RB Rib
Rib
large
1 re ro RL
Output resistance
Rout
Open Circuit Voltage gain
vo
vsig
ro RL
Rsig
1
re
~unity
ro RL
Voltage gain ~1 so emitter follows
base input voltage (emitter follower)
ro
re
Rsig
1
small
Current gain
io
ib
1
ro
ro
RL
large
Good for amplifier output stage:
large Rin, small Rout.
UNIT-2
METAL OXIDE FIELD EFFECT
TRANSISTORS
Field Effect
Transistors
IBM/Motorola Power PC620
Motorola MC68020
IBM Power PC 601
EE314
1.Construction of MOS
2.NMOS and PMOS
3.Types of MOS
4.MOSFET Basic Operation
5.Characteristics
Chapter 12: Field
Effect Transistors
The MOS Transistor
Polysilicon
Aluminum
JFET – Junction Field Effect Transistor
MOSFET - Metal Oxide Semiconductor Field Effect Transistor
n-channel MOSFET (nMOS) & p-channel MOSFET (pMOS)
The MOS Transistor
Gate Oxide
Gate
Source
Polysilicon
n+
Drain
n+
p-substrate
Bulk Contact
CROSS-SECTION of NMOS Transistor
Field-Oxide
(SiO2)
p+ stopper
Switch Model of NMOS Transistor
| VGS |
Source
(of carriers)
Open (off) (Gate = „0‟)
Gate
Drain
(of
carriers)
Closed (on) (Gate = „1‟)
Ron
| VGS | < | VT |
| VGS | > | VT |
Switch Model of PMOS Transistor
| VGS |
Source
(of carriers)
Open (off) (Gate = „1‟)
Gate
Drain
(of carriers)
Closed (on) (Gate = „0‟)
Ron
| VGS | > | VDD – | VT | |
| VGS | < | VDD – |VT| |
MOS transistors Symbols
D
D
G
G
S
S
NMOS Enhancement NMOS Depletion
D
G
D
G
S
PMOS Enhancement
B
S
NMOS with
Bulk Contact
Channel
JFET and MOSFET Transistorsor
Symbol
L = 0.5-10 m
W = 0.5-500 m
SiO2 Thickness = 0.02-0.1 m
Device characteristics depend on L,W, Thickness, doping levels
MOSFET Transistor Fabrication Steps
Building A MOSFET Transistor Using Silicon
http://micro.magnet.fsu.edu/electromag/java/transistor/index.html
It is done. Now, how does it
work?
n-channel MOSFET Basic Operation
Operation in the Cutoff region
pn junction:
reverse bias
iD=0
for vGS<Vt0
Schematic
When vGS=0 then iD=0 until vGS>Vt0
(Vt0 –threshold voltage)
n-channel MOSFET Basic Operation
Operation in the Triode Region
For vDS<vGS-Vt0 and vGS>Vt0 the NMOS is operating in the triode region
Resistor like characteristic
(R between S & D,
Used as voltage controlled R)
For small vDS, iD is proportional
to the excess voltage vGS-Vt0
n-channel MOSFET Basic Operation
Operation in the Triode Region
iD
K 2 v GS
K
Vt 0 v DS
2
v DS
W KP
L 2
Device parameter KP for
NMOSFET is 50 A/V2
n-channel MOSFET Basic Operation
Operation in the Saturation Region (vDS is increased)
Tapering
of the
channel
- increments
of iD are
smaller
when
vDS is
larger
When vGD=Vt0 then the channel
thickness is 0 and
iD
K vGS
Vt 0
2
n-channel MOSFET Basic Operation
Example 12.1
An nMOS has W=160 m, L=2 m, KP= 50 A/V2 and Vto=2 V.
Plot the drain current characteristic vs drain to source voltage
for vGS=3 V.
iD
iD
K 2 v GS
K vGS
Vt 0 v DS
Vt 0
2
2
v DS
K
W KP
L 2
n-channel MOSFET Basic Operation
Example 12.1
Characteristic
Channel length
modulation
id depends on vDS in
saturation region
(approx: iD =const in
saturation region)
iD
Kv
2
DS
p-channel MOSFET Basic Operation
It is constructed by interchanging the n and p regions of nchannel MOSFET.
Symbol
How does p-channel
MOSFET operate?
-voltage polarities
-iD current
-schematic
Characteristic
Fig. 5.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1
to 10 m, W = 2 to 500 m, and the thickness of the oxide layer is in the range of 0.02 to 0.1 m.
Fig. 5.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top
of the substrate beneath the gate.
Fig. 5.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a conductance whose value is
determined by vGS. Specifically, the channel conductance is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS.
Note that the depletion region is not shown (for simplicity).
Fig. 5.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape
and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.
Fig. 5.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with
vGS > Vt.
Fig. 5.8 Derivation of the iD - vDS characteristic of the NMOS transistor.
Fig. 5.9 Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region,
known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p
well.
Fig. 5.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current
flow indicated. (b) The iD - vDS characteristics for a device with Vt = 1 V and k’n(W/L) = 0.5 mA/V2.
Fig. 5.12 The iD - vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V and k’n(W/L) = 0.5
mA/V2).
Fig. 5.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the
effective channel length (by L).
Fig. 5.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA is typically in the range of 30 to 200 V.
Fig. 5.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro.
The output resistance models the linear dependence of iD on vDS and is given by ro VA/ID.
Fig. 5.21 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = -4 V and k’n(W/L) = 2
mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iD - vDS characteristics; (c) the iD - vGS characteristic
in saturation.
Fig. 5.31 Conceptual circuit utilized to study the operation of the MOSFET as an amplifier.
Fig. 5.32 Small-signal operation of the enhancement MOSFET amplifier.
Fig. 5.33 Total instantaneous voltages vGS and vD for the circuit in Fig. 5.31.
Fig. 5.34 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length
modulation effect); and (b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.
Fig. 5.37 the T model of the MOSFET augmented with the drain-to-source resistance ro.
Fig. 5.41 Basic MOSFET current mirror.
Fig. 5.42 Output characteristic of the current source in Fig. 5.40 and the current mirror of Fig. 5.41 for the case Q2 is matched
to Q1.
Fig. 5.45 The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical
construction to determine the transfer characteristic; and transfer characteristic.
Fig. 5.47 The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the
circuit in (b).
Fig. 5.48 The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent
circuit.
Fig. 5.52 (a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer
characteristic.
Fig. 5.53 The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer
characteristic; and (c) transfer characteristic.
Fig. 5.54 Small-signal equivalent circuit of the depletion-load amplifier of Fig. 5.43 (a), incorporating the body effect of Q2.
Fig. 5.55 (a) The CMOS inverter. (b) Simplified circuit schematic for the inverter.
Fig. 5.56 Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical
construction to determine the operating point; and (c) equivalent circuit.
Fig. 5.57 Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical
construction to determine the operating point; and (c) equivalent circuit.
Fig. 5.58 The voltage transfer characteristic of the CMOS inverter.
Fig. 5.59 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c)
trajectory of the operating point as the input goes high and C discharges through the QN; (d) equivalent circuit during the
capacitor discharge.
Fig. 5.64 The CMOS transmission gate.
Fig. 5.65 Equivalent circuits for visualizing the operation of the transmission gate in the closed (on) position: (a) vA is positive;
(b) vA is negative.
Fig. 5.67 (a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is
connected to the substrate (body); (c) the equivalent circuit model of (b) with Cdb neglected (to simplify analysis).
Fig. 5.68 Determining the short-circuit current gain Io/Ii.