T. Govindaraj et al. / IJAIR
ISSN: 2278-7844
An Hybrid Five-Level Inverter Topology with
Single-DC Supply fed Special electric Drive
1
1
Dr.T.Govindaraj and
2
T.Srinivasan ,
2
Professor and Head , M.E., PED Scholar, Department of EEE,
Muthayammal Engineering College,India
Srini070@gmail.com
Abstract—In this paper, a new single-phase, five-level
inverter topology with a single-dc source is presented. The
proposed topology is obtained by cascading a three-level flying
capacitor inverter with a flying H-bridge power cell. This
topology has redundant switching states for generating
different pole voltages. By selecting appropriate switching
states, the capacitor voltages can be balanced instantaneously
(as compared to the fundamental) in any direction of the
current, irrespective of the load power factor. Another
important feature of this topology is that if any H-bridge
fails, it can be bypassed and the configuration can still operate
as a three-level inverter at its full power rating. This feature
improves the reliability of the circuit. A induction motor is run
with the proposed topology for the full modulation range. The
effectiveness of the capacitor balancing algorithm is tested for
for the full range of speed and during the sudden acceleration
of the motor.
Index Terms—Flying capacitor (FC), H-bridge, induction motor
drive, multilevel inverter, Special Electric Drive
I. INTRODUCTION
MULTILEVEL inverters have changed the
face of medium- and high-voltage drives. The most
popular topologies of multilevel converters are the
neutral point-clamped inverter (NPC), the flying capacitor
inverter (FC) , and the cascaded H-bridge (CHB)
inverter[1]. Each one of these inverters has its own merits and
demerits. In the NPC inverter, multiple dc sources are
generated by splitting a single-dc bus voltage using capacitor
banks. This configuration has large number of clamping
diodes and presents the problem of dc bus capacitor
unbalance especially with high number of voltage levels.
An interesting work for balancing capacitor in NPC
inverter that can be operated in limited modulation range
has been presented in . A pulse-width modulation (PWM)
control scheme to balance the dc link capacitor voltages of
the NPC inverter, connected in cascade with a two level
inverter to realize a five level inverter structure for an openend winding induction motor, is proposed. The concept of FC
inverter
was
introduced
first
in
1992[1].
In this configuration, multiple capacitors of different
voltage magnitudes are used to generate multiple voltage
levels.The advantages include modularity, lack of clamping
diodes, lack of problems like unbalance in the split dc -link
capacitors, etc. Also, as in the NPC case, single supply can
be used to generate multiple pole voltage levels. Many
strategies for balancing the capacitor voltages have evolved
over time. However, generating more voltage levels in a FC
inverter requires larger number of capacitors. Interesting
derivatives of this configuration have been presented and
where more levels have been achieved by cross connecting
the capacitors using additional switches. Operation of FC
inverter with improved reliability has been presented , where
additional circuitry is provided to bypass the faulty cell.
However, in this scheme, the devices have to be sufficiently
overrated to operate at full power level when the faulty cell is
bypassed. The operation of FC inverter with asymmetrical
capacitor voltages to generate more voltage levels has been
presented[1].
The multilevel CHB inverter with isolated supplies
presented in has many advantages compared to the NPC and
FC topologolies. The CHB configuration does not require
clamping diodes and the input power is distributed among
different input sources that makes it more suitable for
certain applications. One additional advantage of the CHB
converter is that if any device fails in the H-bridges, the
inverter can still be operated at reduced power level and,
hence, this configuration is fault tolerant to some extent.
The concept of using CHBs with capacitors and their
voltage balancing has been introduced . The advantages
include more redundant states, better voltage balancing, lack
of diodes, and fault tolerant operational ability by bypassing
the faulty H-bridge cells. This configuration is especially
suitable for applications like STATCOM. DC-voltage ratio
control strategy for a CHB converter fed with a single-dc
source is presented. With this control strategy, a higher
number of levels in output voltage waveform can be
achieved
with
capacitor
voltage
balancing
in
a limited range of load power factor. This scheme is very
much suitable for grid-connected applications. A multilevel
configuration with improved reliability has been
presented[1].
Many other multilevel inverter configurations have
been developed based on the three conventional (NPC, FC,
and CHB) topologies. A configuration in which two-level
inverter is cascaded with multiple H-bridges has been
presented , where more voltage levels can be generated.
New multilevel inverter configurations for open-end
winding induction motor formed by cascading two-level
inverters and capacitor-fed H-bridges. Five-level active
neutral point clamped (ANPC) inverter topology is
another configuration{1]-[9].
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542
T. Govindaraj et al. / IJAIR
ISSN: 2278-7844
Fig. 1. Proposed single-phase power circuit formed by connection of a single-phase flying capacitor inverter with H-brige in series
This five-level ANPC converter is being commercialized
by ABB as the ACS2000 (up to 1.6 MW). Derivatives of
CHB where different devices [Integrated GateCommutated Thyristor (IGCT) and insulated gate bipolar
transistor (IGBT)] are used in such a way that the IGCT
would switch at fundamental frequency and IGBT would
switch at carrier frequency. The concept of a hybrid
cascade converter topology with series-connected
symmetrical and asymmetrical diode-clamped H-bridge
cells has been presented in [3]. The hybrid clamped
multilevel inverter topology is a hybrid of NPC topology
and FC topology, which does not have neutral point
fluctuation.
The multilevel inverter proposed in this paper is a
cascaded topology consisting of three-level FC inverters
and capacitor-fed H-bridges, in which balancing of the
capacitor voltages are possible independently of the load
power factor.
II. PROPOSED POWER CIRCUIT
As shown in Fig. 1, the proposed topology has a threelevel FC inverter with dc bus voltage of VDC and FC voltage
equal to VDC /2, which can generate voltages of 0, VDC /2, and
VDC with respect to point 0. A capacitor-fed H-bridge is
cascaded to each phase of the inverter. The voltage across the
H-bridge capacitor has to be maintained at VDC /4. This
combination can produce voltage levels of 0, VDC /4, VDC /2,
3VDC /4, VDC ,−VDC/4, and 5VDC /4. Out of these, the
voltages −VDC /4 and 5VDC/4 are not used in the proposed
inverter as they do not have redundant switching states to
balance the capacitor voltages. The switching states of the
useful voltage levels and their effects on the capacitor
voltages based on the current direction are given in Table I.
The capacitor voltages remain unaffected while
producing the voltages VDC and 0. The capacitors can
either be charged or discharged in any direction of the
current for the voltages VDC /4, VDC /2, and 3VDC /4 as
shown in Figs. 2-4, respectively. In each phase, the switches
AS1, AS2, AS3, AS4 and AS1′ , AS2′ , AS3′ , AS4′are
operated in complementary manner. The output voltage is
based on the switching states that decide the path of the
current flow.
For voltage levels of VDC /4 and 3VDC /4, there are three
redundant states. By switching between these three states the
capacitors C1 and C2 can be charged or discharged for any
direction of the current. The voltage level of VDC /2 has two
redundant states. By switching between them, C1 can be
charged or discharged based on the current direction. When
VDC/2 is applied, the C2 is not affected. As the capacitors
can be either charged or discharged by switching between the
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T. Govindaraj et al. / IJAIR
redundant states, based on the current direction, quick
capacitor voltage balancing is possible, irrespective of the
load power factor. To maintain the capacitor voltages at a
fixed value, the capacitor voltages are sampled at
regular intervals and a hysteresis controller is used to
switch between the redundant states based on the current
direction to balance the capacitor voltages.
The pole can generate one of the five voltage levels 0,VDC /4,
VDC /2, 3VDC /4, and VDC. The effective voltage space
vector formed based on the single-phase pole voltages is
given by
(1)
Where VSV is the voltage space vector and VAO are the pole
voltage in the single phase A respectively.A PWM generation
based on the combination of the seven resulting switching
vectors (0, A, B, C, A’, B’, C’) is called Space Vector
Modulation. The amplitude and the orientation of the
desired field are the inputs for the PWM generation. The
inner circle in the hexagon limits the maximum amplitude
for a field with few harmonics. The area between the inner
circle and the hexagon is called “over modulation area” and
adds harmonics in Fig. 2.
ISSN: 2278-7844
single phase induction motor.first comparative analysis of
Space Vector PWM with conventional SPWM for a five
level Inverter is carried out.
The Simulation study reveals that SVPWM gives
15% enhanced fundamental output with better quality i.e.
lesser THD compared to SPWM. PWM strategies viz.
SPWM
and
SVPWM
are
implemented
in
MATLAB/SIMULINK software and its performance is
compared with conventional PWM techniques. Owing to
their fixed carrier frequencies fc in conventional PWM
strategies, there are cluster harmonics around the multiples
of carrier frequency. PWM strategies viz. Sinusoidal PWM
and SVPWM utilize a changing carrier frequency to spread
the harmonics continuously to a wideband area so that the
peak harmonics are reduced greatly[7].
TABLE I
VARIOUS VOLTAGE LEVELS AND CAPACITOR STATES BASED ON THE
SWITCHING STATES
Fig. 2. Model space vector diagram
Space vector Modulation Technique has become the most
popular and important PWM technique for Three Phase
Voltage Source Inverters for the control of AC Induction,
Brushless DC, Switched Reluctance and Permanent
Magnet Synchronous Motors. But in this paper, we use
© 2012 IJAIR. ALL RIGHTS RESERVED
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T. Govindaraj et al. / IJAIR
Fig. 3. Switch transitions and current path for the redundant states of
VDC /4 for a phase. (a) Current path for switch state of (0,0,0,1), (b) Current
path for switch state of (0,1,1,0). (c) Current path for switch state of
(1,0,1,0)
ISSN: 2278-7844
Fig.5. Switch transitions and current path for the redundant states of
3VD C /4 for a phase. (a) Current path for switch state of (1,1,1,0). (b)
Current path for switch state of (0,1,0,1). (c) Current path for switch state
of (1,0,0,1).
III. SALIENT FEATURES
Fig.4. Switch transitions and current path for the redundant states of
VD C /2 for a phase. (a) Current path for switch state of (1,0,0,0). (b)
Current path for switch state of (0,1,0,0).
The proposed single-phase topology uses 4 switches of
voltage rating VDC /2 and 4 switches of voltage rating VDC /4
(total 8 switches), where VDC is the dc bus voltage. It has
two capacitors per phase, one is rated at VDC/2 and the other
is rated at VDC /4. So in total, the proposed single-phase
configuration requires only two capacitors, while the
conventional three-phase topology uses 12 switches of
voltage rating VDC /2 and 12 switches of voltage rating VDC /4
(total 24 switches), where VDC is the dc bus voltage. It has
two capacitors per phase, one is rated at VDC /2 and the
other is rated at VDC/4.while the conventional five-level FC
inverter requires nine capacitors. The asymmetrical FC configuration requires 12 switches of rating VDC /4,
six switches of rating VDC /2, three capacitors of rating
VDC/4, and three capacitors of rating VDC /2 for a threephase inverter. However, this configuration has limited range
of power factor for five-level operation. The conventional
five-level CHB configuration uses six isolated power
supplies of voltage rating VDC/4 and 24 switches of voltage
rating VDC/4.How ever, the proposed configuration uses just
one dc source of magnitude VDC. The five-level NPC
inverter requires four capacitors of rating VDC /4,
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545
T. Govindaraj et al. / IJAIR
36 clamping diodes of voltage rating VDC /4 and 24 switches
of rating VDC /4. However, the proposed topology does not
require any clamping diode[1].
The five-level ANPC topology requires three capacitors
of voltage rating VDC /4 for three phases and two capacitors
of voltage rating VDC /2. However, this configuration has
neutral point fluctuation. The proposed configuration does not
have any such problem as it has FC front end. The hybrid
clamped multilevel topology requires more number of
switches and clamping diodes as compared to the proposed
configuration. Another important advantage of the proposed
scheme is that if one of the devices in the H bridge fails, the
H-bridge can be bypassed through a fast bypass switch or by
routing
the
current
through
the
devices
in
the complementary path and the inverter can work in threelevel mode at the full power rating. For example, if S3 or S4
fails then the current can be routed through S3′ and S4′ by
switching them ON and removing the gating signals to S3 and
S4 or vice versa.
IV.SIMULATION DIAGRAM AND RESULTS
ISSN: 2278-7844
The proposed five-level inverter circuit has been tested on a
230V, 50Hz , induction motor drive with V/f control scheme
at a switching frequency of 1 kHz. This simulation diagram
are drawn in MATLAB Software package. In this diagram,
IGBT Switches are connected in structure of Flying capacitor
cascaded with H-bridge. SVPWM technique are used in this
project for controlling the inverter by giving gate pulse to
IGBT Switches. The inverter dc-link voltage is set to 230 V.
The hysteresis limit for the capacitor is set at 5% of the
respective capacitor voltage. The capacitors are sized suitably
so that the voltage of the capacitors would not cross the
hysteresis limits in two switching cycles at full load current.
The capacitance C is determined by
(2)
Where ∆VC is the capacitor voltage ripple, TS is the
sampling time, and iL is the peak load current. The capacitor
voltages are sampled every switching cycle (1ms in this case).
A capacitance value of 4400 µF has been used for this single
phase. The motor is run at various modulation indexes
(VSV/VDC) of 0.2,0.4,0.6,0.8 at frequencies of 10,20,30,40Hz,
respectively, at no load.
Fig.6. Simulation diagram for hybrid five-level inverter topology
with single DC Supply fed Single phase induction motor
© 2012 IJAIR. ALL RIGHTS RESERVED
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T. Govindaraj et al. / IJAIR
ISSN: 2278-7844
In this project, modulation index is 0.8 is used in pulse
generator. In SVPWM, we use the sine wave as a reference
input and triangle wave also used for time delay to upper
leg three switches. The negative value gain is given to the
lower leg switches. The gate pulses are given to inverter
through the subsystem. From subsystem the pulses are
given to Goto and then Goto are linked with From blocks
then pulses given to switches. Then output current and
output voltage is determined from the simulation results.
The single phase induction motor is connected in this
circuit. The rotor speed and electromagnetic torque
determined from this simulation. The THD analysis of
output current and output voltage are determined by the
simulation. The main advantages of this project is
harmonics reduction. The THD percentage of output
current is 7.80% and THD percentage of the output
voltage is 23.41%. When compare to other topology it has
better harmonic reduction properties.
Fig.7. (c)
Fig.7. (d)
Fig.7. (a)
Fig.7. (b)
Fig.7.Simulation results for (a) Output current, (b) Output voltage
Vao, (c) Rotor speed, (d) Electromagnetic torque Te
Fig.8 (a)
© 2012 IJAIR. ALL RIGHTS RESERVED
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T. Govindaraj et al. / IJAIR
ISSN: 2278-7844
[5]
[6]
[7]
[8]
[9 ]
Fig.8 (b)
Fig.8. Simulation diagram for THD analysis of (a) Output current
(b) Output voltage of this project
V. CONCLUSION
In this paper, a new single-phase five-level inverter topology
with a single-dc source has been proposed. This configuration
is formed by cascading a three-level FC inverter and
capacitor-fed H-bridges. The key advantages of this
topology compared to the conventional topologies include
reduced number of devices and simple control. An important
feature of this inverter is the ability to balance the
capacitor voltages irrespective of load power factor.
Another advantage of this inverter is that if one of the Hbridge fails, it can operate as a three-level inverter at full
power rating by bypassing the H-bridge. This feature of the
inverter improves the reliability of the system.The proposed
configuration
has
been
analyzed
and
experimentally verified for various modulation indexes and
frequencies by running a single phase squirrel cage
induction motor in V/f control mode, at no load. The
working of the capacitor balancing algorithm has been
tested. The stable operation of the inverter for various
modulation indexes and stability of the inverter voltage
levels during rapid acceleration have been validated
experimentally.
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[1]
[2]
[3]
[4]
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P. P. Rajeevan, K. Sivakumar, C. Patel, R. Ramchand, and K. Gopakumar,“A
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Pablo Lezana, Member, IEEE, José Rodríguez, Senior Member, IEEE,
and Diego A. Oyarzún,”
Cascaded Multilevel Inverter With
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K. Vinoth Kumar, Prawin Angel Michael, Joseph P. John and Dr. S.
Suresh Kumar,” Simulation and comparison of spwm and svpwm control
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Dr.Govindaraj Thangavel born in Tiruppur , India ,
in 1964. He received the B.E. degree from
Coimbatore Institute of Technology, M.E. degree
from PSG College of Technology and Ph.D. from
Jadavpur University, Kolkatta,India in 1987, 1993
and 2010 respectively. His Biography is included
in Who's Who in Science and Engineering 20112012 (11th Edition). Scientific Award of
Excellence 2011 from American Biographical
Institute (ABI). Outstanding Scientist of the 21st century by
International Biographical centre of Cambridge, England
2011.
Since July 2009 he has been Professor and Head of the Department of
Electrical and Electronics Engineering, Muthayammal Engineering
College affiliated to Anna University, Chennai, India. His Current
research interests includes Permanent magnet machines, Axial flux Linear
oscillating
Motor,
Advanced
Embedded
power
electronics
controllers,finite element analysis of special electrical machines,Power
system Engineering and Intelligent controllers.He is a Fellow of
Institution of Engineers India(FIE) and Chartered Engineer (India).Senior
Member of International Association of Computer Science and
Information. Technology (IACSIT). Member of International Association
of Engineers(IAENG), Life Member of Indian Society for Technical
Education(MISTE). Ph.D. Recognized Research Supervisor for Anna
University,Satyabama University Chennai and CMJ University
Meghalaya. Editorial Board Member for journals like International
Journal of Computer and Electrical Engineering,International Journal of
Engineering and Technology,International Journal of Engineering and
Advanced Technology (IJEAT).International Journal Peer Reviewer for
Taylor & Francis International Journal “Electrical Power Components &
System” United Kingdom,Journal of Electrical and Electronics
Engineering Research,Journal of Engineering and Technology Research
(JETR),International Journal of the Physical Sciences,Association for the
Advancement of Modelling and Simulation Techniques in
Enterprises,International Journal of Engineering & Computer Science
(IJECS),Scientific Research and Essays,Journal of Engineering and
Computer Innovation,E3 Journal of Energy Oil and Gas Research,World
Academy of Science, Engineering and Technology,Journal of Electrical
and
Control
Engineering（JECE),Applied
Computational
Electromagnetics Society etc.. He has published Seventy Six research
papers in International/National Conferences and Journals. Organized 20
National / International Conferences/Seminars. Received Best paper
award for ICEESPEEE 09 conference paper. Coordinator for AICTE
Sponsored SDP on Soft Computing Techniques In Advanced Special
Electric Drives,2011.Coordinator for AICTE Sponsored National Seminar
on Computational Intelligence Techniques in Green Energy, 2011.Chief
Coordinator and Investigator for AICTE sponsored MODROBS Modernization of Electrical Machines Laboratory.
© 2012 IJAIR. ALL RIGHTS RESERVED
548