RFG40N10, RFP40N10, RF1S40N10,
RF1S40N10SM
Data Sheet
40A, 100V, 0.040 Ohm, N-Channel Power
MOSFETs
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, relay drivers and emitter switches for bipolar
transistors. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA9846
January 2002
Features
• 40A, 100V
• rDS(ON) = 0.040Ω
• UIS Rating Curve
• SOA is Power Dissipation Limited
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Ordering Information
PART NUMBER
D
PACKAGE
BRAND
RFG40N10
TO-247
RFG40N10
RFP40N10
TO-220AB
RFP40N10
RF1S40N10
TO-262AA
F1S40N10
RF1S40N10SM
TO-263AB
F1S40N10
G
S
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10SM9A.
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
JEDEC TO-263AB
GATE
JEDEC TO-262AA
DRAIN
(FLANGE)
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
SOURCE
©2002 Fairchild Semiconductor Corporation
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM Rev. C
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 1MΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFG40N10, RFP40N10,
RF1S40N10, RF1S40N10SM
100
100
±20
UNITS
V
V
V
40
100
Figures 4, 12, 13
160
1.07
-55 to 175
A
A
W
W/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. TJ = 25oC to 150oC.
2. Repetitive Rating: pulse width limited by maximum junction temperature.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
-
-
V
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 9)
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 8)
2
-
4
V
TC = 25oC
TC = 150oC
-
-
1
µA
-
-
50
µA
VGS = ±20V
-
-
±100
nA
ID = 40A, VGS = 10V (Figure 7)
-
-
0.040
Ω
VDD = 50V, ID = 20A,
RL = 2.5Ω, VGS = 10V, RGS = 4.2 Ω
(Figure 11)
-
-
80
ns
-
17
-
ns
tr
-
30
-
ns
td(OFF)
-
42
-
ns
tf
-
20
-
ns
tOFF
-
-
100
ns
-
-
300
nC
-
-
150
nC
-
-
7.5
nC
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
Drain to Source On Resistance
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
VDS = 80V,
VGS = 0V
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to Ambient
RθJA
VDD = 80V,
ID = 40A,
RL = 2.0Ω
(Figures 11)
-
-
0.94
oC/W
TO-247
-
-
30
oC/W
TO-220AB and TO-263AB
-
-
62
oC/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
©2002 Fairchild Semiconductor Corporation
SYMBOL
VSD
trr
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = 40A
-
-
1.5
V
ISD = 40A, dISD/dt = 100A/µs
-
-
200
ns
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM Rev. C
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM
Unless Otherwise Specified
1.2
40
1.0
32
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
0.2
16
8
0
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
150
1
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
0.1
1
100
125
150
175
100
DC OPERATION
10
75
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
TC = 25oC
SINGLE PULSE
TJ = MAX RATED
VDSS(MAX) = 100V
50
TC, CASE TEMPERATURE (oC)
IAS, AVALANCHE CURRENT (A)
100
25
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
ID , DRAIN CURRENT (A)
24
10
ST
AR
TIN
ST
AR
TIN
C
J =
15 o
0
C
10
If R = 0
tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)LN[(IAS*R)/(1.3 RATED BVDSS - VDD) + 1]
0.1
1
tAV, TIME IN AVALANCHE (ms)
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
J =
25 o
GT
1
0.01
100
GT
10
NOTE: Refer to application notes AN9321 and AN9322.
FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
100
GS
VG
S
=
VGS = 6V
60
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
80
V
ID , DRAIN CURRENT (A)
80
7V
ID, DRAIN CURRENT (A)
=1
0V
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
40
VGS = 5V
20
-55oC
25oC
175oC
60
40
20
VGS = 4V
0
0
0
2
4
6
8
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. SATURATION CHARACTERISTICS
©2002 Fairchild Semiconductor Corporation
10
0
2
4
6
8
10
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 6. TRANSFER CHARACTERISTICS
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM Rev. C
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM
Typical Performance Curves
1.50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 40A
2.0
VGS = VDS
ID = 250µA
1.25
NORMALIZED GATE
THRESHOLD VOLTAGE
1.5
1.0
0.5
1.00
0.75
0.50
0.25
0
-50
0
50
100
150
0
-50
200
TJ, JUNCTION TEMPERATURE (oC)
50
100
150
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2.0
6000
ID = 250µA
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
5000
1.5
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
0
1.0
0.5
4000
CISS
3000
2000
COSS
1000
CRSS
0
0
-50
0
50
100
150
0
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
15
20
25
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
5
VDS , DRAIN TO SOURCE VOLTAGE (V)
VDD = BVDSS
VDD = BVDSS
75
7.5
5.0
50
0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
0.25 BVDSS 0.25 BVDSS
25
2.5
RL = 2.5Ω
Ig(REF) = 2.25mA
VGS = 10V
VGS, GATE TO SOURCE VOLTAGE (V)
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.5
Unless Otherwise Specified (Continued)
0
0
20
Ig(REF)
Ig(ACT)
t, TIME (µs)
80
Ig(REF)
Ig(ACT)
NOTE: Refer to Application Notes AN7254 and AN7260.
FIGURE 11. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
©2002 Fairchild Semiconductor Corporation
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM Rev. C
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 13. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
-
VDD
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
50%
50%
PULSE WIDTH
10%
FIGURE 14. SWITCHING TIME TEST CIRCUIT
FIGURE 15. RESISTIVE SWITCHING WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
DUT
Ig(REF)
VGS = 10V
VGS
-
VGS = 2V
0
Qg(TH)
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
FIGURE 17. GATE CHARGE WAVEFORMS
RFG40N10, RFP40N10, RF1S40N10, RF1S40N10SM Rev. C
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with instructions for use provided in the labeling, can be
effectiveness.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4