PH-315
A. La Rosa
TRANSISTORS
I. PURPOSE
To familiarize with the working principle and characteristics of transistors, including how to
properly implement their DC bias. The bipolar junction transistor as well as the field effect
transistor will be considered.
II. THEORETICAL CONSIDERATIONS
II.1 The pn junction
II.1.1 Formation of the depletion layer
II.1.2 The Fermi Level
II.2 Bipolar Junction Transistor
II.3 Field Effect Transistor (FET)
II.3.1 Junction Field Effect Transistor (JFET)
II.3.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
II.3.2A Metal oxide semiconductor (MOS) capacitor
II.3.2B MOSFET
III. EXPERIMENTAL CONSIDERATIONS
III.1 The Bipolar Junction Transistor
III.1.1 Transistor’s characteristic curves. Current gain and the  value
III.1.2 DC bias circuit and the operating point
III.1.3 Small signal amplifier (this section is not required in Winter 2015)
III.2 The Field Effect Transistor
III.2.1 The Junction Field Effect Transistor (JFET)
III.2.2 The Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
II.1 The pn junction
II.1.1 Formation of the depletion layer
Characteristics of p and n semiconductor materials
p-material
p
n-material
n
Electron
energies
Free
electrons
-
e
+
Acceptor’s
energy levels
“Holes”
acceptors atoms
+ + +
+
donor atoms
e-
donor’s
energy levels
+ + + + + +
x
Electrically neutral
material
Electrically neutral
material
Fig. 1 In the p-material (n-material) the energy level of impurities, indicated by pink (green
segments) are located near the valence (conduction) band. Left: Electrons from the
valence band ‘jump’ to the acceptor impurities, thus creating a negatively charged
impurity and leaving behind a free “hole”. The hole is equivalent to a “free” positive
charge. Right: Electrons from the donor impurities ‘jump’ to the conduction band where
they are free to move, and leaving behind a positively charged donor impurity.
2
The p and n materials are brought together
p-material
p
n-material
n
Electron
energies
NA acceptors /cm3
+
+ + + +
ND donors/cm3
+ + + + + +
x
Charged
region
Electrically
neutral
material
Case:
NA > ND
Electrically
neutral
material
Built-in
electric field
i = i (x)
p
-
-
+
+
+
+
+
+
+
+
+
+
+
+
W
Depletion region
n
Cross section
area A
Practically no free
carriers in this region
Fig. 2 Upon forming a pn junction, free electrons from the n region diffuse
into the p region, leaving behind a positively charged region. Similar
situation occurs with the holes. This result into the formation of a charged
depletion region formed at the pn junction. Notice the depletion region
penetrates more in the lighter doped material.
3
Q=AxnoND
qND
-xpo
+
xno
-
Q=-AxpoNA
qNA
W
Fig. 3 An approximate mode assumes uniform charge distribution
of charges in each section of the depletion layer.
 Electric field
W
-xp0
d 1
 (qN A )
dx ε
xn0
+
d 1
 (qN D )
dx ε
o
Fig. 4 Electric field built in inside the depletion layer, corresponding to
the charge distribution assumed in Fig. 3.
Voltage across the depletion layer
Vo  
x no
  ( x)dx
 x po
Vo 
1 q N AND
W2
2 ε N A  ND
Notice, the higher the potential difference across the depletion layer, the wider the thickness
of the layer.
4
W
n
p
i
Energy of e-
Electrostatic
potential
e Vo
Vo

i
p
EF
Fermi level EF

x
n
p
n
x
Fig. 5 Left: The charges inside the depletion layer establish an electric potential Vo
across the layer. Right: The presence of the electric potential change across the pn
junction is reflected in a bending of the conduction and valence band energy levels.
II.1.2 The Fermi Level
The Fermi level EF coincides here with the chemical potential of the system. At equilibrium
the chemical potential is the same throughout the heterogeneous sample (as indicated in Fig.
5). The value of EF depends on the temperature, and the particular energy levels distribution in
the semiconductor system).
The Fermi level also gives an indication of the concentration of free-electrons in the conduction
band, as well as the population of free-holes in the valence band. The closer the Fermi level is
to a given band determines the type of majority charges in the material. Thus, for example in
Fig. 5, in a n-region the majority of carrier is composed by electrons; this is in agreement with
the Fermi level being closer to the conduction band. On the other hand, in the p-region the
majority of charge-carriers are holes; hence, the Fermi level is located near the valence band.
The Fermi Level in intrinsic semiconductor material
When the semiconductor does not contain impurities (i.e. no donor nor acceptor atoms), the
material is called intrinsic.
For intrinsic semiconductor material
electron concentration
in the conduction band.
concentration of holes
= in the valence band.
ne (electrons/cm )
nh (holes/cm )
3
3
5
(1)
-
e
Eg
Fig. 6 Thermal generation of electron-hole pair carriers. Electrons
are able to jump from the valence to the conduction band, leaving
behind a free-hole.
The population of energy states by electrons follows quantum statistics (instead of the
Boltzmann statistics). Electrons behave in the peculiar way that each allowed quantum state is
occupied by only one electron. The probability that an energy state is occupied by an electron is
given by the Fermi-Dirac distribution,
f (E ) 
1
1  e(E  EF ) / kBT
Fermi-Dirac distribution
(2)
probability to find an electron in a level of energy E.
where we are using the EF (the Fermi level) indistinctly from the thermodynamic chemical
potential of the (homogeneous or heterogeneous) semiconductor material. As mentioned
above, EF depends on the temperature, and on whether the material is doped with impurities
or not.
Notice: 1- f(E) is the probability that the level of energy E is empty.
In other words,
1- f(E) is the probability to find a hole at the energy level E.
6
(3)
T≠0
f (E)
Probability to find
a hole E=EV
1
Probability to
find an electron
at E=EC
1/2
Ei
EV
EF
Energy E
EC
Eg
Carrier
concentration
ne
nh
ne =nh ≡ni
EF
E
Fig. 7 For an intrinsic material, the Fermi level EF is located very close to
the middle of the band-gap. This level is also denoted by Ei.
At a given finite temperature T≠0, the intrinsic carrier population is given by,
ni

N C NV
e
( E EF ) / kBT
(This is a fixed number for a
given finite temperature)
(4)
where NC and NV are quantities that depend on the temperature and on the specific
characteristics of the material.
7
The Fermi Level in extrinsic semiconductor material
f (E)
Probability to find
a hole E=EV
1
Intrinsic
case
Probability to find an
electron at E=EC
1/2
Ei
EV
Donor
impurities
Energy E
EF EC
Eg
Carrier
concentration
ne ≠nh
ne
nh
Ei E F
E
Fig. 8 The Fermi level in extrinsic material illustrated for the case of a
semiconductor doped with donor atoms.
In the extrinsic case, ne (electrons/cm3) ≠ nh (holes/cm3)
There is a useful expression that gives the carriers population of the extrinsic case, in terms of
the intrinsic population ni given in (4),
ne  ni e
( EF E i ) / kBT
nh  ni e
(5)
( Ei  EF ) / kBT
This expressions are very useful in the analysis of devices. The location of the Fermi level EF
relative to the Fermi level Ei corresponding to the intrinsic case determines the population of
free-electrons and free-holes in the conduction and valence bands, respectively.
8
Forward and Reverse Bias Voltage
Case: Vext=0
NA > ND
i = i (x)
-
p
-
+
+
+
+
+
+
+
+
Built-in
electric field
+
+
+
+
Cross section
area A
n
W
Depletion region
Practically no free
carriers in this region
ext
Case: Vext>0
NA > ND
i = i (x)
-
p
+
+
+
+
+
+
+
+
Cross section
area A
n
W
Depletion region
W decreases
ext
Case: Vext<0
NA > ND
i = i (x)
p
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
Cross section
area A
n
W
Depletion region
W increases
9
Forward
bias
Vpn
e- energy
ext
e
p
I
-
p
n
I  I o (e
eVBE / kT
 1)
n
Vpn
Vth
x
II.2 Bipolar Junction Transistor
Transistor modeled as a current amplifier
Transistor is a 3-terminal device: emitter, base, collector. They are available in two flavors: npn
and pnp.
collector
base
collector
base
emitter
emitter
npn
pnp
V2 > V1
Diode model: An initial understanding of the transistor can be obtained considering the baseemitter and the base-collector as diodes.
|V2| > |V1|
n
|V1|
- |V2|
|V2|
B
p
p C
C
0 Volts
n
B
n
p
E
E
+V1
0 Volts
In that context, let’s analyze in more detail the npn transistor.

Consider first the emitter-base diode.
10
e- energy
ext
e
I
-
I  I o (e
eVBE / kT
C
 1)
B p
p
B
n
p
n
E
B
E
e-
n
E
Vth
VBE
x
a)
b)
c)
Fig. 6 Analysis of the base-emitter pn junction. a) The figure on the left shows the energy band
diagram of the (base-emitter) pn junction under equilibrium conditions (no external voltage
applied); a barrier exist for the electrons (solid circles in the figure) to cross from the n-region to the
p-region. The red line is the Fermi level. The figure on the right shows that under an external
forward bias (voltage at p greater than the voltage at n), the barrier is lowered and a forward bias
flow of electrons is established. b) The forward bias current depends critically on the base-emitter
voltage. The current is significant when the VBE voltage is greater than a threshold voltage (~ 0.7 volt
for the case of silicon). c) When the p-base is lightly doped the net bias current is mainly constituted
by electrons from the n-doped emitter.
The p region is made lightly doped, thus the forward current is constituted mainly by electrons
from the n-doped emitter.
The few electrons arriving to the p-type base-region implicitly become minority carriers in the
host region of majority holes population. Subsequently they move by diffusion. If the base
region is made very thin (smaller than the diffusion length), then those minority carriers reach
also the collector where they are swept by the reversed biased that exists at the base-collector
boundary.
The finite time taken by the minority carriers to cross the base-region limits the high-frequency
response of the transistor. Hence, the p region (base) is made narrow (~ 0.5 m) compared to
the diffusion length. That way, out of a number of arriving to the base, only a few are lost by
recombination with the host holes at the base and most diffuse to the depletion region of the
base- collector junction (see Fig. 3).
 The base-collector diode.
Since |V2 | > |V1 |, the latter being of the order of 0.7 V, this diode is reversed biased. Thus,
the role of the VBC voltage is just to sweep the charges that, after arriving from the emitter to
the base, diffuse to the collector.
For this reason, it is found that the collector current varies very little with the collector voltage.
11
|V2|
|V2| >|V1|
e
n
-
|V2|
C
IC
B
|V1|
e
-
|V1|
p
e-
n
C
B
IB p
n
IE
E
n
E
Fig. 7 Transistor currents Left: Injection of majority carriers from the
emitter. A relatively small numbers reaches the base but most are swept
towards the collector. Right: Equivalent picture of the left diagram, but in
terms of the more formal currents.
n
|V2|
IC
n
B
C
IE
e-
IB
e-
p
n
n
p
IC
npn
E
IC
n
e-
n
IE
RL
E
WB
B
VBC
C
A
Fig. 8 Transistor circuit configuration with the npn and depletion layer regions. The
injection of electron from the emitter to the base is controlled by the VEB voltage. By
making the width of the base WB very thin (smaller than the diffusion length), the
electrons diffuse towards the BC junction. In the BC depletion region the electron are
swept by the reversed bias. Notice, the collector current will be practically independent
of the particular value of the sweeping VBC voltage, since any value of the reverse
voltage would be enough to sweep the electrons (that is, the collector current will
change little when changing the load resistor RL).
When the transistor is properly electrically biased, the net result is:
IC is roughly proportional to IB
IC = hFE IB = IB
(1)
The current gain hFE (also called beta) is typically about 100.
( is not a good transistor parameter; its value can vary from 50 to 250. It also depends on
the collector current, collector-to-emitter voltage, and temperature.)
This represents the usefulness of the transistor. A small current into the base controls a much
larger current flowing into the collector. That is, the transistor is a current amplifier.
II.3 Field Effect Transistor ( FET )
12
A field effect transistor is a three-terminal device in which the current through two
terminals is controlled at the third (similar to the bipolar junction transistor.)
Field effect devices are controlled by a voltage at the third gate terminal (rather than by a
current like in the BJT.) The FET nonexistent gate current is its most important characteristics.
The resulting high input impedance (which can be greater than 1014  is essential in many
applications.
FET is a unipolar device; that is, the current involves only majority carriers.
The field effect transistors come in different forms:

Junction FET (JFET) based on controlling the depletion width of reversed-biased p-n
junctions.

Metal-semiconductor FET (MESFET) results when the p-n junction is replaced by a
Schottky barrier (i.e. a metal-semiconductor junction.)

When the metal is separated from the semiconductor by an insulator, a MISFET results.
When an oxide layer is used as the insulator the device is called a MOSFET.
The various types of FET are characterized by high input impedance, since the control voltage is
applied to a reversed-biased junction, or Schottky barrier, or across an insulator.
FETs are well suited for controlling the switch between a conducting state and a nonconducting
state. That is, they fit very well in digital circuits. In fact MOS transistors are used in
semiconductor memory devices. MOSFETs dominate microprocessors, memory and most highperformance digital logic.
Similarities between BJTs and FETs
Both are charge-control devices
Both have 3 terminals, the conduction between two electrodes depend on the availability of
charge carriers, the latter controlled by a voltage applied to a third control electrode.
Difference between BJTs and FETs
The BJT is basically a current amplifier. [For a npn transistor, connecting the emitter-base in ~
0.7 V forward bias overcomes its contact potential barrier causing electrons to enter the baseregion. Most of these electrons (minority carriers in a p-type host base) are swept by the field
of the reversed biased base-collector. Since after the 0.7 V the flow of electrons to the base
grows exponentially for small base-emitter voltage variations, we end up with a device in
which the collector current is controlled by small base current.]
In a FET, conduction in a channel is controlled by an electric filed, produced by a voltage
applied to the gate electrode.
In an FET there are not forward biased junctions, so the gate draws no current. A consequence
of this is its high input impedance (greater than 1014 ). For applications as analog switches
and highinput impedance, FETs have no equals.
II.3.1 Junction Field Effect Transistor (JFET)
13
A n-channel JFET has three terminals: gain (G), drain (D) and source (S).
The input signal is the voltage applied between the gate and source.
The output signal is the current from drain to source (e- flow from source to drain.)
D
Drain
VD
Depletion
region
+
Drain
G
p
p
n
Gate
G
Gate
-
VG
e-
p
n
Channel
S
Source
p
VG
-
Input
voltage
Gate
Source
S
Fig. 9 n-channel JFET. Left: Terminals in a FET. Center: For proper operation the (gatechannel) pn junction must be reversed biased, so that a depletion region is formed as
shown. The drain is operated at a positive voltage relative to the source, hence the gatedrain end is more strongly reversed biased (thicker depletion layer and thinner channel)
than the gate-source end (thinner depletion layer and thicker channel.) The depletion
region acts as a non-conductor; the remainder of the channel acts as a resistor with
peculiar properties. Right: Symbol of the n-channel JFET. The arrow in the JFET symbol is to
identify the source (S) (because, otherwise, the source and the drain are architecturally
symmetric).
Input characteristics.
Because the gate-channel pn junction is reversed biased, very little current flows into the gate.
Consequently, the input impedance of the device is extremely high, up to 1012, and very little
energy is required to control de device.
The gate controls the current in the channel through an electric field that affects the
depletion region.
Output characteristics.
Let’s analyze the circuit for a given fixed value of the input voltage VGS (gate-source
voltage.)
 Let choose VGS = 0 V:
For small increasing values of the drain-source voltage VDS the current also increases,
similar to the case of a simple resistor (ohmic region.)
As VDS increases further, the current begins to level off because the channel narrows at
the drain end (see Fig.3.) When the drain-source voltage reaches the value VDS = -VP (VP is
14
called the pinchoff voltage) a region of the conducting channel reaches a minimum size
at the drain end.
The current remains constant upon further increases of the VDS. This is the saturation
region. (The electrons in the channel are free to move out of the channel and then
through the depletion region attracted by the VDS voltage. The depletion region is free of
carriers and has a resistance similar to silicon. However, an increase of VDS (which would
tend to increase the channel current) will also increase the distance from drain to the
pinch-off point thus increasing the channel resistance. As a result, these two trends
compensate as to keep the channel current constant.) 1
In the saturation region (although it would be better to call it the “active region”) the drain
current is controlled totally by the input signal.
ID
2k
iG ≈ 0 G
VGS
iD
D
4 mA
Ohmic region
Saturation
region
VGS = 0V
3 mA
+10V
S
2 mA
VGS = - 1V
1 mA
VGS = - 1.5V
0
1
2
3
VDS , drain-source voltage
VGS
(V)
VGS = VP = – 2V
Fig. 10 Output characteristics of a JFET. A pinch-off voltage equal to -2 volts has been
assumed; the particular JFET you are using may have a different pinch-off voltage. For
lower (negative) values of VGS, the voltage VDS at which pinchoff occurs decreases.
The maximum current also decreases.

For VGS < VP :
The FET is cut off; no current flows regardless of VDS. The blockage of current occurs for the
same reason (the growth of the depletion region due to the reversed bias).
15
Fig. 11 Source: http://www.physics.csbsju.edu/trace/nFET.CC.html
II.3.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
II.3.2A Metal oxide semiconductor (MOS) capacitor
16
Energy
of e
Conduction band
of the oxide
Ec
EF
Ev
Oxide
Metal
Accumulation
Ec
Ef
Ev
Semiconductor
p-type
Depletion
Inversion
Ec
Ei
EF
Ef
Ev
---- -- --
 Semiconductor
Metal
Ei
EF
Ec
Ei
EF
Ei
E
Ev F
---- -- --
Ef


p-type
Q
Q
+
Q
+
+
-
-
-
Depletion
nh  ni e
( Ei  EF ) / kBT
Since Ei-EF decreases as the bands bent, the electron hole population decreases near the
interface. This decrease implies that holes are leaving the region, leaving behind acceptors
negatively charged; that is, a depletion layer is created.
Inversion
ne  ni e
( EF E i ) / kBT
As the bands bend, EF -Ei passes from being a negative value to become a positive value
when the applied positive voltage reaches a threshold value. Further increases of the applied
17
volatage makes the value of ne (free electrons) to increase. That is, free-electrons are created
at the p-type semiconductor, the charge located near the interface.
II.3.2B MOSFET
MOSFET
VD small
SiO2
CHANNEL
VD = VD,sat
VD > VD,sat
II.3.2C Floating gate non-volatile memory
18
op Down
a)
FLOATING GATE NONVOLATILE MEMORY
SiO2
III. EXPERIMENTAL CONSIDERATIONS
III.1 The Bipolar Junction Transistor
III.1.1 Transistor’s characteristic curves. Current gain and the  value
III.1.2 DC bias circuit and the operating point
III.1.3 Small signal amplifier (this section is not required in Winter 2015)
III.2 The Field Effect Transistor
III.2A The Junction Field Effect Transistor (JFET)
III.2B The Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
III.1.1 Transistor’s characteristic curves. Current gain  and the  value
We will use general purpose transistors: 2N 2222, 2N 3906, or the npn 2N 3904.
Use a npn transistor and setup the circuit indicated in the figure below.
Select RB and RC such that IC fall in the range of mA, and IB in the order of 5A to 200 A.
The suggested use of variable resistors is for you to be able to do the proper changes as to keep
the IB constant while obtaining the trace of one of the current collector curves.
TASK: Obtain the characteristic curves of the transistor. Plot about 04 curves, corresponding to
different values of base current. Label each trace with the corresponding value of IB as
well as the value of VBE.
19
VCC (+ 15 V)
IC A
IC (mA)
npn
RC
IB
Active region
IB3 (A)
IB2 (A)
C
Vin
A
(+15V) Ammeter RB
B
VCE
IB1 (A)
E
VCE
Fig. 5 Grounded-emitter setup for obtaining the collector current characteristics. IB is
approximately constant across the active region.
TASK: Estimate the experimental value of the transistor current gain

iC .
iE
(2)
Keep in mind that usually the current gain is described in terms of the  value of the transistor,
the latter being defined as,
i
i

 C  C 


iB iE  iC 1  
III.1. 2
DC bias circuit and the operating point
Given the transistor curves characteristics, our objective is to bias the transistor properly as to
make it function around a given operating point inside the active region (point P in the diagram
below, for example.) The procedure will help us understand how the output voltage depends on
the input voltage.
IC
VCC (+ 15 V)
Active region
IC
100 A
20 mA
P
10 mA
50 A
Vin
(+ 15 V)
IB
RC
Vout
C
B
VCE
RB
E
VCE
Fig. 6 Given the collector current characteristics. RC and RB should be selected to have the
transistor operating around the point P in the active region.
How to choose RC?
20
IC
15V
RC
Load line analysis
Even though we do not know IC neither VCE
a relationship between them can be obtained
through the Kirchhoff’s law applied to the
right side branch of the circuit above (and
reproduced below for convenience.);
100 A
20 mA
P
10 mA
50 A
15V - IC RC - VCE = 0,
which leads to,
+ 15 V VCE
Fig. 8 Load line superimposed with the
transistor characteristic curves.
IC 
15 V
1

VC E (IC
RC
RC
decreases linearly with VCE.)
IC
RC
IB
+ 15 V
IC
15V
RC
+ 15 V
20 mA
B
VCE
Load line
10 mA
npn
+ 15 V
VCE
Fig. 7 Application of the Kirchhoff law to the right-side branch of the circuit gives a
relationships to be satisfied by IC and VCE.
If we want to work with, for example, a current base of 50 , many values of Rc are possible.
Still, there is a restriction to be satisfied, which is not to exceed the transistor’s heat dissipation
tolerance. For example, the data sheet may specify,
VCE; max ICE; max < 350 mWatts
Applying this condition to our case, one obtains
(15 V) ( 15 V/RC ) < 350 mWatts
Thus, in this case, a resistor RC > 1 K would be good enough
How to choose RB?
Since we want to operate the transistor at the point P, that is a current base of 50 A, all we
have to do is to choose an RB that allows delivering a current of that magnitude
15V  0.7V
50 A
which takes into account that, when operating in the active region, the base voltage is about 0.7
V (for silicon transistors.)
RB ~
21
The operating point P results then from the intersection of the load line and the transistor curve
corresponding to 50 A.
TASK: Set up the transistor to work in one point of the active region
How the output voltage depends on the input voltage
Instead of using a fixed Vin voltage, vary its value a bit as to produce slightly different base
currents. The diagram below helps illustrate the expected variation of the VCE voltage.
IC
VCC (+ 15 V)
IC
Vin
IB
15V
RC
RC
Vout
C
B
100 A
20 mA
P
IC
VCE
RB
IB IB=50 A
B
E
VCE
+ 15 V VCE
Fig. 9 Small variations of IB moves the operating point P along the load line, causing a
variation of VCE (and, correspondingly, a variation in IC.)
TASKS:
Make a plot of Vout vs Vin (Notice, in this case, Vout = VCE)
Verify that the plot looks like the graph shown in the figure at the right.
From this experimentally obtained graph, evaluate the voltage gain: Vout/ Vin
Vout
VCC
Transistor
OFF
Transistor
(saturated)
ON
Fig. 10 The greater Vin, the greater IB, the
greater IC and greater drop of voltage across
RC, the lower VCE voltage.
Vin
NOTE: Notice from figures 9 and 10, that the greater Vin, the greater IB, the greater IC and greater
drop of voltage across RC, the lower VCE (output voltage.) Thus, small variations of the input
voltage around a given value will be 180o out of phase with the output voltage.
22
III.1.3 Small signal amplifier (Not required in 2013) Jump to section III.2
A large signal amplifier operates the transistor in its full range of operation, from near cutoff
to near saturation (from small IC currents to large
currents). Such an operation mode is quite suitable
VCC = + 10 V
for digital electronics application, where LOW and
RC
R2
1 K
HIGH signal levels determine the “0” and “1” binary
IC
50K
Vout
information.
C
Other
applications
require
small-signal
Vin
B
amplifiers. For a given configuration, where the
transistor operates at a given point of the active
npn
R1
E
region, an small modulation of the base-current
5.6 K
translate into a modulation of the collector current
(picture a small audio signal being amplified by the
transistor). If high amplifications are required,
Fig. 11 DC bias circuit (accomplished by
several small-signal amplifiers can be cascaded in
the resistance R1 and R2).
series. In this laboratory session we will construct
and analyze just one small-signal amplifier stage.
A small-signal amplifiers must have:
 a dc bias circuit for placing the transistor in its amplifying region (VERY
IMPORTANT).
 a mean for introducing the input signal
 a mean for supplying its output signal to the next stage.
The circuits used in the previous section deal with the first two aspects. But, as it turns out, such
circuits are very sensitive to temperature variation. For that reason, we will be modify it a bit,
but their equivalence with our older circuit will become transparent in the course of the
discussion. Once the circuit is properly DC biased, we will proceed to input a small AC signal.
(The coupling of a circuit stage to another will be addressed in Lab #4, when we study the
concept of input and output impedance).
III.1.3.A Modified DC-bias Circuit. Placing the transistor in its amplifying region.
The simple bias circuit in Fig. 9 above is generally not satisfactory because the operating point
shifts drastically with temperature.)
A more satisfactory transistor bias is obtained when using a voltage divider, as shown in Fig. 11.

TASK: Construct the circuit shown in Fig. 11.
Thevenin equivalent circuit analysis
We can use the Thevenin’s theorem to show the equivalence between the circuits in Fig. 9 and
Fig. 11. This is made more evident by re-drawing Fig. 11 as shown in Fig. 12 below.
Through the Thevenin theorem one can claim that both circuits, the ones at the left and right
sides of Fig.12 are equivalent. Analyzing the shaded area one obtains:

The Thevenin voltage VBB is the open-circuit voltage (voltage across XY in the circuit
23
VCC
R1 . (VBB = (10V/55k)(5k) =1V.)
R1  R2
when no external load is applied) VBB 

RB designates the Thevenin equivalent series resistance. The short circuit currents (i.e. the
currents when X and Y are shorted) are VCC/R2 and VBB /RB respectively. Since the
circuits are equivalent these two current must be equal. Hence, RB 
value for VBB obtained above, results
R2 R1
(RB = (5k x 5k) / (55k) =5 k ).
R1  R2
RC
1 K
RC
R2
VCC
=+10V
RB 
50K
C
X
VCC =
+10V
Vout
npn
C
RB
B
R1
R2
VBB ; using the
VCC
X
B
npn
VBB
E
Vout
VCC =
+10V
E
5.6 K
Y
Y
Fig. 12 DC bias circuit and its Thevenin equivalent. The latter helps to calculate the different
parameters associated to the intended operating point of the transistor (using the analysis described
in the previous section) based on the values of R1 and R2.

TASKS: For the final values that you use for R1 and R2 calculate the Thevening values for
VBB and RB.
Select the proper value of RC such that the transistor work in the active region.
THIS IS VERY IMPORTANT. More specifically, choose RC such that VCE is ~ 4
Volts. (An RC ~ 1 k should work).
VCC = + 10 V
R2
50K
RC
1 K
IC
VBB
RB
Vout
VCC = +10V
RC
C
C
Vin
B
R1
5.6 K
npn
IC
IB
Vout
B
npn
E
E
Fig. 13 Equivalent representation of the circuits in Fig. 12.
III.1.3.B Connecting to an oscillator
Once the transistor is properly DC biased (VCE ~ 4 volts), proceed to connect the voltage
from a signal generator. See Figure 14. If the oscillator is connected directly at the Vin, unwanted
24
DC voltage offset from the oscillator may change the bias level and/or draw some current away
from Ib., and thus potentially spoil the operation point designed in the previous section. As a
precaution, it is normally convenient to put a capacitor in series with the oscillator to block the
flow of DC current. (You could try C1 =1f but be aware of the frequency range of operation.
Since the impedance of the capacitor is frequency dependent, make sure the capacitive reactance
is small with respect to the other resistance you use at the input; i.e. you need a resistance to limit
the base current).
TASK:
Couple a small sinusoidal signal (start using ~0.03 V amplitude) into the circuit shown in
Fig. 14 (Left diagram).
Monitor the input and output signals in the oscilloscope.
It is convenient to first monitor the output voltage vout with the oscilloscope set to DC
mode, so you can be track whether its value is saturate or not.
Measure the AC voltage amplification, as well as the relative phase between the input and
output voltage. (For this measurement, you may want to switch monitoring the output voltage
with the oscilloscope in ac-mode).
For the coupling capacitance C1 that you choose (C1 = 1 F for example) find out the range
of frequencies for which the circuit works properly. Find out also the range of input-voltages
amplitude tolerated by the circuit.
Make the circuit to work in the low frequency (tens of hertz) and high frequency range (tens
of kHz or higher). You may need a different capacitor for each of these two cases.
Notice:
Your circuit may not allow putting an ac-signal input signal vin of amplitude greater than
~0.3 V (actually the exact value depends on the value you select for Rs), otherwise you
would drive the transistor out of its operation range (this will be reflected in the clipping of
the output signal).
VCC = + 10 V
R2
50K
vin
RC
1 K
VBB
IC
C
Rs
B
C1
R1
5.6 K
VCC = +10V
npn
RB
vout
vin
IC
IB
C
R
Cs2
B
iB C1
E
RC
npn
vout
E
Try Rs = 1 Kork
Fig. 14 Left: Small signal amplifier circuit. Right: Equivalent circuit, which helps to differentiate the
additional (AC) base current injected by the signal generator from the DC base current established by
the bias circuit.
25
C2
Evaluate the maximum amplitude of the input ac-signal that your circuit tolerates (i.e.
avoiding clipping in the output signal). Check whether a Rs= 1 k or Rs= 10 k works
better in this regard.
Monitor the voltage VB at the base of the transistor all the time (with a multi-meter or, better,
with the oscilloscope); the value should be ~ 0.7 volts. Whenever you observe the output
signal “clipping” it may be because VB is deviating very much from this value (If VB is too
high the transistor lead to saturation; if VB is too low the transistor is off).
Eventually, you may need to change the value of RC to have the voltage vout in the proper
range (i.e. vout has to be greater than 0.7 volt, so it can allow ac variation without turning off
the transistor.)
It is convenient to first monitor the output voltage
vout
without the capacitor, so it can be
tracked whether its value is saturate or not. For that purpose monitor vout with the
oscilloscope set to DC mode. After you find your circuit working properly, insert the
capacitor C2 (Fig. 15).
VCC = + 10 V
R2
50K
vin
VBB
IC
C
Rs
B
C1
R1
5.6 K
VCC = +10V
RC
1 K
npn
C2
RB
vout
vin
RC
C
Rs
B
iB C1
E
IC
IB
npn
C2
vout
E
Try Rs = 1 Kork
Fig. 15 Circuit is exactly the same in Fig. 14, except using an out coupling capacitor.
III.2A The Junction Field Effect Transistor JFET
We will use the general purpose JFET 2N5457
TASK: Implement the JFET in the circuit outlined in Fig.4. Determine the characteristics curves,
as well as the pinch-off voltage VP.
III.2B The Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
REFERENCES
J. R. Cogdell, "Foundations of Electronics," Prentice Hall (1999). See Sections 2.3 and 2.4, p.89114.
P. Horowitz and W. Hill, "The Art of Electronics," 2nd Edition, Cambridge University Press
26
(1990).
Ben G. Streetman, “Solid State Devices,” 3rd. Ed. Prentice Hall. (Chapter 8, Field Effect
Transistor).
1
http://en.wikipedia.org/wiki/Field-effect_transistor “Even though the conductive channel formed
by gate-to-source voltage no longer connects source to drain during saturation mode, carriers are not
blocked from flowing. Considering again an n-channel device, a depletion region exists in the p-type
body, surrounding the conductive channel and drain and source regions. The electrons which comprise
the channel are free to move out of the channel through the depletion region if attracted to the drain by
drain-to-source voltage. The depletion region is free of carriers and has a resistance similar to silicon.
Any increase of the drain-to-source voltage will increase the distance from drain to the pinch-off point,
increasing resistance due to the depletion region proportionally to the applied drain-to-source voltage.
This proportional change causes the drain-to-source current to remain relatively fixed independent of
changes to the drain-to-source voltage and quite unlike the linear mode operation. Thus in saturation
mode, the FET behaves as a constant-current source rather than as a resistor and can be used most
effectively as a voltage amplifier. In this case, the gate-to-source voltage determines the level of
constant current through the channel.”
27