A Self-Boost Charge Pump Topology
for a Gate Drive High-Side Power Supply
Shihong Park
Thomas M. Jahns
Department of Electrical and Computer Engineering
University of Wisconsin – Madison
Madison, WI 53706 USA
Abstract - A self-boost charge pump topology is proposed for
a high-side isolated power supply with high voltage isolation and
high current capability for use in IPEM gate drives. The
topology uses a single power supply in a transformerless
configuration. The proposed technique provides additional
attractive features, including elimination of phase leg switching
to refresh the upper switch gate supply capacitor. A piecewise
linear model of the proposed charge pump is derived and the
circuit’s operating characteristics are analyzed. Simulation and
experimental results are provided to verify the desired operation
of the new charge pump circuit.
A new charge pump topology is proposed for high-side
gate drive power supplies that avoid the problems of existing
VDC
D1
D2
VCC
R3
CL
CH
S2
Gate Drive
&
Level Shift
&
Protections
D3
OUTPUT
I. INTRODUCTION
A. Background
Bootstrap circuits are widely used in power integrated
circuits to provide the isolated power supply for high-side
gate drives.
They are preferred over high-frequency
transformer circuits due to their simplicity and basic
compatibility with integrated circuit implementation, making
them well suited for achieving low cost and high reliability.
However, the bootstrap technique imposes some
significant limitations due to its periodic charging time
requirements that can interfere with the desired gate drive
operation under some important operating conditions. One
approach that has been proposed to overcome these problems
uses an auxiliary bootstrapped charge pump [1]. This
technique can provide the needed power for a high-side gate
drive without interfering with the switching sequence.
However, it is not widely used due to its higher complexity
and its requirements for high-voltage level shifting to supply
the auxiliary switches.
Another technique that applies charge pump techniques to
deliver power to a floating voltage reference is described in
[2]. It has a simple topology and overcomes the limitation of
conventional bootstrap high-side power supplies by
transferring charge even when the output terminal remains in
its high-voltage state. However, this technique suffers in high
current applications from high power losses in the charge
pump oscillator and high voltage ripple due to large voltage
These
surges caused by output node state changes.
disadvantages limit this technique to gate drive applications
with low current supply requirements.
RG
Driver
S1
VPULSE
Fig. 1 Proposed charge pump circuit configuration for an inverter
phase leg high-side power supply
D1
D3
+
_CL
S1
Fig. 2 Charging mode (S1 is on and S2 is off)
+
CL_
+
_CH
R3
S2
OUTPUT
Fig. 3 Boost mode (S1 is off and S2 is on)
D2
+
CL_
+
_CH
S2
This work was supported primarily by the ERC Program of National Science
Foundation under Award Number EEC-9731677.
R3
VCC
OUTPUT
Fig. 4 Pumping mode (S1 is off and S2 is on)
techniques while retaining the advantages of simplicity and
IC implementation compatibility. The proposed topology
uses a modified charge-pump configuration to deliver power
from the low side to the high side. Fig. 1 shows the proposed
topology with a standard inverter phase leg configuration.
B. Operating Principles
The operation of this new charge-pump circuit can be
divided into the following three modes: Charge, Boost and
Pump mode. Each mode will be described individually,
assuming that the upper phase-leg switch is on so the output
node voltage is nearly VDC.
Charging Mode (Fig. 2)
The boost capacitor CL in Fig. 1 is charged by VCC through
D1 and D3 when the switch S1 turns on as shown in Fig. 2. S2
and D2 remain in their off-states since the gate-source voltage
VGS2 is forced to –VD3 during the charging mode. D1, D2, S1
and S2 must all be high-voltage devices that can sustain
voltages up to the dc link voltage VDC. D3 can be a lowvoltage diode because the maximum reverse voltage is lower
than VCC. A Schottky diode is preferred for D3 in order to
minimize its voltage drop and resulting conduction losses.
Boost Mode (Fig. 3)
When S1 turns off, the voltage VL on the boost capacitor CL
starts to charge the gate capacitance of S1, CGATE1 , through R3.
Assuming that CL is much bigger than CGATE1, the decrease in
voltage VL is negligible. The value of R3 determines the turnon time of S2, but does affect the magnitude of the voltage
decrease. Once CGATE1 is charged, there is no additional
current flow or loss in R3.
The voltage at the negative (lower) terminal of CL rises
from ground level to VDC (the output node voltage) as switch
S1 turns off and the drain-source voltage of S2 decreases as
shown in Fig.3.
Pumping Mode (Fig. 4)
After S2 fully turns on, the charge in the boost capacitor CL
is transferred to the high-side capacitor CH that serves as the
local supply for the high-side switch gate. This pump mode
ends when S1 is turned on again by the external control.
Continuous switching of S1 insures that gate drive charge is
available at all times to the high-side switch.
C. Paper Organization
In this paper, models for each of the three modes will be
analyzed in Section II using linearized diode and MOSFET
models that include the effects of load current. For high
voltage applications, the voltage drops caused by the internal
resistances of the diode and MOSFET become significant as
the current level increases. Steady-state operation is also
analyzed illuminating the effects of important parameters
including frequency, duty cycle, delay times and switching
times. Following this analysis, simulation and experimental
results are presented in Section III to verify the model and
demonstrate the circuit’s operating characteristics.
II. CHARGE PUMP CIRCUIT ANALYSIS
Figure 5 shows the voltage-current characteristics of a
common piecewise linear diode model that will be used in
this simplified analysis. The V-I characteristics of the diode
can be defined by two parameters – the voltage drop VD and
the on-state resistance rd.
As note above, a Schottky diode is a good choice for D3 in
order to minimize this voltage drop. The Schottky diode
forward voltage drop is typically 0.1~0.2V whereas the
comparable voltage for a standard silicon junction diode is
0.7V.
The MOSFET will be modeled as a simple resistor rds
after it turns on. The reverse leakage current of the MOSFET
and diode are ignored in this analysis. IGBTs could be used
instead of MOSFETs for a high-voltage application (>600V),
but the forward voltage drop of an IGBT is typically higher
than that of a MOSFET for low current conditions.
∆i 1
=
∆v rd
V
VD
Fig. 5 Linearized diode model
The voltage waveforms across the boost and high-side
capacitors during the three operating modes are shown in Fig.
6. The input control pulse signal VPULSE and the switch S1
drain-source voltage VDS1 are also shown in this figure to help
explain the circuit’s operation and operating characteristics.
The equations for the boost capacitor voltage VL(t)and the
high-side capacitor voltage VH(t) will be analyzed for each of
the three operating modes using equivalent circuits. The
value of VH(t) under steady-state conditions will also be
calculated as function of the boost time t21 to illustrate the
control principles for the new charge-pump circuit.
A. Charging Mode Equivalent Circuit and Analysis
During the charging mode, switch S1 is on and switch S2 is
in its off state. The boost capacitor CL is charged through D1,
D3 and S1. The equivalent circuit for a charging mode is
shown in Fig. 7. The maximum charging voltage of CL is
VL,MAX=VCC-VD1-VD3 and the equivalent resistor value is
REQ=rd1+rd3+rds1. The boost capacitor voltage VL(t) can
be calculated as follows:
v L ( t ) = v L (0) + [VL,MAX − v L ( 0)](1 − e
−t
REQ ⋅CL
)
(1)
VH(t)
VH,max
VH(0)
VH,min
V H ( t ) = V H ( 0) −
VL(t)
VL,min
Boost
Boost
Charge
Pump
VH (t ) = VH (0) +
−
Vpulse
VCC
(C L + C H ) 2
0
f
C + CH
1
⋅ L
REQ 2 C L ⋅ C H
REQ=rd1+rd3+rds1
t =1/f
t 21 = t 2 - t1 = δ2/f
+
CL
_ VL,MAX
= VCC - VD1 -VD3
Fig. 6 Self-boost charge pump waveforms
It is worth noting that the same voltage VL,MAX appears
across resistor R3 during the charging mode, resulting in
power dissipation in R3 during this interval.
IL
CH
R3
During the boost mode, S1 turns off, D3 transitions to its
off-state, and the gate capacitance of S2 is charged so S2
begins to turn on. Figure 8 shows the equivalent circuit
during this operating mode.
The voltage of CL (and Cgate) following completion of this
gate charging is
CL ⋅VL (0)
CL + C gate
+
+
_VL(0) VH_
Fig. 7. Charging mode model
B. Boost Mode Equivalent Circuit and Analysis
VL =
(4)
IL
t
CL + C H
V ' L (0) = V L (0) − V D 2
t
t1 t2
−t
(1 − e τ ) −
R EQ2 = rd 2 + rds 2
1 - δ1 - δ2
f
δ1
C LV ' L (0) + C H VH (0)
(1 − e τ )
CL + CH
R EQ 2 C L2 I L
where τ =
gnd
gnd
(3)
−t
t
VDS,S1
VDC
IL
⋅t
CH
C. Pumping Mode Equivalent Circuit and Analysis
The pumping mode begins when S2 fully turns on while S1
remains off. The equivalent circuit for this pumping mode is
shown in Fig. 9, where the equivalent resistance REQ2 is made
up of the equivalent resistances of diode D2 and switch S2.
The high-side capacitor voltage VH can be derived as follows:
VL,max
VL(0)
VL(0) is negligible, and R3 does not affect the final voltage
value.
The gate drive circuit is modeled by a constant load current
IL that flows at all times. The high-side capacitor CH is
discharged by this load current IL during both the charge and
boost modes. Thus, the equation for the high-side capacitor
voltage VH during the boost mode can be expressed simply as
follows:
`(2)
where Cgate is an effective gate capacitance of S2.
It is evident in equation (2) that if CL is much bigger than
Cgate, the voltage decrease of CL compared to its initial value
+
VL _
VL(0)
CL
+
Vgate _
Cgate
+
VH_
V(0) = -VD3
Fig. 8. Boost mode model
CH
IL
REQ2=rd2+rds2
+
VL _
V'L(0)
+
CL
VH_
CH
IL
does not change for a given switch S2 and a given value of R3,
making t21 a key parameter under higher frequency conditions.
Closer examination reveals that the time interval t21 can be
separated into two subintervals consisting of a delay time tD
and fall time tF corresponding to the turn-on modes of switch
S2 as shown in Fig. 10. During tD, the gate node is charged
up to the threshold voltage VTH. At that point, the drain
current starts to flow in S2 and VDS falls during tF while the
gate-source voltage VGS remains nearly constant at VTH due
to the Miller effect.
Fig. 9. Pumping mode model
VGS
The second term in equation (4) represents the voltage
transferred from the low side. The third and fourth terms
describe the voltage drop due to the equivalent resistor and
the load current respectively.
VTH+IL/gm
D. VH under Steady-State Conditions
-Vd3
Under steady-state conditions, the maximum and minimum
voltage levels of VH and VL remain constant. Using these
constraints, the minimum value high-side capacitor voltage
during steady state conditions can be calculated as follow:
VH , min = V H , max −
IL
(δ 1 + δ 2)
CH ⋅ f
t
VDS
VDC
(5)
VON
where
VH , MAX = VCC − VD1 − VD2 − VD 3 −
I L ⋅ REQ 2
1−δ1− δ 2
(6)
tD
t
tD + tF
Fig. 10 Waveforms of VGS and VDS for S2 during t21 interval
and δ1 and δ2 are duty cycle variables as defined in Fig. 6.
In equation (5), the second term represents the ripple
voltage amplitude ∆VH so that this equation can be rewritten
as follows:
V H ,min = V H ,max − ∆V H
∆V H =
IL
(δ 1 + δ 2)
CH ⋅ f
Intervals tD and tF can be calculated as follows [4]:
t D = R3 ⋅ C EQ 2 ⋅ ln
VCC − V D1 − V D 2
VCC − V D1 − 2 ⋅ VD 2 − VTH − gm / I L
V DC ⋅ R3 ⋅ C GD
(9)
(10)
(7)
tF =
(8)
where VTH = Gate threshold voltage [V]
VDC = DC link voltage [V]
gm = Device transconductance [A/V]
IL = Load inductor current [A]
CGD = Device gate-collector capacitance [F]
In order to reduce the ripple voltage amplitude, either the
value of the high-side capacitance CH must be increased or a
higher frequency f is required. However, the switching losses
in switches S1 and S2 make it undesirable to raise the
frequency too high. Lowering the duty cycle interval δ2
makes it possible to transfer more charge from the low to
high sides which helps to reduce the ripple voltage amplitude.
However, it is important to recognize that lowering δ2
corresponds to reducing the value of resistor R3 which causes
higher power dissipation in R3 during the charging mode.
E. Calculation of Boost Time t21
As the operating frequency f increases, the effect of the
boost time t21 (see Fig. 6) on the output voltage is more
significant because the ratio of charging to discharging time
decreases if t21 is fixed in value. It should be noted that t21
V L (0) − VTH − gm / I L
III. SIMULATION AND EXPERIMENTAL RESULTS
Simulations and experimental tests were carried out to
verify the proposed charge pump operation. Figure 11 shows
the test circuit that was used for the laboratory tests. The
simulations have been run using PSPICE with the same test
circuit. The devices used the switches S 1 and S 2 are both the
same MOSFET type BUZ50B rated at 1000V and 3A, and
manufactured by Infineon. Diode types 1N4007 and 1N5818
were selected for the high-voltage diode D2 and the lowvoltage Schottky diode D3, respectively. The reverse blocking
voltage of the 1N4007 diode is 1000V, the same as the
MOSFET voltage rating.
The test conditions used for both the experimental tests and
the simulation are as follows:
Vdc = 600V
Vcc = 20V
f = 5kHz
R3 = 2kΩ
CH =10uF
Rg = 2kΩ
Ro = 600Ω
The value of Ro was set to 600Ω to adjust the load current
to approximately 28 mA for a VH value of 17V.
CL = 10uF
D2
D1
measured Fig. 12 waveform is caused by the reverse recovery
current of diode D2 when S1 turns on. Stored charge in CH is
reversibly transferred to VL during the D2 reverse recovery
time.
It is possible to measure the value of the S1 turn-on interval
t21 directly from the experimental waveforms in Fig. 12.
Even though the duty cycle of VPULSE (i.e., δ 1 ) is set at 50%,
the actual duty cycle of the CH charging interval (=1- δ1 - δ2)
is approximately 40%, meaning that the t21 turn-on
interval
15
Vpulse
D1N4007
D1N4007
Vcc
R3
2k
CL
10uF
CH
10uF
Ro
Experimental
Results
10
5
0
Simulation
Results
-5
S2
VH
18
BUZ50B
D3
D1N5818
17.5
17
600
Vds1
VDC
400
200
Rg
0
100
S1
VPULSE
2k
BUZ50B
From equation (6), the maximum high-side capacitor
voltage can be calculated to be
I L ⋅ R EQ 2
1−δ1−δ2
(11)
= 20 - 0.8 - 0.8 - 0.3 - (0.028*8*2.5)=17.54V
In this calculation, it is assumed that the VD1=VD2=0.8V
and VD3=0.3V because D1 and D2 are high-voltage diodes and
D3 is a Schottky diode. The sum of the duty cycles δ1+δ2 is
assumed to be 0.6 based on observations of typical circuit
operation.
The ripple voltage can be calculated from (7):
∆V H = I L ⋅
1
⋅ (δ 1 + δ 2)
CH ⋅ f
300
400
500
Time [us]
600
700
800
Fig. 12 Overlaid simulation and experimental results
for VPULSE, VH and VDS1
Fig. 11 Self-boost charge pump test circuit
V H ,MAX = VCC − V D 1 − V D 2 − V D 3 −
200
(12)
= 0.028* (0.6)/(10e-6 * 5000) = 0.34V
Figure 12 shows experimental waveforms and overlaid
simulation results for the input control voltage VPULSE, the
high-side capacitor voltage VH ,, and the switch S1 drainsource voltage VDS1 under steady-state conditions. The
calculated maximum capacitor voltage VH,Max and ripple
voltage ∆ VH from the equations demonstrate satisfactory
agreement with the measured values. The simulation and
experiment results also show a good agreement.
The sudden drop in the capacitor voltage VH at the
beginning of the charging mode that is visible in the
reduces the charging duty cycle by approximately 10% (i.e.,
δ2 =0.1). Reducing the value of δ1 will cause the ripple
voltage amplitude ∆VH to decrease.
IV. CONCLUSION
This paper has presented a new charge pump topology for
a gate drive high-side power supply. The model of each
mode was derived based on piecewise linear device models.
Each model provides good predictions of operation and
design considerations under transient as well as steady-state
conditions. This new power supply circuit provides the
following attractive features comparing to conventional
techniques:
• Simple charge-pump configuration requiring no highfrequency magnetic components
• Independent operation without phase-leg refresh
switching requirements
• High steady-state current supply capability for highperformance gate drives
• All parts compatible with future IPEM designs.
Both simulation and experimental results have been
presented to confirm the operating characteristics of the selfboost charge pump circuit and its model. Work is continuing
to explore how these techniques can be best utilized in future
generations of IPEM gate drive circuits.
V. REFERENCES
[1] G. F. W. Khoo, Douglas R. H. Carter, and R. A. McMahon, “Analysis of
a Charge Pump Power Supply with a Floating Voltage Reference”, IEEE
Transactions on Circuits and Systems, vol. 47, no. 10, Oct. 2000.
[2] Ray L. Lin and Fred C. Lee, “Single-Power-Supply-Based
Transformerless IGBT/MOSFET Gate Driver with 100% High-Side
Turn-on Duty Cycle Operation Performance Using Auxiliary
Bootstrapped Charge Pumper”, 1997 PESC Conference Record, Vol.: 2,
June 1997, pp. 1205-1209.
[3] “HW Floating MOS-Gate Drive ICs,” IR Application Note AN-978,
International Rectifier Corp.
[4] B.Jayant Baliga, Power semiconductor devices, PWS Publishing
Company, 1995, pp. 387-397.