Noise on Vcc Webinar
Author: Bob Muro
Wireless Telecom Group
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Webinar Agenda
• Major sources of IC chip interference
–
–
–
–
Vcc droop and ground bounce
SMPS (Switch-mode power supply) noise
EMI/cross-talk radiation
Switching Outputs
• Susceptible Device Types
• Example IC - PLL circuit
– Basic PLL circuit description
– Noise effects the VCO
– Example Test System
• JV9000A series solution
– Example test system
– R&D qualification
– Production cost effectiveness
Page 2
Ground Bounce and Vcc Droop
• All digital switching operations create noise
• The noise impacts the power and ground planes
of the circuit board
• The noise is caused by stray inductance and
capacitance found in the digital components and
the surrounding circuitry
• The noise can affect the IC chip output and
surrounding components
Page 3
Ground Bounce Explained
•
The figure illustrates the ground path
between the power supply, board,
device and output trace
•
The path has four stray inductive
sources from L1GND to L4GND that
will sum together in series as Lsum
•
V is the voltage difference between
the die Vcc and ground caused by
changing current through Lsum
•
The voltage change with respect to
time is equal to V = Lsum × (dI / dt)
across L1, L2, L3, and L4
Page 4
Ground Bounce Scope Example
• CH3 - switching I/O pin input
• CH2 - “quiet” I/O pin input
• (I/O pin LOW)
• Resultant voltage change
caused by changing current
• Ground bounces occurs with an
output switch from logic
level
1 to 0
• High voltage ground bounce can
be misinterpreted by the
receiver as logic level 1
rather than 0
Page 5
Vcc Droop
Conversely, Vcc droop occurs
when the output switches from
logic level “0” to “1”
Die Vcc level drops relative to the
Power Supply Vcc.
The power supply, board, device,
and output trace capacitance are
connected via the Hi-transistor
The discharge current has to pass
inductances L1Vcc to L4Vcc
producing a voltage difference
between the device die Vcc and
power supply Vcc
The voltage with respect to time,
as with GND bounce, is V = Lsum
× (dI / dt)
Page 6
Switch Mode Power Supply Noise
•
Switch mode power supplies (SMPS’s) are found in many modern
electrical devices
•
They are very efficient compared to linear supplies, delivering power
in response to a change in the output load and automatically
adjusting to most world-wide power standards
•
The output power is controlled using PWM with a lower duty cycle
pulse delivering less energy to the output load
•
Their transistor switching speeds must be fast to control the energy
transfer and can vary from 20 kHz up to 1 MHz
•
They generate high-amplitude, high-frequency noise, not completely
attenuated by LP filter networks or bypass capacitors
•
They are major contribution to system EMI/RFI radiation
•
Lower cost SMPSs may couple electrical switching noise back onto the
main power line, creating additional interference
Page 7
EMI/RFI and Cross-talk Sources
High EMI Oscillators
•
All digital circuits require precise timing in the form of oscillators
•
Oscillators can have high power at precise frequencies that radiate
EMI/RFI
•
The EMI/RFI can affect all adjacent circuitry
High Speed Data Signals
•
High frequency data signals with high power harmonic content radiate
high frequency noise on to adjacent data paths via Cross-talk
•
Depending upon the board layout, this high frequency noise can
increase system BER
Page 8
Susceptible Devices
• Package Types:
– TSOP, FPGA, FBGA, … etc
• Devices:
– PLL, Phase Lock Loop
– Oscillators
– FPGA
– MMIC
– ADC and DAC
– Flash memory
– Clock Distribution circuits
Page 9
Highly Susceptible Devices
• Devices with a high sensitivity to Ground bounce, Vcc droop,
EMI/RFI and Cross-talk
– Mixed signal environment
• Sensitive analog IC’s combined with noisy digital ICs
• Handheld devices with radios
– High frequency PLL circuits
– High digital component count within a small footprint
– High I/O output pin counts within a small area
– Devices with lower power supply voltage requirements
Page 10
PLL Block Diagram
•
A closed loop system that generates a frequency-locked output (Fout)
and corrects any phase shift by comparison to an input reference clock
(Fref) via the feedback loop (Ffeedback)
•
Major components are the Phase Frequency Detector (PFD), Charge
pump, loop filter, VCO, pre-scale and feedback counters
•
Uses master clock crystal/oscillator reference to lock phase with other
clocks in the same system
Page 11
PLL Basics
• Ref in – master/crystal clock reference input
• PFD – phase frequency detector circuit
• Up and down inputs – VCO control inputs
• Charge pump – capacitor bank used to tune the VCO and adds
an additional pole to loop filter transfer function
• Loop filter – integrating filter designed to smooth VCO input to
enhance PLL locking
• VCO – voltage control oscillator for final PLL output &
feedback input to the divider, and PFD
• Feedback loop – VCO output to PFD input to compare with the
Reference input
Page 12
Noise Effects of PLL
• PLLs are widely used for generating high-precision, low jitter
timing signals
• They are very susceptible to noise and interference
• PLL Noise
– Power and ground plane noise that change the absolute reference values
– EMI/RFI interference that penetrates the loop filter, VCO section of the PLL
– Intrinsic jitter/noise from the reference oscillator
• Noise Effects
– Noise on the circuit traces can cause the PFD to misinterpret the correct phase
– Reference oscillator noise causes the PFD low/high outputs to constantly vary
attempting to lock the phase
– EMI/RFI on the loop filter, VCO network creates hysteresis in the PLL final
output
– The loss or the inability to lock the phase of Ref in and VCO output signal
Page 13
Example PLL Test System
• Typical test system includes JV9000A noise generator, PLL evaluation board,
DC power supply, and TIA (time interval analyzer) receiver
• An oscilloscope can be used in place of the TIA as the reference receiver
Page 14
Standard Noisecom JV9000
• White Gaussian Noise Source
– Noise Band: 500Hz to 2GHz
– Output Power: nominal 0dBm, attenuated by 100dB with 1dB
minimum step size
• Deterministic Jitter (optional CW generator)
– Frequency range: 1KHz to 1GHz (in 1,3 step)
– Output Power: nominal 0dBm, attenuated by 100dB with 1dB
minimum step size
• Vcc Input & Output
– Bias-Tee output for broadband coupling
– Max input Voltage: 5V
– Maximum Current: 250mA
– Output Connector: SMA
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JV9000 Block Diagram
•
AWGN & CW signals are combined
with DC power via bias-Tee
•
DC supply voltage powers the
DUT through the JV9000 DC input
•
Noise & CW signals disturb the
DUT pulse output
•
AWGN & CW signals are coupled
to the DC power supply voltage
via the bias-Tee (bottom figure)
Page 16
Noise on Vcc Test Demonstration
• DesignCon 2012 test system
demonstration
– JV9000A series instrument,
Oscilloscope, Bench-top
power supply, and DUT
(555 timer circuit)
• Block diagram of the
“Noise on Vcc” test system
Page 17
JV9000 Demonstration Results
• Top figure: 555 timer clock
signal displayed on an
oscilloscope
– Clean square pulse shape
• Lower figure: detail of rising
edge using zoom display
– Analog persistence: displays
multiple sweeps stacked
together
– No noise added to the signal
Page 18
JV9000 Noise Injection
• Top Figure: same rising edge
with 20dB noise increase
• Lower Figure: 30dB noise
increase from clean signal
Page 19
JV9000A Value Proposition
• R&D Instrument
– Broadband noise
– External synthesizer input
– Flexible instrument to experiment with different interference
types
• ATE Production Instrument
– Limited number of CW frequencies and Noise BW after R & D
evaluation
– Lower cost sub-set solution for production with discrete
frequencies and specific noise band
Page 20
Manual R & D Evaluation Unit
• R&D Instrument Value
– Manual operation for short learning curve
– Broadband noise
• Used to measure the system noise floor
• Test signal to graph DUT input impedance vs. frequency
– External synthesizer input to experiment with different
interference patterns
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ATE Production Unit
Production instrument
Lower cost sub-set solution with discrete frequencies that are a problem
for the DUT
Standard Ethernet and optional GPIB remote control for inclusion in ATE
systems
NI Labview VI’s for quick production line implementation
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Summary
•
All digital switching devices create noise
•
RFIC mixed signal IC and high frequency PLL’s are especially sensitive to noise
•
These devices employ bypass capacitors, power & ground plane filtering, and
separate digital and analog power and ground planes attempting to eliminate
noise
•
Mixed signal RFIC’s & HF PLL’s are used in hand held devices with radios and
microprocessors like smart phones, tablets, e-readers and notebook PC’s
•
These devices require sophisticated software modeling for noise immunity
testing
•
The Noisecom JV9000A series can be used to test the accuracy of these software
models
•
Broadband noise output
– Used to measure the test system noise floor
– Used to plot DUT input impedance vs. frequency
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Thank You for Participating
in Today’s Webinar
Any Questions?
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•
Please see us at DesignCon in Santa Clara, CA 2012
•
We will have knowledgeable Sales and Application
Engineers available to discuss your jitter issues including
Noise on Vcc, and 10 & 100GbE stressed receiver test
solutions
WTG Regional Technical Contacts
• Mr. James Lim – Republic of Singapore - JLim@wtcom.com
• Mr. Mazumder Alam – Parsippany, NJ – Malam@wtcom.com
• Mr. Stephen Shaw - Manchester, UK - SShaw@wtcom.com
• Mr. Bob Muro - Parsippany, NJ - RMuro@wtcom.com
For details please visit our official website at
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www.wtcom.com