Power Noise Suppression Technique using Active Decoupling
Capacitor for TSV 3D Integration
Tien-Hung Lin, Po-Tsang Huang, and Wei Hwang
Department of Electronics Engineering & Institute of Electronics, and
Microelectronics and Information Systems Research Center,
National Chiao Tung University, HsinChu 300, Taiwan
ABSTRACT
In three-dimensional
(3D)
integration,
Heavy current
density of power
network
the
increasing supply current through both package
TSV
and through-silicon-via (TSV) would lead to a large
simultaneous switching noise potentially. In this
paper, a noise suppression technique using low
power active decoupling capaCitors (DECAPs) is
proposed for TSV 3D integration. Through the
latch-based noise detection circuitry, the power
supply noise can be detected and regulated via
Fig. 1: Power integrity for TSV 3D integration.
active DECAPs. Based on UMC 65nm CMOS
technology and TSV model at 1V supply voltage,
manage the power supply noise. However, the
the proposed noise suppression circuit can realize
usage of the on-chip passive DECAPs is limited by
maximum 7.4dB supply noise reduction and 12X
two major constraints, including a great amount of
boost fact at the resonant frequency.
gate tunneling leakage and large area occupation
I. INTRODUCTION
have been proposed to reduce power supply noise,
[4].
the
can provide enormous advantages in achieving
integration,
improving
system
density of through-silicon-via (TSVs) and packages
impedance response is dominated by both the
serious problem for power integrity. In view of this,
decoupling
Fig. 2 shows the proposed architecture of the noise
suppression technique to reduce the supply noise.
perform as a local reservoir of charge, which is
This architecture contains four blocks: a low pass
released when the current load varies. Since the
DECAPs
significantly
affect
the
slowly,
design of
filter, a latch-based comparator, a charge pump,
the
and switched DECAPs. The prior three blocks are
the
designed to detect the resonant supply noise and
powerlground (PIG) networks in high performance
to control the switches of the switched DECAPs.
ICs and TSV 3D integration. At higher frequencies,
The details of each block are described as follows.
DECAPs are distributed on chips to effectively
978-1-4244-6683-2/101$26.00 ©2010 IEEE
noise
Depending on the heavy current loading of PIG
capaCitors (DECAPs) are widely used. DECAPs
scales
suppression
This
networks in 3D integration, the supply noise is a
problems for TSV 3D integration.
packages
UMC 65nm
technology.
II. Power Noise Suppression for 3D Integration
suppression will become one of the critical design
of
for TSV 3D integration based on
CMOS
based comparator and switched DECAPs.
the supply
packages and TSVs [3]. In view of these, noise
inductance
detection
technique reduces the supply noise using a latch­
exists in the power network and further increases
noise,
OP-based
leakage current in nano-scale technologies. In this
integrity [2]. Fig.1 shows the power integrity for the
power
and
paper, a noise suppression technique is proposed
TSV 3D integration. It is shown that heavy current
the
delay-line-based
However, the efficiency of these noise suppression
generations of ICs [1]. However, stacking multiple
suppress
techniques
techniques would be reduced significantly by the
dies would face a severe problem of the power
To
suppression
circuits with switched DECAPs, respectively [4, 5].
speed and reducing power consumption for future
the power supply noise. Moreover,
current
and the resonant supply noise is suppressed via
Three-dimensional (3D) integration technology
multi-functional
Therefore,
209
l----OECAP---1
1
charge cycle
1
-14
4
1
.I. Vdd
1
-I
.I. 2Vdd
dc1 I
fdC 1l�R
T
C
d2
T
Cd2
J
�T
parallel
�
High-VT
NMOS
Fig. 3: Resonant noise suppression using switched DECAPs.
A.
Fig. 4: Latch-based comparator with High-Vt•
Switched DECAPs
The
�uppress
switched
the
DECAPs
resonant
are
supply
designed
noise.
Fig.
filter induces the IR drop and further decreases the
to
reference
3
DECAPs.
If
the
power
overshooting than the Vdd_DC,
supply
In order to switch the DECAPs, a latch-base
thus,
comparator is designed to detect the resonant
noise. The supply voltage (Vdd) and the reference
additional charge can be provided for the power
voltage (Vdd_DC) are compared via the latch­
supply from DECAPs to reduce the supply noise.
based comparator. This comparator achieves not
Additionally, the hysteresis voltage levels are the
only good noise tolerant interval but low power
high/low boundary conditions for switching the
consumption. Fig. 4 shows the schematic of the
DECAPS from series to parallel and parallel to
latch-based comparator via High-V! transistor to
series, respectively. The switched DECAPs would
reduce
be switched only when the supply voltage is higher
leakage
power
in
nano-scale
based is higher than the on-chip supply voltage to
words, the hysteresis voltage provides a tolerant
detect the resonant supply noise. Additionally, the
interval and avoids frequent switches with a small
demand current of the comparator is very small
supply noise.
because
the
reference
voltage
(Vdd_DC)
is
connected to the gate of M1.
B. Low pass filter
The RC low pass filter provides the reference
the
the
technologies. The operation voltage of this latch­
or lower than the hysteresis voltage levels. In other
for
the
C. Latch-based Comparator
the
the boosted voltage would be twice Vdd DC. The
voltage
contains
current of the comparator should be small to
Cd2, respectively. On the contrary, if the power
And
current
generate a low-drop reference voltage.
would be transferred to the capacitors, Cd1 and
DECAPs would be connected in series.
The
current of the comparator. Therefore, the demand
is
excess charge
supply is undershooting than the Vdd DC '
voltage.
leakage current of the capacitance and the load
Illustrates the resonant noise suppression using
switched
High-Vr
PMOS
latched-based
comparator.
However, the current through the resistor of the RC
210
The frequency of the clock determines the
sampling rate of the comparison results. When the
clock is high, two discharging paths exist to pull
I'
T
.
I
clk
clk
I·
Fig. 5: Modified Dickson charge pump.
•
•
II
. • .
down n1 and n2. After a half clock cycle, M3 would
be turned off by the low level of the clock. And thus,
the discharging paths would disappear. Therefore,
the data in the weak back-to-back invertors would
IJm
Fig. 6: Layout view of the noise suppression circuit.
Vtnl.low '(0 y[)C-VDD)
be determined according to the charge in n1 and
n2. Additionally, two sampling latches capture the
comparison results at the positive edge of the clock.
The latched-based comparator switches the
switched
DECAPs
with
a
hysteresis
(1)
When ClK is high, the node n1 is pumped to
2Vdd-Vtnl-low. And thus, the threshold voltage of
than
the
threshold
voltage
when
the
body is
connected to ground. In view of this, the leakage
current from n1 to Vdd is reduced. In the following
voltage of n2 is high. While the vdd is a little larger
stages of the charge pump, the threshold voltage
the discharging time is not
of NMOS in each stage is the same as Vtn1. The
enough to flip the data in the back-to-back inverter
body
although the drain current of M2 is larger than that
bias
of
NMOSs
can
both
improve
the
pumping efficieny and reduce the leakage current
of M1. Until the Vdd is larger than the reference
by adjusting the threshold voltage.
voltage plus a hysteresis voltage, M2 has enough
Vtnl-high '(0 y[)CVDD -Vtnl-Iow)
driving ability to flip the data. Therefore, the data in
the back-to-back inverter would be changed and
the DECAPs would be switched into the series
2<11
�]
(2)
III. SIM ULATION RESULTS
stack. If Vdd is decreasing from the overshooting
state to the undershooting state,
�]
2<11
M N1 would be adjusted as Eq. (2) which is smaller
voltage.
Assume Vdd is increasing from the undershooting
state to the overshooting state, and the initial
than the vdd_DC,
•
The noise suppression technique with low
power active DECAPs is implemented via UMC
the switched
DECAPs would be changed to the parallel mode
6Snm CMOS technology and the TSV model [7].
as well as the Vdd is smaller than the reference
According to the speed of the resonant noise, the
frequency of the comparator is 2GHz. This clock
voltage minus a hysteresis voltage.
source is also provided to the charge pump at
D. Charge pump with improving body effect
For
the
latched-based
comparactor,
1GHz by a frequency divider. Fig. 6 shows the
layout
an
and
the
floorplan
of
the
noise
200pF. Moreover, 84% area is occupied by the
switched DECAPs which are implemented by MOS
operated in the saturation region. Additionally, the
capacitors.
hysteresis voltage level is influenced by the level of
The
size
of
the
proposed
noise
suppression circuit is 170x230 IJm .
VDDH and the widths of M1 and M2. With the
Fig. 7(a) and 7(b) show the suppressed noises
increasing of VDDH, both the hysteresis voltage
and power consumption increase. Therefore,
view
suppression circuit. The total value of DECAPs is
additional higher voltage (VDDH) is applied to
ensure that the transistors, M1 and M2, are
resonated at 100MHz and 40MHz, respectively.
a
The two configurations of the pads are set as
modified Dickson charge pump is designed to
pump the VDDH to 1.6V. Fig. S shows the modifed
circuits from the Dickson charge pump [6]. The
l=O.7SnH,
C=1.69nF,
C=1.69nF,
R=O.28 ,
R=O.14
and
l=4.SnH,
which represent a typical
supply impedance for high performance chips [4]
bodies of M N1, MN2 and M N3 are connected to
and
their drains to adjust the threshold voltage and
the footprint and
TSV impedance in
3D
integration. Since the number of the power pins
further increase the efficiency of the charge pump.
When the clock is low, the node n1 is charged
to Vdd-Vtnl-Iow, where Vtnl-Iow is shown as Eq. (1).
would
2D-ICs.
Therefore, Vtnl-Iow is smaller than the threshold
be
limited
in
3D
integration,
and
the
inductance of the package would be larger than the
Compared to the
same
value
of
the
passive capacitance, the active DECAP can realize
voltage when the body is connected to ground.
211
Table1' Comparisons of active DECAPs
-----
Delay Line
Analog OP
Latch-based
141
151
Comparator
Technology
0.13 um
90 nm
65 nm
Static Power
0.65 mW
2.9 mW
0.55 mW
Hysteresis
Voltaae
OmV
5mV
17mV
40mV
50mV
17mV
Triggered
Voltaae
would face leakage problems when shrinking to
50
o
Frequency (MHz)
(a)
nano-scale technologies. The static power of the
200
150
100
proposed scheme is 0.55 mW. In the latch-based
comparator, the demand current from the RC filter
Passive (200pF)
is small because the Vdd_DC is connected to the
80 ................... .. ............................................................
gate of M1 as shown in Fig .4. For the delay-line­
based comparator,
the current of the constant
delay line flows through the resistor and induces
40mV drop. It not only affects the switching timing
but decreases the boost factor. Therefore,
the
proposed scheme can realize not only good noise
tolerant interval but low power consumption.
o
50
100
150
Frequency (MHz)
(b)
v. CONCLUSIONS
200
In TSV 3D integration, the supply noise would
Fig. 6: Noise suppressions of the active and passive DECAPs
be increased with the increasing current density of
for (a) high performance IC (b) TSV 3D integration.
the power network. A noise suppression technique
the improvements of 55%
(6.9dB)
for TSV 3D integration is proposed to reduce the
and 57.6%
supply noise by the latch-based active DECAPs.
(7.4dB) noise reductions for the high performance
IC
and
TSV
3D
integration,
Based on UMC 65nm CMOS technology and TSV
respectively.
model, the proposed scheme can realize maximum
Additionally, in order to evaluate the boost factor of
7.4dB supply noise reduction and 12X boost fact at
the proposed active DECAP, a great amount of
passive DECAPs are traced to achieve the similar
the resonant frequency. Therefore, the proposed
noise
passive
noise suppression circuit can provide a stable
DECAPs with 3400 pF and 2400 pF are deployed
power for the power integrity in TSV 3D integration.
suppression.
Therefore,
the
for the similar noise regulation. And thus, 17X and
12X boost factor can be achieved based on the
REFERENCES
proposed noise suppression circuit. Moreover, the
1.
2.
Table1 lists the comparisons between the
hysteresis
is
voltage for the latch-based
17mV
to
avoid
the
is
between
9mV
to
31mV
Implication,"
Electrical
W. Ahmad, et aI., "Power Integrity Optimization of 3D
perform. Electron. Packaging Syst., pp 105-108, Oct. 2009.
P. Jain, et aI., "A Multi-Story Power Delivery Technique for
3D Integrated Circuits," Proc. IEEE Int. Symp. Low Power
4.
X. Meng, and R. Saleh," An Improved Active Decoupling
Electron. and Des., pp. 57-62, Aug. 2008.
Capacitor for Hot-Spot Supply Noise Reduction in ASIC
across
different process corners from -50-125°C.
Design
3.
continuous
switches if the supply noise is small. The range of
hysteresis
and
Chips Stacked through TSVs," Proc. IEEE Conf. Electrical
proposed active DECAP and other approaches [4,
comparator
Modeling
perform. of Electron. Packaging, pp 205-208, Oct. 2007.
59% due to the reduced DECAP area.
5]. The
G. Huang, et aI., "Power Delivery for 3D Chip Stacks:
Physical
leakage power can also be reduced by 71% and
Designs," IEEE J. Solid-State Circuits, Vol. 44, No. 2,
The
5.
delay-line- based active DECAP uses two delay
pp584-593, Feb. 2009.
J. Gu, et aI., "On-Chip Supply Noise Regulation Using a
Low-Power Digital Switched Decoupling Capacitor Circuit,"
line with biasing starved inverters to compare the
supply noise. However, the delay line using the
6.
bias scheme is too sensitive when the noise is
IEEE J. Solid-State Circuits, pp1765-1775, Jun. 2009.
J.-T. Wu and K.-L. Chang, "MOS Charge Pump for Low­
Voltage Operation," IEEE J. Solid-State Circuits, Vol. 33,
large. The comparisons would be wrong since the
7.
difference between the two delay lines is more
No. 4, pp. 592-597, Apr.1998.
I. Savidis and E.G. Friedman, "Closed-Form Expressions
of 3-D Via Resistance, Inductance, and Capacitance,"
than one clock cycle. Moreover, this approach
IEEE Tran. on Electron Device, Vol. 56, No. 9, pp. 1873-
1881, Sept. 2009.
212