TECHNOLOGY FEATURE
Very high-speed sampling and serial
ADCs in embedded systems
By Thierry Wastiaux
Latest-generation active electronically scaled array (AESA) radar systems can have thousands of TX/RX modules. High
bandwidth is needed to connect each array element data converter to the FPGAs that process incoming and generate outgoing
data streams. New software-defined radio systems use advanced reconfigurable modulation schemes that increase channel
bandwidths and deliver unprecedented wireless data rates. To increase the performance of software radio and electronic warfare
systems, it has become critical to use efficient, low-power, low-pin-count, FPGA-connected converter interfaces.
As the performances of analog-to-digital
converters (ADCs) are quickly improving,
the classical approach of transmitting
samples through low-voltage differential
signaling (LVDS) reaches its limits. LVDS
lanes connected to last-generation FPGA
I/O are limited to around 1.4 Gbps. As an
example, when targeting a four-channel
FPGA Mezzanine Card (FMC) with 12-bit
analog to digital sampling at 2.6 GSps, a
minimum of 96 LVDS lanes is required for
data only, without taking into account
the clock and service signals. This is not
possible on standard VITA 57.1 connectors, and it takes too much I/O resource
on the FPGA.
The insatiable demand for data sampling
thus has led to the need for the standardization body JEDEC to introduce
the JESD204 standard for a high-speed
serial link between data converters and
logic devices. Serial link data rates have
been pushed up to 12.5 Gbps in the last
revision “B” of the standard, released in
2011 for higher-bandwidth requirements.
This revision also includes provisions for
“deterministic latency” of data transfers.
Simplification of design
Compared to the classical parallel
approach, the improvements brought by
JESD204 are many. By moving from highpin-count, low-speed to low-pin-count,
high-speed serial interface, the overall
system design is simplified with a smaller
number of trace routes and easierto-route board designs. The links use
8b/10b encoding, which incorporates
an embedded clock, enabling further
pin-count reduction by removing the
necessity for routing an additional clock
line and the associated complexity of
aligning an additional clock signal with
the transmitted data at high data rates.
In addition, trace-to-trace tolerances
are relaxed relative to synchronous sampling parallel LVDS signals. All these
simplifications in the design eventually lead to cost reduction. Moreover,
this allows reducing the size of the
ADC components, as the output pins
required for FPGA connection are less
numerous using the low differential
swing DC-balanced high-speed current
mode logic (CML) standard. Thus, it can
further increase the number of components on the small FMC footprint.
It must be noted that the last generation
of serial ADCs implements digital downconverters with variable decimation
ratios that provide filtering and reduce
the output data rate. They might include
frequency translation stages (numerical
controlled oscillators), finite impulse
response (FIR) filtering stages, gain
stages, and complex-to-real conversion
stages. Numerically controlled oscillators
(NCOs) and digital mixers allow tuning
the center of the bandwidth of interest
14 | VITA Technologies Resource Guide Spring/Summer 2016
to baseband. The filtering stages allow
filtering the unwanted part of the spectrum. Gain stages allow compensating for
mixer and NCO losses. And complex-toreal conversion enables presenting the
final real signal of interest.
These down-converter features dramatically reduce the complexity of radio and
radar systems, using part of the FPGA
resources to implement these functions.
The FPGA capacity is fully used for the
important signal processing part as
beamforming for radars, for instance.
Deterministic latency
It is important to know the timing relationship between the sampled signal
and its digital representation. This
timing relationship is affected by the
latency of the converter, which is defined
for an ADC as the number of clock cycles
between the instant of the sampling
edge of the input signal until the time
that its digital representation is present
at the converter’s outputs. This latency
is typically in the range of several nanoseconds in classical parallel ADCs. In
JESD204B, this latency is increased by
the process of serialization even if the
speed of the sampling data transmission
lanes is much higher. This latency can
typically be several tens of nanoseconds.
JESD204B-compliant receivers are outfitted with an elastic buffer that is used
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to compensate for skew across serializer/
deserializer (SERDES) lanes, which simplifies board layout. This elastic buffer
stores the data until the data from the
slowest lane arrives. It then releases the
data from all lanes simultaneously for
digital processing. This skew management is possible because the data clock
is embedded in the serial data stream.
While the JESD204B standard has simplified multichannel synchronization
by using deterministic latency, minimal
latency is needed in some applications
such as electronic warfare (EW) and radar
applications where actions are required
immediately after detection. For these
applications, the LVDS interface should
still be considered, as the JESD204Bcompliant data converter’s delay in serializing the data is omitted. However, applications such as radar warning receivers
(RWR) or COMINT that are receiver-only
applications tolerate the latency brought
on by the JESD204B serialization. These
applications thus can benefit from the
last generations of ADCs driven by the
mass market of telecommunication infrastructure, allowing very high-speed sampling and reducing the complexity of the
analog part of the system.
The FMC standard defines a small format mezzanine, similar in width and height
to XMCs or PMCs, but around half the length. As real estate is limited, some features have been included in the standard. First, to save space, its primary power is
supplied by the FPGA carrier board. During the power-up sequence, the host interrogates the FMC as to what the feeding voltage must be. In addition, FMCs directly
connect the I/O devices on the mezzanine to the host FPGA via a high-speed, highdensity connector as if the device was on the host itself, leading to logic reduction
and saved space.
The first generation of the FMC standard allows up to 160 for high-pin-count (HPC)
or 80 for low-pin-count (LPC) “parallel” I/O signals and up to 10 full-duplex highspeed serial connections (along with some clocks). Figures 1 and 2 shown on page 16
depict an Interface Concept ADC FMC, the IC-ADC-FMC, which can be plugged on
a Virtex-7 FPGA carrier board, the IC-FEP-VPX3c, featuring eight high-speed transceivers in front of the mezzanine’s high-speed serial (HSS) links.
FPGA vendors have developed fully
compliant JESD204B intellectual property (IP) that can be implemented in their
products for communication with the
serial ADCs. For example, the JESD204B
Xilinx IP supports 256 bytes per frame
and 32 frames per multiframe. It can be
configured to support up to 32 lanes.
Flexible design follows the fast
moving market of ADCs
In combining the technologies available
on ADCs including the new JESD204B
standard and FPGAs, EW system architects can dramatically improve data
sample processing. FMC (VITA 57 standard), promoted by the VITA FMC
Marketing Alliance, allows high data
throughput and very low latency response
between an ADC or a digital-to-analog
converter (DAC) FMC and the FPGA,
simplification of the design, and above
all, the cost-efficient ability to simply
retarget an FPGA carrier card design. All
that is required is swapping out the FMC
module and adjusting the FPGA firmware.
That is why the standard has become the
open standard mezzanine of choice.
www.vita-technologies.com
VITA Technologies Resource Guide Spring/Summer 2016 |
15
TECHNOLOGY FEATURE
At the inception of the FMC standard, the HPC specification appeared as satisfactory
in terms of the number of allowed I/O. The evolution of ADC technology, as well as
the increasingly demanding requirements of EW system designers, has highlighted
the need to go beyond this first version of the FMC standard.
An effort to define suitable FMC enhancements is now underway within the VITA 57.4
working group. The focus is on creating a standard with an increased number of HSS
links (increased from 10 to 24) operating at increased speed while keeping the existing
connector pinout for I/O. The HSS link throughput is targeted at up to 28 Gbps,
extending the aggregate bandwidth to the huge level of 672 Gbps, to which the
traditional LVDS links can be added. Backward compatibility is ensured by adding to
the FMC connector’s outer columns for additional signals without changing the form
factor, real estate, or mechanics (mounting holes, thermal interface, and so on). The
approval of this new standard is currently in process.
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16 | VITA Technologies Resource Guide Spring/Summer 2016
›
Figure 1 | IC-ADC-FMCc quad 12-bit
1300 MSPS FMC
›
Figure 2 | IC-FEP-VPX3c Virtex-7
carrier with one VITA 57.1 FMC slot
The future of converter
digital interfaces
The industry is requiring better performing ADCs, leading to huge sample
data flows. The big push of the ADC
industry has led to the development of
the JESD204B standard. Looking to the
future, it is clear that JESD204 is poised
to become the industry choice for the
digital interface to converters. Each
revision has answered the demands for
improvements on its implementation
and has allowed the standard to evolve
to meet new requirements brought on
by changes in converter technology. As
system designs become more complex
and converter performances increase,
the JESD204 standard should be able to
adapt to meet the new design requirements necessary.
Thierry Wastiaux is senior VP of
sales for Interface Concept. He has
25 years of experience in the telecom
and embedded systems market. Prior
to joining Interface Concept, he was
responsible for the operations of the
Mobile Communication Group and the
Wireless Transmission Business Unit at
Alcatel-Lucent. He holds an MSc from
Ecole Polytechnique France.
›
Interface Concept
twastiaux@interfaceconcept.com
www.interfaceconcept.com
www.vita-technologies.com