Power Supply Design Parameters For Switching-Noise
Control In Deep-Submicron Circuits Design Flows
M. Graziano, M. Delaurenti, G. Masera, G. Piccinini and M. Zamboni
Electronic Department, Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129
Torino, Italy
Abstract. In the high performance integrated circuits phenomena like crosstalk, IR
drops, electromigration and ground bounce are assuming increasing proportions because of the growing complexity in ultra deep submicron designs: their consequences
are assuming increasing dimensions compromising circuits functionality and not only
their performances.
This paper suggests a methodology to evaluate and to prevent power supply
noise generation in more and more increasing dimensions circuit blocks. The power
supply busses modeling is addressed to find out actual parameters to face early in
the design phase noise phenomena related to power distribution. In particular using
the equations reported in this paper the designer has the possibility to control the
global power bus noise generation depending on the design strategy used, on the
library characteristics and on the given performance constraints.
The appropriateness of the developed methodology seems to be helpful if applied
during the circuit design flow in conjunction with a project tool having as a target
noise reduction besides delay and power optimization.
1. Introduction
The complexity of ultra deep submicron chip design and layout continues to grow driven by increasing speed, chip size, and interconnect
density due to technology scaling down and the high number of metal
levels used. This leads to phenomena, namely crosstalk, IR drops, electromigration, ground bounce, menacing not only performances but also
functionality. The greatest difficulty in tackling these noise problems
during an automated design flow is their non-local increasing proportion, i.e. they are quite negligible when a single gate is considered,
whilst, on the contrary, noise failures depend on the environment due
to the type of neighbour gates, their number and their connections.
From the time-to-market point of view, trial and error methodology is too expensive: for this reason facing these problems during
the chip design process is of basic importance. The way to front noise
phenomena is generating verification tools able to analyze their noise
consequences at the end of the project flow, or developing design tools
facing early in the design sequence the potential noise generation. These
two techniques are not in competition, but, surely, validation can be
c 2001 Kluwer Academic Publishers. Printed in the Netherlands.
°
alog.tex; 29/01/2001; 15:08; p.1
2
more efficiently performed when a good prediction and a noise safety
design have been executed.
This paper focuses on a power supply model thought-out to be inserted in a developing tool for interconnect parameters prediction and
noise safety design. In particular, in §2 the noise problems considered
in this paper is briefly defined together with the solutions currently
adopted as state of the art. In §3 a model is proposed and an accent is
given on its adaptability to the prediction of design parameters; the
purpose is its integration in a noise safety design tool that is not
explained here because this is not the aim of the paper. Details can
be found in [15].
2. Power Supply noise
2.1. The phenomenon
Power supply noise is multi faced, for it involves both physic and circuital phenomena and its impact and complexity grow with UDSM
integration. Without the purpose of giving an exhaustive exploration
of noise in deep-submicron circuits (for which see also [7, 9, 32, 37]), in
the following we will consider the relationship among high performance
issues and noise effects due to power supply lines [19, 20, 29, 31, 28].
Transistor sizes scaling down implies overall an increased number
of gates without total chip area changes. Considering a standard cell
layout style, this means a greater number of gates on a row; this fact is
affected also by the number of circuit blocks used if a system on a chip is
considered, but this doesn’t change the nature of the phenomenon. Taking into account other phenomena, this leads to an increased amount of
current on power supply lines [1]. The amount of area devoted to GND
and VDD increases then to assure electromigration safety because of
the higher total maximum current on the line. Moreover, total current
increment has as a consequence a raise in the IR drop on voltage reference, if parasitics resistance is considered on a metal line.
The spurious GND or VDD signals can affect the functionality of the
gate due to three different causes [14]. First, the non-ideality of the references can delay the transistor switching and then can worse the total
delay of the gate. Second, spikes on power supply can, by capacitive
coupling, change or destroy the precharged nodes of dynamic CMOS
gates. Finally, technology scaling down decreases transistor threshold
voltage making them more sensible to spurious signals on their gate
coupled to voltage reference lines.
The further point connected with transistor sizes scaling down is
the increased frequency of the clock signal. This leads to an higher
alog.tex; 29/01/2001; 15:08; p.2
3
gate switching activity with two different consequences.
First, the higher frequency of current peaks makes life time of metal
strips lower due to the increased electromigration risk. Time-to-failure
of a metal strip [5], indeed, depends directly on the average current
density; but it is influenced by the temperature as well, that depends
on the RMS current: this varies for different frequencies of the peaks
[4].
Second, high frequency is associated to decreased clock rise times: this
relates to higher L dI
dt due to on chip and package inductances, having
as a result a further worsening of supply references [18].
Besides, technology scaling down involves interconnections too and
power supply lines in particular: as line width shrinks, the number of
squares increases, causing an increment in the total resistance along
the line; IR drop enlarges additionally due to resistance grown.
These voltage overshoots on power supply lines are then dangerous
for the gates connected in the same row, but are also risky for signals
traveling on different lines routed not sufficiently far from them. If the
first countermeasure for crosstalk between lines was in the past to interpose GND or VDD lines, now, if such lines are not strongly decoupled
from noisy power supply lines, this remedy is not only useless, but even
hazardous.
Furthermore a global issue connected with supply lines is EMI radiation towards neighbour circuits caused by high-frequency current.
Basically it is possible to distinguish three different mechanisms [41],
[33]. One is the direct radiation from the chip surface: high frequency
current flows through metal wires inside a chip and acts as antennae.
The second effect is conducting noise from the signal ports of the chip.
This noise is transferred to data buses on PCB, connectors and cables.
All those off-chip conductors acts as antennae. Finally, the third effect,
power line conducting noise, is the most significant in terms of EMI.
Finally, in mixed-signal designs analog circuitry suffers from power
supply ground bounce injected into the substrate via bulk contacts,
reverse biased PN junctions acting as capacitances, and body effects
[2],[39].
To corroborate the importance of power supply noise we realized a
set of simulations of a row of cells increasing in number (figure 1).
The power busses are modeled with parasitic impedances distributed
along the line. For the results reported in figure 1 the impedance is a
series of resistance and inductance figured out from GND and VDD
line dimensioning.
Different sets of simulations have been realized, in which different values
of inductance have been used. To have an idea of the noise energy, the
alog.tex; 29/01/2001; 15:08; p.3
4
Row of cells simulation results
3.5
200 gates
400 gates
600 gates
Noise Overshoot [V]
3
2.5
2
1.5
1
0.5
300
400
500
600
Noise Width [ps]
700
800
900
Figure 1. Row of cell simulations results. The number of gates varies from 200
to 600. The distributed resistance of the line is figured out via the current peak,
the electromigration safety paradigm given for the technology used (0.25µm, 2.5V
power supply) and the total length of the line with a trial and error method. Worst
noise overshoot [V] is reported as a function of worst noise width [ps] on GND line.
Three different cases were considered: distributed inductance of the line (0.2pH the “box” point of each reported line), package inductance at a very low value (1nH
- the “triangular” point of each reported line), package inductance at a maximum
value (10nH - the “circle” point of each reported line).
overshoot is measured in terms of peak (maximum voltage difference
with respect to the ideal reference value) and width (time duration of
the overshoot in which the reference has a value different from the ideal
one).
As expected when the number of cell grows the noise peak increases
too, arriving in the worst case at 1.13 V when no package is considered.
When package inductance is inserted the overvoltage grows, but in
the case of 10nH, the voltage peak is lower than the corresponding
measured in the 1nH case; its width becomes nonetheless so wide that
these signals can no more be considered as a reference for the gates in
the row, being the total noise energy no more endurable. In this case,
indeed, the behaviour of the cells was completely wrong.
The reason why the peak is lower when the inductance has the higher
value is in the following. As showed in [8], particular attention should
be used when placing capacitors to decouple the package. The system
“package plus chip” has indeed two operating modes: the one imposed
by the clock and the other intrinsic to the system. The frequency of this
last mode depends roughly on the inductance and capacitance values.
If this frequency is superposed to the frequency due to the clock (in
alog.tex; 29/01/2001; 15:08; p.4
5
this case the frequency of the current flow in the power bus), the peaks
correspondent to the two energies are superposed too, leading to an
overvoltage higher than the expected one. The decoupling capacitance,
that is, the only variable of the system, should be correctly dimensioned, such as the two frequencies are decoupled.
The inductance values used in the reported simulations are chosen to
show this phenomenon: in the 1nH case, the two frequencies are exactly
superposed, while in the 10nH case are completely decoupled. For this
reason the voltage peak is higher in the first case, and the noise width
is larger in the second case.
However, this is only to show how much the power supply sizing
influences noise generation; moreover, when a great number of cells is
connected to the same power supply pair, the references fluctuate in a
not negligible amount, giving as a result a worsening in the gate delay
[20] and sometimes causing no more recoverable errors [14].
This reflects the fact that a rapid noise peak, even of high value, is
dangerous for memory nodes storing a data, but in the case of other
nodes it causes only a delay. On the contrary, a wide noise waveform,
even if it has a lower peak value, causes an abnormal behaviour of the
gates for a longer time: if this interval is of the same order of half a
clock period the probability of a logic error is highly increased.
2.2. Countermeasures
When noise and EMI problems, mainly due to output buffers towards
output pads, were first faced [3], external bypass capacitors were used
to supply current to the IC, shortening the current path. This method is
no longer satisfactory, basically since, if the amount of current increases
and if the die size grows, external capacitors are located too far from
the point they are intended to supply. The next development has been
placing the decoupling capacitors also inside the circuit block to directly
supply current upon it. Unfortunately, as a drawback the chip footprint
increases. To elude this, the capacitors are being formed in unused
space, such as under power supply or ground wiring, and filling empty
regions [35].
However as the noise problem increases, a larger and larger amount of
area should be devoted to capacitors; additionally, perimeter capacitors
can decouple the circuit from the package and from the external circuitry but are not able to avoid IR drop inside the circuit block [36]. For
this reason the trend is the insertion of distributed capacitors as near
as possible to the gates forming circuit blocks critical from the point of
alog.tex; 29/01/2001; 15:08; p.5
6
view of switching noise [30]. The authors give in this paper some design
parameters for the optimized insertion of distributed capacitors.
The parallel approach has been thus to reduce excess performances:
adjusting transistor size for minimal cost, or operating the circuits
inside a chip at a low voltage, or inactivating part of the circuit by
halting the clock signal [22].
Another different attempt is to stagger the gates that are switching together such that they switch at slightly different times, at least enough
to keep the problem within the noise budget [13].
Another efficient measure adopted to decrease wire resistance is to
use copper metalization instead of aluminum [37, 38]. Finally electromigration failures can be reduced in several ways. The basic idea in all
approaches is to reduce the average current density in a metal segment.
These topological and technological solutions are not in competition
with power bus sizing methodology, to which this work would give some
contributions.
In particular, one of the used approaches is to widen the lines, decreasing in this way resistance and then IR drop, but this may not always be
possible due to constraints in the routing area. This method should be
used carefully to avoid the risk of over-designing the line width. One
of the aim of the model proposed in this paper is to give a relation
between line sizing, power supply noise and constrains on the number
of gates that can be abutted along a power bus.
2.3. The importance of power supply design parameters
prediction
All these countermeasures are useful even if sometimes they have a
few drawbacks. The main problem of all these approaches is that in
most of the cases they are strongly joined to designer intervention and
judgment: with the increasing of noise problems in more and more
complex circuits, this is too elaborate and prone to errors. Therefore
the design tradeoffs that satisfy all the necessary constraints are too
complex to handle without tools that provide visibility into specific
problems and their locations on the chip.
For this purpose it is almost of primary importance that interconnection informations are available throughout the design process, so that
the circuitry can be designed and placed using these informations as
an essential constraints. The placement of gates, indeed, is typically
based on the timing requirements of a system, and the size and shape
of blocks is estimated in the floorplanning stage. Alternatively these
design stages should consider as constraints the aftereffects in term of
IR drop and related noise problems. Consequently, sizing the busses
alog.tex; 29/01/2001; 15:08; p.6
7
properly to minimize IR drop while satisfying the required timing and
area constraints is now a design challenge that can only be met if the
behaviour of the power supply is analyzed during floorplanning and
placement.
In the following a model for power supply busses associated to the
corresponding noise phenomena is presented. It has been developed
with the objective to afford the designer with parameters useful to
predict the noise behaviour, given technological and circuit parameters.
Furthermore it has been studied to be easily inserted in an automated
tool having as a purpose noise reductions in high performance circuits
[16].
3. A model for design parameters determination
The purpose of the paper is the explanation of an analytical method
for generating power supply noise evaluation and design parameters.
The final aim, even if not completely fulfilled by the work presented
in this paper, is to create a methodology that can be used in a CAD
tool for power supply noise analysis. This should be accurate enough to
achieve design parameters not too far from the optimal values in terms
of noise and area, but not extremely heavy in terms of computational
complexity.
For this reason in §3.1 will be overviewed the parasitic parameters
relative to a single segment of the power line, without the purpose being
complete (see [17]). An accurate model can be inserted in the reasoning reported in the core of this paper without twisting the proposed
methodology.
The line model used will be considered in §3.2 and in §3.3, while further design parameters for area and noise optimization will be reported
in §3.4 and §3.5 respectively.
3.1. Power supply line segment modeling: how to evaluate
capacitance, resistance and inductance
In general the distributed parasitics in a segment for line and substrate
can be represented with an RCLG model as in figure 2. In practice,
the line is modeled as a distributed RCL model, while the substrate is
described by means of its capacitance and conductance: in the following
some considerations will be made to further simplify the model.
Three modes of operation for the substrate can be distinguished [25].
The dielectric mode is the operation at high frequencies: in this case
we may assume GS = 1/RS = 0 and consider just the substrate as
alog.tex; 29/01/2001; 15:08; p.7
8
R
metal line
L
oxide
C ox
substrate
RS
backplane
CS
Figure 2. RCLG model for a line segment.
a capacitance. The dielectric mode starts at the substrate relaxation
frequency given by:
fr =
1 GS
1
=
2π CS
2π²S ²0 ρ
(1)
where ²S is the substrate dielectric constant and ρ the substrate resistivity.
The skin depth mode is when the substrate starts to be an important
parameter as part of the current flows through it and causes fluctuations.
At low frequency, the substrate enters in the slow wave mode: its
conductivity is so high that it becomes a short circuit bypassing the
capacitance CS .
When the substrate is in the slow wave mode, the capacitance is the
oxide one, that is the one in equation (2):
Cox = ²ox ²0
W
tox
(2)
When the substrate acts as a dielectric, the capacitance will be the
series of the oxide capacitance and the substrate capacitance:
CS = ²S ²0
C=
W
tS
Cox CS
Cox + CS
(3.1)
(3.2)
Since the CS is very small with respect to the Cox when the substrate
is in the dielectric mode, the line capacitance C is of the same order
of CS . Thus, as the frequency increases, the capacitance component
versus the substrate goes from an upper value equal to Cox to a lower
value that is approximatively negligible.
If the frequency is greater than fr , and if the metal considered is the
alog.tex; 29/01/2001; 15:08; p.8
9
first level, the capacitance can then be neglected and the line can be
modeled as a series of a resistance and an inductance. This is exactly
the condition in which the model reported in the following paragraphs
has been developed. Using indeed a substrate doped p-type with NA =
2 · 1015 cm−3 [27], for example, its resistivity will be as in equation (4)
ρ ' (qNA µp )−1 ' 6.5 Ω · cm
(4)
and as a consequence the relaxation frequency computed using the
expression in (1) will be as in (5)
fr = 1.23 GHz
(5)
Figure 3 shows the frequency spectrum of the noise signals traveling
on the ground and VDD lines resulting from one of the simulations
presented in the previous sections.
FFT:
Wave
D0:A2:fftvdd
Vdd
line
Symbol
2
1.8
1.6
Result (lin)
1.4
1.2
1
800m
600m
400m
200m
0
0
10g
20g
30g
FFT:
Wave
D0:A2:fftgnd
Symbol
40g
50g
60g
Result (lin) (fftvdd_ind)
ground
70g
80g
90g
100g
70g
80g
90g
100g
line
2
1.8
1.6
Result (lin)
1.4
1.2
1
800m
600m
400m
200m
0
0
10g
20g
30g
40g
50g
60g
Result (lin) (fftgnd_ind)
Figure 3. Fourier transform (FFT) of the noise signals traveling on lines affected by
switching noise
The noise spectrum covers a range of frequencies going from 1 GHz
to 65 GHz: given a relaxation frequency of 1.23 GHz as found in (5),
almost the totality of the signal energy is located at high frequency.
alog.tex; 29/01/2001; 15:08; p.9
10
For this reason, for the first metal layer it is possible to neglect the
capacitance of the line towards ground.
In a complete model regarding a whichever metal level, the capacitance of the line cannot be neglected, even if it would increase the
computational complexity of an automated tool using it for power supply noise estimation. It is expected that the methodology proposed in
the paragraphs below wouldn’t be affected, but that the power supply
noise prediction would be less pessimistic if the line capacitance would
be inserted in the model.
Since the power distribution network may cover a wide area, the wire
resistance is not negligible if we want to do a chip level analysis. Until
new low-resistivity materials as copper will be available, the resistive
phenomenon is the dominating one inside the chip.
The per-unit-length resistance of a metal line is given by:
R=ρ
1
R¤
=
th W
W
(6)
where ρ is the metal resistivity, th the wire thickness and W the line
width; R¤ is the wire sheet resistance. The total wire resistance can be
obtained multiplying the per unit length resistance by the line length.
The resistance of a wire depends only on the technological parameters
and decreases linearly with the line width; usually th is fixed by the
process, while W is a parameter under the designer’s control. Moreover,
the line width value is chosen tacking into account the electromigration
safety paradigm, which firstly depends on the amount of current density flowing along the line; this is known as Black’s law [5] and states
that electromigration failures follow kinetics that depend on the inverse
square of the current density
t50 =
A
Ea
exp
2
j
kT
(7)
where t50 is the median time to failure in an ensemble of sample material, and Ea is the activation energy. As a practical rule, empirical
laws are used based on (7), on the material and processes used by each
foundry and on current flowing along the line.
Another parameter that influences the global line resistance is skin
effect, which increases the effective resistance values if frequency is
high [11]. At DC, indeed, the charge carriers have an even distribution throughout the section of the wire. As the frequency increases,
a rotational magnetic field around the conductor induces a current in
the metal that opposes the original current. This oppositely-directed
current forces the original current to move outwards to the edge of the
alog.tex; 29/01/2001; 15:08; p.10
11
conductor, decreasing the effective section of the wire and increasing the
apparent resistance. The area through which the charge carriers flow
is referred to as skin depth, and is defined as the depth of penetration
into the conductor at which the current decrease to 1/e (1 neper = -8.7
decibels) and identified by equation (8):
1
δ=√
πf µσ
(8)
where µ is the permeability and σ is the conductivity of the material.
With the achieved frequency in current VLSI circuits, skin depth must
be taken into account when calculating effective resistance values. For
sake of simplicity, in this work the authors don’t consider skin effect
influence, knowing that, in an complete analysis it should be inserted in
the model presented below. The authors consider that the approach for
power supply noise evaluation developed in this work will be affected by
the presence of skin effects in terms of resistance evaluation, but not in
terms of methodology. The expected effect is an increasing of IR drop
value when the frequency of the current flowing along the power supply
line is risen.
Finding the inductance is not as simple as for the resistance. Indeed,
it doesn’t depend only on the technology, but also on the physical layout
and on the influence of neighbouring wires [21].
Inductance effects are due to the generation of a magnetic field for
the presence of time-varying currents along a path, and, normally the
path considered is a loop: the flux arisen is proportional to the area
of the loop. In determining the on-chip inductance the problem is connected to the difficulty in finding the return path of a wire, especially
with the growing circuit complexity.
Actual inductance evaluation is still an unresolved problem and is one
of the more challenging issues discussed both in industry and academia
[6, 26]. Although 3D electromagnetic full wave solvers are available,
they cannot manage the complexity of today’s integrated circuits. To
model the inductive effects of intermediate buses a fast automated
inductance extraction and verification tool will be necessary.
Accurate measurements and modeling show that the inductive effects
are more prominent for lines of intermediate lengths (mm-scale): in [23]
a coplanar waveguide case, where a signal wire is sandwiched between
two ground wires, is considered to evaluate the inductance behaviour.
Results show that inductance increases monotonically with the spacing
between the wire and ground lines; current returns through the closer
ground line in the case of smaller spacing. Larger spacing distributes the
return path of the current between the two ground lines and increases
alog.tex; 29/01/2001; 15:08; p.11
12
w
metal
oxide
electric
field
magnetic field flux lines
h
substrate
bulk metal
Figure 4. Behaviour of the magnetic field for a metal wire
the current return loop and hence inductance.
Moreover, mutual inductance is a no more negligible problem related
to the high interconnection density in today’s VLSI circuits. Finally,
skin effect is another problem connected to inductance evaluation (as
explained for resistance), especially for mutual inductance evaluation:
higher frequency results in smaller inductance because of skin effect.
The authors will consider in this work a single, isolated wire, to
understand roughly the relations between line geometry and the inductance value used in the model, remembering that the aim of the work
is early power supply design parameters prediction.
The inductance of a loop on which a current is flowing is defined as
the ratio of the flux through the loop of the magnetic field produced
by the current to the current itself. Since in general the substrate is
not conductive enough (at high frequency it behaves as an insulator
[24]) to prevent penetration by the magnetic field, the loop will have a
height equal to the substrate thickness (see figure 4).
An empirical extremely simple expression for per unit length inductance of a line is found in [34, 40] and reported in equation 9:
µ
µ
8h
w
L=
ln
+
2π
w
4h
¶
(9)
where H is the height of the loop.
Notice that in general h À w: this means that varying the line width
has a small influence on the per unit length inductance of the wire
(moreover, the relation between L and W is logarithmic). In the following, this relation will be used, even if in a more complete model, a
more complex evaluation should be considered.
alog.tex; 29/01/2001; 15:08; p.12
13
3.2. A general formulation for power bus modeling
For a more comfortable reading only modeling and equations for GND
bus has been reported in this paper, being the VDD formulation exactly
the dual.
The model for the ground bus of a row of N gates is sketched in
figure 5, where for the gate i its Ipi current is considered, and where
the impedance Zi represents the distributed parasitics of the metal line
corresponding to the segment interested by the ith cell.
The current at node i can be easily written as a function of current
at node i + 1 and of injected current Ipi , and the former can again be
recursively seen as a function of current at node i + 2 and of injected
current Ipi+1 :
Isi = Ipi + Isi+1
= Ipi + Ipi+1 + Isi+2
Finally, at the initial node of the chain the current is a function (10)
of the current at the final node N + 1, injected from neighbour circuits
(called hereinafter entry current), and of the current injected by all the
cells connected to this GND bus (called hereinafter injected current).
Is1 = IsN +1 +
N
X
Ipi
(10)
i=1
In an similar way it is possible to draw out the voltages at consecutive
nodes as a function of parasitics and of currents flowing trough them.
I p1
I s i-1
I s1
1
Z1
V1
Z i-1
I s i+1
I si
i-1
Vi-1
Zi
i
Vi
I pN
I p i+1
Ip i
I p i-1
Z i+1
I s N+1
I sN
i+1
V i+1
ZN
N
Z N+1
VN
Figure 5. Model for the ground line of a row of cells. Ipi is the current injected by
a cell ith, Zi is the impedance of the line in correspondence of ith gate.
alog.tex; 29/01/2001; 15:08; p.13
14
Writing the following equations
Vi+1 = Vi
+ Ri+1 · Isi+1 + Li+1 ·
Vi = Vi−1 + Ri · Isi
d
(Isi+1 )
dt
d
(Isi )
dt
d
+ Li−1 · (Isi−1 )
dt
+ Li ·
Vi−1 = Vi−2 + Ri−1 · Isi−1
and using a recursive substitution of currents the total overvoltage at
node N is written as in equation (11). Term V0 is a voltage reference
value that depends on neighbours blocks connected to the beginning of
the considered row.
Proposition 1. The overvoltage VN at the end of the line as expressed
in equation (11)
N
³X
VN = V0 +
+
N µ
X
i=1
Ipi ·
i=1
´
Ri · IsN +1 +
i
X
k=1
¶
Rk +
N
³X
´ µd
Li ·
i=1
N µ
X
d
i=1
dt
Ipi ·
i
X
¶
dt
IsN +1 +
¶
Lk
(11)
k=1
has a contribution due to the entry current IsN +1 through the resistance
and the inductance series in a linear and derivative way respectively,
and an incremental contribution of the injected currents through the
incremental resistance and inductance series, again in an linear and
derivative way respectively.
The derivative term depends on the delay of the transistor chain in
the gate and is thus becoming less and less negligible with technology
scaling down. The switching noise analysis is then dependent on the
current behaviour of the gates connected to the same power bus.
Actual current estimation, in terms of global amount and local distribution, is an objective of basic importance for power supply noise
analysis. Furthermore the worst peak evaluation is no more the only
issue, but the waveform is needed for actual activity computation and
for derivative evaluation in the switching noise (LdI/dt) term.
Different works have addressed this point, first for power estimation
evaluation, and, recently, for IR drop analysis and for power supply lines
design [28, 31, 12]. Considering an exhaustive simulation extremely
expensive to be inserted in a cad design algorithm, more approximated
different evaluation techniques have been developed. One is the generation of test vectors able to find a small input set producing a worst
alog.tex; 29/01/2001; 15:08; p.14
15
switching activity in the circuit, but neglecting the fact that this doesn’t
imply the worst case IR drop; or, another technique is using worst
current for every gate which contribution is computed with respect
to a static timing analysis previously performed, neglecting the fact
that gates do not switch always in the same direction, leading to a too
pessimistic evaluation. Currently investigated methods aim to find the
maximum switching and the direction of switching, which is the only
way to accurately analyze the problem. The open issue is how to solve
it in the as much low-cost way as possible.
The methodology proposed by the authors is based on this last trend
and is described in [15], and is used together with equation (11) to
develop a cad tool for power supply noise analysis. The current term
in this equation is in general intended as a time dependent value I(t).
Nevertheless, the design parameters presented in the following do not
change if, for comfortable reading, the time dependency will not be
considered: the gates along the row will be then considered switching
in the same time (as for example in the case of a pure dynamic standard
cell row) and the peaks value will be used to indicate currents.
From a set of simulations performed, not reported for brevity, it is
possible to confirm the validity of this model, at least when the number
of gates do not increase over a maximum number of gates – 500 in this
case, considering the same conditions used for the simulations reported
in figure 1 without package inductance. The results evaluated using
the model are higher than the simulated ones if the number of gates
is greater then 500. This is due to the fact that capacitance has been
neglected in the model; a greater number of gates implies a greater
value of capacitance, and its influence becomes no more negligible. If
the model is used then to predict the the noise behaviour of a medium
circuit block, then it is possible to achieve optimal values, otherwise,
the prediction would be pessimistic, and should be used as an upper
bound.
Another consideration is the fact that in a 6 metal level process a
few other contributions to the model should be added. As previously
mentioned, if the considered metal level is higher that the first, then
the capacitance cannot be neglected: the expected contribution is the
prediction of lower noise peaks and then nearer to the real ones. Moreover vias to lower metal level should be added: the expected effect is
an increased resistance in the points correspondent to vias positions.
In this case, an interesting points is the definition of the number of vias
for electromigration risk minimizing.
alog.tex; 29/01/2001; 15:08; p.15
16
3.3. Power supply busses uniform sizing
A technology paradigm for electromigration safety is stated as a correct power bus width sizing, in which the width is a function of the
maximum (peak or RMS) current on the line. The maximum current
Is1 of equation (10) can be considered in a pessimistic way as the sum
of the maximum current of each gate: this gives a conservative way
to dimension the GND metal line. Therefore the width of the line is
uniformly sized proportionally to this maximum current. Equation (10)
can be easily written as eq. (12), where current Ip is the average current
among all the gates in the library.
Is1 = IsN +1 + N · Ip
(12)
Using the same approximation for the length of all the cells in the
library, the distributed parasitics, R and L (see equations (13.1) and
(13.2)), can be considered approximately the same in all the segments
depending on the line width wM AX figured out from the maximum
current1 .
R=
lN · R¤
1
·
N
wM AX
µ
L=
lN µ
8h
·
· log
N 2π
wM AX
(13.1)
¶
(13.2)
The resistance is computed from the technological sheet resistance R¤ ,
while the inductance is a rough value from equation (9) due to the fact
that in-chip inductance is still a difficult to extract value 2 . In (13.1) and
(13.2) the term lN = N · lgate is the line length defined as a function of
the average length (lgate ) of the library gates. In this manner equation
(11) becomes as in equation (14):
µ
¶
d
IsN +1 +
dt
¶
µ
N (N + 1)
d
+
· R · Ip + L · Ip
2
dt
VN = V0 + N · R · IsN +1 + L ·
(14)
1
For simplicity hereinafter the approximated function used for electromigration
safety design of the line will be wM AX = IMtAX where t is a value given from the technology used. This function can be obviously more complex without compromising
the equations reported in the following, but only their readableness.
2
In a real case for GND and VDD lines 4h >> w, if we do not consider high level
hierarchy power distribution lines. That is why only the first term in the logarithm
given in equation (9) is used in equation (13.2)
alog.tex; 29/01/2001; 15:08; p.16
17
Equations (14) and (12) are of simple use in a design phase if the designer knows a few technological parameters and the given environment
constraints:
Proposition 2. From equation (14) maximum noise overvoltage is
known from the number of cells inserted on the line.
or, vice-versa:
Proposition 3. From equation (14) maximum number of cells is constrained by the maximum accepted overvoltage.
The corresponding area occupied by the GND bus is
Aline = N · lgate · wM AX
(15)
This region could be very large, considering also that it should be
doubled to take in to account a similar sizing for VDD metal line.
3.4. Optimizing power supply busses dimensions for area
without increasing noise generation
The area waste is due to the pessimistic current value used for a safe
sizing of the line width. It is pessimistic because the maximum current
value present at the beginning of the line is used for a uniform dimensioning for the bus in its whole length.
On the contrary, the ith gate suffers on its GND reference from the
current superposition of N − i gates, and the line sizing could be safely
proportional to such maximum current.
This suggests the possibility to use a non-uniform dimensioning for the
bus in its whole length. Obviously it is not possible to use a “continuous” segmentation from a gate to another, but it is possible to extract
a formula useful to automatically chose the number of segment on the
line having different sizes, as a function of the number of cells N , of
the overvoltage and area constraints.
In figure 6 is sketched the corresponding realization: it is possible to
differentiate the line in M segments, each with constant width dimensioning, where the length of a segment is relative to the equivalent
N
length of M
cells. The gain in area is evident and considering an
interdigited power supply distribution the gain is doubled.
Proposition 4. If the line is dimensioned using M segments, each
with constant width dimensioning, considering resistance and induc-
alog.tex; 29/01/2001; 15:08; p.17
18
row1
vdd
wm -> RM
node
0
.......
N
cells
M
w1 -> R1
row1
gnd
row2
vdd
wm -> RM
N
cells
M
node
0
w1 -> R1
w2 -> R2
w3 -> R3
N
cells
M
w2 -> R2
.......
N
cells
M
w2 -> R2
N
cells
M
N
cells
M
.......
w3 -> R3
w3 -> R3
N
cells
M
w3 -> R3
w2 -> R2
N
cells
M
.......
w1 -> R1
N
cells
M
node
N
wm -> RM
w1 -> R1
N
cells
M
node
N
wm -> RM
row2
gnd
Figure 6. GND and VDD busses width segmentation for area improvement with
minimum noise increase in the case of interdigited power supply distribution.
tance constant in a segment, equation (14) can be written as in (16)
VN = V0 + IsN +1 ·
"
+ Ip
M
M
N X
N X
d
Rm + IsN +1 ·
Lm +
M m=1
dt
M m=1
#
M
M
´X
³ N ´2 X
1 N ³N
+1
Rm +
(M − m) · Rm +
2M M
M m=1
m=1
"
M
M
´X
³ N ´2 X
d
1 N ³N
+ Ip
+1
Lm +
·
(M − m)Lm
dt
2M M
M
m=1
m=1
#
(16)
where
1. there is still the contribution due to the entry current flowing through
the sum of the resistance of each segment and due to the derivative
of the entry current influenced by the sum of the inductance of each
segment;
2. the average current injected by the gates connected to the line has
again a linear and a derivative contribution multiplied by a term
due the resistance and a term due to the inductance respectively,
where these terms are incremental, as in equation (14), because of
the incremental number of cells injecting current from the point of
view of the end of the line;
3. and last, these contribution take into account the variable sizes of
the line in each segment, and as a consequence, the variable values
of resistance and inductance.
alog.tex; 29/01/2001; 15:08; p.18
19
A detailed proof of equation (16) is reported in appendix.
The total resistance contribution is obviously greater with respect
to the case in which the metal strip is uniformly sized. Decreasing
the width along the line, indeed, the resistance of the segments grows,
potentially increasing as a consequence the local overvoltage. On the
other hand, the higher resistance of the line segments is multiplied by
a lower and lower amount of current from a segment to another. It is
then expected that the IR drop can be minimized with an high number
of segments.
The open problem is how to chose the variation of width from a block to
another. It can be defined as a function of the maximum width chosen
for the point suffering maximum current (the beginning of the line) and
the minimum width at the point on which the current is minimum (the
end of the line), as in equation (17).
∆w =
wM AX − wM IN
g(M − 1)
(17)
If wM IN is the minimum allowed by the technology used for power
supply the gain in area is maximized; if a greater value is chosen the
total resistance decreases concealing a lower overvoltage. The function
g(M − 1) is a generic law useful to vary the resistance in a non-linear
way to contrast the amount of current. In the following, when practical
cases will be considered, the linear law g(M − 1) = M − 1 will be used
for simplicity.
Proposition 5. Using the formula (17), the distributed resistance and
inductance in each segment mth are:
Rm =
¡
¢
R¤ · lN
1
·
· fm m, wM IN , g(m − 1)
N
wM AX
µ
Lm
(18.1)
¶
¡
¢
lN µ
8h
=
ln
· fm m, wM IN , g(m − 1)
N 2π
wM AX
(18.2)
where fm is a function that varies the distributed resistance with respect to the corresponding formula in the uniform sizing case (13.1)
and (13.2), depending on the values of ∆w and of g(M − 1) used in
(17).
Proof. The resistance (the same reasoning can be done for inductance
and is not reported for brevity) in a segment m can be computed as in
(13.1) using the square resistance R¤ , the number of squares in each
alog.tex; 29/01/2001; 15:08; p.19
20
segment (#¤)m and the number of cells in each segment (#cells)m ,
that is:
µ
Rm
¶
lm
· R¤
(#¤)m · R¤
R¤ · lm 1
wm
=
=
=
·
and for note3
(#cells)m
wm
N
N
M
M
1
R¤ · lm
lN
·
and if lm =
=
M
N
wM AX − wM IN
wM AX − g(m − 1)
M
g(M − 1)
R¤ · lN
1
1
=
·
·
N
wM AX
g(m − 1) wM AX − wM IN
1−
·
g(M − 1)
wM AX
¡
¢
R¤ · lN
1
=
·
· fm m, wM IN , g(m − 1)
(19)
N
wM AX
3.4.1. Optimized versus uniform dimensioning
It is possible to find the variation for area and maximum noise between
the uniform sizing case (3.3) and the line width optimization previously
described.
Proposition 6. The difference in area (optimized vs. uniform) is a
gain (20) and it depends only on the chosen wM IN , as evident in
equation (20), whichever the function g(M − 1) is:
µ
lN
∆A = −
wM AX − wM IN
2
¶
(20)
Proposition 7. The difference between the noise overshoot found in
(14) and the new value found using the line optimization in (16) is a
3
The line width for a generic segment m is
wm = wM AX − g(m − 1) · ∆w
where 1 < m < M and ∆w is defined in equation (17)
alog.tex; 29/01/2001; 15:08; p.20
21
loss and is reported in equation (21)
∆N = TR · ∆R + TL · ∆L
"
∆R =
µ
IsN +1 1
Is1
M
M
X
m=1
where
¶
fm − 1 +
(21)
µ
´
Ip
1 ³N
+1 ·
Is1 2M M
#
¶
M
N X
N +1
·
fm + 2
(M − m)fm −
M m=1
2
m=1
M
X
and
"
µ
¶
µ
M
´
d
1 X
d
1 ³N
∆L =
IsN +1
ln(fm ) + Ip
+1 ·
dt
M m=1
dt
2M M
#
¶
M
N X
·
ln(fm ) + 2
(M − m) ln(fm )
M m=1
m=1
M
X
where TR and TL are technological factors for resistance and inductance
respectively, and where ∆R and ∆L are the variation contribution due
to resistance and inductance respectively; each of these two terms has
a contribution due to the entry current and one due to the current
incrementally injected through the line.
The proof is not reported but can be found in [15]. This formula is
useful in a design flow to control area and noise, using as parameters the
number of cells to abut along the row (N ), the number of segment with
different width (M ) and the maximum and minimum width at the line
extremes. Let’s consider separately the two contributions ∆R and ∆L ,
being them dependent from two different technology variables. In this
paper we want to understand the behaviour of the two contributions
(resistance and inductance), constant with technology process variation
and with different accuracy in technological parameters extraction.
The behaviour of the term due resistance ∆R is reported in figure 7,
where g(M − 1) = M − 1 for simplicity; wM IN varies between the
minimum width of a line in the present technology and the maximum
value due to maximum current. As a straight dotted line is reported the
gain in area (20), while three different sequences of ∆R variation are
distinguished respectively by “cross”, “circle” and “box” signs. A set
of five different behaviours is reported in each of these three sequences
in which N varies from a minimum of 200 cells to a maximum of 1000
cells inserted along the line.
The three sequences differ with respect to the number of cells in a
segment, while the N sweep is the same. In the sets with the “cross”
and with the “circle” the number of cells in each segment is 2 and 20
respectively, and the loss behaviour is almost superposed: there is a
small number of cells in each segment and this means a great number
alog.tex; 29/01/2001; 15:08; p.21
22
of segments in the line (with the same N ). Oppositely, in the set with
the “box” sign in each segment there are 100 cells: there is a little
number of segments versus the number of nodes i. In this case when
the number of cells grows also the loss in noise safety grows, even if the
gain in area increases towards the maximum.
Losses at node N optimizing for area: N parametric
Delta A
Delta R
2 cells for block m
20 cells for block m
100 cells for block m
area gain
TEC_MIN
w_MAX
W_MIN
Figure 7. Noise overvoltage when design parameters varies (wM IN , N, N/M ).
wM IN varies between the minimum of current technology and wM AX ; three different
evaluations of ∆R are superposed: in each of them N varies in five steps from 200
to 1000 cells (step 200). The three ∆R evaluations differ for the number of cells in a
line segment mth (see factor N/M in equation (21)): 2 cells in each segment in the
“cross” signed lines, 20 cells in each segment in the “circle” signed series, and 100
cells in each segment in the “box” signed series. Straight dotted line is for the power
supply line area variation from maximum value (minimum gain) and minimum value
(maximum gain).
Proposition 8. If the line is fractioned in a optimized number of segments with increasing dimensions, the number of cells on the line does
not influence too much the loss in noise safety.
The “appropriateness” of this number of segments is connected to
the reduced parasitics influence. Moreover the area does not change
when the number of segments grows. Obviously, this choice makes
the layout realization of the line more complex, but, as seen from the
superposition of the first two cases (“cross” and “circle” signed lines), it
is possible to achieve good compromises among the number of segments
and the number of cells in each.
alog.tex; 29/01/2001; 15:08; p.22
23
From the point of view of a designer the two equations (20) and (21)
are useful in two directions.
First:
Proposition 9. If a maximum noise overvoltage contribution due to
resistance is given (∆R ), it is possible to minimize the area of the line
∆A using different numbers of cells in the line or different numbers of
segments.
Second:
Proposition 10. If an area constraint is given (∆A ), it is possible to
derive the corresponding wM IN and then to foresee the line overvoltage
range (∆R ) due to resistance when the number of cells inserted on the
line varies and when the number of segments varies.
The behaviour of the term due to the inductance ∆L is reported in
figure 8. The parameters variation is the same as in figure 7. In the ∆R
Losses at node N when optimizing for area: N parametric, Inductance influence
Delta L
2 cells for block m
20 cells for floc m
100 cells for block m
TEC_MIN
w_MAX
W_MIN
Figure 8. Loss in noise overvoltage due to inductance when design parameters varies.
The parameters variation is the same as in figure 7. The derivative used is 1.
I
p
term, the factor Is1
is inversely proportional to the number of cell, and
is independent from the absolute current value. On the contrary in the
dI
∆L term the factor dtp is the absolute derivative value of the current
waveform of a medium cell, so it depends on library characterization
and it would be necessary to realize a case study. To have an idea of the
alog.tex; 29/01/2001; 15:08; p.23
24
behaviour in figure 8 the derivative used is 1. As a result, differently
from previously analyzed term:
Proposition 11. The inductance influence does not depend strongly
on the number of segments used but only on the number of cells and on
the minimum width of the line used.
Moreover, as expected:
Proposition 12. The inductance influence depends on the derivative
coefficient.
As an example in figure 9 the same number of cells in a segment
is used (20) and the same N and M variation law is used, while two
derivative coefficients are used.
Losses at node N when optimizing for area: N parametric, derivative influence
Delta L
20 cells for block m, derivative 1
20 cells for bloc m, derivative 10
TEC_MIN
w_MAX
W_MIN
Figure 9. Comparison between two set of noise overvoltage contribution due to
inductance using two different derivative values. Parameters variations are the same
as in previous figure in the case of 20 cell for each segment. The two ∆L evaluations
differ on the the derivative used, 1 and 10 respectively.
The optimization technique presented in this paragraph can be used
to determine a good compromise among noise overvoltage and waste of
area in a given cell row. The problem remaining is that the worst IR
drop could be still large if a great number of cells is forced in this row.
This last goal can be achieved using capacitors at the line extremes,
with an obvious area dispense. But still this does not reduce the noise
alog.tex; 29/01/2001; 15:08; p.24
25
along the row: the capacitors at the line extremes only provide all the
gates in the row the necessary current, which causes however a drop
along the line due to parasitics that are not reduced.
The only effective system to abate this problem is to diminish parasitics
and total current. The direct way to overcome these objectives could
be the use of copper instead of aluminum and the reduction of the
requested current via diminishing performances. Notwithstanding the
efficient use of copper actually adopted in high performance circuits,
this solution can only postpone this noise issue to ICs with larger number of gates. On the other hand reducing performances or staggering
current switching is a solution that opposes the high speed trend of
evolving circuits; furthermore this is often a complex and unsystematic
way to be followed.
Proposition 13. The virtuous circle to reduce both power supply area
occupancy and noise generation should be: decreasing the total current
delivered along the row making it local to the gate; reducing in this
way the line width necessary to overcome electromigration phenomenon;
decreasing line parasitics by increasing the line width, now possible from
the previous step.
3.5. Optimized distributed capacitors insertion to minimize
noise generation
The technique proposed to accomplish this positive reaction is the insertion of distributed capacitors along the row between GND and VDD.
To obtain an effective methodology each capacitor must be created with
each cell during its transistor optimization phase. Normally integrated
capacitors are realized using non conducting transistors. The capacitance size must be proportional to a given percentage of the current to
be delivered to the cell, where this ratio depends on the effect of the
remaining current over total IR drop and on the increased area of the
cell (and as a consequence of the total row) for the capacitor presence.
We realized a tool for transistor sizes optimization, designed at first
to achieve optimal results, during the creation of a cell library, in terms
of speed and power [10]. Being one of its quality the possibility to
optimism multiobjective functions, we easily added a noise issue to be
analyzed during the optimization phase, without neglecting the original
high performance objective. It is thus possible to obtain the capacitor
sizes necessary to maximize its current delivered to the gate, minimizing
in this way the current delivered along the line by the generator. For
example the peak current of an AND2 gate realized in TSPC was
initially 240 µA if optimized for high speed. After the optimization of
alog.tex; 29/01/2001; 15:08; p.25
26
the capacitor the current to be delivered to the gate was reduced to a
peak of 85 µA using a capacitance of 340 fF, without a delay reduction.
Maximum overvoltage versus distributed capacitor sweep
0.8
200 gates
400 gates
600 gates
0.75
0.7
0.65
Overshoot [V]
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0
200
400
600
800
1000
Distributed capacitance [fF]
Figure 10. Worst case noise measured on GND line as a result of a simulation of
a row of gates: each gate has a capacitor connected to it. A sweep of distributed
capacitance values has been done to show the noise decreasing.
To prove the usefulness of the capacitor insertion we realized a set
of simulations for a row with increasing number of cells (from 200 to
600) and parasitics conditions as in the ones used for the simulations
which main results are reported in figure 1 in the case in which package
inductance has not been considered. In these simulations a capacitor
has been added to each cell and a capacitance sweep from 100 fF to
1000 fF has been performed. In figure 10 noise peak values are reported
as a function of the increasing capacitance values. As expected noise
peak decreases as capacitor increases: for example the worst noise peak
in table 1 when no package is considered is reduced from 1.13 V to
0.56 V using distributed capacitors of 300 fF.
This proves that creating a library cell having an optimized capacitor
automatically coupled, can be a good methodology to effectively reduce
noise on power supply line. This does not mean that everywhere in the
circuit the cell with the connected capacitor should be used blindly,
but only that critical blocks from the point of view of current injection
should be better realized with cells which current is partially supplied
by capacitors placed as near as possible and with suited dimensions.
If a library cell with an autonomous current source (the capacitor)
is used, the noise, current and area formulae obtained in §3.2 and §3.4
will change as reported below.
alog.tex; 29/01/2001; 15:08; p.26
27
In figure 11 the corresponding model for the row is drawn. The total
current to be provided by the generator to the row becomes:
¯
¯
Is1 ¯¯
= IsN +1 +
cap
N
X
¡
Ipi − Ici
¢
(22)
i=1
where the term Ipi − Ici is the residual current not supplied by the ith
capacitor to the ith cell.
In the same way, the greater overshoot at node N , from equation (11),
becomes:
¯
¯
VN ¯¯
= V0 +
cap
N
X
Ri IsN +1 +
i=1
N µ
X
¡
Ipi − Ici
i
¢X
i=1
¶
Rk
(23)
k=1
In equation (24) is given the maximum current on the metal line in
the case of uniform dimensioning: a term Ic is added because the real
maximum current peak suffered by the most critical point of the line is
the one relative to the first cell in the row. The maximum noise becomes
in the case of uniform sizing of the line as in equation (25).
¯
¯
Is1 ¯¯
¯
¯
VN ¯¯
¡
cap
Ic i
I c i-1
I s i-1
1
Z i-1
Z1
V1
¢
N (N + 1) ¡
R Ip − Ic
2
= V0 + N R IsN +1 +
I p i-1
I s1
(24)
cap
I c1
I p1
¢
= IsN +1 + N Ip − N − 1 Ic
i-1
Vi-1
Zi
I c i+1
Ip i
I p i+1
I si
I s i+1
i
Z i+1
Vi
(25)
IcN
I pN
I s N+1
I Ns
i+1
V
i+1
ZN
N
Z N+1
VN
Figure 11. Model for the ground line of a row of cells with distributed capacitors
optimized for each cell. Ici is the current delivered by the ith capacitor to the ith
cell.
alog.tex; 29/01/2001; 15:08; p.27
28
3.5.1. Uniform dimensioning without capacitors versus uniform
dimensioning with capacitors
Evaluating what is the gain or loss in the case of distributed capacitors
with respect to the simplest case of uniform sizing without capacitors
is useful to create design parameters and constraints both for cell capacitor optimization and for optimal line width delineation.
In the following the contribution due to IsN +1 will be neglected in
order to obtain more readable formulae. This approximation simply
neglect the effect of noise due to the current IsN +1 and the fact that
line width should be computed tacking into account this current as
well. It is important to take into account this contribution in a CAD
tool for power supply analysis, even if, it should be considered that
decoupling capacitors at the end of the line make this current negligible
with respect to the maximum current along the line.
Subtracting (14) from equation (25) the approximated value in (26) is
achieved: this is an impressive gain because it grows with a quadratic
dependence from the number of cells.
¯
¯
VN ¯¯ − VN = −
cap
N (N + 1)
N2
RIc ≈ −R
Ic
2
2
(26)
This difference is obtained by comparing two quantity where resistance
must be the same, but the resistance depends on the line width, that it
is possible to shrink (to save area) being smaller the maximum current
value on the line (eq. (24) vs. eq. (12)).
Proposition 14. The difference between the two noise values if the
minimum width is chosen proportional to the decreased current on the
line when capacitor are present (that is eq. (24)) is in equation (27):
¯wMIN
¯
VN ¯¯
− VN ≈ R¤ t lcap
cap
N
2
(27)
where lcap is the length of the standard cell devoted to the capacitor
layout.
Proof. Equation (14) without the term due to inductance for simplicity,
can be transformed in the following way:
VN = V0 + R N IsN +1 + R
N (N + 1)
Ip
2
and using 13.1
VN = V0 + IsN +1 N
lN R¤
1
1
N (N + 1) lN R¤
+ Ip
N
wM AX
2
N
wM AX
alog.tex; 29/01/2001; 15:08; p.28
29
and then
VN
lN R¤
= V0 +
wM AX
If lN = lgate N and wM AX =
a gate,
µ
IM AX
t
(N + 1)
IsN +1 +
Ip
2
¶
where lgate is the medium length of
Ã
VN = V0 + lgate N R¤ t
IsN +1 +
(N + 1) !
Ip
2
IM AX
(28)
In the same way the maximum noise overvoltage in the case in which
capacitors are present will be:
¯
¯
VN ¯¯
Ã
= V0 + N (lgate + lcap )R¤ t
(N + 1)
!
(Ip − Ic )
2¯
(29)
¯
¯
IM AX ¯
IsN +1 +
cap
cap
where lgate + lcap is the medium length of a ¯cell and its capacitor.
¯
Using for IM AX equation (12) and for IM AX ¯¯ equation (24), the two
cap
previous equation will be
Ã
VN = V0 + lgate N R¤ t
¯
¯
VN ¯¯
(30)
(N + 1)
!
(Ip − Ic )
2
(31)
= V0 + N (lgate + lcap )R¤ t
IsN +1 + N Ip − (N − 1)Ic
Ã
cap
(N + 1) !
Ip
2
IsN +1 + N Ip
IsN +1 +
IsN +1 +
respectively. Neglecting now the term IsN +1 and considering that for
large values of N , N + 1 ≈ N − 1 ≈ N , equation (30) becomes:
VN ≈ V0 + lgate R¤ t
N
2
(32)
and equation (31) becomes
¯
¯
VN ¯¯
≈ V0 + (lgate + lcap ) R¤ t
cap
N
2
(33)
Finally subtracting term (32) from (33) equation (27) will be found.
alog.tex; 29/01/2001; 15:08; p.29
30
This formula underlines that, if the line width is reduced to the minimum allowed by electromigration safety paradigm, no gain is achieved
in terms of noise by the insertion of distributed capacitors, but at most
a loss due to the increased length of the line caused by the capacitors
presence. This means that in the IR contribution, even if the current
decreases, the resistance increases due to the reduced line width, as
sketched in figure 12: even if in figure 12.b a considerable gain in area
is achieved, the global overshoot is the same or greater than in the case
of figure 12.a.
a)
b)
c)
Figure 12. Sketch of the different sizing styles for power busses. In part a) a uniform
sizing is used where the width depends on the maximum current on the line and
on electromigration safety paradigm. In part b) each gate has a local generator in a
capacitor: this increase the length of the cell and then the length of the total line, but
a lower current on the lines gives the possibility to decrease the width of the line to
save area, using the same electromigration safety paradigm. Besides, the resistance
grows because of the line width decreasing: the total noise on the line is then the
same of the case a). In case c) the same distributed capacitor is inserted but the
line width is increased with a reduction of the gain in area but with decreased total
noise due to the reduced parasitics.
Besides, a great gain in area suggests that it is possible to use a
greater line size with respect to the minimum, in order to diminish the
resistance value and then to gain in noise generation, even with an area
gain reduction, as represented in figure 12.c.
Proposition 15. Supposing to choose a value as an upper limit for
the line width not greater than the one used in the case in which the
capacitors are not present, that is eq. (12), the overshoot difference will
be:
alog.tex; 29/01/2001; 15:08; p.30
31
¯wMAX
¯
¢
N Ic ¡
N
VN ¯¯
− VN ≈ R¤ t lcap
− R¤ t
lgate + lcap
2
2 Ip
cap
(34)
where lgate is the length of the cell devoted only to the layout of transistors performing the logic function of the cell.
Proof. In¯ this case the term VN will be the same found in (32), while the
¯wMAX
will be derived from equation (29) using as maximum
term VN ¯¯
cap ¯
¯
equation (12):
current IM AX ¯¯
cap
¯
¯
VN ¯¯
Ã
= V0 + N (lgate + lcap ) R¤ t
(N + 1)
!
(Ip − Ic )
2
IsN +1 + N Ip
IsN +1 +
cap
à (N + 1)
≈ V0 + N (lgate + lcap ) R¤ t
≈ V0 + (lgate + lcap ) R¤ t
N
2
!
(Ip − Ic )
2
N Ip
Ã
1−
Ic
Ip
!
(35)
At this point equation (32) can be subtracted from equation (35) to
obtain (34):
¯
¯
VN ¯¯
− VN
cap
N
≈ V0 + (lgate + lcap ) R¤ t
2
Ã
!
Ic
N
1−
− V0 − lgate R¤ t
Ip
2
N
N
N Ic
+ lcap R¤ t − lgate R¤ t
+
2
2
2 Ip
N
N Ic
− V0 − lgate R¤ t
− lcap R¤ t
2 Ip
2
¢
N Ic ¡
N
− R¤ t
≈ R¤ t lcap
lgate + lcap
2
2 Ip
≈ V0 + lgate R¤
In equation (34) the same loss term as in eq. (27) is present, but a
gain term due to the reduced resistance exists also: to assure a gain the
second term must be higher than the first, that is
alog.tex; 29/01/2001; 15:08; p.31
32
Proposition 16. The gain in reduced resistance must compensate the
loss due to the longer line (for the capacitor presence). The resulting
condition on the minimum line width (wLOW ) to have the gain assured
is in equation (36).
¯wLOW
µ
¶
¯
lcap
Ip − Ic
¯
VN ¯
< VN ⇒ wLOW ≥ N
1+
t
l
(36)
gate
cap
Proof. Leaving the width as in equation (29) and considering the usual
approximations:
¯
¯
VN ¯¯
cap
N (lgate + lcap )R¤
= V0 +
wLOW
(lgate + lcap )R¤
= V0 +
wLOW
Ã
Ã
!
(N + 1)
IsN +1 +
(Ip − Ic )
2
!
N2
(Ip − Ic )
2
and using as VN term the one in equation (32) the noise limit
¯wLOW
¯
VN ¯¯
< VN
cap
is assured if:
(lgate + lcap )R¤
V0 +
wLOW
Ã
!
N2
N
(Ip − Ic ) < V0 + lgate R¤ t
2
2
´
(lgate + lcap ) ³
N Ip − Ic ) < lgate t
wLOW
wLOW
Ã
Ip − Ic
lcap
>N
1+
t
lgate
!
A corresponding constraints on the capacitance is also extracted by
equations (36):
Proposition 17. If during the cell optimization the relationship between the current needed by the gate and the current delivered by the
capacitor is the one in equation (37) the possibility to choose a line
width as suggested in proposition 21 is assured.
Ic
lcap
<
lgate + lcap
Ip
(37)
alog.tex; 29/01/2001; 15:08; p.32
33
Proof. From equation (34)
R¤ t
¢
N Ic
N¡
> R¤ t lcap
lgate + lcap
2 Ip
2
Ic
lcap
>
Ip
lgate + lcap
An evaluation corresponding the ones in proposition 14 and 15
can be performed about the area waste and results are reported in
proposition 18 and 19.
Proposition 18. In the case in which the minimum width is chosen
corresponding to the maximum current when capacitors are present (eq.
(24)), equation (38) will be found:
¯wMIN
¯
lcap 2
lgate + lcap 2
Aline ¯¯
− Aline =
N Ip −
N Ic
t
t
cap
(38)
Proof. The area occupied by the ground line in the case without capacitors is:
Aline = N lgate
≈
¢
IM AX
lgate ¡
=
N IsN +1 + N Ip
t
t
lgate 2
N Ip
t
(39)
The area occupied by the ground line in the case with capacitors if the
maximum current (24) is used is
¯wMIN
¯
¡
= N lgate + lcap
Aline ¯¯
cap
¯
¯
IM AX ¯¯
¢
cap
t
¢
lgate + lcap ¡
N IsN +1 + N Ip − (N − 1)Ic
t
lgate 2
lcap 2
lcap + lgate 2
≈
N Ip +
N Ip −
N Ic
t
t
t
(40)
=
(41)
alog.tex; 29/01/2001; 15:08; p.33
34
Subtracting then term (39) from term (41)
¯wMIN
¯
Aline ¯¯
− Aline =
cap
lgate 2
lcap 2
lcap + lgate 2
N Ip +
N Ip −
N Ic +
t
t
t
lgate 2
N Ip
t
lcap 2
lcap + lgate 2
=
N Ip −
N Ic
t
t
−
In the other case
Proposition 19. If the width of the case without capacitors proportional to current in eq. (12) is used, equation (42) is found:
¯wMAX
¯
Aline ¯¯
− Aline =
cap
lcap 2
N Ip
t
(42)
Proof.
¯
¯
¯wMAX
¯
Aline ¯¯
¡
= N lgate + lcap
¢
IM AX ¯¯
cap
=
t
cap
=
¢
lgate + lcap ¡
N IsN +1 + N Ip
t
lgate + lcap 2
N Ip
t
(43)
Subtracting then equation (39) from equation (43) term in (42) is found.
In equation (38) a loss and a gain term are present; the loss term is the
one in eq. (42) and it is caused by the influence on the line length of
the capacitor. The gain value is due to the reduced area achieved via
the reduced current.
Proposition 20. To avoid a loss in area the relation in the (44) formula must be respected.
¯wHIGH
¯
Aline ¯¯
< Aline
⇒
cap
wHIGH ≤
N Ip
lgate
t lgate + lcap
(44)
Proof. Leaving in term (40) the line width we have simply
¯wHIGH
¯
¢
¡
Aline ¯¯
= N lgate + lcap wHIGH
(45)
cap
alog.tex; 29/01/2001; 15:08; p.34
35
Then to assure the limit
¯wHIGH
¯
Aline ¯¯
< Aline
(46)
cap
if the term in (39) is used for Aline
¡
¢
lgate 2
N Ip
t
lgate
N Ip
<
lgate + lcap t
N lgate + lcap wHIGH <
wHIGH
Finally, using previous results,
Proposition 21. If a value for the line width between
wLOW < w < wHIGH
is chosen, and each cell in the library is automatically connected to an
optimized capacitor, a gain in noise and in area is assured with respect
to the case without distributed capacitors.
Moreover, it is easy to improve the gain in area using the method
proposed in §3.4 (optimized dimensioning): if the maximum overvoltage
to be respected imposes capacitors which total area compromises the
reduction given by the lower current achieved, i.e. the line width should
be near to wHIGH , then the line optimization performed as explained
in §3.4 would supply to the forced increasing of area.
4. Conclusions
The model presented in section §3 for power bus size prediction and
sizing has versatile properties towards both first approximation problem and high performance issues. It is not a complete model, because
the first purpose is its inclusion in a CAD tool able to predict power
supply noise early in a design phase without a great computational
complexity. Anyway the authors consider that the use of a more accurate model would not compromise the effectiveness of the proposed
design methodology.
The uniform dimensioning presented in §3.3 can be used for the
estimation of generated noise and of area waste; or it can also be
inserted in a tool that, from equation (14), is able to chose how many
gates to insert in a row, given maximum noise allowed and given average
alog.tex; 29/01/2001; 15:08; p.35
36
characteristics of the library cells.
The optimization process for bus sizing presented in §3.4 gives a rule,
equation (21), to define the optimal area and noise suffered, using as
design parameters the number of segments, their sizes and the number
of cells in a row.
Finally, to reduce the generated noise without a variation of the cell
number, the design formulae in §3.5 was presented as a further improving of the whole model; a cell library with integrated capacitors
must be used, where equation (37) should be met during the capacitors
optimization to assure a good performance. Given then the number of
cells to be abutted along the row, a line width between the values
defined in (36) and (44) can be used: in this way a noise and an area
reduction is assured with respect to the case of uniform sizing without
distributed capacitors, in a measure defined by equations (34) and (38).
Moreover, the methodology in §3.4 for bus segmentation can be added
to the one in §3.5 to further enhance the design results.
Due to the raising influence of power supply noise in high performance integrated circuits, new methodologies to predict and to avoid
noise generation must be inspected: the one proposed in this paper
seems to be appropriate and advantageous if inserted in a design flow
of a tool having as an issue noise besides delay and power.
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Appendix
VN = V0 + IsN +1 ·
"
+ Ip
M
M
N X
d
N X
Rm + IsN +1 ·
Lm +
M m=1
dt
M m=1
#
M
M
´X
³ N ´2 X
1 N ³N
+1
Rm +
(M − m) · Rm +
2M M
M m=1
m=1
"
M
M
´X
³ N ´2 X
1 N ³N
d
+1
·
(M − m)Lm
+ Ip
Lm +
dt
2M M
M
m=1
m=1
#
(16)
alog.tex; 29/01/2001; 15:08; p.38
39
Proof. In equation (11) the two terms to be redefined considering
the segmentation are
N
X
Ri
(47)
i=1
and
N µ
X
i
X
i=1
k=1
Ipi ·
¶
Rk
(48)
for resistance contribution and analogous terms (which can be redefined
in the same way as resistance) for inductance contribution.
It is then easy to find for the term (47) that
N
X
Ri =
i=1
M
N X
Rm
M m=1
for M segments.
As an easy example, if the number of segments is 2:
N
X
i=1
N
Ri =
2
X
i=1
R1 +
N
X
i= N
2
R2 =
N
· (R1 + R2 )
2
Indeed, in the two extreme cases, if the number of segments is M = 1 :
M
N X
Rk = N R
M k=1
while if the number of segments is M = N
M
N
X
N X
Rk =
Rk
M k=1
k=1
alog.tex; 29/01/2001; 15:08; p.39
40
For the term in equation (48) we have:
N
−1 µ
X
i
X
i=1
k=1
Ipi ·
Ã
= Ip ·
¶
Rk
= Ip ·
= Ip ·
2N
N
i
M X
X
Rk +
N
N
i= M
N
2M
R2 +
N
k= M
+1
Ã
i
M
X
X
N
3M
X
+ R1
N
i= M
N
M
···
−
M
X
N
M
X
i + R1
i=1
+ R2
³ N ´2
M
1 + R2
R1 +
R1 +
k=1
!
´
R2 + · · ·
i
X
M
X
N
i= M
+1
N
2M
M
X
+1
N
M
³X
N
k= M
+1
1 + R2
N
k= M
N
3M
X
Rk
X
1 + R3
1+
+1
i
X
1+
N
N
+1 k=2 M
+1
i=2 M
´
!
1 + ···
k=1
³ N ´2
M
3N
M
X
+ R3
X
2N
N
k=1
= Ip · R1
³X
¶
N
2M
N
N
+1 k= M
+1
i=2 M
N
R1
N
i=2 M
+1
+1 k=1
X
M
X
R2 +
N
M
X
N
3M
1 + R2
3N
N
M
M
X
1 + R1
³
Ã
N
k= M
N
X
k=1
k=1
N
+1 k=1
i=2 M
+
R1 +
k=1
2N
X
Rk + . . . −
´
i
X
R3 + · · · −
i=1 k=1
i
X
N
i=2 M
+1 k=1
N
k=2 M
+1
N
= Ip · R1
Rk +
´
i
X
Rk
M
X
N
+1
¶
3N
2M ³ M
X
X
R1 +
N
X
k=1
N
i= M
+1 k=1
i=1 k=1
+
i
X
M
X
N
i
M X
X
X
Rk −
i=1 k=1
i=1 k=1
Ã
µX
N X
i
N
+1
i=2 M
N
2M ³
X
+ R2
i−
N
i= M
+1
³
N´
i−2
M
+
³ N ´2
N´
+
+ R1
M
M
···
M
N X
·
Rm
−
M m=1
!
N
N
and using successive variable change as j = i, j = i − M
, j = i − 2M
,
· · · becomes
Ã
= Ip · R1
N
M
X
j=1
+
³ N ´2 ³
M
N
j + R2
M
X
j=1
N
j + R3
M
X
j +
···
j=1
´
R1 + (R1 + R2 ) + · · ·
M
N X
−
·
Rm
M m=1
!
alog.tex; 29/01/2001; 15:08; p.40
41
Ã
= Ip ·
M
M
´X
³ N ´2 X
1 N ³N
+1
Rm +
(M − m)Rm +
2M M
M m=1
m=1
M
N X
Rm
·
−
M m=1
!
and, finally, collecting the first and second terms in parenthesis
Ã
= Ip ·
M
M
´X
³ N ´2 X
1 N ³N
−1
(M − m)Rm
Rm +
2M M
M m=1
m=1
!
alog.tex; 29/01/2001; 15:08; p.41