EDISON ROBERTO C. DA SILVA,
EUZELI CIPRIANO DOS SANTOS, JR.,
AND CURSINO BRANDÃO JACOBINA
Nonsinusoidal Carrier-Based PWM
and Space Vector Modulation Techniques
I
n power electronics, pulsewidth modulation (PWM) has been the subject of intensive
research and is widely employed to control the output voltage of static power converters.
A large variety of feed-forward and feedback control schemes has been described in the literature [1]–[3], but the most widely used methods of PWM are the sinusoidal PWM (SPWM) and
the space vector PWM (SVPWM).
In SPWM, introduced by Schönung in 1964 [4] to produce the output voltage waveform, a
sinusoidal control signal (modulating control signals) is compared with a triangular signal (carrier signal). An SVPWM uses complex voltage vector for control. Although one of the first suggestion
for employing the complex voltage vector in PWM control was made by Jardan et al. [5], the SVPWM
technique was first published by Busse and Holtz [6] followed by Pfaff et al. [7] in the same year.
Prof. Joachim Holtz has had a lifelong contribution and achievement in PWM [8]–[22]. He was one
of the pioneers not only of SVPWM technique but also of the three-level inverter topology [23]. Most
of his papers on the topic use SVPWM, but he has not neglected other possibilities, including new
Digital Object Identifier 10.1109/MIE.2011.941120
© INGRAM PUBLISHING
Date of publication: 17 June 2011
1932-4529/11/$26.00&2011IEEE
JUNE 2011 n IEEE INDUSTRIAL ELECTRONICS MAGAZINE 37
In power electronics, PWM has been the subject
of intensive research and is widely employed to
control the output voltage of static power
converters.
approaches for solving specific problems such as low-frequency operation
in high-power applications [18]–[22].
On the other hand, modification of the
modulating signal introduced many
improvements to SPWM technique,
resulting in nonsinusoidal carrierbased PWM (CPWM) techniques [24],
[26]–[36]. Also, the superior performance characteristics of SVPWM led to
the investigation of new solutions,
resulting in modified SVPWM methods [37]–[42].
This article is a tribute to Prof.
Holtz. His efforts have been appreciated by exhibiting the continuous
efforts of researchers trying to reproduce with other approaches the characteristics of the powerful concept
he pioneered, the SVPWM. For that,
the article recalls the evolution of
the parallel advances of CPWM and
SVPWM, discusses their relationship
already established in [43]–[54],
and shows another possible relation, allowing to develop an alternative algebraic PWM modulator
with the same SVPWM characteristic. In addition, it extends the algebraic algorithm to the control of
both two-level Z-source inverter
and a three-level neutral-pointclamped (NPC) inverter.
CPWM Concept Evolution
In the SPWM technique [Figure 1(b)],
the amplitude modulation index ma is
defined as the relation between the
peak amplitude of modulating control signals and the amplitude of the
carrier signal. An important feature is
that the amplitude of the fundamental frequency component of the pole
voltage, Va0 in Figure 1(a), is linear
with the variation of ma. This occurs
when the modulation ratio mf between
the switching frequency of the carrier signal and the fundamental frequency of the control signal is high
enough, e.g., 21.
A value ma > 1 causes overmodulation, i.e., a reduction in the number
of pulses in the pole voltage va01
waveform and a consequent loss of
its linearity. After Buja and Indri [25],
it was gradually recognized that the
addition of an adequate third harmonic zero-sequence components to
each of the pole voltage reference
waveform makes it possible to increase
the fundamental of the output voltages
by 15.5%. The new modulating wave
νT
+
E
+
E /2
–
b
νc∗
νT
νa∗
νT
νa∗
∗
νa0
νh
n
c
+
E /2
νb∗
a
0
–
νa∗
obtained with the third harmonic
injection PWM (THIPWM) is somewhat flattened on the top and has
been discussed in detail in [29]. Zerosequence component with maximum
amplitudes of 1/6 [29] and other peak
values for the sinusoidal modulating
signal have been investigated. It was
concluded that the amplitude of 1/4
reduces the harmonic distortion in
the inverter output voltage [30]. Figure 1(b) and (c) (top) compares the
THIPWM (1/4) with the SPWM. Note
that, for a high mf in SPWM, the
three-pole voltage pulses, va0, vb0,
and vc0, inside a switching interval Ts
are almost centered [25]. These high
switching frequencies can be avoided
with the use of regular-sampled PWM
(RSPWM), which was first introduced
by Bowes [55].
On the other hand, as concluded
by Depenbrock [26], the use of discontinuous zero-sequence components not only makes this increase
of 15.5% possible but also reduces
the number of times the switches
are turned on and off by clamping
each pole voltage at 60°. It should be
noted that an alternative approach
for modifying the carrier has been
investigated [28], [35], but this results in complex implementation [36]
so that the modified modulating reference approach has been preferred.
The use of an injected zero-sequence
signal for a three-phase inverter [25],
[29] initiated the research on nonsinusoidal CPWM [26], [31]–[38].
This concept can be expressed in
–
(a)
(b)
∗
νa0
νh
(c)
FIGURE 1 – (a) Three-phase inverter, (b) SPWM—principle and pole voltages, and (c) THIPWM (1/4), top: zero-voltage signal vh (middle)
and flat-modulating signal generated, va0
; symmetric modulation (equivalent to SVPWM), bottom: zero-voltage signal vh (middle, l ¼ 0:5)
.
and modulating signal generated, va0
38 IEEE INDUSTRIAL ELECTRONICS MAGAZINE n JUNE 2011
terms of the sinusoidal reference
and the zero-sequence signal vh, i.e.,
vj ¼ vj þ vh
(j ¼ a, b, c):
(1)
An important feature is that the
injected zero-sequence signal vh will
not increase the low-frequency harmonic distortion for vab. From (1),
the SPWM corresponds to vh ¼ 0.
After studying the mean inverter
pole voltages obtained by SVPWM,
van der Broeck et al. [38] concluded
that an SVPWM could be obtained
by substitution of the sinusoidal
reference signal in a normal threephase modulator by the nonsinusoidal modulating curve shown in
Figure 1(c), bottom. This means
that an SVPWM can be obtained by
the adequate choice of vh in (1). van
der Broeck also realized that other
curves could be synthesized as
reference curves, some of them
already mentioned in the literature.
With the conception of modified
SVPWM techniques [37], [39], [40],
many researchers investigated the
relationship between these techniques and vh, i.e., between SVPWM
and nonsinusoidal CPWM techniques [43]–[45], [47], [54] or other
techniques [48]. Based on these
Va
+
E
Vb
–
Vb
E
Vc
E
Vb
–
Vc
(f)
E
Vb
–
Vc
(g)
Vc
(d)
Va
E
Vb
–
Vc
+
Va
+
(c)
Va
+
Vb
–
Vc
period of the three-phase references into six intervals. In the switching interval inside of Sector I
shown in Figure 3(b), v a and v c
have the maximum and minimum
values, respectively, while v b has
an intermediate value. Because v a ,
v b , and v c change for each sector,
working with the maximum v M ,
medium v mid , and minimum v m voltages (which can be defined by
comparing the values of the three
reference signals) simplifies the
algorithm.
The intersection of reference voltages vM, vm, and vmid with the triangle defines 1) the pulsewidths for
each of the phase voltages, s1 , s2 ,
and s3 , 2) the distances between the
switching instants for phases a, b,
and c (the delay of the first switching procedure t01, the distances of
the switching instants, t1 and t2, and
the remaining time of the sampling
period t02), and 3) the time intervals
tp1, tp2, and tp3 (switching delays)
before each leg changes in a given
switching interval. Note that intervals t1 and t2 correspond to the time
intervals calculated in SVPWM during which switch states S0, S1, S2,
and S7 are on and define the line
voltage.
Va
+
(b)
Vb
(e)
Va
–
Va
–
To understand the correlations among
SVPWM, HPWM, and DSPWM, some
points have to be considered. There
are eight possible switch combinations
for a three-phase inverter (inverter
switch states) Si , (i ¼ 0, 1, . . . 7),
which is shown in Figure 2. Six of
them, S1, S2,. . . S6, apply voltages at
the output (active switch states or
active vectors), while S0 and S7 correspond to the short-circuiting of the
bottom and top switches (zero switch
states or zero vectors), respectively.
Now, consider sectors I–VI in Figure 3(a). They divide the fundamental
E
(a)
E
Understanding the
Relationships Among
SVPWM, HPWM, and DSPWM
+
Vc
+
relations, different modulators, with
easier implementation than that of
SVPWM, have been developed. This is
the case of hybrid PWM (HPWM) [49],
digital scalar PWM (DSPWM) [50],
[51], [53], and generalized PWM
algorithm [52]. Among them, the
DSPWM has a simple software algorithm to generate the SVPWM and is
based on the concept of imposing
an average voltage corresponding
to each reference phase during the
sampling interval [53]. The idea is
similar to that in [45].
Va
+
E
Vb
–
Vc
(h)
FIGURE 2 – Eight possible phase leg switch combinations for a voltage source inverter (VSI) (a) S1, (b) S2, (c), S3, (d) S4, (e) S5, (f) S6, (g) S0,
and (h) S7.
JUNE 2011 n IEEE INDUSTRIAL ELECTRONICS MAGAZINE 39
addition or subtraction of vh to the
reference voltages only influences the
pole voltages [47], [49], [51]. This
influence can be measured by the
distribution ratio [43] (also named as
apportioning factor [48]),
Note from Figure 3(b) that
tz ¼ t01 þ t02 ¼ Ts (t1 þ t2 ):
(2)
In (2), tz ¼ t01 þ t02 constitutes the
total freewheeling interval. Note, in the
case of the figure, that t01 and t02 are
equally distributed at the beginning
and end of the switching interval. In
reality, these zero-interval constituents
can assume different values, provided
that the condition in (2) is respected.
l¼
VI
I
II
III
νa∗
IV
V
νc∗
νb∗
(a)
p1 p1′
νT
τh
p2 p2′
p3 p3′
νh
νa∗
νb∗
νc∗
tp1
τ1′
τ1
tp1′
tp2
τ2′
τ2
tp2′
tp3
τ3′
tp3′
t01
t01′
t1
Ts
τ3
t02
t2
(3)
which indicates the distribution of
the freewheeling switch states inside
the switching interval.
Values 0l1 define a particular
distribution of freewheeling switch
states and is really the ultimate basis
for the definition of phase-modulating signals.
1) The use of l ¼ 0:5 results in the
conventional SVPWM in which tz
is equally distributed at the beginning and end of the switching
The Concept of Distribution
Ratio and Its Use
When a zero-sequence component vh
is added to each sinusoidal reference, new references v0M , v0M , and v0i
are generated, according to (1). Note
that t1 and t2 remain unchanged, while
0
t01 increases to t01
and t02 decreases to
0
t02 . It can be concluded that the
V
t02
,
t01 þ t02
t02′
(b)
FIGURE 3 – Two-level CPWM and zoom of one switching interval inside of Sector I,
including intervals for different modulation approaches.
40 IEEE INDUSTRIAL ELECTRONICS MAGAZINE n JUNE 2011
interval, i.e., t01 ¼ t02 . The corresponding zero-sequence component is equal to the average
voltage value at the switching
interval, i.e., vh ¼ (vM þ vm )=2
[32], [43], [49], [51], which has
already been seen in Figure 1(c),
bottom. In reality, l ¼ 0:5 is the
best choice [43] among the other
continuous possibilities 05l51,
which have been investigated
in [31].
2) With l ¼ 0, one of the pole voltages is connected to the negative
dc-bus clamping the pole voltage
during 120° while the other two
phases modulate. In this case,
t02 ¼ 0 and t01 ¼ tz, meaning that
only the freewheeling switch state
S0 is employed, together with S1
and S2 shown in Figure 2. The corresponding modified modulating
signal is obtained by subtracting
vm from E=2. It is illustrated in
Figure 4(a) and was first proposed in [40].
3) With l ¼ 1, one of the pole voltages is connected to the positive dc-bus clamping the pole
voltage during 120° while the
other two phases modulate. In
this case, t01 ¼ 0 and t02 ¼ tz ,
meaning that only the freewheeling switch state S7 is employed,
together with S1 and S2. The
zero-sequence component is obtained from vh ¼ ðE=2 þ vm Þ,
as shown in Figure 4(b), and
was introduced in [39].
4) There are four possibilities for
changing l from l ¼ 0 to l ¼ 1
and back, each change lasting
for 60°. They are shown in Figure
4(c)–(f) and are referred as
discontinuous PWM 1 (DPWM1)DPWM4. Consider DPWM1 in
Figure 4(c), in which the change
of l coincides with the middle of
the sector. In DPWM2, a phase
shift of 30° phase difference exists
in relation to DPWM1 (the change
occurs at the beginning of the
sector), as shown in Figure 4(d).
So it is for DPWM3 in relation to
DPWM2 and for DPWM4 in relation to DPWM3. This makes the
changes in DPWM3 and DPWM4
νa∗
∗
νa0
μ
1
νa∗
νh
0
νa∗
30°
0
∗
νa0
μ
0
νa∗
1
(d)
νh
(b)
νh
μ
∗
νa0
1
(a)
1
νa∗
νh
μ
1
0
∗
νa0
60°
∗
νa0
(c)
νa∗
νh
μ
∗
νa0
μ
90°
1
0
νh
0
(e)
(f)
FIGURE 4 – Modified modulating signals (a)–(f) and their relation with l. (a) l ¼ 0, (b) l ¼ 1, (c) DPWM1, (d) DPWM2, (e) DPWM3, and (f) DPWM4.
complementary to those in DPWM1
and DPWM2, respectively, as
shown in Figure 4(c)–(f). Some
of these cases have been investigated in [41].
Although there is a large number
of possible modified reference signals, the seven (including the case of
l ¼ 1) depicted earlier are the most
employed. The characteristics of all
these cases have been investigated in
[49], [52], [56], and [57].
A general relation that allows for
building the zero-sequence component, vh, as a function of l, vM, and vm
inside each sector is given by [49], [51]
E
vh ¼ (1 2l) þ lvM þ (1 l)vm :
2
(4)
An Algebraic Algorithm
Figure 5 gives the block diagram of the
hybrid modulator for generating
the different zero-sequence signal. The
generation of PWM must be accomplished in two steps: 1) the choice of
the zero-sequence component and 2)
the determination of pulsewidths.
The choice of the zero-component
sequence has been well discussed in
[42], [56], and [57]. The modulation
index, for a given dc-link voltage E, is
the ratio of the fundamental voltage of
the modulated switching sequence,
V1m, to the fundamental component
magnitude of the six-step mode voltage, 2E=p [1], i.e., ma ¼ pV1m =2E.
The performance of the seven possibilities depends on ma. In terms of
harmonic distortion factor (HDF) the
SVPWM method ðl ¼ 0:5Þ is superior
to all the discussed methods in the
low-modulation index range. However, in the high-modulation index
range, a transition to one of the DPWM
methods should be realized [49], [56],
[57]. The DPWM selection can be
based on the switching loss characteristics, which depend on the load phase
angle. Inside the variation of this angle
in the 30° and þ30° range, DPWM1
presents the smallest losses. Besides
these angle limits, 30° or þ30°,
DPWM2 or DPWM3 present the smallest losses, respectively, for any modulation index greater than 0.3 [49].
Besides the linear modulation range,
the voltage gain characteristic favors
DPWM1 [14], [49].
In analog implementation, the
pulses are determined by the comparison of the modified modulating
νa∗ νb∗
reference with the triangular waveform. For digital implementation,
there are three possibilities of calculation of pulsewidths after the addition of the zero-sequence signal vh.
These are obtained from Figure 3 by
using the triangle equivalence.
1) First Possibility: Calculation of
duration of the modified phase
pulses, i.e., s01 , s02 , and s03 , from
s0i ¼
vj þ vh 1
þ Ts
2
E
3 (i ¼ 1, 2, 3; j ¼ a, b, c; i ¼ j),
0
t01 ¼ Ts sM ,
t02 ¼ s0m :
(5)
The comparison of s0i allows
determination of s0M , s0m , and s0mid .
This method corresponds to the
DSPWM strategy with direct
measurement of the average values of the three modified reference phase voltages at a given
νc∗
Determination of
νM and νm
νa∗ νb∗ νc∗
Choice of μ
μ
νM + (1 – μ)ν
νm}
νh = –{(1 – 2μ) E + μν
2
νh
∑
νa∗′
νb∗′ Calculation
of Gating
νc∗′ Pulses
FIGURE 5 – Block diagram for the HPWM.
JUNE 2011 n IEEE INDUSTRIAL ELECTRONICS MAGAZINE 41
switching interval [45], [53].
Note that (4) can also be written
as a function of sM , sm , and smid .
2) Second Possibility: Calculation of
the switching distances between
the phase pulses, i.e., duration
of line voltage pulses t1 and t2
[43], [49], from
Ts (v vmid ),
E M
Ts
t2 ¼ (vmid vm ),
E
t1 ¼
(6)
and t01 þt02 ¼ Ts ðt1 þt2 Þ as in (2).
Values of t1 and t2 are proportional to the three reference line
voltages (the same as in SVPWM)
at a given switching interval. The
use of vh as a function of l, and
calculation of t1, t2 (related to the
differences between the maximum
and the middle values and between
the middle and minimum values for
reference voltages va , vb , and
vc , respectively), characterizes
the HPWM technique. Each interval corresponds to the interval
time in which each of the inverter
switching states employed are
on, at a given switching interval.
3) Third Possibility: Calculation of
the time intervals before each
leg changes inside the switching
interval (switching delays), tp1,
tp2, and tp3, using the distances
E
vM ,
2
E
p2 ¼ pmid ¼ vmid ,
2
E
p3 ¼ pM ¼ vm
2
p1 ¼ pm ¼
(7)
that can be used to determine
both the sector of operation and
vh, given by
vh ¼ lpmin (1 l)(E pmax ): (8)
The final pulsewidths are given by
0
pi Ts
,
E
(i ¼ 1, 2, 3; j ¼ a, b, c; i ¼ j),
0
,
t01 ¼ tp1
tpj0 ¼
0
,
t02 ¼ Ts tp3
(9)
where pi 0 ¼ E2 (vj þ vh ).
The signal’s width to command the inverter switches (s01 ,
s02 , and s03 are given by
0
, (i ¼ 1, 2, 3):
s01 ¼ Ts tpi
(10)
The steps for implementation of the
approach after calculating p1, p2, and
p3 are
n Step 1—define pm, pmid, and pM
from (7).
n Step 2—determine vh by using (8).
n Step 3—calculate the distorted
control
signals
by
vx 0ref ¼
vx ref þ vh :
n Step 4—determine the modified
delay times tp1 0 , tp2 0 , and tp3 0 from
(9).
n Step 5—calculate the pulsewidths
for the inverter switches (s01 , s02 ,
and s03 ) from (9).
n Step 6—determine pole voltages
(va0, vb0, and vc0) by
If (t5tpj 0 )or(t52si 0 ), vj 0 ¼ E=2.
If ðtpj 0 5t52si 0 Þ; vj 0 ¼ þ E=2.
Any of the three possibilities can
be directly applied to the three-phase
VSI, including transients, and can
also be adapted for other converters.
Application of the
Algorithm to the Z Inverter
The Z-source inverter [58] provides
the unique feature of buck and boost
operation capability with the same
circuit, which is not found in neither
voltage–source nor current–source
converters. Such a converter employs
an impedance circuit to connect the
converter to the primary energy
source, as observed in Figure 6(a). A
virtual ‘‘0’’ defines the pole voltages
va0, vb0, and vc0. Figure 6(b) shows the
generation of the pole voltages by
the comparison of the triangle with the
sinusoidal waveforms for the Z-source
inverter. As described in [59], the
shoot-through configuration is evenly
distributed among the three-phase
legs, while the line voltage pulses and,
consequently, the active configuration
operating inside of the switching interval remain unchanged as seen in Figure 6(b) (t1 and t2 remain the same).
During the shoot-through, the pole
voltages are equal to zero, since
42 IEEE INDUSTRIAL ELECTRONICS MAGAZINE n JUNE 2011
vi ¼ 0. Equations (2) and (5) are valid
when zero-sequence signals are added
to the reference voltages. In this case,
each pulsewidth needs to be recalculated to insert the shoot-through zero
vector time (s0) equally distributed
among the legs, i.e., s0/3 for each leg.
To guarantee that this method generates the same active states as the
converter, as in Figure 7(b), the intervals of time sa1 , sa2 , sb1 , sb2 , sc1 , and sc2
need to be compensated as follows:
s0ai ¼ sai þ
s0
,
3
s0bi ¼ sbi ,
s0ci ¼ sci s0
:
3
(11)
where i ¼ 1, 2, referring to the top
and bottom switches.
For generalization purpose, this
can be written as
s0M ¼ sM þ
s0
,
3
s0mid ¼ smid ,
s0m ¼ sm s0
:
3
(12)
The algorithm for generation of the
modified pulses is the same except
that the calculation of the pulsewidths is done by using (11) or (12)
for a given s0 . Figure 6(c) shows the
simulated results obtained with the
proposed algorithm for the modulating signal, zero-sequence component, capacitor voltage, and input
voltage, vi, of the Z-source inverter
for l ¼ 0:5. Other parameters used
were the switching frequency 10 kHz,
C1 ¼ C2 ¼ 1 mF,
L1 ¼ L2 ¼ 160 lF,
E ¼ 100 V, s0 ¼ 10 ls, and modulation
index ¼ 0.9. Boost characteristic is
clear.
Application of the Algorithm
to the NPC Multilevel Inverter
Multilevel inverters have emerged as a
solution for working with higher voltage
levels. They have been considered for
an increasing number of applications
because of not only their high-power
capability but also lower output harmonics and lower commutation losses.
Only the three-level NPC inverter
[60], shown in Figure 7(a), will be
considered here. Its light adaptation
νa∗ ′ νb∗ ′
νa∗ νb∗ νc∗
νc∗ ′
νt
L1
+
E
C2
C1
νh
a
b
νh
n
–
c
τo
τo
L2
6T
3T
(a)
νh
τo
τo
6T
3T
τa1
τa2
τb1
τb2
τc1
τc2
toi′
t1
t2
tof′
(c)
toi
t1
t2
tof
(b)
FIGURE 6 – (a) Z-source inverter, (b) modified reference voltages generated for Z-source inverter with vh given in (4), and (c) experimental results
for DPWM1: capacitor and inverter input voltage (top), pole voltage (middle), and nonsinusoidal modulating signal (bottom) ðfs ¼ 10 kHzÞ.
allows for applying the algorithm proposed in the control of the multilevel
NPC inverter [61].
1) Values of the levels N2 are
given by
Eixo(k) ¼
3) To extend the result to any s
number of levels (N2), Step 2
changes to
vh ¼ lpmin (1 l)
1 (k 1)
E,
2 (N 1)
(k ¼ 1, 2, . . . ,N)
(13)
and are shown for N ¼ 3 in
Figure 4.
2) Step 1 is generalized as
If (Axis(k)4vj ref 4Axis(k þ 1)), then
pi ¼ Axis(k) vj ref ,
( j ¼ a, b, c; i ¼ 1, 2, 3; i ¼ j):
(14)
Figure 7(b) shows the definition of pi for a three-level NPC
inverter.
E
pmax :
N 1
(15)
4) The equation for Step 4 becomes
tpi ¼
pi
E
N1
Ts
(i ¼ 1, 2, 3):
(16)
5) The determination of the pole
voltages (va0, vb0, and vc0) for
(k = 1, 2, . . . , (N-1) is now
If(t5tpi 0 ) or (t52ti 0 ),
vj 0 ¼ value of axis(k þ 1):
If(tpi 0 5t52ti 0 ),
vj 0 ¼ value of axis(k):
Figure 7(c) presents the experimental results for the clamped pole
voltage for the converter. Although
not addressed in this article, special
attention should be paid to the neutral point balance [22], [64]. Also, it is
desired to operate medium-voltage
drives at switching frequencies
below 1 kHz to minimize the switching losses. However, using SVPWM
and other techniques at low switching frequency cause high harmonic
distortion of the machine currents.
One good solution to reduce the
switching frequency without sacrificing harmonic content is using
synchronous optimal modulation
[19]–[21], [65].
Conclusions
This article reviews the nonsinusoidal CPWM and SVPWM techniques
JUNE 2011 n IEEE INDUSTRIAL ELECTRONICS MAGAZINE 43
+E/2
p1
+
E/2
E /2
–
E
+
–
0
a
νa
b
n
νb
νc
0
c
p2
+
E /2
E/2
–
p3
–E/2
(a)
(b)
(c)
FIGURE 7 – (a) Three-level NPC inverter, (b) definition of p1, p2, and p3 in the case of three-level inverter, and (c) pole voltage (experimental) for DPWM1 (pf = 0.9, fs ¼ 4 : 43 kHz; 50 V=div).
and deals with the three possibilities
of calculation of pulsewidths after
the addition of a zero-sequence signal. A general algorithm is proposed
and adapted for dealing with the control of the three-level NPC inverter
and also the Z-source converter.
Experimental results corroborate the
proposed technique.
Biographies
Edison Roberto C. da Silva received his B.S.E.E. degree from the
Polytechnic School of Pernambuco,
Recife, Brazil, his M.S.E.E. degree
from the University of Rio de Janeiro,
Brazil, and his Dr. Eng. degree from
the University Paul Sabatier, Toulouse, France, in 1965, 1968, and 1972,
respectively. From 1967 to 2002, he
was with the University of Paraı́ba,
and since 2002, he has been a professor of electrical engineering and a
director of the Research Laboratory
on Industrial Electronics and Machine
Drives with the University of Campina
Grande, Brazil. He has worked with
research projects on power converters, fault diagnosis, and PWM strategies. He is a Fellow of the IEEE.
Euzeli Cipriano dos Santos, Jr.,
received his B.S., M.S., and Ph.D. degrees in electrical engineering from
the University of Campina Grande,
Brazil, in 2004, 2005, and 2007, respectively. From August 2006 to March
2009, he was with the Centro Federal
de Educação Tecnológica da Paraı́ba–
UNED/CZ, Cajazeiras, Brazil. From
December 2010 to March 2011, he
was a visiting professor at the University of Siegen, Germany. Since
March 2009, he has been with the
Federal University of Campina Grande,
where he is currently a professor of
electrical engineering. His research
interests include power electronics,
electrical drives, and PWM strategies.
He is a Member of the IEEE.
Cursino Brandão Jacobina
received his B.S. degree in electrical
engineering from the University of
Paraiba, Campina Grande, Brazil, in
1978 and his Diplome d’Etudes Approfondies and Ph.D. degrees from
the Institut National Polytechnique
de Toulouse, France, in 1980 and
1983, respectively. From 1978 to
March 2002, he was with the Electrical Engineering Department, University of Paraı́ba. Since April 2002, he
has been with the Electrical Engineering Department, University of
Campina Grande, Brazil, where he
is now a professor of electrical engineering. His research interests
include electrical drives, power electronics, and energy systems, including PWM strategies. He is a Senior
Member of the IEEE.
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