MAGNT Research Report (ISSN. 1444-8939)
Vol.2 (4):PP. 62-71
A Study of a Three Phase Diode Clamped Multilevel Inverter Performance For Harmonics
Reduction
Rosli Omar, Mohammed Rasheed, Marizan Sulaiman, Ahmed Al-Janad
Universiti Teknikal Malaysia Melaka, Industrial Power, Faculty of Electrical Engineering, Hang Tuah
Jaya 76100 Durian Tunggal, Melaka, Malaysia.
Abstract: This paper presents a comparative study five to nine levels of diode clamped multilevel
inverter, for reduction of harmonics in the multilevel inverter output. The proposed system is designed
using MATLAB/SIMULINK and it consists of diode clamped multilevel inverter. The controller is
based on the sinusoidal pulse width modulation (SPWM) technique which is applied to the purposed
three phase multilevel inverters. The various performances of simulation results of the diode clamped
multilevel inverters have been investigated. The Total harmonic distortion (THDv) of the output
voltage is measured of the five to nine levels of multilevel inverters. Based on varying simulation
results, it is found that the THD voltage of the nine levels is considerably lower than the seven and
five levels diode clamped multilevel inverter.
Keywords- Multilevel inverter, Diode Clamped Inverter (NPC), SPWM.
I. INTRODUCTION
Nowadays, multilevel inverters have become
more attractive for their initial usage in highvoltage and high-power applications. Multilevel
converters (or inverters) have been used for AC
to DC, AC to DC to AC, DC to AC, and DC to
DC power conversion in high power applications
such as utility and large motor drive applications
[1]. Multilevel inverters provide more than two
voltage levels. The generalized multilevel
inverter topology can balance each voltage level
by itself regardless of inverter control and load
characteristics. The concept of multilevel
converters has been introduced since 1975 [2].
The usage of these applications has become more
diverse and affects a wide field of electrical
engineering from a few watts to several hundred
megawatts. Converting static structures that
comprise mainly applications of power
electronics are becoming increasingly powerful,
the technology has had to adapt to the growth of
the power to convert Multilevel inverters have
three topologies.
 Cascaded H-bridge (CHB)
 Diode–Clamped (NPC)
 Flying Capacitors (FC)
Cells with separated DC sources shown in
Fig.1. This growth has been possible to the
development of technologies of semiconductor
components. Changing templates voltage and
current as well as improved performance of these
components has to use more power electronics
performance for applications of greater power
[3]. The emergence and development of new
components controllable powers opening and
closing as the GTO (gate turn-off Thyristor) and
IGBT (insulated gate bipolar transistors) allowed
the design of new converters reliable, fast and
powerful. Thus, all drives (static machine
converter current AC) saw costs are reduced
considerably.Progress in the field of the
microcomputer
(fast
and
powerful
microcontrollers)
Allowed the syndissertation control algorithms
of these sets more efficient converter machine
and robust [4]. The Pulse Width Modulation
(PWM) is a technique to control static converters
for interfacing between a load (electrical
machine) and supply means (three-phase
inverter). It is a technique used for energy
conversion, having its base in the field of
telecommunications (signal processing). It bears
the English name of Pulse Width Modulation
(PWM) or Pulse-Duration Modulation (PDM),
using a name older. Far from being an accessory
element in the chain of variable speed (inverter
power associated with an electric machine), the
PWM stage plays an important role with impact
on the performance of all system performance
driving, loss in the inverter or in the machine, the
acoustic noise, electromagnetic noise, even the
destruction of the system, eg due to over voltages
which occur during the use of long cables [5].
Vol.2 (4):PP. 62-71
(a) Cascaded H-Bridge
(CHB)
(c) Flying capacitor
(FC)
(b) Diode Clamped
(NPC)
Fig 1: Topologies of Multilevel Inverter, (a)
Cascaded H-Bridge (CHB), (b) Diode Clamped
(NPC) (c) Flying Capacitor (FC).
II. MULTILEVEL INVERTER
The Concepts of multilevel inverters (MLI)
depends not only on two voltage levels to create
the AC signal. Instead, it is added to most levels
of voltage to the other to create a form of
reinforced smooth wave, with a low dv/dt and
less harmonic distortion. With more in the
inverter voltage levels it creates a smoother
waveform becomes, but with many levels of
design becomes more complex, with more
components and must be more complex
controller for inverter [6].
The multilevel inverters diagrams Fig. 2.
Illustrates of the inverters have been 2-level
inverter, 3-level inverter, and the N-level inverter.
All the capacitors include to a voltage of Vdc.
Vdc/N-1
Vdc/2
Vdc
Vdc/N-1
Vdc/N-1
a
a
Vdc/2
Vdc/N-1
Vdc/N-1
(a)
(b)
(c)
where the objectives were to improve
performance, simplify PWM strategies and
applications of microprocessors later, to produce
a reduction of harmonic distortion and reduce
switching losses [7]. Has been extended to
several principles support levels based PWM
technology as a means of controlling the active
devices in a multilevel converter. PWM three
techniques commonly used are- the sinusoidal
PWM technology [8].
l)- High-qualify utilization of a DC power supply
that is to deliver a higher output voltage with the
same DC supply.
2)- Good linearity in voltage and/ or current
control.
3)- Low harmonic contents in the output voltage
and/ or currents, especially in the low-frequency
region.
4)- Low switching losses.
A. Sinusoidal Pulse-Width Modulation
Control technology is the most popular
method of pulse width modulation sine adapter’s
two traditional levels. The tem sinusoidal PWM
reference is made to the production of the PWM
output signal with a sine wave as a modulation
signal [9]. The on and off instants of a PWM
signal ill this case, can be determined by
comparing the sinusoidal signal (wave
modulation) with a triangular wave frequency
(carrier wave), as shown in Fig 3 sinusoidal
PWM technology is commonly used in industrial
applications and abbreviated here as SPWM [10].
Frequency of the modulating wave determines
the frequency of the output voltage. The
enlargement of the height of the modulation
a
index of the waveform and determines the
composition turn control the RMS value of the
output voltage [11].
V
Reference single
Carrier wave
Triangle No
4
8
7
Fig. 2. The MLI diagrams of (a) 2-levels (b) 3levels (c) N-llevels.
6
5
0
4
3
2
1
-4
4
Output Voltage
III. PULSE WIDTH MODULATION (PWM)
TECHNIQUES
In the early 1970s, the majority of PWM
inverters using techniques based on the sampling
method. Sinusoidal pulse width modulation of the
primitive techniques, which are used to suppress
the harmonics, present in a quasi-square wave.
Over the years, he has developed technical PWM
0
t
-4
Fig 3: Sinusoidal Pulse-Width Modulations.
The RMS value of the output voltage can be
varied by changing the modulation index. The
Vol.2 (4):PP. 62-71
output voltage of the inverter contains harmonics.
However, to be paid for the harmonics of the
band around the carrier frequency and its
complications [12]. To perform sinusoidal PWM
using analog circuit, use a series of bricks:
1) High-frequency triangular wave generator.
2) Sine wave generator.
3) Comparator.
4) Inverter circuits with dead-band generator
to generate complimentary driving Signals with
required dead band.
IV. TOPOLOGIESMULTILEVELINVERTE
R
B. Diode Clamped Multilevel Inverter
Vdc
2
, Vdc , 0,  Vdc and  Vdc depending on
4
4
2
which switches that are switched on. Waveform
from one-phase leg to the inverter as shown in
Fig 4 in which the steps are clearly visible.
NPCMLI: S with a larger number of voltage
levels the steppes will be smaller and the
waveform smaller to a sinusoidal signal. Of
course, with a higher number of voltage levels
the complexity of the inverter increase and also,
as earlier mentioned, the number of components
needed. To achieve the different voltage levels in
the output a setup of switching state
combinations are used [15].
+
Vdc/2
S1
According to the patent, developed the first
Multi-Level Inverter (MLI) in 1975, and was
cascaded inverter blocking diode source. This
inverter was later derived into the Diode
n
Clamped Multilevel Inverter, also called NeutralPoint Clamped Inverter (NPC), as shown in Fig 4.
NPCMLI topology and the use of voltage
limiting diodes are essential. Shared DC bus is
divided by an even number, depending on the
number of voltage levels of the inverter and the
majority of capacitors in series with the neutral
point in the middle of the line as shown in Fig
4.[13]. The DC bus, with neutral point and
v
capacitors, there are clamping diodes connected
in an M-1 number of valve pairs, where M is the
Vout
number of voltage levels in the inverter (voltage
levels it can generate). By adding two identical
t
circuits the three phases-legs can together
generate a three-phase signal where the sharing
of the DC-bus is possible. Note that the required
number of clamping diodes is very high and a
large number of voltage levels topology NPC
Fig 4: One phase-leg for a five-level NPC
would not be practical due to this fact[14]. Due to
Inverter.
the inverter for clamping diodes connected in
series so that all the diodes can be the same
voltage rating and be able to block the right
V. STUDY OF MUTLILEVEL INVERTER
number of voltage levels. In Fig 4 all diodes are
BASED
ON
rated for Vdc ( Vdc ) and the D1´ diodes need to
ATLAB/SIMULINKMODELING
m 1
2
This paper describes the study of the three
Vdc
block 3 (
) Thus, there are three diodes in
phase
diodes clamped in multilevel inverters
4
using MATLAB/SIMULINK. It describes the
series.
However, for low-voltage application, it is not layout of the proposed multilevel inverters to
necessary to connect a plug-in series to withstand simulate the step-by-step procedure to build the
the voltage, since components with sufficient simulation model. MATLAB / Simulink version
high voltage ratings are easy to find. Can be 7.8 was used to model, analyse and Simulink for
generated with this configuration five voltage five to nine levels for modelling, simulation and
levels between point a and the neutral point n; analysis. It supports the systems, as in the time of
C1
S2
D1
Vdc/4
S3
D1'
D2
C2
S4
Vdc
a
D3
S1'
C3
S2'
D2'
- Vdc/4
D3'
S3'
C4
S4'
_
- Vdc/2
load
Vol.2 (4):PP. 62-71
linear, time samples and non-linear, constantly.
As for the model, Simulink provides the
construction of models and diagrams. Control
block generates a PWM signal is given to the
new level inverters for reduce total harmonic
distortion can be calculated using equations (3.1,
3.2, 3.3).

H
THD 
n2
2
(n)
H2
(1)
Where: H1 is the amplitudes of the
fundamental component, whose frequency is w0
and Hn is the amplitudes of the nth harmonics at
frequency nw0
4 s
(2)
hn 
 cos(n k )
n k 1
4 s
hn 
 cos(n k )letH (n)  hnandH1  h
n k 1

1 s
n2 ( n k 1 cos(n )) 2
(3)
THD 
s
cos(
n

)
k 1
k
C. Sinusoidal Pulse Width Modulation SPWM
The generations of gating signals with
sinusoidal Pulse Width Modulation (SPWM) are
shown in Fig 5(a). There are sinusoidal reference
waves ( ra ,rb and rc ) and each is shifted by
1200. A carrier wave is compared with the
reference signal corresponding to a phase to
generate the gating signal for that phase.
Furthermore, when comparing the carrier
signal  rc
with the reference phase
ra ,rb and rc
it produced g 2 and g 5 ,
respectively as shown in Fig 5(b). The
instantaneous line-to-line output voltage is:
ab  VS  g1  g3 
where;
(4)
ab = Sinusoidal reference.
VS
= Line-to-line output voltage.
The output voltage as shown in Fig 5(c), is
generated by eliminating the condition that two
switching devices in the same arm cannot be
conducted at the same time. The normalized
carrier frequency, mf , should be odd and
multiplied by three. Thus, all phase-voltage
( ra ,rb and rc ) were identical, but 1200 out of
phase was without even harmonics; moreover
harmonics at frequency multiplier of three were
identical in amplitude and phase in all the phases.
For instance, if the ninth harmonic voltage in
phase a is
aN 9  t    ˜9sin  9wt 
where;
(5)
aN 9 = Phase-voltage.
wt = 2 f .
The corresponding ninth harmonics in phase b
would be,
aN 9 t    ˜9 sin 9wt 120)   ˜9 sin 9wt 1080)   ˜9 sin 9wt 
Thus,
(6)
the
ac output line voltage
ab aN bN does not contain the ninth
harmonics. Therefore, for the odd multiples of
three time of the normalized carrier frequency
mf , the harmonics in the ac output voltage
appeared to be at a normalized frequency fh
centred around mf and its multiple, specifically,
at
n  jmf k
n  jmf k 1
(7)
(8)
where;
mf = Carrier frequency.
Besides, it is considered as good quality for
the output voltage if the modulation index (MI) is
in the range of 0 to 0.95. In the case of MI is
greater than 0.95, there is a direct correlation
between the anti-wave quality and amplitude of
the output voltage if the quality decreases, and
then increases the output voltage wave size. The
SPWM technology has its limitations regarding
the maximum voltage that can be achieved, and
the transfer of power. In the case of a three-phase
inverter, the proportion of the main ingredient to
the line of maximum possible line voltage to a
DC supply voltage is 86.6% and this indicates the
use of poor DC power supply. Besides, the
SPWM is an effective way to reduce the lower
harmonics of the system while varying the output
voltage. However, the low-frequency harmonic
content is in minimum value
Vol.2 (4):PP. 62-71
Vra
Vrb
Vrc
V
(a) 0
wt
V+
wt
(b)
0
(c)
wt
-V
wt
Fig 5: Sinusoidal Pulse Width Modulation for
three-phase inverter.
D. Models of Diodes Clamped in Multilevel
Inverter(NPC)
In order to convert five level of multilevel
inverter, it requires control signal. Five level of
multilevel inverter has (m-1) levels, where “m” is
the number of voltage levels. Thus, the controller
of the five level inverter needs eight control
signals. Fig 6, show the control signals generated
by the Diodes Clamped in Multilevel Inverter.
Moreover, the simulation diagrams for the seven
and nine level similarly are shown in one block.
Four sets of saturation phase arm devices are
connected to the block. Thus, the lower four
signals can be generated from the major brands,
but this requires the signals to be reversed and the
dead time to be included.
Next, in the implementation of SPWM system,
the samples were regularly implemented to
reduce the carrier frequency of equity in 2500 for
the implementation of the total harmonic
reduction (THDv), which is less than 5%, based
on many calculations. In this system, block
consists of 4 switches GTO in Diodes Clamped
(NPC) Thyristor as shown in Figure 7. the diodes
in the multi-level inverter (NPCMLI) are not
used for generating control signals. This is due to
the low levels of harmonic that have been created
by the multi-level converters that are able to
work within the switching frequencies. Therefore,
it is easy to calculate the modulating wave
compared to the sampling frequency.
Fig 6:Simulink Multilevel Inverter diagram
with Five Levels of control signal generated by
Clamped Diodes.
Fig 7: Switching GTO Thyristor for five Levels
with Diodes Clamped in Multilevel Inverter.
VI. HARMONIC REDUCTION BY INCREASING
THE NUMBER OF VOLTAGE
MULTILEVEL INVERTERS
LEVEL
IN
Reduction of harmonics in multilevel
converters could not be achieved by increasing
the number of levels of the staircase wave form
output. THD was produced less by increasing the
number of voltage sources. The effective values
of the output voltage depended on the number of
units in a multilevel inverter. The switching
pattern that was used in this dissertation for all of
the multilevel inverters was indeed a harmonic
elimination method. In this method, the switching
angles for the switches were calculated in such a
way that the lower dominant harmonics were
eliminated. In this study, the cases of 5-level, 7level and 9-level multilevel inverters were
investigated. For the 5-level inverter, the 5th
harmonic was eliminated. On the other hand, as
for the 7-level inverter, the and the harmonic
were removed. Lastly, in the 9-level inverter, the,
and harmonics were eliminated. The Fourier
analysis was conducted to determine the
frequency spectra of the output wave form. The
Vol.2 (4):PP. 62-71
Fourier series of a 5-level unity DC source is
shown in (9).
and the output voltage was 167.6 V RMS in
value. When the Modulation Index decreased to
0.8, as shown in Fig 9, the inverter output voltage
2V 
f  t   f 1  t   f 2  t   dc   cos  h1   cos  h 2  (9)
was equal to 158.7 V RMS. The number of steps
 h 1
for both the figures were 5 (n=5) for the quarter
wave and in the case of full wave, the number of
2Vdc   2
 sin  hwt 
(10) steps was 10 (2n=10,n=5).The simulation result

 [cos  h1  h ]
 h 1  i 1
is shown in Fig 10, for the five-level diodes
clamped in the multilevel inverter. The output
VII.
SIMULATION RESULTS
voltage wave form for line to line in the of
This paper presents the data and the results number of steps in this level increased to 10 for
gathered from the preceding paper. In this work, the quarter wave and 20 steps for full wave, with
two types of multilevel inverter; diodes clamped the Modulation Index equal to 0.95, whereas, the
(NPC), were tested with three phases, using output voltage produced 285.5 V RMS. When the
sinusoidal pulse width modulation (SPWM) Modulation Index decreased to 0.8, the output
control inverter, and a simulation module by voltage value was equal to 272.6 V RMS. The
MATLAB/SIMULINK three phase multilevel number of steps used was similar, as in Fig 11.
The THDV for voltage for the five level output
inverters. Based on the simulation results, a Fivelevel to Nine levels (odd levels) of SPWM diodes clamped in the multilevel inverter was
inverters was presented to alleviate harmonic measured when the Modulation Index was equal
components of output voltage. The inverters were to 0.95. It was found that the value of THDV for
designed in different ways, the multilevel voltage was around 7.21%, as shown in Fig 12.
inverters applied a GTO Thyristor inverter, which Furthermore, FFT analysis is shown in Fig 13 for
generated 50 Hz. Additionally, the selected the five level Diodes clamped in the multilevel
carrier frequency was 2500 Hz and he inverter output. The THDV for voltage obtained
from the output of diodes clamped in the
modulation index was equal to 0.8 and 0.95.
multilevel inverter when the Modulation Index
A. Diode Clamped Multilevel Inverter Results
was equal to 0.8, was actually lower when the
The simulation result is shown in Fig 8. As for Modulation Index was equal to 0.95 and its value
the five-level diodes clamped in the multilevel was 7.06%.
inverter, the output voltage wave form for line to
neutral with Modulation Index was equal to 0.95
300
200
Phase Voltage (V)
Phase Voltage (V)
200
100
0
-100
0
-100
-200
-200
0
100
0.02
0.04
0.06
Time (sec)
0.08
0.1
-300
0
500
500
Line Voltage (V)
0
-500
0
0.02
0.04
0.06
Time (sec)
0.08
Fig 10. Line Voltage of MI=0.95
0.04
0.06
Time (sec)
0.08
0.1
Fig 9.Phase Voltage of MI= 0.8
Line Voltage (V)
Fig 8. Phase Voltage of MI=0.95
0.02
0.1
0
-500
0
0.02
0.04
0.06
Time (sec)
0.08
Fig 11. Line Voltage of MI=0.8.
0.1
Vol.2 (4):PP. 62-71
Fundamental (50Hz) = 382 , THD= 7.06%
Mag (% of Fundamental)
Mag (% of Fundamental)
Fundamental (50Hz) = 382.4 , THD= 7.21%
4
3
2
1
0
0
100
200
300
400
500
600
700
800
900
1000
3.5
3
2.5
2
1.5
1
0.5
0
0
100
200
300
400
500
600
700
800
900
1000
Frequency (Hz)
Frequency (Hz)
Fig 13. Harmonic Voltage of MI=0.8.
Fig 12. Harmonic Voltage of MI=0.95.
The simulation result is shows in Fig 14. for
the Seven-level diodes clamped in the multilevel
inverter. The output voltage wave form for line to
neutral with the Modulation Index was equal to
0.95, as shown in Fig 15, and the output voltage
was 216.4 V RMS. The Modulation Index
decreased to 0.8 as the inverter output voltage
was equal to 174.1 V RMS. The number of steps
for both the figures were 7 (n=7) for the quarter
wave and in the case of full wave, the number of
steps was 14 (2n=14,n=7). Next, the simulation
results for the Seven-level diodes clamped in
multilevel inverter showed that the output voltage
wave form for line to line in the number of steps
increased to 14 for the quarter wave and 28 steps
for the full wave, with Modulation Index equal to
0.95, as shown in Fig 16. The output voltage
produced was about 373.6 V RMS. When the
Modulation Index decreased to 0.8, the output
voltage value was equal to 300.1 V RMS. The
number of steps used was similar as in Fig 17.
The THDV for voltage of the seven level
output for the diodes clamped in multilevel
inverter was around 5.74% when the Modulation
Index was equal to 0.95, as shown in Fig 18. The
FFT analysis is shown in Fig 19 with the seven
level Diodes clamped in multilevel inverter. The
THDV for the voltage obtained when the
Modulation Index was equal to 0.8, was lower
when the Modulation Index was equal to 0.95
and its value was 5.34%.
400
400
Phase Voltage (V)
Phase Voltage (V)
300
200
0
-200
200
100
0
-100
-200
-300
-400
0.02
0.04
0.06
Time (sec)
0.08
-400
0.1
0.02
Fig 14. Phase Voltage of MI=0.95.
0.08
0.1
Fig15.Phase Voltage of MI=0.8.
800
600
600
400
400
Line Voltage (V)
Line Voltage (V)
0.04
0.06
Time (sec)
200
0
-200
200
0
-200
-400
-400
-600
-800
0
0.02
0.04
0.06
Time(sec)
0.08
Fig16. Line Voltage of MI=0.95.
0.1
-600
0
0.02
0.04
0.06
Time (sec)
0.08
Fig 17. Line Voltage of MI=0.8.
0.1
Vol.2 (4):PP. 62-71
Fundamental (50Hz) = 419.4 , THD= 5.34%
Mag (% of Fundamental)
Mag (% of Fundamental)
Fundamental (50Hz) = 304.7 , THD= 5.74%
2
1.5
1
0.5
0
0
100
200
300
400
500
600
700
800
900
1000
3.5
3
2.5
2
1.5
1
0.5
0
Frequency (Hz)
400
500
600
700
800
900
1000
500
Phase Voltage (v)
Phase Voltage (v)
300
voltage produced was about 542.7 V RMS. When
the Modulation Index decreased to 0.8, the output
voltage value was equal to 492.9 V RMS. The
number of steps used was similar as in Fig 23.
The THDV for the voltage of the output diodes
clamped in multilevel inverter was measured
when the Modulation Index was equal to 0.95. It
was found that the value of the THDV of the
voltage was around 3.9%, as shown in Fig 24.
The FFT analysis is shown in Fig 25 for Diodes
clamped in multilevel inverter.
The THDV for the voltage was obtained when
the Modulation Index was equal to 0.8, which
was lower, when the Modulation Index was equal
to 0.95 with value of 3.07%.
500
0
0.02
0.04
0.06
0.08
0
-500
0
0.1
Time (sec)
0.02
0.04
0.06
0.08
0.1
Time (sec)
Fig 20.Phase Voltage of MI=0.95.
Fig 21.Phase Voltage of MI=0.8.
1000
1000
500
Line Voltage (v)
Line Voltage (v)
200
Fig 19.Harmonic Voltage of MI=0.8.
Next, the simulation result is shown in Fig 20.
for the Nine-level diodes clamped in multilevel
inverter. The output voltage wave form for line to
neutral when the Modulation Index was 0.95, was
315.5 V RMS. When the Modulation Index
decreased to 0.8, as shown in Fig 21 the inverter
output voltage was equal to 285.4 V. The number
of steps for both figures were 9 (n=9) for the
quarter wave and in full wave, the number of
steps was 18 (2n=18,n=9). As for the Nine-level
diodes clamped in multilevel inverter, the
simulation result is shown in Fig 22 The output
voltage wave form for line to line in the number
of steps for this level increased to 18 for the
quarter wave and 36 steps for the full wave with
Modulation Index equal to 0.95. The output
0
-500
-1000
0
100
Frequency (Hz)
Fig 18.Harmonic Voltage of MI=0.95.
-500
0
0
0.02
0.04
0.06
0.08
Time (sec)
Fig 22.Line Voltage of MI=0.95.
0.1
500
0
-500
-1000
0
0.02
0.04
0.06
0.08
Time (sec)
Fig 23. Line Voltage of MI=0.8.
0.1
Fundamental (50Hz) = 766.6 , T HD= 3.90%
3
Mag (% of Fundamental)
Mag (% of Fundamental)
Vol.2 (4):PP. 62-71
Fundamental (50Hz) = 694.8 , T HD= 3.07%
1
2
0.5
1
0
0
0
200
400
600
800
1000
Frequency (Hz)
Fig 24.Harmonic Voltage of MI=0.95.
158.7
272.6
7.06%
216.4
373.6
5.74%
MI=0.8
174.1
3000.1
5.34%
MI=0.95
315.5
542.7
3.90%.
MI=0.8
285.4
492.9
3.07%.
Seven MI=0.95
Nine
200
400
600
800
Frequency (Hz)
Fig 25.Harmonic Voltage of MI=0.8.
TABLE I: Comparison of five to nine levels
diodes clamped inverters with different
modulation index (m=0.95,m=0.8).
Phase
Line
Voltage Voltage THDv
Index(M)
RMS
RMS
Diode
Diode
Diode
167.6
285.5
7.21%
Five MI=0.95
MI=0.8
0
VIII. CONCLUSION
The choice was based on the topology of each
inverter and depended on the use of the inverter.
Each topology had its advantages and
disadvantages. By increasing the number of
ACKNOWLEDGMENT
“The authors wish to thank University of
Technical Malaysia Melaka. This work was
supported primarily by the MTUN-CoE, Project
code: MTUN/2012/UTeM-FKE/4 M00012
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