AU J.T. 9(2):79-82 (Oct. 2005)
XC9572 CPLD Board for Digital Design Applications
Wutthikorn Threevithayanon, Kittiphan Techakittiroj,
Narong Aphiratsakun and Myint Shwe
Faculty of Engineering, Assumption University
Bangkok, Thailand
Abstract
This paper presents the implementation of Complex Programmable Logic Devices
(CPLDs) boards for digital design application and develop on XC9500’s Family
Xilinx’s CPLD user programmable in the system (ISP). The objective of the designed
board is for the laboratory experiments in the University. The CPLD board will be use
in Digital Logic Design Laboratory, it will help student to implement various digital
logic circuits such as Digital Clock, Digital Counter or any digital logic in a simple and
efficient way.
Keywords: Complex programmable logic device, CPLD, digital devices, Xilinx,
XC9500, ISP
developed chip, and hardware programming can
be easily configuring the device (Brown and
Verilog 2003).
After
implemented
FPGA
board
(Threevithayanon et al. 2005), the research team
of Assumption University tries to further
develop an educational evaluation CPLD board
for small-medium capacity digital design. Our
work is focused on XC9572 CPLD chip from
Xilinx, which can contain 1600 logic gates.
CPLD is nonvolatile device, so no need to
reprogram when the power is up.
This paper composes of six sections. The
next section reviews on XC9500 family the
CPLD core from Xilinx. Board design and
specification will be discussed in Section 3.
Sections 4 and 5 will discuss with CPLD
software development and board application.
The main summarized will be concluding at the
end of this paper.
1. Introduction
In universities, students spend most of the
time to do tedious task of wire wrapping
individual logic gates. For industries, electronic
product design has to be implemented by
making a Print Circuit Board (PCB) mounting
basic multiples of IC chips. Testing the
designed circuit can be done only after assembly
and
soldering
IC
chips
onto
PCB
(Threevithayanon
et
al.
2005).
Now
programmable logic devices, especially
Complex Programmable Logic Device (CPLD),
have begun to take on this role in system design.
CPLD will reduce both cost and time in
implementing the IC chip and Digital design
compare with the old fashion method. As an
extension
from
the
previous
article
(Threevithayanon et al. 2005), CPLD is taken in
for further research.
Digital logic circuit is widely used in
many applications. Thus many companies
(Xilinx, Atera, Atmel) are trying to develop the
way to implement digital logic circuit easier,
quicker and cheaper. To implement larger
circuits, it is convenient to use a chip that has
larger logic capacity. CPLD is a programmable
logic device supporting implementation of
medium capacity logic circuit and is a
2. Overview of CPLD XC9500 family
The XC9500 CPLD family has six models:
XC9653, XC9572, XC95108, XC95144,
XC95216 and XC95288. The system gates will
range from 800 gates to 6,400 gates following
the end of the model number. These six devices
cover the range from 36 to 288 macrocells.
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AU J.T. 9(2):79-82 (Oct. 2005)
Microcells are functional blocks that perform
combinatorial or sequential logic. System clock
can use up to 125MHz (Xilinx 2002). Chip of
this family have multiple function blocks that
internally connected by a full-populated
FastCONNECT switch matrix. The basic
architecture of XC9572 CPLD is shown as in
Fig.2-1 (Xilinx 1998a and b). The fast
CONNECT switch matrix connects all the
macrocells output to the function blocks. 18
macrocells are group in the function blocks that
provides logic flexibility within the blocks.
Macrocells are functional blocks that perform
combinatorial or sequential logic, and feedback
signals to the fastCONNECT switch matrix
(Xilinx 1998a and b; Alkfe 1998).
pin Plastic Leaded Chip Carrier (PLCC) package
is used in our work due to low cost package and
easily mounted on PCB (Xilinx 1998a and b).
The board is design to be a module plug-in like a
dual in-line (DIP) package as shown in Fig. 3-1.
Board is designed to be plug into a normal
breadboard and easily expanded it peripherals by
an attachable daughter board. The size of final
design board is 5.8x3.2 cm and shown in Fig. 3-2.
The board is designed to train students to connect
with external inputs/outputs. 34 I/Os are
available with some pins reserve for global clock
and global reset pins.
DC 5 V can power the board. The
designed board can operate either 3.3V or 5V,
by connected the reference voltage to pin 32 of
the chip. The board can operate as standalone
once being programmed. The available I/Os and
pins assignment for this CPLD board is given in
the appendix.
44
23
22
5.8 cm
1
3.2 cm
Fig. 2-1. XC9500 architecture
Fig. 3-1. DIP CPLD designed board
The user I/O for each series also depends
on the package of the CPLD. PC44, VQ44,
CS48 PC84, PQ100, TQ100, PQ160, HQ208
and BG352 are examples of the package
combination. JTAG configuration can be used
to configure the 9500 CPLD devices, as they are
supported the IEEE 1149.1 boundary-scan
instruction standard (Xilinx 2002).
3. Board Design and Specification
Our work concentrated on XC9572 CPLD
model from Xilinx. Xilinx’s CPLD XC9572 chip
contains 1,600 gates with the 34 maximum
available I/O ports. PC44 (18 mm by 18 mm) 44-
80
Fig. 3-2. CPLD XC9572 designed board
AU J.T. 9(2):79-82 (Oct. 2005)
Once the circuit is designed and
downloads to the CPLD chip, the chip can be
imagined as an IC itself as in Fig. 5-1. Inputs
and outputs pins (I/Os) have to connect to other
device to check for the designed function. This
board is designed to use with ETS-7000 training
board that contained 7-segments, LEDs, TTL
mode clock. Currently XC9572 CPLD board is
used in Digital Logic Design Laboratory’s
experiment to teach student to implement a
simple digital circuit such as digital clock and
digital counter.
4. Software Development
Xilinx ISE WebPack can develop a logic
circuit by Verilog, VHDL, or Schematic
drawing. Then input and output pin of the
design circuit is assign to map with the
hardware device. After design has been
implemented, the utilization of gates in the chip
can be realized at Place & Route window.
JEDEC file is generated and send to
CPLD chip by JTAG programming board
(Threevithayanon et al. 2005; Xilinx 2002). The
download cable is software compatible with
Xilinx Parallel Cable III, so that can be using
Xilinx’s software for CPLD configuration. The
JTAG download cable is implemented and
shown as in Fig. 4-1.
The 9500 CPLD is supported by the
Xilinx ISE WebPack free development system.
It can be downloaded from Xilinx web site.
ModelSim is the partner software for simulation
and need to register before download to use
synchronous with the Xilinx ISE Webpack.
Input
pins
C P LD
C hip
O utput
pins
D esigned
program m ed
Fig. 5-1. CPLD board implemented as an IC chip
6. Conclusion
For the small-medium scale application,
XC9572 CPLD board is designed by the
research team at Assumption University to use
in Digital Logic Design Laboratory and other
digital circuit applications in the Engineering
Department. With the knowledge of Verilog or
VHDL, the designed board can be used
efficiently to design any complicated digital
circuit logic.
Fig. 4-1. JTAG programming board
5. Board Application
The board designed is very flexible and
can be used for many applications, such as:
• Learning of programmable logic design
• Digital Logic Design application
• ASIC replacement
• System on Chip design
• Digital signal processing
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AU J.T. 9(2):79-82 (Oct. 2005)
7. Appendix
8. References
Pins mapping for CPLD board is given under
(Xilinx 1999). Used pins have to be assign to the
Xilinx ISE Webpack before configure the chip.
Pin No. Xilinx Pin No. Pin Name
Alfke, P. 1998. Choosing a Xilinx Product
Family. Xilinx, XAPP100 (Vol.4), December
1998.
Brown, S.; and Vranesic, Z. 2003.
Fundamentals of Digital Logic with Verilog
Design. McGraw-Hill, New York, NY, USA.
Threevithayanon, W.; Techakittiroj, K.,
Aphiratsakun, N.; and Nyun, S.M. 2005.
XC2S50 FPGA board for microprocessor and
digital design application. AU J.T. 9: 41-5.
Xilinx. 1998a. Designing with XC9500 CPLDs.
XAPP073 (Vol.3), January 1998.
Xilinx. 1998b. XC9572 In-System Programmable CPLD. Product Specification (vol.
3.0), December 1998.
Xilinx. 1999. XC9500 In-System Programmable
CPLD Family (Vol. 5.0), September 1999.
Xilinx. 2002. A Quick JTAG ISP Checklist.
XAPP 104 (Vol. 2.1), June 2002.
Function
1
1
IO1
I/O
2
3
4
5
6
7
8
9
10
11
12
2
3
4
5
6
7
8
9
10
11
12
IO2
IO3
IO4
IO/GCK1
IO/GCK2
IO/GCK3
IO8
IO9
IO10
IO11
IO12
I/O
I/O
I/O
I/O/Clk Input
I/O/Clk Input
I/O/Clk Input
I/O
I/O
I/O
Ground
I/O
13
13
IO13
I/O
14
14
IO14
I/O
*15
15
TDI
Test Data Input
*16
16
TMS
Test Mode Select
*17
17
TCK
Test Clk Input
18
18
IO18
I/O
19
19
IO19
Input/ Output
20
20
IO20
I/O
21
21
Vcc
Vcc
22
22
IO22
I/O
23
23
Gnd
Ground
24
24
IO24
I/O
25
25
IO25
I/O
26
26
IO26
I/O
27
27
IO27
I/O
28
28
IO28
I/O
29
29
IO29
I/O
*30
30
TDO
Test Data Output
31
31
Gnd
Ground
32
32
Vccio
I/O reference
33
33
IO33
I/O
34
34
IO34
I/O
35
35
IO35
I/O
36
36
IO36
I/O
37
37
IO37
I/O
38
38
IO38
I/O
39
39
IO/GSR
I/O/Set-Reset
40
40
IO/GTS2
I/O/3-State
41
41
Vcc
Vcc
42
42
IO/GTS1
II/O/3-State
43
43
IO43
I/O
* Pins
for JTAG connection
4415, 16, 17 and
44 30 are used
IO44
I/O
* Pins 15, 16, 17 and 30 are used for JTAG connection
82