a
High Speed, Low Noise Quad
Operational Amplifier
OP471
FEATURES
Excellent Speed: 8 V/s Typ
Low Noise: 11 nV/÷Hz @ 1 kHz Max
Unity-Gain Stable
High Gain Bandwidth: 6.5 MHz Typ
Low Input Offset Voltage: 0.8 mV Max
Low Offset Voltage Drift: 4 V/C Max
High Gain: 500 V/mV Min
Outstanding CMR: 105 dB Min
Industry Standard Quad Pinouts
PIN CONFIGURATIONS
14-Lead
Hermetic Dip
(Y-Suffix)
14-Lead
Plastic Dip
(P-Suffix)
OUT A
1
14
OUT D
OUT A
1
14
OUT D
–IN A
2
13
–IN D
–IN A
2
13
–IN D
+IN A
3
12
+IN D
+IN A
3
12
+IN D
V+
4
11
V–
V+
4
11
V–
GENERAL DESCRIPTION
+IN B
5
10
+IN C
+IN B
5
10
+IN C
The OP471 is a monolithic quad op amp featuring low noise,
11 nV/÷Hz Max @ 1 kHz, excellent speed, 8 V/ms typical, a
gain bandwidth of 6.5 MHz, and unity-gain stability.
–IN B
6
9
–IN C
–IN B
6
9
–IN C
OUT B
7
8
OUT C
OUT B
7
8
OUT C
OP471
The OP471 has an input offset voltage under 0.8 mV and an
input offset voltage drift below 4 mV/∞C, guaranteed over the full
military temperature range. Open-loop gain of the OP471 is over
500,000 into a 10 kW load ensuring outstanding gain accuracy
and linearity. The input bias current is under 25 nA limiting
errors due to signal source resistance. The OP471’s CMR of
over 105 dB and PSRR of under 5.6 mV/V significantly reduce
errors caused by ground noise and power supply fluctuations.
OP471
16-Lead SOIC
(S-Suffix)
OUT A 1
16
OUT D
2
15
–IN D
+IN A 3
14
+IN D
13
V–
–IN A
V+ 4
The OP471 offers excellent amplifier matching which is important
for applications such as multiple gain blocks, low-noise instrumentation amplifiers, quad buffers and low-noise active filters.
The OP471 conforms to the industry standard 14-lead DIP
pinout. It is pin-compatible with the LM148/LM149, HA4741,
RM4156, MC33074, TL084 and TL074 quad op amps and can
be used to upgrade systems using these devices.
OP471
+IN B 5
12
+IN C
–IN B 6
11
–IN C
OUT B 7
10
NC 8
9
OUT C
NC
NC = NO CONNECT
For applications requiring even lower voltage noise the OP470
with a voltage density of 5 nV/÷Hz Max @ 1 kHz is recommended.
V+
BIAS
OUT
–IN
+IN
V–
Figure 1. Simplified Schematic
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
OP471–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 15 V, T = 25C, unless otherwise noted.)
S
Parameter
Symbol
Input Offset Voltage
VOS
Input Offset Current
IOS
Input Bias Current
Conditions
A
Min
OP471E
Typ Max
OP471F
Min Typ Max
OP471G
Min Typ Max
Unit
0.25 0.8
0.5
1.5
1.0
1.8
mV
VCM = 0 V
4
10
7
20
12
30
nA
IB
VCM = 0 V
7
25
15
50
25
60
nA
Input Noise Voltage
en p-p
0.1 Hz to 10 Hz
250 500
250 500
250 500
nV p–p
Input Noise
Voltage Density2
en
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
9
7
6.5
9
7
6.5
9
7
6.5
nV/÷Hz
nV/÷Hz
nV/÷Hz
Input Noise
Current Density
in
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
1.7
0.7
0.4
1.7
0.7
0.4
1.7
07
0.4
Large-Signal
Voltage Gain
AVO
V = ± 10 V
RL = 10 kW
RL = 2 kW
500
350
700
550
300 500
175 275
300 500
175 275
V/mV
V/mV
Input Voltage Range3
IVR
± 11
± 12
± 11 ± 12
± 11 ± 12
V
Output Voltage Swing
VO
RL ≥ 2 kW
± 12
± 13
± 12 ± 13
± 12 ± 13
V
Common-Mode
Rejection
CMR
VCM = ± 11 V
105
120
95
95
dB
Power Supply
Rejection Ratio
PSRR
VS = 4.5 V to 18 V
Slew Rate
SR
Supply Current
(All Amplifiers)
ISY
No Load
9.2
Gain Bandwidth
Product
GBW
Av = 10
6.5
6.5
6.5
Channel Separation1
CS
VO = 20 V p-p
fO = 10 Hz
150
125 150
125 150
dB
Input Capacitance
CIN
2.6
2.6
2.6
pF
Input Resistance
Differential-Mode
RIN
1.1
1.1
1.1
MW
Input Resistance
Common-Mode
RINCM
11
11
11
GW
Settling Time
tS
4.5
7.5
4.5
7.5
4.5
7.5
ms
ms
1
1
6.5
125
AV = 1
To 0.1%
To 0.01 %
16
12
11
5.6
8
11
115
5.6
6.5
16
12
11
17.8
8
9.2
11
pA÷Hz
pA÷Hz
pA÷Hz
115
5.6
6.5
16
12
11
17.8
8
9.2
mV/V
V/ms
11
mA
MHz
NOTES
1
Guaranteed but not 100% tested.
2
Sample tested.
3
Guaranteed by CMR test.
–2–
REV. A
OP471
(Vs = ±15 V, –25 C £ TA £ 85C for OP471E/F, –40C £ TA £ 85 for OP471G,
ELECTRICAL CHARACTERISTICS unless otherwise noted.)
OP471G
Min Typ Max
Input Offset Voltage
VOS
0.3
1.1
0.6
2.0
1.2
Average Input
Offset Voltage Drift
TCVOS
1
4
2
7
4
Input Offset Current
los
VCM = 0 V
5
20
8
40
20
50
nA
IB
VCM = 0 V
13
50
25
70
40
75
nA
Large-Signal
Voltage Gain
Avo
VO = ± 10 V
RL = 10 kW
RL = 2 kW
Input Voltage Range*
IVR
Output Voltage Swing
VO
Common-Mode
Rejection
Power Supply
Rejection Ratio
Supply Current
(All Amplifiers)
Min
OP471F
Min Typ Max
Symbol
Input Bias Current
Conditions
OP471E
Typ Max
Parameter
2.5
Unit
mV
mV/∞C
375
250
600
400
200 400
125 200
200 400
125 200
V/mV
± 11
± 12
± 11 ± 12
± 11 ± 12
V
RL ≥ 2 kW
± 12
± 13
± 12 ± 13
± 12 ± 13
V
CMR
VCM = ± 11 V
100
115
90
90
dB
PSRR
VS = ± 4.5 V to ± 18 V
3.2
10
18
31.6
18
31.6
mV/V
ISY
No Load
9.3
11
9.3
11
9.3
11
mA
110
110
*Guaranteed by CMR test.
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ± 1.0 V
Differential Input Current2 . . . . . . . . . . . . . . . . . . . . ± 25 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . Continuous
Storage Temperature Range
P, Y-Package . . . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C
Junction Temperature (Ti) . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
OP471E, OP471F . . . . . . . . . . . . . . . . . . . –25∞C to +85∞C
OP471G . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
NOTES
1
Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.
2
The OP471’s inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise performance. If differential
voltage exceeds ± 1.0 V, the input current should be limited to ± 25 mA.
Package Type
JA*
JC
Unit
14-Lead Hermetic DIP(Y)
94
10
∞C/W
14-Lead Plastic DIP(P)
76
33
∞C/W
16-Lead SOIC (S)
88
23
∞C/W
*␪JA is specified for worst-case mounting conditions, i.e., ␪JA is specified for device
in socket for TO, CERDIP, PDIP packages; ␪JA is specified for device soldered to
printed circuit board for SO packages.
ORDERING GUIDE
TA = 25∞C
VOS MAX
(mV)
800
1,500
1,800
1,800
Package Options
Operating
Temperature
Range
14-Lead CERDIP Plastic
OP471EY
OP471FY*
OP471GP
OP471GS
IND
IND
XIND
XIND
*Not for new design. Obsolete April 2002.
For military processed devices, please refer to the standard
microcircuit drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
5962-88565022A - OP471ARCMDA
5962-88565023A - OP471ATCMDA
5962-8856502CA - OP471AYMDA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP471 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
OP471–Typical Performance Characteristics
100
10
TA = 25C
20
10
5
4
3
I/F CORNER = 5Hz
AT 10Hz
1s
5mV
NOISE VOLTAGE – 100nV/DIV
40
30
VOLTAGE NOISE – nV/ Hz
VOLTAGE NOISE – nV/ Hz
TA = 25C
VS = 15V
8
AT 1kHz
6
4
100
90
10
TA = 25C
VS = 15V
0%
2
0
1
1
10
100
FREQUENCY – Hz
2
1k
15
8
10
20
INPUT OFFSET VOLTAGE – V
20
10
I/F CORNER = 5Hz
2
300
200
100
0
–75 –50
1
10
100
FREQUENCY – Hz
CHANGE IN OFFSET VOLTAGE – V
VS = 15V
40
30
1
4
6
TIME – Seconds
TPC 3. 0.1 Hz to 10 Hz Noise
400
TA = 25C
VS = 15V
1k
–25 0
25
50 75
TEMPERATURE – C
100
INPUT OFFSET CURRENT – nA
9
10
5
14
12
10
8
6
4
2
0
1
2
3
TIME – Minutes
4
5
TPC 6. Warm-Up Offset
Voltage Drift
10
20
15
16
TPC 5. Input Offset Voltage vs.
Temperature
TPC 4. Current Noise Density
vs. Frequency
VS = 15V
VCM = 0V
TA = 25C
VS = 15V
18
0
125
10
VS = 15V
VCM = 0V
TA = 25C
VS = 15V
8
INPUT BIAS CURRENT – nA
5
4
3
2
20
TPC 2. Voltage Noise Density
vs. Supply Voltage
100
VOLTAGE NOISE – nV/ Hz
10
SUPPLY VOLTAGE – V
TPC 1. Voltage Noise Density
vs. Frequency
INPUT BIAS CURRENT – nA
5
0
7
6
5
4
3
2
9
8
7
6
1
0
–75 –50
–25 0
25
50 75
TEMPERATURE – C
100
125
TPC 7. Input Bias Current vs.
Temperature
0
–75 –50
–25 0
25 50
75
TEMPERATURE – C
100 125
TPC 8. Input Offset Current vs.
Temperature
–4–
5
–12.5
–7.5
–2.5
2.5
7.5
12.5
COMMON-MODE VOLTAGE – V
TPC 9. Input Bias Current vs.
Common-Mode Voltage
REV. A
OP471
TA = 25C
VS = 15V
100
90
80
70
60
50
40
30
TA = +125C
8
TA = –55C
6
4
VS = 15V
9
TOTAL SUPPLY CURRENT – mA
110
TA = +25C
TOTAL SUPPLY CURRENT – mA
120
CMR – dB
10
10
130
8
7
6
5
4
3
20
10
1
100
1k
10k
FREQUENCY – Hz
100k
2
1M
TPC 10. CMR vs. Frequency
–PSR
70
60
50
+PSR
40
30
20
10
0
10
1
100
25
15
140
GAIN
5
PHASE MARGIN
= 57
160
0
180
–5
200
220
2
3
4 5 6 7 8 9 10
FREQUENCY – MHz
–10
1
TPC 16. Open-Loop Gain,
Phase Shift vs. Frequency
REV. A
70
60
50
40
30
10
100
1k
75
100 125
60
40
20
0
–20
1k
10k 100k 1M 10M 100M
10k
100k
1M
FREQUENCY – Hz
8
VS = 15V
GBW
1000
500
0
10M
TPC 15. Closed-Loop Gain
vs. Frequency
80
1500
0
50
TA = 25C
VS = 15V
TA = 25C
RL = 10k
100
120
10
90
80
2000
OPEN-LOOP GAIN – V/mV
PHASE
110
100
TPC 14. Open-Loop Gain vs. Frequency
PHASE SHIFT – Degrees
OPEN-LOOP GAIN – dB
20
80
TA = 25C
VS = 15V
FREQUENCY – Hz
80
TA = 25C
VS = 15V
25
TPC 12. Total Supply Current
vs. Temperature
1
TPC 13. PSR vs. Frequency
0
TPC 11. Total Supply Current
vs. Supply Voltage
20
10
0
1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
–25
TEMPERATURE – C
CLOSED-LOOP GAIN – dB
PSR – dB
90
80
OPEN-LOOP GAIN – dB
110
100
2
–75 –50
20
SUPPLY VOLTAGE – V
140
130
120
TA = 25C
VS = 15V
15
PHASE MARGIN – Degrees
140
130
120
10
5
0
5
10
15
SUPPLY VOLTAGE – V
20
TPC 17. Open-Loop Gain vs.
Supply Voltage
–5–
70
6
60
4
50
40
–75 –50 –25
2
GAIN-BANDWIDTH PRODUCT – MHz
10
0
0 25 50 75 100 125 150
TEMPERATURE – C
TPC 18. Gain-Bandwidth Product,
Phase Margin vs. Temperature
OP471
TA = 25C
VS = 15V
THD = 1%
20
16
12
8
TA = 25C
VS = 15V
16
POSITIVE
SWING
14
12
NEGATIVE
SWING
10
8
6
4
4
240
180
120
AV = 100
60
2
10k
100k
1M
FREQUENCY – Hz
AV = 1
0
100
10M
1k
LOAD RESISTANCE – 170
9.0
TA = 25C
VS = 15V
VO = 20V p-p TO 100kHz
160
CHANNEL SEPARATION – dB
–SR
8.0
+SR
7.5
7.0
6.5
10k
TPC 20. Maximum Output Voltage
vs. Load Resistance
TPC 19. Maximum Output Swing
vs. Frequency
8.5
150
140
130
120
110
100
90
80
70
60
6.0
0
25
50
75
–75 –50 –25
TEMPERATURE – C
50
10
100 125
TA = 25C
VS = 15V
AV = 1
90
10
0%
TPC 25. Large-Signal Transient
Response
1M
10M
1k
10k 100k
1M
FREQUENCY – Hz
10M
100M
TPC 21. Closed-Loop Output
Impedance vs. Frequency
1
TA = 25C
VS = 15V
VO = 10V p-p
RL = 2k
0.1
0.01
AV = 10
AV = 1
0.001
10
100
1k
FREQUENCY – Hz
10k
TPC 24. Total Harmonic Distortion
vs. Frequency
TA = 25C
VS = 15V
AV = 1
90
10
5µs
1k
10k
100k
FREQUENCY – Hz
100
0%
5V
100
TPC 23. Channel Separation vs.
Frequency
TPC 22. Slew Rate vs. Temperature
100
0
100
TOTAL HARMONIC DISTORTION – %
0
1k
SLEW RATE – V/s
TA = 25C
VS = 15V
300
OUTPUT IMPEDANCE – 24
18
MAXIMUM OUTPUT – V
PEAK-TO-PEAK AMPLITUDE – V
360
20
28
0.2µs
50mV
TPC 26. Small-Signal Transient
Response
–6–
REV. A
OP471
100
5k
500
1/4
OP471
TOTAL NOISE – nV/ Hz
V1 20V p-p
50k
50
1/4
OP471
OP11
10
OP400
OP471
V2
OP470
RESISTOR
NOISE ONLY
CHANNEL SEPARATION = 20 LOG
V1
V2 / 1000
1
100
Figure 2. Channel Separation Test Circuit
1k
10k
RS – SOURCE RESISTANCE – 100k
Figure 4. Total Noise vs. Source Resistance (Including
Resistor Noise) at 1 kHz
+18V
2
+1V
3
100
6
4
1
A
5
+1V
11
B
7
9
–1V
10
TOTAL NOISE – nV/ Hz
–18V
13
C
8
D
12
–1V
14
OP11
OP400
10
OP471
OP470
RESISTOR
NOISE ONLY
Figure 3. Burn-In Circuit
1
100
APPLICATIONS INFORMATION
Voltage and Current Noise
The OP471 is a very low-noise quad op amp, exhibiting a typical
voltage noise of only 6.5 Hz @ 1 kHz. The low noise characteristic of the OP471 is, in part, achieved by operating the input
transistors at high collector currents since the voltage noise is
inversely proportional to the square root of the collector current.
Current noise, however, is directly proportional to the square
root of the collector current. As a result, the outstanding voltage
noise performance of the OP471 is gained at the expense of current
noise performance which is typical for low noise amplifiers.
To obtain the best noise performance in a circuit, it is vital to
understand the relationship between voltage noise (en), current
noise (in), and resistor noise (et).
Total Noise and Source Resistance
The total noise of an op amp can be calculated by:
En =
(e n ) + (inR S ) + (et )
2
2
2
where:
100k
Figure 5. Total Noise vs. Source Resistance (Including
Resistor Noise) at 10 Hz
Figure 4 shows the relationship between total noise at 1 kHz
and source resistance. For RS < 1 kW the total noise is dominated by the voltage noise of the OP471. As RS rises above 1 kW,
total noise increases and is dominated by resistor noise rather
than by voltage or current noise of the OP471. When RS exceeds
20 kW, current noise of the OP471 becomes the major contributor
to total noise.
Figure 5 also shows the relationship between total noise and source
resistance, but at 10 Hz. Total noise increases more quickly
than shown in Figure 4 because current noise is inversely proportional to the square root of frequency. In Figure 5, current
noise of the OP471 dominates the total noise when RS > 5 kW.
From Figures 4 and 5, it can be seen that to reduce total noise,
source resistance must be kept to a minimum. In applications
with a high source resistance, the OP400, with lower current
noise than the OP471, will provide lower total noise.
En = total input referred noise
en = op amp voltage noise
in = op amp current noise
et = source resistance thermal noise
RS = source resistance
The total noise is referred to the input and at the output would
be amplified by the circuit gain.
REV. A
1k
10k
RS – SOURCE RESISTANCE – –7–
OP471
1000
For reference, typical source resistances of some signal sources
are listed in Table I.
OP11
PEAK-TO-PEAK NOISE – nV
OP400
TABLE I.
OP471
100
Device
Source
Impedance
Strain gauge
< 500 W
Typically used in
low-frequency applications.
Magnetic
tapehead
< 1,500 W
Low IB very important to reduce
self-magnetization problems
when direct coupling is used.
OP471 IB can be neglected.
Magnetic
phonograph
cartridges
< 1,500 W
Similar need for low IB in direct
coupled applications. OP471
will not introduce any
self -magnetization problem.
OP470
RESISTOR
NOISE ONLY
10
100
100k
1k
10k
RS – SOURCE RESISTANCE – Figure 6. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs. Source
Resistance (Includes Resistor Noise)
Figure 6 shows peak-to-peak noise versus source resistance over
the 0.1 Hz to 10 Hz range. Once again, at low values of RS, the
voltage noise of the OP471 is the major contributor to peak-to-peak
noise. Current noise becomes the major contributor as RS increases.
The crossover point between the OP471 and the OP400 for
peak-to-peak noise is at RS = 17 W.
Linear variable < 1,500 W
differential
transformer
Comments
Used in rugged servo-feedback
applications. Bandwidth of
interest is 400 Hz to 5 kHz.
*For further information regarding noise calculations, see “Minimization of
Noise in Op Amp Applications,” Application Note AN-15.
The OP470 is a lower noise version of the OP471, with a typical
noise voltage density of 3.2 nV/÷Hz @ 1 kHz. The OP470 offers
lower offset voltage and higher gain than the OP471, but is a slower
speed device, with a slew rate of 2 V/ms compared to a slew rate
of 8 V/ms for the OP471.
R3
1.24k
R1
5
R2
5
C1
2F
OP471
DUT
OP27E
R5
909
R4
200
C4
0.22F
R6
600k
D1
1N4148
D2
OP15E
1N4148
R9
306k
R8
10k
R10
65.4k
R11
65.4k
C3
0.22F
R14
4.99k
OP15E
R13
5.9k
C2
0.032F
eOUT
C5
1F
R12
10k
GAIN = 50,000
VS = 15V
Figure 7. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
–8–
REV. A
OP471
100
Noise Measurements - Peak-to-Peak Voltage Noise
The circuit of Figure 7 is a test setup for measuring peak-to-peak
voltage noise. To measure the 500 nV peak-to-peak noise specification of the OP471 in the 0.1 Hz to 10 Hz range, the following
precautions must be observed:
80
GAIN – dB
1. The device must be warmed up for at least five minutes. As
shown in the warm-up drift curve, the offset voltage typically
changes 13 mV due to increasing chip temperature after
power-up. In the 10-second measurement interval, these
temperature-induced effects can exceed tens-of-nanovolts.
60
40
20
2. For similar reasons, the device must be well-shielded from
air currents. Shielding also minimizes thermocouple effects.
0
0.01
3. Sudden motion in the vicinity of the device can also “feedthrough”
to increase the observed noise.
4. The test time to measure 0.1 Hz to 10 Hz noise should not exceed
10 seconds. As shown in the noise-tester frequency-response curve
of Figure 8, the 0.1 Hz corner is defined by only one pole. The
test time of 10 seconds acts as an additional pole to eliminate
noise contribution from the frequency band below 0.1 Hz.
0.1
1
FREQUENCY – Hz
10
Figure 8. 0.1 Hz to 10 Hz Peak-to-Peak Voltage Noise
Test Circuit Frequency Response
Noise Measurement - Noise Voltage Density
The circuit of Figure 9 shows a quick and reliable method of
measuring the noise voltage density of quad op amps. Each
individual amplifier is series connected and is in unity-gain, save
the final amplifier which is in a noninverting gain of 101. Since
the ac noise voltages of each amplifier are uncorrelated, they
add in rms fashion to yield:
5. A noise voltage density test is recommended when measuring
noise on a large number of units. A 10 Hz noise voltage density
measurement will correlate well with a 0.1 Hz to 10 Hz
peak-to-peak noise reading, since both results are determined
by the white noise and the location of the 1/f corner frequency.
e OUT = 101 Ê e nA 2 + e nB 2 + e nC 2 + e nD 2 ˆ
Ë
¯
6. Power should be supplied to the test circuit by well bypassed,
low noise supplies, e.g, batteries. These will minimize output
noise introduced through the amplifier supply pins.
The OP471 is a monolithic device with four identical amplifiers.
The noise voltage density of each individual amplifier will
match, giving:
e OUT = 101 Ê 4e n 2 ˆ = 101 (2e n )
Ë
¯
R1
100
1/4
OP471
1/4
OP471
1/4
OP471
R2
10k
1/4
OP471
eOUT
TO SPECTRUM ANALYZER
eOUT (nV Hz) = 101(2en)
VS = 15V
Figure 9. Noise Voltage Density Test Circuit
REV. A
100
–9–
OP471
Noise Measurement - Current Noise Density
The test circuit shown in Figure 10 can be used to measure current
noise density. The formula relating the voltage output to current
noise density is:
(
2
Ê e nOUT ˆ
Á
˜ - 40nV / Hz
Ë G ¯
in =
)
2
adds phase shift in the feedback network and reduces stability. A
simple circuit to eliminate this effect is shown in Figure 11. The
added components, C1 and R3, decouple the amplifier from the
load capacitance and provide additional stability. The values of
C1 and R3 shown in Figure 11 are for load capacitances of up
to 1,000 pF when used with the OP471.
In applications where the OP471’s inverting or noninverting inputs
are driven by a low source impedance (under 100 W) or connected
to ground, if V+ is applied before V–, or when V– is disconnected,
excessive parasitic currents will flow.
RS
where:
Most applications use dual tracking supplies and with the device
supply pins properly bypassed, power-up will not present a
problem. A source resistance of at least 100 W in series with all
inputs (Figure 11) will limit the parasitic currents to a safe level
if V– is disconnected. It should be noted that any source resistance,
even 100 W, adds noise to the circuit. Where noise is required to
be kept at a minimum, a germanium or Schottky diode can be
used to clamp the V– pin and eliminate the parasitic current
flow instead of using series limiting resistors. For most applications, only one diode clamp is required per board or system.
G = gain of 10,000
RS = 100 kW source resistance
Capacative Load Driving and Power Supply Considerations
The OP471 is unity-gain stable and is capable of driving large
capacitive loads without oscillating. Nonetheless, good supply
bypassing is highly recommended. Proper supply bypassing
reduces problems caused by supply line noise and improves the
capacitive load driving capability of the OP471.
R3
1.24k
R1
5
Rf
R2
100k
OP471
DUT
en OUT TO
SPECTRUM ANALYZER
OP27E
OP471
R5
8.06k
R4
200
8V/s
GAIN = 10,000
VS = 15V
Figure 10. Current Noise Density Test Circuit
V+
C2
10F
+
R2
C1
200pF
R1
OP471
100*
C4
10F
+
VOUT
CL
1000pF
C5
0.1F
*
*SEE TEXT
R3
50
Unity-Gain Buffer Applications
When Rf £ 100 W and the input is driven with a fast, large signal
pulse (>1 V), the output waveform will look as shown in Figure 12.
During the fast feedthrough-like portion of the output, the input
protection diodes effectively short the output to the input, and a
current, limited only by the output short-circuit protection, will
be drawn by the signal generator. With Rf ≥ 500 W, the output
is capable of handling the current requirements (IL £ 20 mA at
10 V); the amplifier will stay in its active mode and a smooth
transition will occur.
C3
0.1F
VIN
Figure 12. Pulsed Operation
When Rf > 3 kW, a pole created by Rf and the amplifier’s input
capacitance (2.6 pF) creates additional phase shift and reduces
phase margin. A small capacitor (20 pF to 50 pF) in parallel with
Rf helps eliminate this problem.
APPLICATIONS
Low Noise Amplifier
V–
PLACE SUPPLY DECOUPLING
CAPACITORS AT OP471
Figure 11. Driving Large Capacitive Loads
In the standard feedback amplifier, the op amp’s output resistance
combines with the load capacitance to form a lowpass filter that
A simple method of reducing amplifier noise by paralleling
amplifiers is shown in Figure 13. Amplifier noise, depicted in
Figure 14, is around 5 nV/÷Hz @ 1 kHz (R.T.I.). Gain for each
paralleled amplifier and the entire circuit is 100. The 200 W
resistors limit circulating currents and provide an effective output
resistance of 50 W. The amplifier is stable with a 10 nF capacitive
load and can supply up to 30 mA of output drive.
–10–
REV. A
OP471
High-Speed Differential Line Driver
NOISE DENSITY – 0.58nV/ Hz/DIV
REFERRED TO INPUT
The circuit of Figure 15 is a unique line driver widely used in
professional audio applications. With ± 18 V supplies, the line
driver can deliver a differential signal of 30 V p-p into a 1.5 kW
load. The output of the differential line driver looks exactly like
a transformer. Either output can be shorted to ground without
changing the circuit gain of 5, so the amplifier can easily be set
for inverting, noninverting, or differential operation. The line
driver can drive unbalanced loads, like a true transformer.
+15V
VIN
90
10
0%
R3
200
1/4
OP471E
R1
50
100
Figure 14. Noise Density of Low-Noise Amplifier, G = 100
R2
5k
–15V
R6
200
1/4
OP471E
R4
50
R4
10k
R5
5k
R7
50
VOUT = 100VIN
R8
10k
R2
2k
R9
200
1/4
OP471E
1/4
OP471
R6
2k
R8
5k
R12
200
R10
50
R3
2k
R13
10k
R9
10k
R12
1k
R10
50
1/4
OP471
R5
10k
R11
5k
Figure 15. High-Speed Differential Line Driver
Figure 13. Low-Noise Amplifier
High-Output Amplifier
The amplifier shown in Figure 16 is capable of driving 20 V p-p
into a floating 400 W load. Design of the amplifier is based on a
bridge configuration. A1 amplifies the input signal and drives
the load with the help of A2. Amplifier A3 is a unity-gain inverter
which drives the load with help from A4. Gain of the high output
amplifier with the component values shown is 10, but can
easily be changed by varying R1 or R2.
+15V
C1
10F
+
R5
5k
C2
0.1F
R2
9k
R6
5k
R1
1k
1/4
OP471E
A1
R3
50
R7
50
VIN
C3
0.1F
1/4
OP471E
A2
C4
10F
+
R4
50
RL
R8
50
–15V
Figure 16. High-Output Amplifier
REV. A
–OUT
R14
1k
R7
2k
IN
R1
10k
1/4
OP471E
R11
50
1/4
OP471
–11–
1/4
OP471E
A4
1/4
OP471E
A3
+OUT
OP471
Quad Programmable Gain Amplifier
The combination of the quad OP471 and the DAC8408, a quad
8-bit CMOS DAC, creates a space-saving quad programmable gain
amplifier. The digital code present at the DAC, which is easily
set by a microprocessor, determines the ratio between the fixed
DAC feedback resistor and the impedance the DAC ladder presents
to the op amp feedback loop. Gain of each amplifier is:
where n equals the decimal equivalent of the 8-bit digital code
present at the DAC. If the digital code present at the DAC
consists of all zeros, the feedback loop will be open causing the
op amp output to saturate. The 20 MW resistors placed in parallel
with the DAC feedback loop eliminates this problem with a very
small reduction in gain accuracy.
VOUT
256
= –
VIN
n
VDD
DAC-8408ET
RFBA
VINA
VREF A
IOUT1A
R1
20M
DAC A
+15V
1/4
OP470E
VOUTA
IOUT2A/2B
–15V
RFBB
VINB
VREFB
IOUT1B
DAC B
R2
20M
1/4
OP470E
VOUTB
1/4
OP470E
VOUTC
1/4
OP470E
VOUTD
RFBC
VINC
VREF C
IOUT1C
R3
20M
DAC C
IOUT2C/2D
RFBD
VIND
VREF D
DAC D
DAC DATA BUS
PINS 9 (LSB) – 16 (MSB)
IOUT1D
R4
20M
DGND
Figure 17. Quad Programmable Gain Amplifier
–12–
REV. A
OP471
Low Phase Error Amplifier
R2 = R1
R2
The simple amplifier depicted in Figure 18 utilizes monolithic
matched operational amplifiers and a few resistors to substantially reduce phase error compared to conventional amplifier
designs. At a given gain, the frequency range for a specified phase
accuracy is over a decade greater than for a standard single op
amp amplifier.
R2
K1
1/4
OP471E
A2
The low phase error amplifier performs second-order frequency
compensation through the response of op amp A2 in the feedback loop of A1. Both op amps must be extremely well matched
in frequency response. At low frequencies, the A1 feedback loop
forces V2/(K1 + 1) = VIN. The A2 feedback loop forces Vo/(K1 +1)
= V2/(K1 + 1) yielding an overall transfer function of VO/VIN =
K1 + 1. The dc gain is determined by the resistor divider at
the output, VO, and is not directly affected by the resistor divider
around A2. Note that similar to a conventional single op amp
amplifier, the dc gain is set by resistor ratios only. Minimum
gain for the low phase error amplifier is 10.
1/4
OP471E
A1
VIN
V2
R1
R1
K1
VO
VO = (K1 + 1) V IN
ASSUME: A1 AND A2 ARE MATCHED.
AO (s) = sT
Figure 18. Low Phase Error Amplifier
Figure 19 compares the phase error performance of the low
phase error amplifier with a conventional single op amp amplifier
and a cascaded two-stage amplifier. The low phase error amplifier
shows a much lower phase error, particularly for frequencies where
␻/␤␻T < 0.1. For example, phase error of –0.1∞ occurs at 0.002 ␻/␤␻T
for the single op amp amplifier, but at 0.11 ␻/␤␻T for the low
phase error amplifier.
0
PHASE SHIFT – Degrees
–1
For more detailed information on the low phase error amplifier,
see Application Note AN-107.
–2
SINGLE OP AMP
(CONVENTIONAL
DESIGN)
–3
CASCADED
(TWO STAGES)
–4
–5
LOW-PHASE ERROR
AMPLIFIER
–6
–7
0.001
0.005 0.01
0.05 0.1
FREQUENCY RATIO – 1/, /T
0.5
Figure 19. Phase Error Comparison
REV. A
–13–
1
OP471
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead PDIP Package
(N-14)
0.795 (20.19)
0.725 (18.42)
14
8
0.280 (7.11)
0.240 (6.10)
7
1
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.130
(3.30)
0.160 (4.06)
MIN
0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING
PLANE
0.014 (0.356) 0.045 (1.15)
0.015 (0.381)
0.008 (0.204)
14-Lead CERDIP Package
(Q-14)
0.005 (0.13) MIN 0.098 (2.49) MAX
14
8
PIN 1
1
7
0.100 (2.54) BSC
0.785 (19.94) MAX
0.200 (5.08)
MAX
0.310 (7.87)
0.220 (5.59)
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.070 (1.78) SEATING
PLANE
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
15
0
0.015 (0.38)
0.008 (0.20)
16-Lead SOIC Package
(R-16)
0.4133 (10.50)
0.3977 (10.00)
9
16
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4193 (10.65)
0.3937 (10.00)
8
1
0.050 (1.27)
BSC
0.0118 (0.30)
0.0040 (0.10)
0.1043 (2.65)
0.0926 (2.35)
8
0.0192 (0.49) SEATING
0
0.0125
(0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
–14–
0.0291 (0.74)
45
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
REV. A
OP471
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Deleted WAFER TEST CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
REV. A
–15–
–16–
PRINTED IN U.S.A.
C00307–0–4/02(A)