Construction Analysis
Analog Devices
ADSP-21062-KS-160
a
e
lS
miconductor
In
d
us
try
Since 1964
n
Servi g the G
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b
Report Number: SCA 9704-537
®
15022 N. 75th Street
Scottsdale, AZ 85260-2476
Phone: 602-998-9780
Fax: 602-948-1925
e-mail: ice@primenet.com
Internet: http://www.ice-corp.com/ice
INDEX TO TEXT
TITLE
PAGE
INTRODUCTION
MAJOR FINDINGS
1
1
TECHNOLOGY DESCRIPTION
Assembly
Die Process
2
2-3
ANALYSIS RESULTS I
Assembly
4
ANALYSIS RESULTS II
Die Process and Design
5-7
ANALYSIS PROCEDURE
8
TABLES
Overall Evaluation
Package Markings
Wirebond Strength
Die Material Analysis
Horizontal Dimensions
Vertical Dimensions
9
10
10
10
11
12
-i-
INTRODUCTION
This report describes a construction analysis of the Analog Devices ADSP-21062-KS-160
SHARC Digital Signal Processor. One device which was packaged in a 240-pin Plastic
Quad Flat Package (PQFP) was received for the analysis. The device was date coded 9630.
MAJOR FINDINGS
Questionable Items:1
• Metal 2 aluminum thinned up to 90 percent2 at vias (Figure 16).
Special Features:
• Sub-micron gate lengths (0.55 micron).
1These items present possible quality or reliability concerns.
They should be discussed
with the manufacturer to determine their possible impact on the intended application.
2Seriousness
depends on design margins.
-1-
TECHNOLOGY DESCRIPTION
Assembly:
• The device was packaged in a 240-pin Plastic Quad Flat Package (PQFP). A copper
heat slug (heatsink) was employed on the top of the package (cavity down
orientation). It was internally connected to ground to bias the substrate.
• Wirebonding method: A thermosonic ball bond technique employing 1.2 mil O.D.
gold wire was used.
• Dicing: Sawn (full depth) dicing.
• Die attach: A silver epoxy compound.
Die Process
• Fabrication process: Selective oxidation CMOS process employing a twin-well
process in a P substrate.
• Die coat: No die coat was used on the device.
• Final passivation: A layer of nitride over a layer of silicon-dioxide.
• Metallization: Two levels of metal defined by standard dry-etch techniques. Metal 2
consisted of aluminum with a titanium-nitride cap and a titanium barrier. Metal 1
consisted of aluminum, a titanium nitride cap and barrier, and a titanium adhesion
layer. Standard vias were used between metal 2 and metal 1. Tungsten plugs were
used as the vertical interconnect under metal 1.
• Interlevel dielectric: Interlevel dielectric consisted of two layers of silicon-dioxide
with a planarizing spin-on-glass (SOG) between them.
-2-
TECHNOLOGY DESCRIPTION (continued)
• Pre-metal dielectric: This dielectric consisted of a layer of reflow glass over
densified oxide.
• Polysilicon: Two layers of polysilicon were used on the die. Poly 1 (polysilicon
and tungsten silicide) was used to form redundancy fuses, all gates on the die, and
word lines in the array. Poly 2 was used to form “pull-up” resistors in the cell
array, and formed resistors in fuse blocks which were connected to one end of the
poly 1 fuses. Both poly layers were defined by a dry-etch of good quality.
• Diffusions: Implanted N+ and P+ diffusions formed the sources/drains of
transistors. No silicide was present on diffusions. An LDD process was used with
the oxide sidewall spacers left in place. N+ diffusions were “pushed down” at
tungsten contacts.
• Wells: Planar (no step in LOCOS) twin-well process in a P substrate. No epi layer.
• Redundancy: Fuses consisting of poly 1 were present on the die. Passivation and
interlevel dielectric cutouts were made over the fuses. One end of the fuse structure
was connected to metal 1, while the other end was connected to a poly 2 resistor.
Some laser blown fuses were noted.
• Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a
4T CMOS SRAM cell design. Metal 2 distributed GND and Vcc (via Metal 1), and
formed the bit lines using metal 1 links. Metal 1 was used as the “piggy-back”
word lines. Poly 1 formed the word lines, select, and storage gates. Poly 2 formed
“pull-up” resistors and distributed Vcc.
• Design features: Slotted and beveled Metal 2 bus lines were employed for stress
relief. Both metals 1 and 2 were used in the bond pads.
-3-
ANALYSIS RESULTS I
Assembly:
Figures 1 - 3
Questionable Items:1 None.
Special Features: None.
General Items:
• Overall package: The device was packaged in a 240-pin PQFP. A large copper heat
slug (heatsink) was employed on the top of the package (cavity down orientation). It
was internally connected to GND and the substrate.
• Wirebonding method: A thermosonic ball bond technique employing 1.2 mil gold
wire was used. All bonds were well formed and placed. Bond strengths were
normal as determined by wire pull tests.
• Dicing: Sawn (full depth). No large chips or cracks were noted.
• Die attach: A silver epoxy compound of normal quality.
1These items present possible quality or reliability concerns.
They should be discussed
with the manufacturer to determine their possible impact on the intended application.
-4-
ANALYSIS RESULTS II
Die Process and Design:
Figures 4 - 45
Questionable Items:1
• Metal 2 aluminum thinned up to 90 percent2 at vias (Figure 16).
Special Features:
• Sub-micron gate lengths (0.55 micron).
General Items:
• Fabrication process: Selective oxidation CMOS process employing twin-wells in a
P substrate.
• Process implementation: Die layout was clean efficient. Alignment was good at all
levels.
• Die surface defects: None. No contamination, toolmarks or processing defects
were noted.
• Passivation: A layer of nitride over a layer of silicon-dioxide. Passivation coverage
and edge seal were good.
• Metallization: Two levels of metallization. Metal 2 consisted of aluminum with
titanium-nitride cap and titanium barrier. Metal 1 consisted of aluminum, titaniumnitride cap and barrier, and a titanium adhesion layer. Standard vias were used
between metal 2 and 1. Tungsten plugs were employed under metal 1.
1These items present possible quality concerns.
They should be discussed with the
manufacturer to determine their possible impact on the intended application.
2Seriousness
depends on design margins.
-5-
ANALYSIS RESULTS II (continued)
• Metal patterning: All metal layers were defined by a dry etch of good quality.
• Metal defects: None. No voiding, notching or cracking of the metal layers was
found. No silicon nodules were found following removal of the aluminum.
• Metal step coverage: Metal 2 aluminum thinned up to 90 percent at most vias. The
barrier aided in retaining the connections. Virtually no metal thinning was noted in
metal 1. The tungsten plugs were nearly level with the oxide surface, so no large
steps were present for the metal to cover.
• Vias and contacts: Vias were defined by a two step process while contacts were
defined by a dry-etch. No significant over-etching was noted.
• Interlevel dielectric: Interlevel dielectric consisted of two layers of silicon-dioxide
with a spin-on-glass (SOG) to aid in planarization.
• Pre-metal dielectric: This dielectric consisted of a layer of reflow glass over
densified oxide. No problems were found.
.• Polysilicon: Two layers of polysilicon were employed. Poly 1 (polysilicon and
tungsten silicide) formed the redundancy fuses, all gates on the die, and word lines
in the array. Poly 2 was used to form resistors in the cell array and outside the fuse
blocks. Definition was by a dry etch of good quality. No problems were found.
• Isolation: LOCOS (local oxide isolation). No problems were noted and no step was
present at the well boundaries.
• Diffusions: Implanted N+ and P+ diffusions were used for sources and drains.
Deep (pushed down) N+ diffusions were noted under contacts in N regions.
Diffusions were not silicided. No problems were found.
-6-
ANALYSIS RESULTS II (continued)
• Wells: Twin-wells were employed in a P substrate. No step was present at the well
boundaries, but both wells were delineated by a silicon etch. No problems were
noted.
• Buried contacts: Direct poly-to-diffusion (buried) contacts were only used in the
SRAM array. No problems were found in these areas.
• Redundancy: Poly 1 fuses were present along the row and column decode logic
outside the array. Passivation and interlevel dielectric cutouts were made over the
fuses. Laser blown fuses were noted.
• Memory cells: The die employed a 2 Mbit SRAM array. The memory cells used a
4T CMOS SRAM cell design. Metal 2 distributed GND and Vcc, and formed the
bit lines using metal 1 links. Metal 1 was used as the “piggy-back” word lines.
Poly 1 formed the word lines, select, and storage gates. Poly 2 formed “pull-up”
resistors and distributed Vcc. Cell size was 3.3 x 5.7 microns (19 microns2).
-7-
PROCEDURE
The devices were subjected to the following analysis procedures:
External inspection
X-ray
Delid
SEM of passivation
Passivation integrity test (chemical)
Wirepull test
Passivation removal
SEM inspection of metal 2
Aluminum 2 removal
Delayer to metal 1 and inspect
Aluminum 1 removal and inspect barrier
Delayer to polycide/substrate and inspect
Die sectioning (90° for SEM)*
Measure horizontal dimensions
Measure vertical dimensions
Die material analysis
*Delineation of cross-sections is by silicon etch unless otherwise indicated.
-8-
OVERALL QUALITY EVALUATION: Overall Rating: Normal
DETAIL OF EVALUATION
Package integrity:
Die placement:
Die attach quality:
Wire spacing:
Wirebond placement:
Wirebond quality:
Dicing quality:
Wirebond method
Die attach method
Dicing
G
G
G
N
N
G
G
Thermosonic ball bonds using 1.2 mil
gold wire.
Silver-epoxy
Sawn (full depth)
Die surface integrity:
Toolmarks (absence)
Particles (absence)
Contamination (absence)
Process defects (absence)
General workmanship
Passivation integrity
Metal definition
Metal integrity
Metal registration
Contact coverage
Contact registration
G
G
G
G
N
G
G
NP*
G
G
G
*Metal 2 aluminum thinning up to 90 percent.
G = Good, P = Poor, N = Normal, NP = Normal/Poor
-9-
PACKAGE MARKINGS
TOP
(LOGO) ANALOG DEVICES
ADSP-21062
9630 KS-160
HD/BA5454.1-1.2 (SHARC LOGO)
BOTTOM
S6 2A2
HONG KONG
WIREPULL TEST
Sample
1
# of wires tested:
22
Bond lifts:
0
Force to break - high:
12g
- low:
8g
- avg.:
9.1g
- std. dev.:
0.5
DIE MATERIAL IDENTIFICATION
Overlay passivation:
Nitride over silicon-dioxide.
Metallization 2:
Aluminum with a titanium-nitride cap and a
titanium barrier.
Interlevel dielectric:
Multiple layers of silicon-dioxide.
Metallization 1:
barrier, and a
Aluminum with a titanium-nitride cap and
titanium adhesion layer.
Plugs:
Tungsten.
Pre-metal glass:
Silicon-dioxide.
Silicide (Poly 1):
Tungsten.
- 10 -
HORIZONTAL DIMENSIONS
Die size:
11.9 x 14.9 mm (468 x 586 mils)
Die area:
177 mm2 (274,248 mils2)
Min pad size:
0.11 x 0.11 mm (4.4 x 4.4 mils)
Min pad window:
0.09 x 0.09 mm (3.7 x 3.7 mils)
Min pad space:
40 microns
Min metal 2 width:
0.7 micron
Min metal 2 space:
1.0 micron
Min metal 2 pitch:
1.7 micron
Min metal 1 width:
0.6 micron
Min metal 1 space:
0.7 micron
Min metal 1 pitch:
1.3 micron
Min via:
0.65 micron (round)
Min contact:
0.5 micron (round)
Min polycide width:
0.55 micron
Min polycide space:
0.8 micron
Min gate length* - (N-channel):
0.55 micron
- (P-channel):
0.55 micron
Min LOCOS:
0.8 micron
SRAM cell size:
19.0 microns2
SRAM cell pitch:
3.3 x 5.7 microns
*Physical gate length.
- 11 -
VERTICAL DIMENSIONS
Die thickness:
0.5 mm (21 mils)
Layers
Passivation 2:
0.6 micron
Passivation 1:
0.15 micron
Metal 2 - cap:
0.05 micron (approx.)
- aluminum:
0.75 micron
- barrier:
0.17 micron
Interlevel dielectric - glass 2:
- glass 1:
Metal 1 - cap:
0.5 micron (average)
0.15 micron (average)
0.05 micron (approx.)
- aluminum:
0.5 micron
- barrier:
0.1 micron
- plugs:
0.6 - 1.0 micron
Pre-metal glass:
0.6 micron (average)
Polycide - silicide:
0.1 micron
- poly:
0.13 micron
Local oxide:
0.4 micron
N+ S/D diffusion:
0.2 micron
Deep N+ S/D diffusion:
0.4 micron
P+ S/D diffusion:
0.2 micron
N-well:
2.0 microns (approx.)
P-well:
2.5 microns (approx.)
- 12 -
INDEX TO FIGURES
ASSEMBLY
Figures 1 - 3
DIE LAYOUT AND IDENTIFICATION
Figures 4 - 9
PHYSICAL DIE STRUCTURES
Figures 10 - 46
COLOR DRAWING OF DIE STRUCTURE
Figure 31
EEPROM MEMORY CELL STRUCTURES
Figures 32 - 40
CIRCUIT LAYOUT AND I/O
Figures 41 - 46
- ii -
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Figure 1. Package photographs of the Analog Devices ADSP-21062-KS-160
SHARC Digital Signal Processor. Mag. 1.5x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
top
side
Figure 2. X-ray views of the package. Mag. 3x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
EDGE OF
PASSIVATION
DIE
Mag. 800x
EDGE OF
PASSIVATION
METAL 2
METAL 1
N+
Mag. 6500x
Figure 3. SEM section views of the edge seal.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Figure 4. Portion of the Analog Devices ADSP-21062-KS-160 whole die. Mag. 26x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Figure 5. Portion of the Analog Devices ADSP-21062-KS-160 whole die. Mag. 26x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Figure 6. Portion of the Analog Devices ADSP-21062-KS-160 whole die. Mag. 26x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
PIN 1
Figure 7. Remaining portion of the Analog Devices ADSP-21062-KS-160 whole die. Mag. 26x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Figure 8. Optical views of die markings. Mag. 750x.
Integrated Circuit Engineering Corporation
Figure 9. Optical views of die corners. Mag. 80x.
Analog Devices ADSP-21062-KS-160
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
SLOT
Figure 10. Optical views illustrating a slotted bus line and resolution patterns.
Mag. 410x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
PASSIVATION 1
PASSIVATION 2
METAL 2
METAL 1
LOCOS
POLY 1 GATE
W PLUG
N+ S/D
METAL 2
PASSIVATION 2
METAL 1
LOCOS
W PLUG
POLY 1 GATE
glass etch
Figure 11. SEM section views illustrating general structure. Mag. 13,000x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Mag. 4600x
Mag. 15,000x
Figure 12. SEM views illustrating final passivation. 60°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
PASSIVATION 2
PASSIVATION 1
METAL 2
INTERLEVEL DIELECTRIC
Mag. 26,000x
TIN CAP
ALUMINUM 2
TiN BARRIER
Mag. 52,000x
Figure 13. SEM section views illustrating metal 2 line profiles.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Mag. 3200x
MASK
CHANGES
Mag. 6500x
VIAS
Mag. 6500x
METAL 2
Figure 14. Topological SEM views of metal 2 patterning. 0°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Mag. 10,000x
Mag. 10,000x
TiN CAP
Mag. 20,000x
ALUMINUM 2
Ti BARRIER
Figure 15. Perspective SEM views of metal 2 step coverage. 60°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
PASSIVATION 2
METAL 2
Mag. 13,000x
METAL 1
SOG
LOCOS
POLY 1
METAL 2
Mag. 26,000x
INTERLEVEL
DIELECTRIC
METAL 1
METAL 2
Mag. 52,000x
90% THINNING
METAL 1
Figure 16. SEM section views of typical vias.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
PASSIVATION
INTERLEVEL
DIELECTRIC
SOG
METAL 1
Mag. 26,000x
TiN CAP
ALUMINUM 1
TiN
BARRIER
Ti ADHESION LAYER
Mag. 52,000x
Figure 17. SEM section views of metal 1 line profiles.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
POLY 1
METAL 1
VIA
Figure 18. Topological SEM views of metal 1 patterning. Mag. 6500x, 0°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Mag. 5000x
Mag. 10,000x
TiN CAP
Mag. 20,000x
ALUMINUM 1
TiN
BARRIER
Figure 19. Perspective SEM views of metal 1 step coverage. 60°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Mag. 16,000x
TiN
BARRIER
W PLUG
Mag. 32,000x
Figure 20. Perspective SEM views of metal 1 barrier and plug. 60°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
METAL 1
W PLUG
POLY 1
LOCOS
METAL 1
W PLUG
LOCOS
N+
DEEP N+
METAL 1
W PLUG
P+
Figure 21. SEM section views illustrating typical metal 1 contacts. Mag. 26,000x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Mag. 3200x
Mag. 3200x
N+
Mag. 5000x
POLY 1
P+
Figure 22. Topological SEM views of poly 1 patterning. 0°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Mag. 8000x
Mag. 12,000x
POLY 1 GATE
LOCOS
Mag. 32,000x
DIFFUSION
Figure 23. Perspective SEM views of poly 1 coverage. 60°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
REFLOW GLASS
POLY 1
GATE
N-channel
N+ S/D
GATE OXIDE
DEEP N+ S/D
REFLOW GLASS
POLY 1
GATE
P-channel
P+ S/D
GATE OXIDE
SIDEWALL
SPACER
W SILICIDE
glass etch
POLY 1
Figure 24. SEM section views of typical transistors. Mag. 52,000x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
DENSIFIED OXIDE
POLY 1
LOCOS
GATE
OXIDE
Figure 25. SEM section view of a typical birdsbeak. Mag. 52,000x.
Mag. 1200x
P-WELL
N-WELL
P-SUBSTRATE
METAL 2
LOCOS
Mag. 6500x
P-WELL
P+
N+
Figure 26. Section views illustrating well structure.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Mag. 750x
BLOWN FUSE
Mag. 1000x
Figure 27. Optical views of typical fuses.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
INTACT
FUSE
LASER
BLOWN
FUSE
Mag. 1600x
PASSIVATION
CUTOUT
Mag. 3200x
Figure 28. Topological SEM views of typical fuses. 0°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
BLOWN FUSE
Mag. 2400x
PASSIVATION
CUTOUT
Mag. 4800x
Figure 29. Perspective SEM views of typical fuses. 60°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
CUTOUT
Mag. 6500x
POLY 1
FUSE
CUTOUT
Mag. 13,000x
REFLOW GLASS
LOCOS
POLY 1
FUSE
PASSIVATION 2
METAL 2
Mag. 13,000x
METAL 1
POLY 2
LOCOS
POLY 1 FUSE
Figure 30. SEM section views of a poly 1 fuse.
TiN CAP 1
TiN BARRIER 1
W SILICIDE
SOG
Ti BARRIER
POLY 1
GLASS
PASSIVATION
NITRIDE PASSIVATION
ALUMINUM 2
,,,,
,,,,
ALUMINUM 1
,,,
,,,
,,,
,,,
,,,
,,,
,,
,,
,,
,,,,
,,,,
INTERLEVEL DIELECTRIC
,,,,,
,,,,,
,,,,
,,,
,,,,
Analog Devices ADSP-21062-KS-160
Ti ADHESION LAYER
TiN CAP 2
,,,,,,,,,,
,,,,,,,,,,
PRE-METAL GLASS
W PLUG
LOCAL OXIDE
N-WELL
P-WELL
N+ S/D
DEEP N+
P SUBSTRATE
Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly,
Red = Diffusion, and Gray = Substrate
Figure 31. Color cross section drawing illustrating device structure.
Integrated Circuit Engineering Corporation
GATE OXIDE
P+ S/D
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
GND
metal 2
BIT
BIT
“PIGGY BACK”
WORD LINE
GND
WORD
metal 1
unlayered
BIT
GND
BIT
Figure 32. Perspective SEM views of the SRAM cell array. Mag. 10,000x, 60°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
POLY 2
POLY 1
WORD LINE
POLY 1
POLY 2
POLY 1
Figure 33. Detailed SEM views of the SRAM cell structures (unlayered).
Mag. 42,000x, 60°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
metal 2
GND
BIT
BIT
“PIGGYBACK”
WORD LINE
GND
VCC
metal 1
WORD LINE
unlayered
Figure 34. Topological SEM views of the SRAM cell array. Mag. 3200x, 0°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
GND
BIT
BIT
metal 2
“PIGGYBACK”
WORD LINE
VCC
GND
BIT
BIT
metal 1
Figure 35. Detailed topological SEM views of an SRAM cell. Mag. 13,000x, 0°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
VCC
GND
4
R1
1
BIT
3
BIT
2
R2
GND
unlayered
WORD
R1
BIT
R2
1
2
3
BIT
4
Figure 36. Detailed topological SEM view and schematic of an SRAM cell.
Mag. 13,000x, 0°.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
METAL 2 BIT LINE
Mag. 13,000x
POLY 1
STORAGE
GATE
METAL 1 LINK
N+ S/D
METAL 2 BIT LINE
SOG
Mag. 20,000x
METAL 1 LINK
POLY 2
W
PLUG
POLY 1
SELECT GATE
Mag. 26,000x
N+ S/D
DEEP
N+ S/D
Figure 37. SEM section views of an SRAM cell (parallel to bit line).
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
POLY 2 “PULL-UP”
RESISTOR
POLY 1 STORAGE
GATE
Mag. 35,000x
LOCOS
GATE OXIDE
POLY 2
Mag. 52,000x
POLY 1
LOCOS
N+ S/D
POLY 1 SELECT
GATE
Mag. 52,000x
N+ S/D
GATE OXIDE
DEEP
N+ S/D
Figure 38. SEM section views of SRAM cell details (parallel to bit line).
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
METAL 2
BIT LINE
POLY 1
WORD/SELECT
LINE
BIT LINE
CONTACT
Mag. 13,000x
POLY 1
WORD/SELECT
LINE
LOCOS
GATE OXIDE
Mag. 26,000x
Figure 39. SEM section views of the SRAM cell array (perpendicular to bit lines).
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
METAL
2
SOG
METAL 1 GND
POLY 1 STORAGE GATES
N+ S/D
Mag. 13,000x
POLY 2
POLY 1 STORAGE GATE
LOCOS
N+ S/D
Mag. 26,000x
Figure 40. SEM section views of the SRAM cell array (perpendicular to bit lines).
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
intact
unlayered
Figure 41. Optical views of typical device circuit layout. Mag. 820x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
intact
unlayered
Figure 42. Optical views of typical I/O circuitry. Mag. 400x.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
Au
EDGE OF PASSIVATION
METAL 1
Mag. 3200x
Au
METAL 2
METAL 1
LOCOS
POLY 1
Mag. 13,000x
Figure 43. SEM section views illustrating wirebond interface.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
METAL 2
SOG
METAL 1
POLY 1 GATE
P+ S/D
Mag. 13,000x
SOG
METAL 1
POLY 1 GATE
P+ S/D
Mag. 26,000x
Figure 44. SEM section views of P-channel I/O circuitry.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
METAL 2
METAL 1
N+ S/D
POLY 1 GATE
Mag. 13,000x
SOG
METAL 1
REFLOW GLASS
POLY 1 GATE
N+ S/D
Mag. 26,000x
Figure 45. Additional SEM section views of N-channel I/O circuitry.
Analog Devices ADSP-21062-KS-160
Integrated Circuit Engineering Corporation
METAL 2
POLY 1 GATE
P-WELL
N+ GUARDBAND
N+ S/D
P+ GUARDBAND
N-channel
METAL 2
LOCOS
POLY 1 GATE
P+ S/D
N+ GUARDBAND
P-channel
Figure 46. SEM section views illustrating guardbands at the edge of the I/O circuitry.
Mag. 6500x.