Metal Source/Drain Junctions
Professor K.N.Bhat
Electrical Communication Engineering Department
Indian Institute of Science
Bangalore-560 012
Email : knbhat@gmail.com
E3-327 Nanoelectronics Devices lecture series
Lecture # 28 & 29
8th and 13th November, 2007
1
Metal Source /Drain Junctions
Properties of Schottky Junctions in
Si, Ge and compound semiconductors
Fermi level pinning
2
Nanoscale MOSFET
S/D Junctions are made shallow especially at the gate
edge to reduce their encroachment into the channel.
• ND should be made higher
to keep sheet resistance
constant.
• Upper limit is solid
solubility of dopants.
• Hence shallow junctions
increase external
resistance.
•Abruptness of junctions
reduces while Implanted
dopants are annealed . 3
Need For Metal Source /Drain Contacts
• Parasitic
Resistance of source drain regions of
conventional scaled down MOSFET is primarily
responsible for reduction of Drive currents in
transistor scaling.
I D = WCox [(VGS − IRs ) − Vt ] vinj
• Replacing S/D regions of transistors with Metal
can reduce the series resistance effect.
( Y. Nishi in Japan and S. M. Sze in USA
invented the Metal S/D MOSFET in 1968 !! )
4
Additional benefits of Metal S/D
in scaled down MOSFET
•
Eliminates the parasitic BJT action.
Inherent physical scalability of gate lengths to
sub-10-nm due to atomically abrupt junctions
formed at silicide-silicon interface and also due
to low resistance of metal.
•
• Low temperature processing for S/D formation.
5
Schematic Cross section of SB-MOSFET
Inversion Layer
6
Requirements on SB S/D source drain junctions
• Low barrier heights with the channel and high barrier
height with the substrate.
•In N-channel MOSFET the SB should have hegh
barrier height with the P-substrate and low barrier
height with th n-channel inversion layer.
7
Metal
Semiconductor
Contacts
• Ohmic Contacts
• Rectifying Contacts
8
I-V Characteristics of
contacts
Ohmic contact
I
V
I
Current flows with
minimum voltage drop in
both polarity of voltage
Rectifying Contact
V
Blocks current flow in
one polarity of voltage
9
Metal Semiconductor Contacts
Metal with φm > φs N-Type SC
(a) “M” and “S” not in contact
Metal (M)
Semiconductor (S)
Vacuum Level
φm
Efm
χ
φs
Ec
Ef
EV
10
Definitions
• Work Function : Energy difference
between the Vacuum level and the
Fermi level
• φm–Work function of Metal
• φs– Work Function of
semiconductor
• χ - Electron affinity of electrons in
the conduction band of SC
11
(b) “M” and “S” connected
Electrons transferred to metal till
the Fermi levels equalized. Depletion
layer is created at SC surface
Metal (M)
φm
EFM
δ
Semiconductor (S)
χ
δ
δ is the gap
Vi
Vi is voltage drop
across the gap
EC
EF
EV
12
(C) Gap δ reduced
Electric field is constant.
Vi falls as δ is reduced
Semiconductor (S)
Metal (M)
χ
φm
Vi = Electric field x δ
EC
EF
EFM
δ
EV
13
(d) δ very small
Electrons with energy > φBn can
tunnel across the gap
Metal (M) Semiconductor (S)
φm
χ
φBn
Vi = Electric field x δ
EC
EF
EFM
δ
EV
14
(e) when δ = 0
φBn = ( φm - χ ) is the barrier height
for electron transfer from “M” to “S”
qVbi = φBn- (EC- EF)
S
M
φm
EF
χ
φBn
φBp = (Eg- φBn)
Depleted Layer width Wd
qVbi
EC
EF
EV
15
Rectifying MS Contact
(i) Thermal equilibrium
Large value of φBn
Depleted
M
Io
φBn
EF
Io
S
N-type
Jo = q nso vx
Electron
distribution as
function of
energy
EC
EF
EV
nno
Electron
Concentration n = n e − qVbi / kT
so
no
In Silicon
Distance in SC
16
Thermionic emission : Current Density Jo
If v x is the mean velocity of electrons emitted over the
barrier in the x-direction, we have J o = q nso v x − − − (1)
nso = nno e − qVbi / kT = N c e − ( Ec − EF ) / kT . e − qVbi / kT
= Nce
−φ Bn / kT
J o = ( qN c v x ) e −φ Bn / kT − − − − (3)
Using (2) in (1),
 2π m* kT 
n
Nc = 2 

2



h
− − − − (2)
3/ 2
and

vx =
Substituting for Nc and vx in (3),
A* =
4π mn* qk 2
kT
2π mn*
* 2 −φ Bn / kT
Jo = A T e
mn*
= 120
Amp / cm 2 / K 2
mo
h3
A* is Richardsons Constant
17
Rectifying MS Contact
(ii) Reverse biased
Io
M
S
J o = A*T 2 e −φ Bn / kT
VR
Io= IMS
φ Bn
Electrons from SC do not cross
the barrier = q ( Vbi +VR )
EC
EFn
EF
EV
IMS is due to electron flow from M to S
J o = A*T 2 e −φ Bn / kT
J0 is higher if
φ Bn
is lower
18
Rectifying MS Contact : (iii) Forward biased
J SM = qns v x
ns = nno e − q(Vbi −V ) / kT = nso eV / VT
J SM = qns v x = qnso eV / VT v x = ( qnso v x )eV / VT
V/VT -1)
=
I
(e
I o
M
I
S
V
ISM
EF
IMS =Io
V / VT
∴J SM = J o e
J = J SM − J MS
= J o eV / VT − J 0
EC
EFn
ISM=Io eV/VT
EV
ISM = is due to electron flow from S to M
19
I.V Characteristics
I0
is high when φBn is low with n-type s.c
20
Qualitative picture of I-V showing the effect of φ Bn
21
MS Contact on N-type SC when φm < φs
φ Bn
is small
∴ Ohmic Contact
22
MS Contact on P-type SC φm < φs
23
Valence Band picture of MS contact on P-SC in
TE ,FB and RB conditions
24
MS contact with
p-type S.C (ϕm < ϕs )
φBp = Eg − φBn
• Current flow in MS contacts with p-type
S.C. is due to hole transport across φBp .
• Rectifying contact requires Low I which
0
φ
needs high Bp .
• MS contacts with p-type S.C are rectifying
when φBp is high (I.e; φBn is low)
25
Summary
φBn = (φm − χ )
φBp = Eg − (φm − χ )
Schottky Limit
High (φm − χ ) :
Rectifying contact with n-type
Ohmic contact with p-type.
Low (φm − χ ) :
Ohmic contact with n-type
Rectifying contacts with p-type.
26
Experimental Results
On φBn for metals
with different φm
Measurement of φBn showed
that the first order theory
φBn= (φm - χ)
is not satisfactory.
27
Experimental results of φBn on Si
Reference : Turner and Rhoderick , Solid State
Electronics, Vol.11, pp291-300, 1968
28
Results on cleaved
(110) GaAs
Reference : Smith and Rhoderick , J. Phys.D. :
Appl.Phys. Vol.2, pp.465-467,1969.
29
Results on Chemically
Prepared GaAs
30
Experimental Results of φ Bn on Ge
Bardeen
Strong
pinning Limit
Ideal
Scottky limit
Schottky limit
φ Bn = (φm − χ )
Bardeen limit
φ Bn = ( E g − φ0 )
Reference: A. Dimoulas,et.al. “Fermi level pinning and
31
charge neutrality level in Ge” Appl. Phys.Lett. Vol.89, 2006
Summary of the Experimental Results
φ Bn can be expressed by the relation
(
φBn = γ (φm − χ ) + (1 − γ ) Eg − φ0
Where φ 0 ≈
Eg
3
)
for GaAs and Si ; and it is
γ
equal to 0.09eV for Ge.
Is the Pinning
Factor and it varies between 0 and 1 , the
value depends upon the Surface condition.
(i) γ<1 with chemically prepared S.C surface.
(ii) γ =0 with freshly cleaved S.C surface.
(iii) γ =1 expected from the first order theory.32
Effect of Interface state density on φBn
•Surface is never ideal and has density
2 / eV
D
/
cm
of states it
due to the
dangling bonds on the surface.
•A thin layer δ of material (mostly
native oxide) exists between metal and
the S.C surface
•
and Dit values determine γ
δ
33
Surface States or
Interface states
Acceptor states
φ0
E0
Donor states
Bulk region of SC
Surface
E0 is the neutral level.( E0 − Ev ) = φ0
If EF = E0 , net charge at the surface
Is zero. (surface is neutral)
34
Effect of Surface States on
surface potential
Ec
φ0
E0
EF
Ev
In this case the acceptor levels between EF and Eo are
occupied and are negatively charged by accepting
electrons from the adjacent semiconductor layer which
gets depleted (see the next slide) causing band
bending till the charge in the interface traps Qit is
35
equal to the depletion layer charge QD
Band bending due to charge trapping in he
acceptor type surface states
Qit
Ec
EF
E0
Qit = − qDit ( EF − E0 )
Qit
(Negative)
Ev
(Positive )
Depleted
region Q D
Bulk neutral
region (Ntype)
The Fermi level moves closer to the neutral level Eo.
When Dit → ∞ the Fermi level almost coincides with
Eo at the surface causing the Fermi level to pin at Eo
36
Effect of
δ
and Dit on φBn
χ
φm
Vi
MS Contact
φBn
φ0
E0
Eg
Qit
φ Bn = φ m − χ − V i
Ec
EF
EV
− − − ( 1)
QD + Qit = voltage across “δ”
Vi =
Ci
37
Expression for φBn
φ Bn = φ m − χ − V i
Vi
− − − ( 1)
= voltage across “δ”
QD + Qit
=
− − − (2)
Ci
(
)
−Qit = qDit ( EF − E0 ) = qDit Eg − φBn − φ0 − ( 3 )
QD=charge /cm2 in the depleted region of S.C
(positive in n-type s.c)
ε
ε
2
r
0
Ci =capacitance of interface layer/cm =
δ
38
From equations
(1),(2) and (3)
(
)
qDit
QD
φBn = φm − χ +
Eg − φBn − φ0 −
Ci
Ci
Rearranging,
φ m = γ (φ m − χ ) + ( 1 − γ
γ
) (E g − φ0 ) −
γ QD
Ci
1
1
=
=
qD it
qD it δ
1+
1+
Ci
εr ε0
39
Particular cases
(i) γ =0 when D it → ∞
φBn = E −φ
( g 0 ) Bardeen’s limit of φBn
This is independent of φ m
(ii) γ=1, when D it → 0 or / and δ → 0
φBn = (φm − χ )
This is the Schottky limit of φBn
40
Experimental Results of φ Bn on Ge
Bardeen
Strong
pinning Limit
Ideal
Scottky limit
Schottky limit
φ Bn = (φm − χ )
Bardeen limit
φ Bn = ( E g − φ0 )
Reference: A. Dimoulas,et.al. “Fermi level pinning and
41
charge neutrality level in Ge” Appl. Phys.Lett. Vol.89, 2006
Fermi level Pinning
φ Bn
φ Bp
E0
Ec
EF
φ0
Ev
Fermi level almost coincide with the neutral level Eo.
For SB on Si
and GaAs
For SB on Ge
2
φ Bn = E g − φo ≈ E g
3
φo ≈ 0.09eV
φ Bn = E g − 0.06 = 0.66 − 0.06 = 0.6eV
42
Effect of Fermi level pinning
Almost all metals form rectifying contact on N-type Si and
GaAs: They form lower barrier height contacts (Ohmic
Contacts) on P- type Si and p-type GaAs.
It is easier to realize P-Channel SB S/D MOSFETs than the
N-channel SB S/D MOSFETs on Si , GaAs and Ge
• Almost
all metals tried so far have formed ohmic
contacts on P-type Ge ; they form high barrier
contacts on N-type Ge.
•It is easy to realize P-channel SB S/D MOSFETs on
Ge ; but it is difficult to realize N-Channel SB S/D
MOSFTS on Ge
43
P-Channel SB S/D MOSFET
Gate oxide thickness =25nm.
Phosphorus doped Polysilicon gate.
Aluminum
S
(100) N-Silicon
N D = 2 × 1015 / cm 3
G
PtSi
D
SiO2
Ref: C.J.Koeneke, S. M.
Sze , R.M.Levi &
E.Kinsbron, “Schottky
MOSFET for VLSI” ,
IEDM 1981,pp.367-370
Transistors fabricated
with fixed W=100µm
and different L in the
range 1µm to10µm.
Long channel behavior
was seen for L=1µm
•Gate poly was etched and its sides were protected by deposited SiO2 .
• SiO2 was removed from source ,drain and gate areas.
• Approximately 15 nm of Pt was sputtered and then sintered at 625°C
for 30 minutes in Argon to form 30nm of PtSi over all previously
exposed silicon region. PtSi forms φ Bp = 0.24eV with holes in Si
•The un-reacted Pt was then removed with aqua regia
44
Energy band diagrams of SB S/D MoSFET
N-layer below gate
(a) VGS = 0 , VDS = 0
N-Si
Depleted n-layer
Inverted p-channel, VDS=0
(b) VGS = Vth , VDS = 0
N-Si
Depleted n-layer
P-Channel , VDS < 0
(c) VGS = Vth , VDS < 0
N-Si
45
-VDS
The Output currents in SB S/D MOSFETs were
found to be smaller than those for the
conventional MOSFETs. This was explained by
the potential barrier arising in the gap
δ
between the SB source and the inversion
channel.
46
Gap
δ
δ ≈ 10 nm
47
N-Channel MOSFET with S.B.S/D
Al
TaSi
Ta
Poly Si
δ
(100) P − Si ρ = 2Ω cm
Ref: Mochizuki and Wise, IEEE
EDL ,Vol-5,p.108 April 1984
TaSi
δ
δ ≈ 200nm
Schematic
Diagram
Band
Diagram of
n-Channel
SBMOSFET
N-Channel
S.B.MOSFET
Structure t0x=90nm
W = 100µ m, L = 10µ m
100nm thick Ta ion
beam deposited and
sintered at 450°C for
30 min. in forming
gas. Source drain
defined and Ta
patterned by etching
in CF4 plasma.
Between Ta and p-Si
φ Bp = 0.7eV
48
Ref: EDL-5, April 1984
ID
Xj =1.5µm
(×10 −4 A)
ID-VD Characteristics of
Conventional (dashed
lines) and S.B.MOSFET
(solid line)
VDsat = VD − VS
S
Vs
VD
D
Between Ta and pSi, φBp = 07eV
VD
Current reduction
in SB MOSFET is
due to the barrier
between source
and channel
49
•The diode is formed at the source – channel edge
and the Schottky barrier. VS is the bias required to
accommodate the current ID
•Once the lateral voltage drop VS is established at this
diode, current will flow as for a reverse biased metal
n-Silicon Schottky diode.
• Barrier
ID
height can be calculated independent of ID
− qVS / kT
* 2 −φ Bn / kT
= [A A T e
](1 − e
)
2
(
V
−
V
)
W
S ]
I D = µ cox [(VG − Vt )(VD − VS ) − D
L area and A* is richrdsons constant
2
A is the effective
50
Silicides of other Materials for N-channel
Schottky Source Drain Transistors (SSDT)
• P-Channel SSDT (P-SSDT) with PtSi as S/D (hole barrier
φ Bp = 0.24 − 0.28 eV has been reported with quite
8
I
/
I
≈
10
acceptable ON OFF
• N- channel SSDT performance has been rather poor
due to the high barrier height for electrons
• Materials with low
φm
are required for achieving lowφ Bn
Ytterbium
Material Erbium Dy
(silicide) (ErSi2-x) (DySi2-x) (YbSi2-x)
φm (eV) 3.12
3.09
2.59
ION/IOFF
105
105
107
51
Reference: Shiyang Zhu, etal “ N-type Schottky
Barrier Source /Drain MOSFET using Ytterbium
Silicide” IEEE Electron Device Letters, vol.25, pp51565-567, August 2004
• ErSi2-x SSDT resulted in poor film morphology
formed by solid –state reaction of deposited Er and
substrate Si and has shown poor On/Off ratio . It also
showed two slopes in sub-threshold region and high
electron barrier height φ Bn = 0.37 eV
•YbSi2-x resulted in better surface morphology , with
on/off ratio of about 107 and φ Bn = 0.27eV
52
EEE Electron Device
Letters, vol.25, pp51-565567, August 2004
High-k gate dielectric
and metal gate, YbSi
SB S/D MOSFET
W = 400 µ m
HfO2 EOT = 2.5nm
Vth = 0.4V
53
EEE Electron Device Letters, vol.25, pp51-565-567, August 2004
W = 400 µ m
•YbSi2-x/p-Si contact has the highest hole barrier
height of 0.85eV (determined from C-V), lowest
reverse bias leakage current, and the best
rectifying property with near unity ideality factor.
Other diodes have high I (leakage), ideality factor
>1.0 and higher difference in φ pI −V and φ Cp −V
indicating barrier height in-homogeneity as
confirmed by many square pits
In the YbSi2-x MOSFET
S=75mv/decade with a
single slope and the
Ion/Ioff ratio = 107
54
Refer: EEE Electron Device Letters, vol.25,
pp51-565-567, August 2004
Silicide/p-Si
(100)
ErSi2-x TbSi2-x DySi2-x YbSi2-x PtSi / nSi(100)
I −V
φ Bp
(eV)
0.71
0.60
0.67
0.82
I −V
φ Bn
= 0.86
C −V
φ Bp
(eV)
0.78
0.87
0.87
0.88
C −V
φ Bn
= 0.84
φ Bp (eV)
0.75
0.74
0.75
0.85
φ Bn = 0.85
Average
Average
φ Bn = ( E g − φ Bp ) 0.37
(eV).
E g = 1.12eV
Ideality factor
in I-V
1.57
0.38
0.37
0.27
1.83
1.33
1.04
φ
Bp = 0.27
1.02
55
Summary Of SB S/D MOSFETs on Silicon
•The principle feature of SB-CMOS technology is metal
S/Ds.
•Metal S/Ds are inherently lower resistance and
atomically abrupt, providing a long –term scalability
advantage.
•The metal S/D junction to the channel forms a SB,
which provides improved IOFF leakage control. It further
enables lower doping in the channel region, which
results in higher channel mobility.
•SB junctions eliminate parasitic BJT action and latch
up and are much less sensitive to radiation effects that
induce soft errors.
•Low thermal budget process allows integration of
56
• Low-thermal
budget process enables integration of
performance- enhancing materials such as high-k
gate dielectrics, metal gates, and strained silicon ,
all of which lead to other substantial advantages
such as reduced gate leakage, lower power, and
higher effective carrier mobility.
• Together
, these features and benefits
make SB-CMOS technology an
attractive candidate for scaling to sub25 nm gate lengths- coupled with SOI
approach promises scaling down to
10nm
57
Present Status of SB-MOS Technology
• During
the past decade considerable advancement
has taken place in the SB-MOS technology
•PtSi S/D devices with 25nm, 60nm and 80 nm gate
length have been demonstrated.
•The On current and OFF currents of these devices do
not yet meet the ITRS requirements, even though SBPMOS FETs with fT = 280 GHz with Lg =30nm have
been fabricated and reported in the literature. (highest
for any MOSFET)
(REF:IEEE EDL , Vol 25,pp. 220-222, April 2004).
58
• YbSi2-x
has been identified as an
alternative to ErSi2-x for SB-NMOS
Technology , because it provides
slightly lower barrier height (0.27eV)
for electrons . It also provides better
film quality and improved
manufacturability.
REFER: EEE Electron Device Letters,
vol.25, pp51-565-567, August 2004
59
A very Good overview for SB MOS FET :
John M. Larson and John P. Snyder,
“Overview and Status of Metal S/D
Schottky-Barrier MOSFET Technology”
IEEE TED Vol.53, May 2006, pp.1048-1058
60