OPTIMIZATION AND CHARACTERIZATION OF 130 NM
CMOS TRANSISTOR DESIGN USING TCAD SIMULATION
HANI NOORASHIQIN BINTI ABD. MAJID
FACULTY OF SCIENCE
UNIVERSITY OF MALAYA
KUALA LUMPUR
2007
OPTIMIZATION AND CHARACTERIZATION OF 130 NM
CMOS TRANSISTOR DESIGN USING TCAD
SIMULATION
HANI NOORASHIQIN BINTI ABD. MAJID
DISSERTATION SUBMITTED IN FULFILMENT
OF THE REQUIREMENTS
FOR THE DEGREE OF MASTER OF SCIENCE
FACULTY OF SCIENCE
UNIVERSITY OF MALAYA
KUALA LUMPUR
2007
ABSTRACT
Microelectronic device manufacture encompasses the fabrication, testing and simulation,
of structures utilized in a variety of application specific integrated circuits. The
fabrication of transistors, traditionally from elemental silicon wafer is conducted in a
clean room environment utilizing various types of equipment. Process simulation is a
critical element in facilitating the optimization of fabrication stages, confirming test
results and theoretical models and providing physical insight into structural operation.
TSUPREM-4 and MEDICI are two simulators that had been calibrated and used in this
work. As device sizes are scaled down, novel structures are proposed such as halo
(pocket), lightly doped drain (LDD) and source/drain process. In order to characterize
and optimize Silterra 130 nm CMOS transistor design, TCAD simulation is done in this
work and the results is compared with measured data and was verified to be in the
Silterra specification range. Various doses, implant energies and tilt angle is used to
upgrade the transistor performance, reduce the short channel effect and increase the
transistor lifetime. Halo implant, lightly doped drain (LDD) implant and source/drain
(S/D) implant is the three drain engineering structure to be characterized in this work. It
is found that at certain dose, implant energy and tilt angle, the best saturation drain
current, Idsat and threshold voltage, Vt that can match the specification target for NMOS
and PMOS transistor can be achieved. It is also proved in this work that by using
process and device simulator, the correct process can be predicted and the physical
insight of the structure such as current flow lines and doping concentrations can be
further analyzed.
ABSTRAK
Pengeluaran peranti mikroelektronik merangkumi pembuatan, menguji dan simulasi,
struktur-struktur yang digunakan dalam pelbagai aplikasi khusus litar-litar bersepadu.
Pembuatan transistor, terdiri daripada wafer silikon asas dikendalikan dalam satu
persekitaran tempat bersih dengan menggunakan pelbagai jenis peralatan. Proses
simulasi adalah satu unsur penting yang membantu dalam mengoptimumkan peringkatperingkat pembuatan, mengesahkan hasil percubaan dan model-model teori dan
menyediakan fahaman secara fizikal ke atas operasi struktur. TSUPREM-4 dan
MEDICI adalah dua jenis simulator yang telah ditentukurkan dan digunakan dalam
tugas ini. Setelah saiz-saiz peranti telah diturunkan, struktur-struktur novel telah
dicadangkan seperti proses implant halo ‘halo (pocket)’, ‘lightly doped drain (LDD)’
dan proses ‘source/drain’. Dalam peringkat untuk mencirikan dan mengoptimumkan
rekabentuk transistor CMOS Silterra 130 nm, simulasi TCAD telah dijalankan dalam
projek ini dan hasil-hasilnya telah dibandingkan dengan data yang telah diukur dan
telah disahkan ia berada di dalam julat spesifikasi Silterra. Pelbagai dos, tenaga
mengimplan dan sudut mengimplan digunakan untuk menaiktaraf prestasi transistor,
mengurangkan kesan saluran pendek dan menambah jangka hayat transistor. Implan
halo, ‘lightly doped drain (LDD)’ dan proses ‘source/drain’ adalah tiga jenis struktur
kejuruteraan parit yang akan dikaji dalam kerja ini. Didapati, dengan dos tertentu,
tenaga implan dan sudut condong implan, arus parit tepu, Idsat dan voltan ambang, Vt
yang terbaik dapat menepati sasaran spesifikasi bagi transistor NMOS dan PMOS.
Dalam kerja ini ia dapat dibuktikan bahawa dengan menggunakan proses dan alat
simulator, proses yang menepati spesifikasi dapat diramal dan struktur dalaman seperti
aliran arus dan kepekatan pengedopan seterusnya dapat dianalisa.
ACKNOWLEDGEMENT
First of all, I would like to acknowledge my supervisor, Prof Dr. Muhamad Rasat
Muhamad. He has been a great mentor to me with his management skills and
enthusiasm. He has also been an exceptional role model of life. He has done his utmost
to help relieve concerns that his advisees have.
I also would like to thank my co-supervisor, Mr Albert Victor Kordesch, Senior
Manager of Device Modeling Department, Silterra. Throughout my association with
him, he gave me strong motivation in doing my research. I consider him to be a moving
library that has the answers to all my queries. Besides that, his encouragements also
make me feel more comfortable and confidence while carrying out my research in
Silterra.
I am indebted to my second co-supervisor, Mr Binod Kumar Gopalakrishnan, ex-Senior
Engineer of Process Integration Department, Silterra. With all his advice and support I
am able to finish my thesis with a success results.
My special gratitude to Mr Chew Soon Aik, ex-Engineer, Silterra. Being my mentor is
the best thing that had ever happen to me. I would like to thank him a lot for his
guidance and constructive comments in various step of this project. His enthusiasm and
support have made this project a very rewarding, enriching and interesting one. His
useful ideas, advices are a memorable thing. He is also the one who encourage me and
support me to finish this thesis in only one year.
I wish to thank the Silterra (M) Sdn Bhd, pioneer of Malaysia semiconductor industry
for the support of this work through postgraduate internship program. Silterra provides
every technical support including financial, equipment, research environment and
technical advice for my research work. I would like to acknowledge the Device
Modeling Department team, (Norliza, Izahan Syemylona, Norhafizah, Wan Rosmaria,
Ayu Ismail, Shahrul Amran, Mohd. Fahmi) and Mrs. SL Lee for her advice on process
and procedure. Mrs. Nor Asmah Zainal Abidin and Mr. Abdullah Lin for the nontechnical support in Silterra. Many thanks to Silterra management for their support on
the managing of the postgraduate internship program.
Last but not least, I express my deepest love and appreciation to my parents and Hailmy
Rizuan for providing me their continuous inspiration and love that keep motivating me
to achieve my goal.
TABLE OF CONTENTS
Page
Abstract
i
Abstrak
ii
Acknowledgement
iii
Table of Contents
v
List of Tables
viii
List of Figures
ix
Chapter I
INTRODUCTION
1.1
Background
1
1.2
Deep Sub-micron CMOS Process Technology
3
1.3
Overview of Process and Device Simulation
5
1.4
Motivation of this work
6
1.5
Objectives
8
1.6
Thesis Overview
8
Chapter 2
BACKGROUND AND LITERATURE REVIEW
2.1
Introduction
10
2.2
MOSFET Basic Characteristics
10
2.2.1 CMOS
11
CMOS Electrical Characteristics
13
2.3.1 Threshold Voltage, Vt
13
2.3.2 I-V Characteristics
16
2.4
CMOS Process
18
2.5
MOSFET Ion Implantation
20
2.5.1 Punchthrough Stop (Halo) Implants
21
2.5.2 Source/Drain Extension Implant or Lightly Doped Drain (LDD)
23
2.5.3 Source/Drain Implants
25
MOSFET Scaling Effects
26
2.6.1 Short Channel Effects
27
2.6.2 On-State Saturation Current
30
2.3
2.6
2.6.3 Punchthrough Effect
31
2.6.4 Hot Carrier Effect
32
2.7
Methods Attempted by Other Researchers
34
2.8
Summary
37
Chapter 3
CALIBRATION AND VALIDATION OF TSUPREM-4
AND MEDICI
3.1
Introduction
38
3.2
TSUPREM-4
38
3.3
TAURUS-MEDICI
39
3.4
Calibration of 130 nm MOSFET
40
3.5
Validation of TSUPREM-4 and MEDICI
49
3.6
Summary
51
Chapter 4
4.1
4.2
4.3
RESULTS
Investigation of Halo Implant in PMOS and NMOS Device
53
4.1.1 Introduction
53
4.1.2 Simulation Procedure
53
4.1.3 Simulation Results
54
4.1.3.1 PMOS Halo Analysis
55
4.1.3.2 NMOS Halo Analysis
59
4.1.4 Summary
62
Investigation of Lightly Doped Drain Implant (LDD) in PMOS and
NMOS Device
63
4.2.1 Simulation Procedure
63
4.2.2 PMOS Simulation Results
64
4.2.2.1 Boron Di-Fluoride (BF2) dose splits
64
4.2.2.2 Boron Di-Fluoride (BF2) energy splits
72
4.2.3 NMOS Simulation Results
78
4.2.4 Summary
82
Investigation of Source/Drain Implant (S/D) in PMOS and NMOS
Device
83
4.3.1 Simulation Procedure
83
4.3.2 Simulation Results
84
4.3.2.1 PMOS Source/Drain Analysis
85
4.3.2.2 NMOS Source/Drain Analysis
88
4.3.3 Summary
Chapter 5
5.1
ANALYSIS AND DISCUSSION
Introduction
93
5.1.1 Analysis and Discussion of Halo Implant in PMOS and NMOS
Transistor
5.1.1.1 PMOS Device
93
5.1.1.2 NMOS Device
5.1.2 Analysis and Discussion of Lightly Doped Drain (LDD) Implant in
PMOS and NMOS Device
93
105
111
5.1.2.1 PMOS Device
111
5.1.2.2 NMOS Device
115
5.1.3 Analysis and Discussion of Source/Drain (S/D) Implant in PMOS
and NMOS Device
5.2
92
118
5.1.3.1 PMOS Device
118
5.1.3.2 NMOS Device
121
Summary
Chapter 6
124
CONCLUSION
6.1
Conclusion
125
6.2
Limitation and Recommendation
127
6.3
Summary
129
REFERENCES
130
LIST OF PUBLICATIONS
135
APPENDIXES
136
LIST OF TABLES
Page
Table 3.1
SIMS data obtain for this experiment.
Table 3.2
Standard 0.13 µm CMOS process in Silterra.
Table 3.3
Saturation current, Idsat data between simulation using MEDICI
and real wafer measurement.
Process split for PMOS and NMOS halo implant with various
dose.
Dose and energy process split for PMOS LDD implant using
Boron Di-fluoride species.
Table 4.1
Table 4.2
41
49
51
55
65
Table 4.3
Dose process split for NMOS LDD implant using arsenic species.
Table 4.4
Process split for PMOS and NMOS source/drain implant with
various implant parameters.
85
Table 5.1
Threshold voltage simulated using MEDICI and measured value
for different PMOS halo implant dosage at L=0.13 µm.
97
Table 5.2
Measured and simulation data for Vt with different PMOS halo
implant energy at L=0.13 µm.
99
Table 5.3
Measured and simulation data for Vt with different halo implant
tilt angle at L=0.13 µm.
100
Table 5.4
Effects of halo implant parameters on threshold voltage, Vt and
saturated drain current, Id for PMOS.
105
Table 5.5
Measured and simulation data for Vt with different NMOS halo
implant dosage at L=0.13 µm.
107
Table 5.6
Measured and simulation data for Vt with different NMOS halo
implant energy at L=0.13 µm.
108
Table 5.7
Measured and simulation data for Vt with different NMOS halo
implant tilt angle at L=0.13 µm.
110
Table 5.8
Advantages and disadvantages of BF2 implant in CMOS
transistor.
Tilt angle and energy splits for NMOS transistor simulation using
TCAD. Fixed parameters: dose at 1.5E+15 atom/cm2, rotation=0.
Table 5.9
78
113
116
LIST OF FIGURES
Page
Figure 1.1
Kilby's Integrated Circuit (flip-flop using two transistors).
Figure 1.2
Simple CMOS transistor cross-sectional view.
Figure 2.1
(a) Current-controlled and, (b) voltage-controlled amplifiers.
Figure 2.2
a) Circuit of CMOS inverter and b) its logic symbol.
Figure 2.3
Drain Current (Id) versus gate voltage (Vg) graph.
Figure 2.4
Terminology for charges associated with thermally grown SiO2.
Figure 2.5
Drain current (Id) versus drain voltage (Vg).
Figure 2.6
Figure 2.7
Transistor in saturation mode (current remains constant or
saturates).
NMOS and PMOS process flow
Figure 2.8
Comparisons of ion implantation and diffusion doping profiles
Figure 2.9
Halo structure in transistor.
Figure 2.10
Source/Drain Extension implants diagram.
Figure 2.11
Charge sharing phenomenon.
Figure 2.12
Threshold voltage variation with channel length.
Figure 2.13
Drift velocity becomes a constant above the critical field.
Figure 2.14
Punch-through effect in a short channel transistor.
Figure 2.15
Id vs Vd curve due to punch-through effect.
Figure 2.16
Impact ionization effect in transistor.
Figure 2.17
Hot carrier effect.
Figure 3.1
Initial discrepancies between SIMS measurement and profile
simulated by TSUPREM4 using default moment parameters.
43
Figure 3.2
Cut line done on PMOS and NMOS device simulated by
TSUPREM-4 to obtain doping profile.
45
Figure 3.3
Comparison of Phosphorus Nwell doping concentration profile,
simulated and measured by SIMS.
46
3
3
11
12
14
15
16
18
19
20
22
24
29
30
31
32
32
33
33
Figure 3.4
Comparison of PMOS Lightly Doped Drain (PLDD) Boron
doping concentration profile, simulated and measured by SIMS.
46
Figure 3.5
Comparison of Boron doping concentration profile by simulated
and measured by SIMS for Pwell.
47
Figure 3.6
Comparison of NMOS Source/Drain (NSD) Phosphorus doping
concentration profile, simulated and measured by SIMS.
48
Figure 3.7
Comparison of Arsenic doping concentration profile by simulated
and measured by SIMS for NMOS Source/Drain (NSD).
48
Figure 3.8
Simulated drain current (Id) versus drain voltage (Vd) using
MEDICI for 0.13 µm PMOS device
50
Figure 3.9
Simulated drain current (Id) versus drain voltage (Vd) using
MEDICI for 0.13 µm NMOS device.
50
Figure 4.1
Workflow for experimental procedure.
Figure 4.2
Arsenic doping profile for three different arsenic doses to
optimize the Halo implant step, (a) HaloPD1 (3.3E+13
atom/cm2), (b) HaloPD2 (3.1E+13 atom/cm2) and (c) HaloPD3
(3.5E+13 atom/cm2).
56
Figure 4.3
PMOS Halo dose for 10/0.13 device accuracy plot between
measured and simulated.
58
Figure 4.4
Simulated Id versus Vd curve for different PMOS halo dose, (a)
HaloPD1 (3.3E+13 atom/cm2), (b) HaloPD2 (3.1E+13 atom/cm2)
and (c) HaloPD3 (3.5E+13 atom/cm2).
Figure 4.5
Figure 4.6
Figure 4.7
Figure 4.8
54
58
Boron concentration for NMOS Halo implants with various
doses, (a) HaloND1 (1.0E+13 atom/cm2), (b) HaloND2 (1.3E+13
atom/cm2) and (c) HaloND3 (1.6E+13 atom/cm2).
60
Current flow line (grey lines) in conjunction with electric
potential concentration for different boron doses, (a) HaloND1
(1.0E+13 atom/cm2), (b) HaloND2 (1.3E+13 atom/cm2) and (c)
HaloND3 (1.6E+13 atom/cm2).
61
Current flow vertical cutline align along the poly gate profile for
various halo dose, 1.0E+13, 1.3E+13 atom/cm2 and 1.6E+13
atom/cm2.
61
NMOS Halo dose for 10/0.13 µm device accuracy plot between
measured and simulated for 3 different boron doses, (a) HaloND1
(1.0E+13 atom/cm2), (b) HaloND2 (1.3E+13 atom/cm2) and (c)
HaloND3 (1.6E+13 atom/cm2).
62
Figure 4.9
Workflow for experimental procedure.
Figure 4.10
Doping profile for three different BF2 doses, BF2-PD1 (2.2E+14
atom/cm2), BF2-PD2 (2.5E+14 atom/cm2) and BF2-PD3 (2.8E+14
atom/cm2) compared to boron (2.5E+14 atom/cm2).
63
66
Figure 4.11
Device vertical cut line example; all through the silicon substrate.
Figure 4.12
Boron vertical cut line doping profile comparing three different
BF2 doses, (a) BF2-PD1 (2.2E+14 atom/cm2), (b) BF2-PD2
(2.5E+14 atom/cm2) and (c) BF2-PD3 (2.8E+14 atom/cm2)
compared to boron (2.5E+14 atom/cm2).
Figure 4.13
Figure 4.14
Figure 4.15
Current flow profile (grey lines) for PMOS device with different
LDD dose, (a) BF2-PD1 (2.2E+14 atom/cm2), (b) BF2-PD2
(2.5E+14 atom/cm2) and (c) BF2-PD3 (2.8E+14 atom/cm2)
compared to compared with without fluorine implant.
Current flow vertical cutline example done at the drain of the
PMOS device.
67
68
69
70
Current flow vertical cutline profile comparing various BF2 dose,
(a) BF2-PD1 (2.2E+14 atom/cm2), (b) BF2-PD2 (2.5E+14
atom/cm2) and (c) BF2-PD3 (2.8E+14 atom/cm2) with nonfluorine species dose (boron species).
70
Current density vertical cutline profile comparing various BF2
dose, (a) BF2-PD1 (2.2E+14 atom/cm2), (b) BF2-PD2 (2.5E+14
atom/cm2) and (c) BF2-PD3 (2.8E+14 atom/cm2) with nonfluorine species dose (boron species).
71
Figure 4.17
PMOS LDD dose for 10/0.13 device accuracy plot between
measured and simulated.
72
Figure 4.18
Doping profile for three different BF2 energy, (a) BF2-PE1 (3.0
KeV), (b) BF2-PE2 (3.5 KeV) and (c) BF2-PE3 (4.0 KeV)
compared to boron (0.7 KeV).
Figure 4.16
Figure 4.19
Figure 4.20
Figure 4.21
Figure 4.22
Figure 4.23
Vertical cutline on boron concentration profile for 3 different BF2
energy, (a) BF2-PE1 (3.0 KeV), (b) BF2-PE2 (3.5 KeV) and (c)
BF2-PE3 (4.0 KeV) compared with non-fluorine corporation
doping, boron (0.7 KeV).
Current flow cutline profile and electric potential for three
different BF2 energy, (a) BF2-PE1 (3.0 KeV), (b) BF2-PE2 (3.5
KeV) and (c) BF2-PE3 (4.0 KeV) compared with boron (0.7
KeV).
Total current profile with the vertical cutline under the gate edge
for three different BF2 energy, (a) BF2-PE1 (3.0 KeV), (b) BF2PE2 (3.5 KeV) and (c) BF2-PE3 (4.0 KeV) compared with nonfluorine corporation doping, boron (0.7 KeV).
PMOS total current cutline profile with different LDD energy, (a)
BF2-PE1 (3.0 KeV), (b) BF2-PE2 (3.5 KeV) and (c) BF2-PE3 (4.0
KeV) compare with boron (0.7 KeV).
PMOS LDD energy for 10/0.13 µm device accuracy plot between
measured and simulated data.
73
74
75
76
77
77
Figure 4.24
Figure 4.25
Figure 4.26
Figure 4.27
Doping profile for two different arsenic doses, (a) As-NLDD1
(1.5E+15 atom/cm2) and (b) As-NLDD2 (1.3E+15 atom/cm2).
Vertical cutline under gate for two arsenic concentrations, (a) AsNLDD1 (1.5E+15 atom/cm2) and (b) As-NLDD2 (1.3E+15
atom/cm2).
Current flow line profile for different arsenic dose used, (a) AsNLDD1 (1.5E+15 atom/cm2) and (b) As-NLDD2 (1.3E+15
atom/cm2).
Current flow lateral cutline profile for different NMOS LDD
dose, (a) As-NLDD1 (1.5E+15 atom/cm2) and (b) As-NLDD2
(1.3E+15 atom/cm2).
79
80
81
81
Figure 4.28
NMOS LDD dose for 10/0.13 µm device accuracy plot between
measured and simulated data.
82
Figure 4.29
Workflow of experimental procedure for source/drain process
simulation.
84
Figure 4.30
Net doping and depletion region line for three different boron
doses for PMOS source/drain process, (a) S/D1 (2.6E+15
atom/cm2), (b) S/D2 (2.7E+15 atom/cm2) and S/D3 (2.8E+15
atom/cm2).
86
Figure 4.31
Figure 4.32
Figure 4.33
Figure 4.34
Figure 4.35
Id-Vd curve for PMOS source/drain implant process with different
dosage used for this process, (a) S/D1 (2.6E+15 atom/cm2), (b)
S/D 2 (2.7E+15 atom/cm2) and S/D 3 (2.8E+15 atom/cm2).
PMOS S/D dose for 10/0.13 µm device accuracy plot between
measured and simulated data.
Current flow profiles for 0.13 µm NMOS device with 3 different
source/drain implant energy, (a) S/D_energy1 (45 KeV), (b)
S/D_energy2 (50 KeV) and S/D_energy3 (40 KeV
Current density cutline profiles for 0.13 µm NMOS device with 3
different source/drain implant energy, (a) S/D_energy1 (45 KeV),
(b) S/D_energy2 (50 KeV) and S/D_energy3 (40 KeV).
Drain current, Id versus drain voltage, Vd for NMOS device
simulated using MEDICI for 3 different implant energy, (a)
S/D_energy1 (45 KeV), (b) S/D_energy2 (50 KeV) and
S/D_energy3 (40 KeV).
Figure 4.36
PMOS S/D energy for 10/0.13 µm device accuracy plot between
measured and simulated data.
Figure 5.1
Two different transistors size with halo implant. It is shown here
that too small gate length will result in halo overlapping each
other and leads to Vt roll-off.
87
88
89
90
90
92
94
Figure 5.2
Threshold voltage, Vt versus gate length. This shows the effect of
halo to Vt with a different gate length.
Figure 5.3
Transistor with different halo depth. Note that for a shallower
halo, junction capacitance, Cj will not be affected. For halo
deeper than source/drain implant, Cj will increase.
PMOS halo Vt roll-off curve for different arsenic dose, (a)
HaloPD1 (3.3E+13 atom/cm2), (b) HaloPD2 (3.1E+13 atom/cm2)
and (c) HaloPD3 (3.5E+13 atom/cm2).
Figure 5.4
Figure 5.5
Measured PMOS threshold voltage (Vt) curve for 10/0.13 µm
transistor.
Figure 5.6
Measured and simulated PMOS threshold voltage, Vt for different
halo dose. The smallest difference is seen at halo dose 3.3E+13
atom/cm2.
95
95
96
97
98
Figure 5.7
PMOS Vt roll-off for different halo implants energy, 70, 90 and
110 KeV.
Figure 5.8
Measured and simulated PMOS threshold voltage, Vt for different
halo implants energy, 70, 90 and 110 KeV.
100
Figure 5.9
Measured and simulated PMOS threshold voltage, Vt with
different halo implants tilt angle 200, 250 and 300 with rotation=0.
101
Figure 5.10
Transistor with different halo implant tilt angle and rotation=0.
Normal tilt is at 300.
102
Figure 5.11
PMOS net doping profile for different implant tilt angle (200, 250
and 300).
103
Figure 5.12
PMOS total doping profile for different implant tilt angle, (200,
250 and 300).
103
Figure 5.13
Transistor showing resists shadowing problem.
Figure 5.14
NMOS Vt roll-off for three different halo implant doses, (a)
HaloND1 (1.0E+13 atom/cm2), (b) HaloND2 (1.3E+13
atom/cm2) and (c) HaloND3 (1.6E+13 atom/cm2).
Figure 5.15
Figure 5.16
Figure 5.17
Figure 5.18
High dose halo doping on a PMOS transistor, (a) breakdown
voltage versus doping concentration and (b) band-to-band
tunneling or Zener effect leakage.
Measured NMOS Vt roll-off for different halo implants doses, (a)
HaloND1 (1.0E+13 atom/cm2), (b) HaloND2 (1.3E+13
atom/cm2) and (c) HaloND3 (1.6E+13 atom/cm2).
Measured and simulated NMOS threshold voltage, Vt with
different halo implants dose, HaloND1 (1.0E+13 atom/cm2),
HaloND2 (1.3E+13 atom/cm2) and HaloND3 (1.6E+13
atom/cm2).
Measured and simulated NMOS threshold voltage, Vt with
different halo implant energy, 10, 12 and 15 KeV.
99
104
105
106
107
108
109
Figure 5.19
Simulated NMOS Vt roll-off for different halo implants energy,
10, 12 and 15 KeV.
Figure 5.20
Measured and simulated NMOS threshold voltage, Vt with
110
different halo implant tilt angle, 150, 250 and 350.
Figure 5.21
Threshold voltage, Vt for 1.2 V 10/0.13 µm PMOS LDD for BF2
and boron.
112
Figure 5.22
Threshold voltage, Vt difference for 1.2 V 10/0.13 PMOS for
both BF2 and boron.
113
Figure 5.23
Saturation drain current, Idsat for 1.2 V 10/0.13 PMOS for both
BF2 and boron.
114
Figure 5.24
Idsat comparison for 1.2 V 10/0.13 PMOS for both BF2 and boron.
It can be noted Idsat degrades (~ 4 µA/µm) after changing to BF2
species.
109
115
Figure 5.25
Simulated NMOS Vt roll-off for different LDD implants tilt
angle, 00, 30 and 70.
Figure 5.26
Simulated Vt roll-off curves comparing 3 different implant energy
117
used for NMOS LDD process, 2, 3 and 5 KeV.
Figure 5.27
Simulated Vt roll-off curve comparing 3 different implant doses
used for NMOS S/D process, 2.6E+15 atom/cm2, 2.7E+15
atom/cm2 and 2.8E+15 atom/cm2.
116
119
Figure 5.28
Simulated PMOS structure showing (a) net doping profile and
depletion region and (b) electric potential and current flow lines.
120
Figure 5.29
Simulated Vt roll-off curve comparing 3 different implant energy
used for NMOS S/D process, 45, 40 KeV and 50 KeV.
122
Figure 5.30
Simulated NMOS structure showing depletion region for different
122
implant tilt angle.
Figure 5.31
Net doping vertical cutline profile for NMOS source/drain
implant with different implant energy.
Figure 6.1
(a) Denser grid factor, (b) less dense grid factor.
123
129
CHAPTER 1
INTRODUCTION
1.1
Background
Complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) have
played a dominant role in the semiconductor world and are likely to retain this position
for the foreseeable future. Nowadays, leading microprocessors, application specific ICs
(ASICs) and dynamic random access memory (DRAMs) larger than 1Mb are most
entirely fabricated using CMOS technology. The key factors contributing to the
popularity of CMOS technology are its low power consumption and ability to
miniaturize.
Sah and Wanlass originally proposed the pairing of complementary n- and p-channel
transistors to form low power ICs in 1963 [1]. The first CMOS IC was fabricated in
1966 and lay dormant for nearly a decade because of several drawbacks that were
difficult to overcome at that time. For many years, CMOS lagged behind the advanced
silicon gate n-channel MOS (NMOS) and bipolar technologies. After the process of
local oxidation of silicon (LOCOS) isolation and ion implantation became available, the
performance and density of CMOS ICs improved dramatically.
From late 1970s, with the dawning of the VLSI era, the power consumption in NMOS
circuits began to exceed tolerable limits. It was apparently impractical to design future
generations of MOS circuits with NMOS technology. Subsequently, CMOS process
technology began to undergo rapid development. IC density and speed increased at a
rapid pace. The electronic industry is now able to fabricate more than 64 billion
transistors on a single chip with the minimum feature size of 90 nm. In the next
generations it will be necessary to reduce minimum feature size to 45 nm. Gigabyte
DRAMs and sophisticated ultra large-scale integrated circuit (ULSI) processing using
20nm technology are likely to appear in the near future. Even at the present time,
CMOS transistor designers working in advanced process laboratories are able to
fabricate transistors with channel length smaller than 20nm.
Since the semiconductor devices have evolved tremendously, today transistors are
extremely small and come packed in millions onto tiny silicon chips called IC. In 1958,
Jack Kilby (Nobel Laureate at Texas Instruments) [2] and Robert Noyce (Fairchild)
invented the IC as shown in Figure 1.1. This invention is essential for digital
technologies like computers, mobile phones, CDs, mp3s, DVDs; the list could be made
almost infinite.
“What we didn’t realize then was that the integrated circuit would reduce the cost of
electronic function by a factor of a million to one, nothing had ever done that for
anything before” (Jack Kilby, 1958)
The dramatic advances in integrated circuit IC’s over the past 20 years has propelled the
integrated circuit industry from small-scale integration (SSI) of less than 30 devices per
chip in 1970s, to medium-scale integration (MSI) of 30 to 103 devices per chip, to largescale integration (LSI) of 103 to 105 device per chip, to very-large scale (VLSI) of 105 to
107 devices per chip, and now to ultra-large scale (ULSI) of 107 to 109 devices per chip.
The increase in packing density is made possible by reduction in the transistor
dimension. As transistors are being scaled down to the sub micrometer regime, the
fabrication parameters, circuit design constraints and process information become
critical to the transistor performance. Therefore, there is a need to consider these factors
before the transistor is fabricated.
Figure 1.1:
1.2
Kilby's Integrated Circuit (flip-flop using two transistors) [2].
Deep Sub-micron CMOS Process Technology
A new technology can be considered from three perspectives: performance, reliability
and manufacturability. The continued ability of CMOS to be scaled to 20 nm and below
will require many new innovations in the design of CMOS structures. The crosssectional view of the simple CMOS transistor is shown in Figure 1.2.
Figure 1.2:
Simple CMOS transistor cross-sectional view.
It is likely that many of the innovations will rely heavily on the abilities of high-energy
ion implanters to precisely place dopants just where they are needed. Also, rapid
thermal processing is likely to play a key role in reducing overall thermal budgets. At
the same time, it is probable that the differences between n- and p- channel MOSFETs
will have to be addressed more openly, perhaps leading to different gate material and
drawing schemes for each type. But whichever transistor structure and process
technology is ultimately deemed the best, the choice of production will hinge as much
on manufacturability concerns as it does on reliability and performance.
While the dimension of MOSFET is scaling down steadily, there are two goals for
MOSFET scaling. The first goal is increased transistor saturation drain current per unit
width, Idsat, needed to increase the speed in charging and discharging parasitic
capacitance. This strengthens the major use of short channels and thin gate oxide.
The second goal of scaling is reduced size, needed to increase density. This requires
short channel lengths, and increased current per unit channel width so that less width is
needed to provide the necessary drive current. Reduced size also leads to reduced
transistor and interconnect capacitance for speed and power consumption improvement.
In the case of deep sub-micron transistors, some secondary effects, neglected for long
channel transistor become critical issues. They impose some constraints on the
performance and reliability of scaled transistors. Several new processes and transistor
structures were developed to overcome them. Thus, as the process becomes increasingly
complex for continuously scaled transistors, manufacturability must be taken into
consideration in volume production to guarantee high yield.
Two important effects must be avoided for scaled transistors. The first is the shortchannel effect. It causes threshold voltage (Vt) lowering, also known as drain induced
barrier lowering (DIBL), which leads to leakage while transistor is turned off. A thin
gate is required so that the gate control is strong and the leakage is suppressed. Bulk
punch-through, which causes sub-surface drain leakage current is another phenomenon
of the short-channel effect. Shallow source/drain junction depth and high bulk (well)
concentration are required to avoid punch-through. Additional punch-through implant
steps can be introduced to improved punch-through susceptibility independently.
The hot-carrier effect is the other undesired effect for scaled transistors. When the
physical dimensions of the MOS transistor are scaled down and the operation voltage
does not scale proportionally, high electric fields occur in the channel. Hot carriers
created in the high field region result in increased substrate current (Isub) and transistor
degradation, which includes threshold voltage shift, transconductance degradation and
capacitance degradation. The principal mechanism for NMOS field effect transistor
(NMOSFET) degradation appears to be interface state generation in the gate oxide.
1.3
Overview of Process and Device Simulation.
Simulation is the activity of carrying out experiments with the aid of a computer, using
mathematical models formulated to describe the phenomenon being studied. Process
and device simulators can be used to predict the effect of a process change on the circuit
or a process step or device electrical characteristics. Visualizing the details of a process
step and the physical phenomena involved in the transistor operation gives immediate
insight into a miniaturized transistor that is not always accessible by experimental
diagnostics.
Process simulations with calibrated models have proven to be valuable tools for new
process development. Process simulation can significantly reduce the cost and cycle
time of developing a new technology. It also allows the analysis of physical effects that
are difficult to be measured, such as lateral impurity profiles, electrical field
distribution, the location of depletion regions and the locations of impact ionization.
Process simulators are capable of simulating many of the individual process steps with a
high degree of accuracy.
On the other hand, many of the physical processes involved in IC fabrication are still
not completely understood. As a result, computer simulations must still be regarded as
useful guides, but not yet perfect representatives of actual process sequences. The
outputs from process simulators are subsequently used as the inputs to device simulators.
These outputs of device simulators can be internal device phenomena such as potential,
charge, and current distributions, as well as device thermal behavior (i.e., threshold
voltage and current-voltage characteristics, etc.).
1.4
Motivation of this work
Basic CMOS processes usually use seven to nine ion implants per wafer, current
leading edge CMOS processes used thirteen to fifteen implants, and some specialized
CMOS circuits use up to twenty implantation steps. The scaling of CMOS required to
move silicon transistors to deep submicron dimensions faces several major problems.
The anticipated performance improvements (e.g., higher speed, lower power usage, etc.)
of scaled transistors are often partially offset by transistor performance degradations
resulting from the scaling. These problems include:
•
Ultra-shallow junction formation in PMOS transistors.
•
Sub-threshold leakage and punch through in transistors.
•
Reliability problems caused by “hot electron” effects resulting from higher
peak electric fields in the transistor channel near the drain.
•
Performance degradation from the increasingly large contribution of parasitic
resistances and capacitances in the scaled transistor structure.
•
Packing density limitations (“layout” constraints) in scaled CMOS circuits
required for avoiding latch-up, leakage between circuit elements, and other
undesirable interactions between different parts of the circuit structure [3].
Ion implantation plays an important role in solving all of these problems. Hence in this
project, particular attention has been given into the investigation of the ion implantation
process as many challenges in submicron CMOS are due to this process.
This work investigates the effect of different dose, energy and tilt angle in Halo, Lightly
Doped Drain (LDD) and Source/Drain (S/D) implant step for PMOS and NMOS
transistors in order to characterize the 0.13 µm CMOS process at Silterra (M) Sdn. Bhd.
The process parameters for these implantation steps will be characterized. This work is
done using a calibrated TCAD simulator, consisting of a process simulator, TSUPREM4 and a device simulator, MEDICI. The electrical result (saturation drain current, Idsat
and threshold voltage, Vt) from the simulation will be analyzed and compared with the
measured data obtained from real wafer fabricated at Silterra. From here, optimized
implant parameters for Halo, LDD and S/D in 0.13 µm CMOS process will be
suggested for further use at Silterra.
1.5
Objectives
The objectives of this work are as follows:
1)
To calibrate and validate the TCAD deck, (TSUPREM-4 and MEDICI) for the
CMOS 0.13 µm Process Technology.
2)
To simulate and characterize 0.13 µm CMOS for Halo, lightly doped drain and
source/drain implant.
3)
To match the simulated parameters with Silterra (M) Sdn Bhd 0.13 µm CMOS
transistors specification by adjusting the dose, energy, tilt and rotation in the implant
steps.
4)
To suggest a practical approach for the design and optimization of sub
micrometer MOSFETs.
1.6
Thesis Overview
This thesis is organized into six chapters.
Chapter 1 provides an introduction to the CMOS transistors, motivation of this work,
and an outline of the thesis.
Chapter 2 focuses on the problems encountered during the process of downscaling
CMOS. A review of other works in process and transistor optimization for CMOS is
also discussed in this chapter.
Chapter 3 describes the calibration and validation of TSUPREM-4 and MEDICI. A
characterization technique called Secondary Ion Mass Spectrometry (SIMS) is used for
calibration in this chapter.
In chapter 4, the experimental procedure and results is presented. All halo, LDD and
S/D structure results for NMOS and PMOS is discussed here. In this chapter, the
simulation and experimental results are given and compared. Here, interpretation is
made based on the observation of the structural and electrical analysis.
Chapter 5 focuses on the analysis and discussion. Here, thorough and further analysis is
discussed and from this analysis, the suggested process parameter for all halo, LDD and
S/D structure is determined and it is further clarified with the measured silicon data
from Silterra.
Chapter 6 summarizes the work done in this project. Conclusions of this work and
recommendations for future improvement of Silterra’s process parameters are also
described in this chapter.
CHAPTER 2
BACKGROUND AND LITERATURE REVIEW
2.1
Introduction
This chapter covers the literature review of earlier work done on ion implantation with
special focus on drain engineering in submicron CMOS processes. This chapter is split
into four main sections. First section covers the basic MOSFET characteristics. Second
section goes over the 0.13 µm CMOS fabrication process flow. The third reviews the
chronology of ion implantation and the last covers the non-ideal effects due to
MOSFET scaling.
2.2
MOSFET Basic Characteristics
The MOSFET is a four terminal active transistor that is usually used in analog and
digital electronic circuits. It has nearly the same functions as the Bipolar Junction
Transistor (BJT). Kahng and Atalla [4,5] invented the first field effect transistor (FET)
from thermally annealed metal oxide silicon (MOS) in 1960.
There are two types of MOSFET, n-channel and p-channel MOSFET. The n-channel or
NMOS depends on electrons as the majority carrier while p-channel or PMOS depends
on holes for conduction.
The primary conceptual difference between FET and BJT is the fact that the BJT
transistor is a current-controlled transistor as depicted in Figure 2.1(a), while the FET is
a voltage-controlled transistor as shown in Figure 2.1(b). The major advantage of
CMOS is that it uses much less power compared to BJT.
Figure 2.1:
(a) Current-controlled and, (b) voltage-controlled amplifiers
2.2.1 CMOS
Beginning in the 1970’s, electronic watches and hand-held calculators developed very
quickly. Light-emitting diodes (LEDs) were use for the displays. However, LEDs
consume a lot of power and consequently limit the battery lifetime, so the IC industry
was eager to find a replacement for electronic watch and calculator applications.
Liquid-crystal display (LCD), which consumes much less power than LED, quickly
replaced LED for those applications after its introduction in early 1980 [3].
The need to reduce power consumption of the circuits for calculators and electronic
watches was one of the major driving forces for complementary MOS (CMOS)-based
IC chip development. CMOS is used in logic and memory chips, and dominates the IC
market [3]. Figure 2.2 shows a CMOS inverter circuit. We can see that it has two
transistors, one NMOS and one PMOS. When the input is high voltage, or logic 1, the
NMOS is turn on and the PMOS is turn off. Therefore the output voltage is the ground
voltage, VSS’ and Vout is low voltage, or logic 0. Conversely, if the input is low voltage,
or logic 0, the NMOS will be switch off and the PMOS switched on. The output voltage
will be the high voltage, Vdd, and Vout will be high voltage, or logic 1. Because it inverts
the input signal, it is called an inverter. This design is one of the basic logic gates used
in logic circuits.
Figure 2.2:
a) Circuit of CMOS inverter and b) its logic symbol [3]
From Figure 2.2, we can see that when the NMOS is on, the PMOS will be off, and vice
versa. This is why the circuit is call complementary MOS, or CMOS. The circuit is
always open between high-voltage biased Vdd and grounded VSS’. Ideally, there is no
current flow between Vdd and VSS, so CMOS has very low inherent power consumption.
The main power consumption of the CMOS inverter comes from leakage or switching,
which has very high frequency. Other advantages of CMOS over NMOS are that it has
higher noise immunity, lower chip temperature, wider operation temperature range, and
less clocking complexity.
Combining both CMOS and bipolar technology, the BiCMOS IC developed rapidly in
the 1990s. The CMOS circuit is use for the logic part, and the bipolar for input/output to
increase transistor speed.
2.3
CMOS Electrical Characteristics
During the last three decades, transistor lengths have been reduce from 20 µm to much
less than a micron, which has resulted in high fields in the transistor. Here we will
discuss some main electrical characteristics of the PMOS transistor.
2.3.1 Threshold Voltage, Vt
One of the most important physical parameters of a MOSFET is its threshold voltage Vt,
defined as the gate voltage at which the transistor starts to turn on. Present day MOS
process invariability use ion implantation into the channel region; a step often called the
threshold adjusts implant, which alters the doping profile near the surface of silicon
substrate.
Threshold adjust implantation is a low-energy, low dosage implantation process.
Threshold implantation determines at what voltage a transistor can be turned on or off,
which is called threshold voltage, or Vt. For example, some old electronic transistors
require 12 V DC power supply; the majority of electronic circuits need 5 V or 3.3 V,
and the most advanced IC chips operate at 1.8 V or 1.2V. These operating voltages must
be higher than two times the threshold voltage to make sure these transistors can be
turned on or off, however they can’t be so high that it will break down the gate oxide
and destroy the transistors. By changing dose and energy of the threshold implant, a
desired threshold voltage is achieved [3].
To simplify, threshold voltage, Vt is the minimum gate voltage needed to create a
channel between source and drain. It can be defined as the minimum voltage for strong
inversion to occur. During operation, we supply a voltage between source and gate to let
the inversion occur so that current IDS can flow from source to drain. Vt value is
controlled during the fabrication process as mentioned above and is typically VDD/4.
Figure 2.3 shows the threshold voltage point in the drain current, ID versus gate voltage,
VG graph. For PMOS, the value is negative to attract positive charges (holes) in the
channel [6]. In ideal form, Vt is related to physical parameters as follows:
Vt ≈
2ε s qN A (2ψ B )
C ox
+ 2ψ B
(2.1)
where ε s is the dielectric permittivity of silicon, q is electric charge, N A is impurity
(acceptor) concentration in p-type silicon and ψ B is surface potential at inversion.
However, the real condition is different because the interface charges and the metal or
polysilicon work function that must be taken into consideration.
Figure 2.3:
Drain Current (Id) versus gate voltage (Vg) graph.
In reality threshold voltage must be calculated from the flat band voltage due to work
function difference and interface charges,
Vt effective ≈ VFB + Vt
(2.2)
where V FB is the flat band voltage. V FB can be defined as the function of φ ms , where
φ ms is the polysilicon work function, Q , for difference defect charges, and oxide
capacitance, C ox .
Q f Qot Qm 
Q

V FB = φ ms  it +
+
+
C
C
C
C
ox
ox
ox
ox


(2.3)
As shown in Figure 2.4, the defect charges are classified with respect to their location
and action as follows:
Figure 2.4:
1)
Terminology for charges associated with thermally grown SiO2.
Interface-state charges Qit, which are located so close to the Si-SiO2
interface and have energy states so close to the EF variation range of the
semiconductor, that is, mainly within the silicon forbidden bandgap as to be
able to exchange charges with the semiconductor in a short time.
2)
Fixed charges Qf, which are located at or very near the interface but cannot
exchange charges unlike Qit.
3)
Dielectric-trapped charges Qot, the trap sites of which are distributed
inside the bulk dielectric and capture (or emit) the charges brought into the
dielectric film by hot-carrier injection, and so on.
4)
Mobile ionic charges Qm, such as sodium ions, which are mobile within the
oxide under bias-temperature aging conditions. [40]
From equation (2.1) and (2.2), in order to control Vt , the N A and φ ms values must be
controlled. We use the implantation of phosphorus ions to control N A and we replaced
aluminum with polysilicon as the gate. This is because the work function for polysilicon
to oxide is smaller than for aluminum to oxide.
2.3.2 I-V Characteristics
Current-Voltage (I-V) characteristics for the PMOS transistor can be divided into two
regions, the linear region and the saturation region. Figure 2.5 shows the relation
between current and voltage for PMOS by dividing it into two different regions.
Figure 2.5:
Drain current (Id) versus drain voltage (Vg)
The linear region is the region where drain current increase linearly with the drain
voltage for every gate voltage, Vg value. The saturation region in other hand refers to
the region where drain current is almost constant, regardless of the changes of drain
voltage.
(a)
Linear Region:
The relation between current that flows from drain to source, Ids and voltage between
drain and source, Vds for linear region ( Vds << ( Vgs-Vt )) is given as:
I ds =
W
µ N C ox (V gs − Vt )Vds
L
(2.4)
where µ N is the electron activation, W is the channel width, L is the channel length,
V gs is the voltage between gate and source, C ox is the oxide capacitance density per unit
area which is defined as:
Cox =
ε 0ε ox
tox
(2.5)
where ε ox is the oxide permittivity and t ox is the gate oxide thickness.
(b)
Saturation region:
Saturation occurs when Vds > Vgs – Vt, the situation where drain-source voltage, Vds is
greater than the gate-source voltage, Vgs, as shown in Figure 2.6. Current will flow
constantly and will not be dependent on the increasing of Vds.
Figure 2.6:
Transistor in saturation mode (current remains constant or saturates) [9]
The drain current in this region is given by:
I dsat =
Wµ N ε ox
(Vgs − Vt )2
2t ox L
(2.6)
2.4 CMOS Process
The basic CMOS process steps are wafer preparation, well formation, isolation
formation, transistor making, interconnection, and passivation, as shown in Figure 2.7.
The wafer preparation includes epitaxial silicon growth, wafer clean, and alignment
mark etch. Well formation defines the substrate type for NMOS and PMOS transistors.
Depending on the technology generation, there are different techniques for well
formation: single well or self-aligned twin well. Shallow Trench Isolation (STI) has
replaced the Local Oxidation of Silicon (LOCOS) process in the manufacturing of deep
submicron transistors [10].
Transistor
making
involves
gate
oxide
growth,
polysilicon
deposition,
photolithography, polysilicon etch, ion implantation, and thermal annealing. These are
the most crucial process steps in the IC processing sequence. Interconnection processes
use the combination of deposition, photolithography, and etch processes to define metal
wires and connect millions of transistors built on the silicon surface. Finally the
passivation dielectric deposition, photolithography, and etch process seals the IC chip
from the outside world, leaving only the bonding pad open for testing and wire bonding
[3].
Figure 2.7:
NMOS and PMOS process flow
2.5
MOSFET Ion Implantation
One of the most important properties of semiconductor materials is that adding dopants
can control their conductivity. Semiconductor materials such as silicon, germanium, and
gallium arsenide are doped with either n-type or p-type dopant in IC fabrication. There
are two common methods to dope semiconductors: furnace diffusion from solid sources
and ion implantation. Before 1970, diffusion was use in IC fabrication. Currently
doping is mainly done by ion implantation.
Figure 2.8:
Comparisons of doped region for (a) diffusion process and (b) ion
implantation process
Ion implantation is processes by which dopant ions are forcefully add into the
semiconductor in the form of energetic ion beam injection. The ion implantation
process provides much more precise control of doping than the diffusion process [3].
For example, the dopant concentration and junction depth cannot be independently
controlled in the diffusion process because both are related to the diffusion temperature
and time; ion implantation can independently control both dopant concentration and
junction depth [Figure 2.8]. Dopant concentration can be control by the combination of
ion beam current and implantation time and junction depth can be controlled by the ion
energy. The ion implantation process can dope with a wide range of dopant
concentration, from 1011 to 1017 atoms/cm2.
In this project we are going to discuss the drain engineering implantation which covers
halo implant, source/drain extension implant or LDD, and source/drain implant. By
changing dose, energy and rotation of this implants can change the profile and the
electrical characteristics of the 0.13 µm CMOS.
2.5.1 Punchthrough Stop (Halo) Implants
Halo implants are use in submicron scaled transistors to prevent expansion of the drain
depletion region into the lightly doped transistor channel when the transistor is biased
for operation [3]. This behavior can short the channel (punchthrough) and increase
subthreshold leakage currents from the source to the drain [11,12]. It is also known as
the “drain-induced barrier lowering” (DIBL). In submicron transistors with short
channel lengths, punchthrough stopper implants are very necessary. The punchthrough
condition (channel is shorted) with undesirable leakage current will lead to circuit
failure. It occurs when channel length is reduced for scaling. The high electric fields
occur at the drain end of the channel. In the case of an n-channel MOSFET, the
electrons moving from source to drain are accelerated by this high electric field and by
energetic collision can create a free electron and hole pair. This can cause avalanche
breakdown [13].
Punchthrough stop implants (halo implant) place the dopant just below the active
channel, adjacent to the source and drain, as shown in Figure 2.9, in order to carefully
modify the well doping and prevent expansion of the drain depletion region into the
lightly doped channel when the transistor is biased for operation. A boron or indium
implant is employed with NMOS transistors; phosphorus, arsenic or antimony is
employed in PMOS transistors. The active channel region of scaled CMOS transistors is
an area of intense process characterization and development, and advanced ion
implantation applications characterized by complex lateral and vertical doping profiles
in the channel are required to allow implementation of submicron transistors in
mainstream production. Punchthrough stop implants are the best example for this.
Figure 2.9:
Halo structure in transistor.
As channel lengths shrink, all MOS transistors become increasingly susceptible
to punchthrough effects. The effect is most severe for buried channel transistors, but
surface channel transistors are affected as well. There are two main methods of
preventing punchthrough. The first is to aggressively scale S/D extension and S/D
junction depth to be as shallow as possible [10,12]. This puts extra burdens on the
implantation and annealing equipment used to manufacture these junctions, especially
for p-MOSFETs. The other method is to increase the well doping just adjacent to and
beneath the S/D extension regions, to minimize the depletion width spread in these
areas. Precise placement of dopant is required to minimize the increases in junction
capacitance and decreases in channel mobility that result from additional well doping
[15-21].
Recent punchthrough stop implants are also known as “halo” implants, or “LATIPS”
implants (Large Angle Tilt Implanted Punchthrough Stopper). As this name implies,
these implants are usually performed using higher tilt angles (10-30o) [22,23]. As gate
dimensions shrink, less undercutting of the gate is required to produce the punchthrough
stop effect. Consequently, tilt angle requirements for this application are steadily
decreasing below the 0.25µm node, and are expected to reach the “low tilt” threshold of
10o by the 0.1µm node [24].
2.5.2 Source/Drain Extension Implants or Lightly Doped Drain (LDD)
Lower and lower energy implantation is being used to form the deep “source” and
“drain” regions and their “extensions”, which interface with the channel region in
today’s MOS transistors. The more lightly doped (1019 cm-3 range) extensions provide a
gradual dopant concentration gradient between the S/D and the channel region, which
reduces the maximum electric field. The extension region is also called the lightly
doped drain.
A lightly doped drain (LDD) implant is used when defining the source and drain regions
of the MOS transistors. This type or region is referred to as a source/drain extension as
shown in Figure 2.10. It is needed to achieve dimensional reductions for the scaling of
submicron transistors. The implant places the LDD dopant just to the edge of the
channel region under the gate to provide a gradual dopant concentration to the
source/drain regions. The LDD creates complex lateral and vertical doping profiles in
the interface region at the channel edge. The LDD implants for NMOS and PMOS
transistors occur in two separate masking and implant operations. The gate of each
MOSFET is implanted as the shallow junctions of the source and drain are also formed
[3].
Figure 2.10:
Source/Drain Extension implants diagram.
The LDD structure is formed by a medium-to-low-dose implant aligned with the gate
structure (this is the n- or p- implant), followed by a high dose (called the n+ or p+)
source/drain implant. The source/drain implant is aligned to the gate by an oxide
sidewall spacer formed between the two implants. If an LDD is not formed, then high
electric fields are present between the junction and channel regions during normal
transistor operation. Electrons exposed to a high electric field during their movement
from source to drain (for an n-channel) are accelerated by this high field. Energetic
electron collisions create a free electron and hole pair (called hot carriers or hot
electrons) [25]. Hot electrons acquire energy from the electric field and cause electrical
performance problems, such as becoming trapped in the gate oxide layer and interfering
with the gate threshold voltage control of the transistor.
The LDD creates a gradual lateral dopant concentration gradient between the high
concentrations in the S/D regions (1020 to 1021 atoms/cm3) and the low concentrations in
the channel region (1016 to 1017 atoms/cm3) under the gate [26]. The reduced doping of
LDD decreases the electric field between the junction and channel regions. This
technique separates the maximum current path in the channel from the maximum
electric field location in the junction to avoid creating hot carriers.
In a dual-doped polysilicon process both NMOS and PMOS transistors rely on surface
channel operation to reduce the short-channel effect (SCE) and improve subthreshold
characteristics. The important challenge for this process is the Boron penetration from
the polysilicon gate into the channel area of PMOS transistor. Boron penetration causes
a shift in the threshold voltage (Vt) of the transistor, leads to subthreshold swing
degradation, reduces process control, and degrades gate oxide reliability.
2.5.3 Source/Drain Implants
Source/Drain (S/D) implants form highly doped regions (1020 to 1021 ions/cm3) that
interface with the lightly doped active channel and well regions (1016 to 1017 ions/cm3)
of an MOS transistor. S/D regions are doped to have the opposite conductivity type as
the well that surrounds them. Arsenic implants are often used to form n-type
source/drain for n-channel (NMOS) transistors, and boron or BF2 implants are usually
used to form p-type source/drain for p-channel (PMOS) transistors [10].
These highly doped S/D regions are contacted through cobalt silicide to the rest of the
circuit. In the absence of a bias on the gate and drain, the S/D regions form two back-toback semiconductor junction diodes. When a sufficiently large bias is applied to the
gate electrode, a surface inversion layer is formed creating a conducting “channel”
between the source and the drain (for normally-off, enhancement type transistor [12]).
Current can be made to flow in the channel by the application of a bias on the drain and
varying the bias on the gate can modulate the conductance.
Scaling of the S/D and LDD implants, to keep up with the transistor scaling
requirements, has posed the biggest challenge in recent years. Present transistor scaling
rules demands that the vertical and lateral dimensions be reduce by a factor of two,
approximately every 5 to 6 years [42]. Accordingly, both the deep S/D and the LDD
junction depths need to be reduce by the same factor. The challenge in scaling the S/D
implant is, primarily, meeting the junction depth requirement while maximizing the
active dopant concentration. The later is necessary to reduce the contact resistance of
the silicide to the doped S/D. For the deep S/D, unlike the LDD, meeting the junction
depth requirement also means not making it too shallow, otherwise the silicidation
process can consume the entire junction. It is also important to minimize the electrically
active residual damage in the S/D regions, which increases the reverse leakage current
of the S/D junctions and thus the leakage current of the transistor in the off state (Ioff).
Reducing the implant energy leads to a reduction in the junction depth. By using
implantation with its excellent control of doping placement, the lateral diffusion of the
source/drain dopant ions into the channel region is minimized.
2.6
MOSFET Scaling Effects
Scaling has major effects on silicon transistors and the wiring interconnects that are
used in silicon technology. In order to increase the semiconductor chips performance
and to match the MOSFET dimension, internal connections have to be scale down along
with the silicon transistor. Scaling doesn’t only change the transistor structure; it also
brings new problems to the transistor performance.
2.6.1 Short Channel Effect
A MOS transistor is termed short channel if the channel length is below a minimum
length given by Brew’s rule [27]
[
Lmin ≈ 0.4 x j t ox (Wd + Ws )
where
1
2 3
]
(2.7)
x j = junction depth in µm
t ox = oxide thickness in Å
Wd = drain depletion width in µm
Ws = source depletion width in µm
For a short channel transistor, the threshold voltage decreases as the channel length
decreases. This is due to charge sharing between the gate region and both the source and
drain depletion region as shown in Figure 2.11. As the channel length decreases, this
effect becomes more pronounced. The equation for the threshold voltage for an NMOS
transistor (assume zero substrate bias, Vbs = 0 ) is as shown below
Vt 0 = φ MS + 2φ F +
QB 0 Qox
−
C OX C ox
(2.8)
where
(2.9)
φ MS = φ M − φ S
φF =
QB 0 =
(2qε
kT  N A 

ln
q  ni 
o
ε Si N A 2φ F
(2.10)
)
(2.11)
C ox =
ε o ε ox
t ox
Qox = QF + QIT + QM + QOT
φ ms :
work function difference between the gate and the channel
2φ F : total band bending at surface inversion
QBO : depletion region charge density at surface inversion
QF :
fixed oxide charge
QIT : interface charge
QM : mobile ion charge
QOT : oxide trapped charge
kT / q : thermal voltage
NA :
substrate doping density
ni :
intrinsic carrier concentration
C ox :
oxide capacitance
εo :
permittivity of free space
ε si :
dielectric constant of silicon
ε ox :
dielectric constant of silicon oxide
t ox :
gate oxide thickness
k:
boltzmann constant
q:
electronic charge
(2.12)
(2.13)
Figure 2.11:
Charge sharing phenomenon [27].
However, for short channel transistor, the threshold voltage is given by:
Vt 0 = φ MS + 2φ F +
QB 0 Qox
−
C OX C ox
(2.14)
where
  ∆L + ∆LD
QB 0 ' = 1 −  S
2L
 

 (2qε 0 ε Si N A 2φ F

)
(2.15)
∆LS = lateral extension of depletion region of the source
∆LD = lateral extension of depletion region of the drain
From the above equation, QB 0 ’ becomes smaller than QB 0 as the channel length is
decreased. As result, Vt 0 decreases for short channel transistor as shown in Figure 2.12.
The reduction of the threshold voltage represents the amount of charge differential
between the rectangular and trapezoidal depletion region.
Figure 2.12:
Threshold voltage variations with channel length.
2.6.2 On-State Saturation Current
For long channel transistor, the equation for the on-state saturation current is as follows:
I on = µ n c ox
where
w
(Vgs − Vto )2
2L
(2.16)
w = channel width
L = channel length
µ n = electron mobility
In this equation, it is assumed that the drift velocity, v d = µ n E as shown in Figure 2.13,
where E is the average electric field inside the channel, for E << E c (critical electric
field). For a short channel transistor, the equation for the on-state saturation current
becomes:
I on = cox w(V gs − Vto )v d
(2.17)
In this equation, due to high lateral electric field E because of reduction in channel
length, the drift velocity v d becomes saturated (v d ≠ µ n E ) .
Figure 2.13:
Drift velocity becomes a constant above the critical field [27].
2.6.3 Punchthrough Effect
In small geometry MOS transistors, a large drain bias voltage will result in the
extension of the drain depletion region towards the source. Once the two depletion
regions meet each other as shown in Figure 2.14, the gate voltage loses control over the
drain current. This can eventually lead to punch-through. If punch-through occurs, there
is a sudden increase in drain current as shown in Figure 2.15.
Figure 2.14:
Punch-through effect in a short channel transistor.
Figure 2.15:
Id vs Vd curve due to punch-through effect [27].
2.6.4 Hot Carrier Effect
When the lateral electric field becomes high particularly near the reverse biased drainto-substrate junction due to dimension reduction, carriers are accelerated into the
depletion region. These carriers possess energy higher than the thermal energy, thus
they are known as hot carriers. When they collide with the ions present in the depletion
region, electron-hole pairs are generated by impact ionization. This is shown in Figure
2.16.
Hot carrier effect causes current to flow in the substrate, Isub which can subsequently
lead to latch-up. It also results in the formation of interface states which reduce the
electron mobility and hence decreases the saturation drain current as well as degrade the
transconductance. The threshold voltage will also increase due to electron trapping in
the oxide. This is show in Figure 2.17 [27].
Figure 2.16:
Impact ionization effect in transistor.
Figure 2.17:
Hot carrier effect
2.7 Methods Attempted by Other Researchers
As gates get smaller, the channel length below the gate structure (the silicon region
between the source and drain) also decreases. This reduction, although is good for
manufacturer, it causes many problems for CMOS transistors. Deep sub-micrometer
MOS transistors often need special structures to optimize their performance.
Researchers have been trying to find alternative ways to reduce many downscaling
problems and to optimize CMOS transistors. The halo structure, or halo implant, is
usually adopted to reduce off-state leakage current and enhance on-state drive current.
Jiong-Guang Su [25], mentioned that transistor with higher halo implant tilt angle
reduced body effect and increase source resistance as compared to those with low tilt
angle. They investigate the influence of tilt angle of halo implant on optimizing PMOS
performance based on process and device simulation. If a proper dose is adopted, large
tilt angle halo implant should be adapted to reduced parasitic capacitance and enhanced
transistor performance.
In the work reported by Wen-Kuan Yeh [28], it was proposed that for high performance
sub-0.1µm channel length MOSFETs, we must use optimized indium halo structures
and arsenic implantations. They found that:
1) Compared to B-halo NMOS, In-halo NMOS form localized high-dose structures
that improve transistor punch-through margins and are free of apparent Reverse
Short Channel Effect (RSCE) due to indium deactivation. Thus In-halo
structures reduced Vths while increasing transistor resistance to Short Channel
Effect (SCE).
2) In-halo NMOS junction leakage and capacitance were affected by indium
dosage levels and off-state leakage increased due to and increase in the n+ junction
breakdown field.
3) Larger junction fields occurred around deep source/drain junction regions with
larger junction areas due to locally heavy doses of implanted indium and junction
leakage and capacitance were found to be sensitive to In-halo implantation energies.
4) Lower temperature composite liner-oxide/SiN spacer technology is proposed for
PMOS to suppress transistor performance degradation due to high-temperature
processing.
Work from C.Chen [29] also suggest that to improve PMOS Vt roll-off, high energy As
P-halo implant through the polysilicon gate should be used, and this was confirmed by
Secondary Ion Mass Spectroscopy (SIMS) and simulation. They also optimized the
drain engineering with proper BF2 P-extension energy and As P-halo energy, angle and
dose.
Besides using halo structures, researchers also did many studies on source/drain
junctions. Fu-Cheng Wang [26] reported that compared to the conventional single BF2
implant fabrication technique, the double-implanted source/drain junction technique
allows further downscaling of BF2 implant energy without increasing the junction
leakage. This technique also offers the advantages of lower junction capacitance, less
boron penetration, thinner gate oxide, and wider process window.
K.K. Bourdelle [30] reported the effect of fluorine from BF2 source/drain extension
implants on performance of PMOS transistors with thin gate oxides. Boron penetration,
which causes a degradation of many transistor parameters, is further enhanced when
BF2 is used to dope the gate electrode. In the paper, a comprehensive study of the
fluorine enhanced boron diffusion in gate oxide is presented. Boron penetration causes a
shift in the threshold voltage (Vt) of the transistor, leads to subthreshold swing
degradation, reduces process control, and degrades gate oxide reliability. A range of
methods was used to suppress fluorine enhanced boron penetration is as follows:
1)
nitrogen implantation into poly-Si
2)
stacked amorphous/poly gate structure
3)
sacrificial gate stack process
These techniques focus on preventing fluorine migration from the implanted gate to the
gate oxide. In order to prevent fluorine from the source/drain (S/D) areas from diffusing
into the gate oxide-channel region, this paper suggests to use W-polycide process, in
which gate and S/D doping is done separately. In this paper they also show that
enhanced boron penetration due to fluorine from the BF2 extension implants degrades
PMOS transistor performance for gate oxide thicknesses less than 27 Å and gate lengths
less than 0.5 µm.
Many researchers have proposed methods not only to optimize the process parameters
but also to control the electrical characteristics, mainly the threshold voltage and
saturation current. Hajime Kurata and Toshihiro Sugii [31], suggested a new method to
control the threshold voltage (Vth) in sub-0.2 µm MOSFET’s. They changed the
concentration of the channel impurity according to the gate length by tilted ion
implantation from two directions after the polysilicon gate formation. Their results
show that the short channel effect is effectively reduced by this method without
increasing the S/D junction capacitance.
From the literature review work, the process characterization and device optimization
are developing rapidly for CMOS technology today. It is important for us to
characterize our technology in Silterra as there are many possibilities that problems will
occur when a transistor is scaled down. Based on the literature, equipment and software
availability in Silterra, TCAD simulator was chosen to simulate the process and
transistor for Silterra 0.13 µm CMOS and to compare all the simulated data with the
measured data obtained from the real wafers that were fabricated at Silterra.
2.8 Summary
In this chapter, the basic properties and operation of a transistor have been discussed.
The importance of ion implantation especially Halo, LDD and source/drain implant in
the CMOS process has also been addressed. The importance of characterizing the
electrical characteristics for CMOS has also been discussed. In the following chapter,
the experimental procedure for calibrating and validating the TSUPREM-4 and
MEDICI input files would be described.
CHAPTER 3
CALIBRATION AND VALIDATION OF TSUPREM-4 AND
MEDICI
3.1
Introduction
Commercial TCAD tools, TSUPREM-4 [32] and MEDICI [33] are used for 0.13 µm
process and device simulation. Since they are not calibrated to any specific technology,
use of default simulation parameters can lead to significant differences between the
simulated and measured I-V characteristics. Therefore, certain levels of calibration
work are necessary for judicious selection of different models and modification of some
important default parameters. This tuning of model parameters to match measured data
is one of the objectives of the thesis. Simulated results from both TSUPREM-4 and
MEDICI are compared to measured data to evaluate agreement.
Based on optimized models and parameters, simulation work is focused on 0.13 µm
technology mainly for drain engineering consisting halo, lightly doped drain and
source/drain structures. These critical parameters are optimized for performance and
reliability improvement.
3.2
TSUPREM-4 [34]
Taurus TSUPREM-4 is an advanced 1D and 2D process simulator for developing
semiconductor process technologies and optimizing their performance. With a
comprehensive set of advanced process models, Taurus TSUPREM-4 simulates the
process steps used for fabricating semiconductor devices, reducing the need for costly
experiments using silicon. In addition, Taurus TSUPREM-4 has extensive stress
modeling capabilities, allowing optimization of stress to increase transistor performance.
Benefits:
•
Develop leading edge CMOS, bipolar, and power-device manufacturing
processes cost-effectively.
•
Predict 1D and 2D device structure characteristics by accurately simulating ion
implantation, diffusion, oxidation, silicidation, epitaxy, etching, and deposition
processing, reducing experimental runs and technology development time.
•
Analyze stress history in all layers as a result of thermal oxidation, silicidation,
thermal mismatch, etching, deposition, and stress relaxation.
•
Study impurity diffusion, including oxidation-enhanced diffusion (OED),
transient-enhanced diffusion (TED), interstitial clustering, dopant activation, and
dose loss.
3.3
TAURUS MEDICI [35]
Taurus Medici is a 2D device simulator that models the electrical, thermal, and optical
characteristics of semiconductor devices. A wide variety of devices including
MOSFETs, BJTs, HBTs, power devices, IGBTs, HEMTs, CCDs, and photodetectors
can be modeled. Taurus Medici can be used to design and optimize devices to meet
performance goals, thereby reducing the need for costly experiments. With the
continued scaling of CMOS devices, device design and optimization become more
difficult. Previously unimportant phenomena, such as direct tunneling, can now
dominate device performance and design. The vast array of advanced transport and
quantum models available in Taurus Medici allow users to perform accurate simulations
of deeply scaled devices.
Benefits:
•
Analyze electrical, thermal, and optical characteristics of devices through simulation
without having to manufacture the actual device.
•
Determine static and transient terminal currents and voltages under all operating
conditions of interest.
•
Understand internal device operations through potential, electric field, carrier,
current density, and recombination and generation rate distributions.
•
Investigate breakdown and failure mechanisms, such as leakage paths and hotcarrier effects.
3.4
Calibration of 130 nm MOSFET
This section will discuss the calibration done before we start our simulation using
TCAD tools. Calibration of TCAD simulator is done by tuning the implant condition
based on the Secondary Ion Mass Spectrometry (SIMS) implant data taken on finished
wafers.
Silterra SIMS vendor, Charles & Evans, performed the SIMS profiling. Samples were
identified and selected based on the sheet resistance results. Details such as dopant
species, implant doses, implant energy, the expected dopant depth and full process of
the samples were provided in order to get a more accurate result. Samples were also cut
into small pieces at the centre of the wafer before being delivered to the vendor in order
to save the cost. The profiling takes 2 weeks to complete for normal price; extra charges
will be needed if the duration of the profiling is shorter than 2 weeks. Results are
available in both hard copy and soft copy (in the form of excel sheet).
The TCAD simulator is calibrated by comparing the SIMS data with the simulated
result. If the matching does not fit well, the process parameter such as annealing and
deposition time was adjusted to make the calibration curve fit well. The implant
condition was not changed, as it will change the process that was used in fabricating the
wafer that was sent for SIMS. In this chapter, we will calibrate one-dimensional asimplanted profiles. With the help of the optimization function in TSUPREM-4 version
W-2004.12, some key implant moment parameters for Gaussian or Pearson distribution
are optimized to fit the measured data. Implant profiles from secondary ion mass
spectroscopy (SIMS) measurement are selected as the optimization target. The
optimized distributions parameters are subsequently incorporated into the simulations.
The SIMS data that was obtained in order to tune and optimize our TCAD NMOS and
PMOS simulator deck is shown is Table 3.1.
Table 3.1:
SIMS data obtain for this experiment.
No.
Structure Name
Implant Profile
1
Nwell_STI
Phosphorus
2
Pwell_STI
Boron
3
HP_NSD_S
4
HP_PSD_S
Arsenic,
Phosphorus
Boron
5
HP_Ngate_S
6
HP_Pgate_S
7
HP_NLDD
Arsenic, Boron,
Indium, Phosphorus
Arsenic,
Phosphorus
Arsenic, Boron
8
HP_PLDD
Boron
9
DNWell_STI
Phosphorus
During the calibration, some matching problem has occurred and troubleshooting has to
be done in order to get an accurate result with percentage error less than 10%. In this
PMOS and NMOS transistor calibration, the accuracy of as-implanted doping profiles,
especially in the channel region, is crucial to the final simulation results. The implant
moment tables for the analytic model in TSUPREM-4 give very accurate results after
implantation into bare, <100> silicon, but are normally not appropriate under other
implant conditions. In this calibration process, the analytic implant models, including
Gaussian, Pearson and dual-Pearson functions, are found to be suitable in predicting
implant profiles. The parameters associated with these models need to be optimized for
best fit to SIMS profile. This analysis is called standard regression analysis. However,
there are some limitations on standard regression analysis method. It is based on some
assumptions, which are not always valid in analysis.
Actually, the importance and the accuracy of the information about the value of y
(concentration) for each x (depth) may differ substantially in SIMS profile. In this study,
it is desirable to give greater emphasis to the data at the near-surface part (from silicon
surface to the depth of 0.1 µm) because the dopants there have more influence on basic
transistor characteristics.
We first select a phosphorus profile implanted at energy of 380 KeV and a dose of
6E+12 atom/cm2 for calibration. Figure 3.1 shows the discrepancy between SIMS
profile and simulated profile before calibration. The default implant table of phosphorus
defined in the implant data file is used for Pearson function. The MOMENT parameters
are fitted to the results of Monte Carlo calculations and hence, no channeled tail can be
simulated and fitted. It is shown that the SIMS profile has a clear channel tail. Thus,
dual-Pearson function should be used to fit it. Appendix B lists the TSUPREM-4
program in which parameters of dual-Pearson functions are determined for the
phosphorus profile. A SIMS data file (concentration versus depth) is used as a target for
the optimization.
Phosphorus concentration
(atoms/cc)
1E+18
Nwell Simulation
Nwell SIMS
1E+17
1E+16
1E+15
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Depth (micron)
Figure 3.1:
Initial discrepancies between SIMS measurement and profile simulated
by TSUPREM4 using default moment parameters.
During the optimization loop, successive estimates of the Pearson parameters are
introduced into the simulation using the MOMENT statement. The MOMENT statement
sets distribution moments for specific materials. The used of this statement overrides
the reading of implantation data file that would normally occur. The EXTRACT
statement extracts the chemical phosphorus concentration at the locations specified in a
SIMS data file. At each step in the optimization procedure the parameters to be
optimized are varied to match the extracted phosphorus concentration with the target
concentrations given in a specified SIMS data file.
Now the calibration of multiple implanted profiles will be discussed. For a quartermicron transistor, doping profile in N-channel region consists of P-well implant, Nchannel anti-punchthrough (NPT) implant and N-channel threshold voltage adjust
(NVT) implant. In designing a new transistor for a specified Vt requirement, we
generally fabricate some wafers simultaneously with different implant conditions.
Among these wafers, the implant energies are fixed. The doses of NVT and NPT
implant are varied to ensure that transistors in one or more wafers can hit the target. For
such purpose, accurate prediction of Vt by process and device simulation is desirable.
This cannot be accomplished without calibrations of implant moment parameters related.
In this case, wafers are prepared for each implant and send out for SIMS measurement.
The basic optimization measure is similar to that of previous section and detail steps
will not be described here. The comparison of simulated and SIMS data is discussed
further in section below.
1)
PMOS Transistor
Figures below are the calibration graphs comparing the SIMS profile and the simulated
profile obtained from TSUPREM-4. The TCAD deck for PMOS and NMOS were
calibrated focusing more at the implant step, because at this step is the critical part for
optimization and characterization analysis of 130 nm CMOS for this experiment.
We start with PMOS deck, which have three main implant steps to be calibrated, Nwell,
PLDD and PSD. Figure 3.2 shows the cut line that was done on the PMOS transistor
simulated by TSUPREM-4.
Cut line
y (µm)
x (µm)
Figure 3.2:
Cut line done on PMOS and NMOS transistor simulated by TSUPREM4 to obtain doping profile.
As shown in Figure 3.3 to Figure 3.4, the TCAD deck for PMOS transistor is calibrated
as the SIMS profile data fits well with the TSUPREM-4 profile. Figure 3.3 shows the
Nwell matching plot. The maximum percentage difference between simulation and
SIMS is 27.3%.
Phosphorus concentration (atoms/cc)
1.00E+18
Nwell Simulation
Nwell SIMS
1.00E+17
1.00E+16
1.00E+15
-0.4
Boron concentration (atoms/cc)
Figure 3.3:
-0.2
0
0.2
0.4
Depth (microns)
0.6
0.8
1
Comparison of Phosphorus Nwell doping concentration profile,
simulated and measured by SIMS.
6.00E+19
PLDD Simulation
5.00E+19
PLDD SIMS
4.00E+19
3.00E+19
2.00E+19
1.00E+19
0.00E+00
0
0.005
0.01
0.015
0.02
Depth (um)
Figure 3.4:
Comparison of PMOS Lightly Doped Drain (PLDD) Boron doping
concentration profile, simulated and measured by SIMS.
Figure 3.4 shows the comparison for PMOS Lightly Doped Drain (PLDD) implant
which is much shallower than the Nwell implant. The maximum error is 1.36%.
2)
NMOS Transistor
Figure shown below is for NMOS transistor calibration. It includes the Pwell implant,
NSD and NLDD. Figure 3.5 below shows the comparison for Pwell in NMOS. The
Boron cencentration (atoms/cc)
maximum percentage difference for this plot is 5.02%.
6.00E+17
5.00E+17
Pwell SIMS
Pwell Simulation
4.00E+17
3.00E+17
2.00E+17
1.00E+17
0.00E+00
-4.00E-01 -2.00E-01 0.00E+00 2.00E-01
4.00E-01 6.00E-01
8.00E-01 1.00E+00
Depth (um)
Figure 3.5:
Comparison of Boron doping concentration profile by simulated and
measured by SIMS for Pwell.
For Figure 3.6, shows the comparison between SIMS and simulated of phosphorus
concentration for NMOS Source/Drain (NSD). It is shown that the simulated NSD
implant for phosphorus fits almost 1% over depth of 0.06 µm till 0.1-µm. the maximum
percentage difference for this plot is 3.15%.
Phosphorus concentration (atoms/cc)
2.00E+20
NSD SIMS
NSD Simulation
1.80E+20
1.60E+20
1.40E+20
1.20E+20
1.00E+20
8.00E+19
6.00E+19
4.00E+19
2.00E+19
0.00E+00
0.00E+0 1.00E0
02
2.00E02
3.00E02
4.00E02
5.00E02
6.00E02
7.00E02
8.00E02
9.00E02
1.00E01
Depth (um)
Figure 3.6:
Comparison of NMOS Source/Drain (NSD) Phosphorus doping
concentration profile, simulated and measured by SIMS.
Figure 3.7 below shows the comparison for Arsenic concentration. The maximum
Arsenic concentration (atoms/cc)
percentage error for this plot is 11.62%.
1.80E+21
1.60E+21
1.40E+21
1.20E+21
1.00E+21
8.00E+20
6.00E+20
4.00E+20
2.00E+20
0.00E+00
NSD Simulation
NSD SIMS
0
0.02
0.04
0.06
0.08
0.1
Depth (um)
Figure 3.7:
Comparison of Arsenic doping concentration profile by simulated and
measured by SIMS for NMOS Source/Drain (NSD).
3.5
Validation of TSUPREM-4 and MEDICI
After calibrating the TSUPREM-4 and MEDICI input files, we have to validate the data
that we simulate to make sure the data is comparable to the data measured on real
wafers fabricated at Silterra. We used the device simulator MEDICI to simulate our
transistor to get Id-Vd curves. Table 3.2 shows the standard process for Silterra 0.13 µm
CMOS process. This same process is used both in the real wafer fabrication and also in
our process simulator, TSUPREM-4.
Table 3.2:
Standard 0.13 µm CMOS process in Silterra.
Implant steps
Pwell-Thin-Imp-HE
Standard Recipe
VTN-Thin-Imp1
VTN-Thin-Imp2
B11, 1.2E+13(Total),260 KeV,Ti-5,Tw-5,Q+
B11, 7E+12(Total), 180 KeV, Ti-5,Tw-5,Q
B11, 5.5E+12, 40 KeV, Twist 22, Tilt 7
In115, 4E+12, 100 KeV, Twist 22, Tilt 7
VTN-Thin-Imp3
BF2, 1.1E+12, 40 KeV, Twist 22, Tilt 7
NPT-Thn-G-Imp
NPT-Thn-G-Imp2
B11, 1.3E+13, 15 KeV, Twist 0, Tilt 25, Quad
In115, 2.0E+13, 120 KeV, Twist 22, Tilt 30, Quad
NLDD-Thn-Imp
NSD-Imp1
NSD-Imp2
NSD-Imp3
PSD-Imp1
PSD-Imp2
As75, 1.5E+15, 3.5 KeV, Twist 0, Tilt 7, Quad
As75, 4.72E+15, 40 KeV, Twist 0, Tilt 7, Quad
P31, 6E+14, 10 KeV, Twist 0, Tilt 7, Quad
P31, 9.32E+14, 35 KeV, Twist 0, Tilt 7, Quad
B11, 2.7E+15, 2.5 KeV, Twist 0, Tilt 7, Quad
B11, 5E+13, 11KeV, Twist 0, Tilt 7, Quad
Figure 3.8 below shows the Id-Vd curve for a PMOS transistor that was simulated using
MEDICI device simulator. The Idsat value was taken at Vd = -1.2 V. The Idsat for this
transistor is 230 µA/µm. Figure 3.9 shows the Id-Vd curve for the NMOS transistor that
was simulated in the device simulator MEDICI. The Idsat value for the NMOS transistor
is 531 µA/µm at Vd = 1.2 V.
-2.50E-03
Drain current, Id(A)
-2.00E-03
PMOS simulated drain
current
-1.50E-03
-1.00E-03
-5.00E-04
0.00E+00
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
Drain voltage, Vd(V)
Figure 3.8:
Simulated drain current (Id) versus drain voltage (Vd) using MEDICI for
0.13 µm PMOS transistor.
6.00E-03
Drain current Id, (A)
5.00E-03
NMOS simulated drain
current
4.00E-03
3.00E-03
2.00E-03
1.00E-03
0.00E+00
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain voltage Vd, (V)
Figure 3.9:
Simulated drain current (Id) versus drain voltage (Vd) using MEDICI for
0.13 µm NMOS transistor.
Table 3.3:
Saturation current, Idsat data between simulation using MEDICI and real
wafer measurements.
PMOS
230
Idsat (electrical
measurement), µA/µm
240
NMOS
531
542
Transistor
Idsat (MEDICI), µA/µm
From the comparison table shown above, we can conclude that MEDICI simulator is
reliable in its use for the experiments that will be explain later in this work. The
percentage error between simulator MEDICI and real wafer measurement for PMOS is
4.17%. The percentage error for NMOS transistor between the simulated data and the
real wafer measurement is 2.03%.
3.6
Summary
In this chapter, we first make a detailed description of the SIMS measurement and, the
analytic model adopted by TSUPREM-4. Some statistical methods, which are useful for
dopant profile calibration, are introduced. A systematic as-implanted profile calibration
methodology is described.
Generally, we used dual-Pearson functions to model an angle-implanted profile. The
calibration of dual-Pearson functions for a specific energy and impurity is divided into
three phases. First, the moment parameters of the primary Pearson function are
optimized to fit the amorphous part of the SIMS profile. Then, the moment parameters
of the secondary Pearson function are optimized to fit the channeled tail of the SIMS
profile. Finally, some key parameters (or all parameters) in the dual-Pearson functions
are varied in a small range and fine-tuned to fit the whole SIMS profile based on the
previous optimization results.
These profiles were matched with the doping profile obtained from TSUPREM-4
simulator and it is proved that the simulator is calibrated and reliable to be used further
in this work.
The use of the device simulator MEDICI has also been described and validated in order
to gain confidence in its use and its application to the measurements that will be
described later in Chapter 4.
CHAPTER 4
RESULTS
4.1
Investigation of Halo Implant in PMOS and NMOS Device
4.1.1 Introduction
In this chapter the simulation procedure used to study the Halo implant in the PMOS
and NMOS device is described. The simulated results were analyzed using TCAD
process simulation, TSUPREM-4 and device simulation, MEDICI. The simulation
result is then compared to measure data obtained from the real wafer fabricated in
Silterra. The optimized processes for Halo implant were analyzed and were validated to
be used further in Silterra 0.13 µm CMOS process.
4.1.2 Simulation Procedure
Figure 4.1 below shows the process flow for PMOS and NMOS in this work. First, the
current process recipe for 0.13 µm PMOS and NMOS is obtained from Silterra
specifications. Three splits were done for each device in order to see any discrepancies
between the splits. The simulation was run using the same process recipe running in the
real wafer fabrication in Silterra. Process simulator TSUPREM-4 was used to do the
profile analysis. In this analysis, the dopant concentration was clearly seen, current flow
and many other changing parameters that cannot be seen in real device. Then, the
experiment was continued using device simulator MEDICI to see the electrical
characteristics, which are the threshold voltage, Vt and drain current, Id. From here, the
halo dose, energy or tilt angle was adjusted in order to match with the measured data
from the real wafer.
Figure 4.1: Workflow for experimental procedure
Obtain Silterra’s 0.13
µm Halo process splits
for NMOS and PMOS
Simulate all PMOS
halo process splits
using TSUPREM-4
Analyzed Halo
doping profiles
from TSUPREM-4
Repeat the step
for NMOS
Simulate using
device simulator,
MEDICI
Compared and
match the measured
data with simulation
data
Calculate the best dose to
meet Silterra’s specification
target
4.1.3 Simulation Results
In this work, effects of dose, energy and tilt angle were analyzed. Table 4.1 below
shows the split done for different dose for halo implant. Arsenic species was used for
PMOS device and boron was used for NMOS device.
Table 4.1:
Process split for PMOS and NMOS halo implant with various dose.
Samples
(Splits)
PMOS
HaloPD1
HaloPD2
HaloPD3
NMOS
HaloND1
4.1.3.1
HaloND2
HaloND3
Halo Implant
Dose
(atom/cm2)
Arsenic,
3.3E+13
Arsenic,
3.1E+13
Arsenic,
3.5E+13
Energy
(KeV)
Tilt Angle
(0)
90
30
90
30
90
30
Boron, 1.0E+13
15
25
Boron, 1.3E+13
15
25
Boron, 1.6E+13
15
25
PMOS Halo Analysis
After simulating PMOS device with different dose of Arsenic, the doping profile for
PMOS device was plotted using TV2D in TCAD software. This will allow doping
concentration to be plotted and use to detect any discrepancies when the dose is tuned to
find the optimized and correct dose for PMOS Halo.
Based on Figure 4.2 (a), (b) and (c), it can be summarized that by using HaloPD1 dose
is the best-optimized dose for halo implant in this work. Too high dose concentration
can give a distortion to the channel and will short the channel eventually. So it is
suggested here that arsenic with 3.3E+13 atom/cm2 is used for PMOS halo implant.
Arsenic
Junction
(a)
Arsenic
(b)
Arsenic (Nearly overlap)
y (µm)
(c)
x (µm)
Figure 4.2:
Arsenic doping profile for three different arsenic doses to optimize the
Halo implant step, (a) HaloPD1 (3.3E+13 atom/cm2), (b) HaloPD2
(3.1E+13 atom/cm2) and (c) HaloPD3 (3.5E+13 atom/cm2).
In sequence to support the result of using the HaloPD1 dose, the PMOS device was
simulated using MEDICI to further investigate the best dose to be used as an optimized
dose in this work. Figure 4.3 below is Idsat versus PMOS halo dose comparing between
measurement and simulation. From this graph, Idsat is taken at Vd = 1.2 V. It is shown
that Idsat for HaloPD1 (3.3E+13 atom/cm2) dose is near to the value measured from real
wafer. According to the experimental result, conclusion can be made that HaloPD1 is
the recommended dose in PMOS implant with the percentage difference from the real
wafer measurement is less than 2%. This dose is suggested, as it is the best dose that
can match and meet Silterra electrical specification target. Figure 4.4 shows the
simulated I-V curve for Lg=0.13 µm transistor at different halo implant doses, 3.3E+13,
3.1E+13 and 3.5E+13. It is found that decreasing halo implant dosage will increase Id,
which implies Vt will roll-off.
-180
Idsat (uA/um)
-185
-190
-195
-200
-205
-210
Measured
-215
Simulated
-220
3E+13
3.1E+13
3.2E+13
3.3E+13
3.4E+13
3.5E+13
3.6E+13
2
PMOS Halo Dose (atom/cm )
Figure 4.3:
PMOS Halo dose for 10/0.13 device accuracy plot between measured
and simulated.
Drain current, I d (A)
-2.5E-03
-2.0E-03
-1.5E-03
-1.0E-03
As 3.1E+13 atom/cm2
As 3.3E+13 atom/cm2
-5.0E-04
As 3.5E+13 atom/cm2
0.0E+00
0
Figure 4.4:
-0.2
-0.4
-0.6
-0.8
-1
Drain voltage, Vd (V)
-1.2
-1.4
Simulated Id versus Vd curve for different PMOS halo dose, (a) HaloPD1
(3.3E+13 atom/cm2), (b) HaloPD2 (3.1E+13 atom/cm2) and (c) HaloPD3
(3.5E+13 atom/cm2).
4.1.3.2
NMOS Halo Analysis
NMOS is one of the devices that have a stable process developing them. For this work,
analysis for NMOS is done only on different dose of boron. The dose for this implant
has to be optimized in order to upgrade the device performance. Note that from
literature, researchers always work on controlling the dose for NMOS halo implant, as
this dose will affect the device electrical characteristics.
For this work, three different boron doses were used for NMOS halo implant. Boron
dose varies from 1.1E+13 atom/cm2 to 1.6E+13 atom/cm2. After simulating the device
with process simulator TSUPREM-4, device profile analysis will be discussed. Figure
4.5 below shows boron concentration for various doses to optimized NMOS halo
process. It can be observed from this figure that with a medium dose used (1.3E+13
atom/cm2), halo structure can be formed perfectly without overlapping source and drain.
Figure 4.6 below shows the current flow line with existence of electric potential.
Current flow line (grey colour) is different for every dose simulated. To get clearer
picture of which dose have a significant effect to the current flowing in the NMOS
device, a cutline is done under each gate of the device simulated. Figure 4.7 shows the
vertical cutline profile of the current density. It is obvious here that different dose might
affect the current density at the drain. The process of characterizing the correct dose that
match the Silterra specification range using the TCAD simulator have been done. The
measured data and simulated data will now be compared as in Figure 4.8.
Overlapping
Halo
y (µm)
Overlapping
(a) Boron,
1.0E+13atom/cm2
(b) Boron,
1.3E+13atom/cm2
(c) Boron,
1.6E+13atom/cm2
x (µm)
Figure 4.5:
Boron concentration for NMOS Halo implants with various doses, (a)
HaloND1 (1.0E+13 atom/cm2), (b) HaloND2 (1.3E+13 atom/cm2) and
(c) HaloND3 (1.6E+13 atom/cm2).
In order to further find the right dose to be used for NMOS device that can match the
electrical specification, simulated data for Idsat that was extracted from MEDICI device
simulator was compared with the measured data obtained from real wafer measurement.
Figure 4.8 shows the accuracy plot for NMOS halo implant. The simulated data show a
good agreement with the measured data at HaloND2, which used 1.3E+13 atom/cm2
boron dose. The percentage error for this dose is only 0.2 %. This shows that this is the
right selected dose that shall be used in NMOS halo process in order to meet the
specification target.
Vertical cutline
Boron,
1.0E+13
Current flow line
Vertical cutline
Boron,
1.3E+13
Current flow line
y (µm)
Vertical cutline
Boron,
1.6E+13
Current flow line
x (µm)
Figure 4.6:
Current flow line (grey lines) in conjunction with electric potential
concentration for different boron doses, (a) HaloND1 (1.0E+13
atom/cm2), (b) HaloND2 (1.3E+13 atom/cm2) and (c) HaloND3
(1.6E+13 atom/cm2).
Figure 4.7:
Current flow vertical cutline align along the poly gate profile for various
halo dose, 1.0E+13, 1.3E+13 atom/cm2 and 1.6E+13 atom/cm2.
Idsat (uA/um)
560
550
Measured
540
Simulated
530
520
510
500
490
480
470
9E+12
1.1E+13
1.3E+13
1.5E+13
1.7E+13
NMOS Halo Dose (atom/cm 2)
Figure 4.8:
NMOS Halo dose for 10/0.13 µm device accuracy plot between
measured and simulated for 3 different boron doses, (a) HaloND1
(1.0E+13 atom/cm2), (b) HaloND2 (1.3E+13 atom/cm2) and (c)
HaloND3 (1.6E+13 atom/cm2).
4.1.4 Summary
It has been demonstrated in this chapter how simulations can predict the right dose for
implanting PMOS and NMOS halo. Characterization of the doping profile after the
simulation has been done. From this doping profile, the internal part of the transistor is
clearly analyzed and how the dopant diffuses to form the halo structure is shown. From
here the suggested dose is taken from the dose that form the perfect halo structure. It is
important to determine the right structure as it has an important role for controlling the
Idsat variations. After analyzing the simulation profile, electrical characterization is done
and was compared with the real data measured from the real wafer. The simulation Idsat
value agrees with measured for arsenic 3.3E+13 atom/cm2 in PMOS and boron 1.3E+13
atom/cm2 in NMOS. These doses have been selected as it can give the Idsat value that
can meet and match the Silterra specification target.
4.2
Investigation of Lightly Doped Drain (LDD) Implant in PMOS
and NMOS Device
4.2.1 Simulation Procedure
More implant parameter will be tuned in Lightly Doped Drain (LDD) for PMOS and
NMOS. Besides using different dose and energy, a new species will be introduced to
this process by using BF2 species in order to find out the optimized process for this
implant step. More variation of parameters needs to tune up because this is the critical
implant step for the CMOS process. Figure 4.9 below shows the process flow for this
implant step. First, the standard process for 0.13 PMOS and NMOS with splits at the
Lightly Doped Drain (LDD) step is analyzed. All split ran in the TSUPREM-4 and
MEDICI simulator is also in real wafer fabrication. Then the profile for this device is
plotted and analyzed.
Figure 4.9:
Workflow for experimental procedure
Obtain Silterra’s 0.13 µm Lightly Doped Drain
(LDD) process splits for NMOS and PMOS
Simulate all the PMOS LDD
process splits using TSUPREM-4
Analyzed PMOS LDD doping
profiles from TSUPREM-4
Repeat the step
for NMOS
Simulate using device simulator, MEDICI
Compared and match the measured
data with simulation data
Calculate the best dose to meet
Silterra’s specification target
4.2.2 PMOS Simulation Results
In this section, the work done for PMOS device in optimizing the Lightly Doped Drain
(LDD) implant step is discussed. It will cover the process split using Boron Di-Fluoride
(BF2) species and new BF2 energy process split. The new process using BF2 species,
which has many advantages for PMOS device, will be analyzed and discussed further in
this section.
4.2.2.1
Boron Di-Fluoride (BF2) dose splits
From literature it is known that since the device dimension is scaling down, the use of
p+ polysilicon gate to achieve surface channel PMOS becomes indispensable. The p+
gates surface channel PMOS devices offer the advantages of lower threshold voltage
operation, superior short channel effect, and subthreshold leakage characteristics. On
the other hand, since ultra shallow junction is required, BF2 is often used as the implant
species to achieve self-aligned p+ poly gate MOSFET with shallow junctions. However,
fluorine has been found to enhance the boron diffusion from the polysilicon gate
through thin oxide into silicon substrate. Boron penetration results in the instability of
threshold voltage, the decreasing of low-field mobility, and the increasing of
subthreshold slope and electron trapping rate. Hence, boron-penetration through thin
gate oxide and channel is detrimental to the success of surface channel p-MOSFET. To
prevent the penetration of boron in BF2-implanted p-poly gate MOS device, a coimplant method is used. The appropriate phosphorus dose or arsenic species is used to
retard this penetration. In Silterra process, phosphorus doses has been set high and coimplanted with BF2, so that it can effectively reduce the boron-penetration without
degrading the poly-depletion.
In this section, the work will focus on finding the correct dose and energy for BF2 that
will have a similar manner as boron species used before this new process is
implemented. Table 4.2 shows the implant split table for this work.
Table 4.2:
Dose and energy process split for PMOS LDD implant using Boron Difluoride species.
Lightly Doped Drain (LDD) Implant
Samples
(Splits)
(a) Dose Splits
(b) Energy
Splits
Dose
Energy
(KeV)
Tilt Angle
(0)
BF2-PD1
BF2,
2.8E+14
3.5
7
BF2-PD2
BF2,
2.2E+14
3.5
7
BF2-PD3
BF2,
2.5E+14
3.5
7
BF2-PE1
BF2,
2.8E+14
3.0
7
BF2-PE2
BF2,
2.8E+14
3.5
7
BF2-PE3
BF2,
2.8E+14
4.0
7
Note that BF2 species is compared with boron species, which was used in the earlier
process before BF2 is implemented for PMOS LDD. Boron dose and energy for this
comparison is 2.5E+14 atom/cm2 and 0.7 KeV respectively.
y (µm)
x (µm)
Figure 4.10:
Doping profile for three different BF2 doses, BF2-PD1 (2.2E+14
atom/cm2), BF2-PD2 (2.5E+14 atom/cm2) and BF2-PD3 (2.8E+14
atom/cm2) compared to boron (2.5E+14 atom/cm2).
Figure 4.10 above shows doping profile for three different BF2 doses. This result is then
compared to the current process for PMOS LDD, which is using boron. It can be
observed from this figure that the device implanted with BF2 diffuse laterally compared
to device that is implanted using boron only. Even though BF2 is implanted with much
more higher implant energy, the boron only diffuses laterally and not into the junction.
It proves that fluorine incorporated in LDD implant is suitable for shallow junction
devices. This is supported in literature [37], which states that fluorine implantation with
B+ for PMOS transistor combined with conventional spike annealing, produce reduced
junction depths.
From Figure 4.11 below shows the cut line done on the PMOS device to study the
doping concentration for boron, which plays a major role in this PMOS LDD
implantation. The cut line is done vertically all through the silicon substrate as shown
below.
Cutline 2
y (µm)
x (µm)
Figure 4.11:
Device vertical cut line example; all through the silicon substrate.
Figure 4.12 below shows the result of the vertical cut line done on PMOS. It can be
seen clearly the benefit of introducing fluorine into the implantation step, it will
decrease the boron diffusion into the silicon substrate. The blue line as indicated in this
figure is without fluorine incorporation, which clearly shows boron diffuses
considerably and produces a junction deeper than 250 nm. The addition of co-implanted
fluorine significantly reduces the boron diffusion and creates a more box-like profile.
The junction depth is only 200 nm.
Figure 4.12:
Boron vertical cut line doping profile comparing three different BF2
doses, (a) BF2-PD1 (2.2E+14 atom/cm2), (b) BF2-PD2 (2.5E+14
atom/cm2) and (c) BF2-PD3 (2.8E+14 atom/cm2) compared to boron
(2.5E+14 atom/cm2).
The results from TSUPREM-4 simulators will be the input to the device simulator
MEDICI. Section below will analyze various internal device phenomena such as
potential, charge and current distributions and also device thermal behavior; (threshold
voltage and current-voltage characteristics). Figure 4.13 shows the current flow profile
for PMOS device with different LDD BF2 dose doping and compared to without
fluorine implant. There is a significant change in current flow for high dose and low
dose implant. The right energy must be identified in order to match the characteristics
with the current process that use non-BF2 implant. Hypothesis can be made that the
current flow pattern shows similar manner between BF2 dose BF2-PD1 (2.8E+14
atom/cm2) and the non-fluorine incorporated, boron with 2.5E+14 atom/cm2 dose.
y (µm)
x (µm)
Figure 4.13:
Current flow profile (grey lines) for PMOS device with different LDD
dose, (a) BF2-PD1 (2.2E+14 atom/cm2), (b) BF2-PD2 (2.5E+14
atom/cm2) and (c) BF2-PD3 (2.8E+14 atom/cm2) compared with without
fluorine implant.
To make the results more reliable, cutline profile of the current flow for PMOS device
was done as in Figure 4.14. From the cutline profile in Figure 4.15, it shows how the
non-fluorine implant (blue line) agrees and overlapping with BF-PD1 dose respectively.
This proves that by using BF2-PD1 dose (2.8E+14 atom/cm2), it can give a similar
electrical characteristics manner as the previous process using non-fluorine incorporated
implant. It also gives more advantages to the process development as the fluorine
incorporated implant is proved to have a good advantage over shallow junction devices.
Figure 4.16 shows another cutline profile done at the same place under the gate edge.
This profile shows current density is high for non-corporate fluorine dopant.
Cut line
Current
flow
y (µm)
x (µm)
Figure 4.14:
device.
Current flow vertical cutline example done at the drain of the PMOS
Figure 4.15:
Current flow vertical cutline profile comparing various BF2 dose, (a)
BF2-PD1 (2.2E+14 atom/cm2), (b) BF2-PD2 (2.5E+14 atom/cm2) and (c)
BF2-PD3 (2.8E+14 atom/cm2) with non-fluorine species dose (boron
species).
Figure 4.16:
Current density vertical cutline profile comparing various BF2 dose, (a)
BF2-PD1 (2.2E+14 atom/cm2), (b) BF2-PD2 (2.5E+14 atom/cm2) and (c)
BF2-PD3 (2.8E+14 atom/cm2) with non-fluorine species dose (boron
species).
In order to prove the accuracy of the simulated electrical data with the measured data,
the Idsat accuracy plot is shown in Figure 4.17 below. The critical parameter such as Idsat
has to be constant, as it will affect the performance of the device. It is proven in the
figure below that the suitable dose to match the previous process that use non-fluorine
incorporated implant is at the 2.8E+14 atom/cm2 BF2 dose. The use of BF2 in this step
has proved to have the same effect as the previous process, which used boron in PMOS
LDD step. The usage of BF2 also will not affect any electrical characteristics for this
device. As stated before, the co-implanted BF2 with heavy dose of phosphorus will
reduce the boron-penetration without degrading the poly-depletion effect.
All these results imply that the proper BF2 dose to be used in order to replace the
previous process is the BF2-PD1 (2.8E+14 atom/cm2) dose.
-265
Idsat (uA/um)
-260
-255
-250
Measured
-245
Simulated
-240
2.1E+14 2.2E+14 2.3E+14 2.4E+14 2.5E+14 2.6E+14 2.7E+14 2.8E+14 2.9E+14
PMOS LDD Dose (atom/cm 2)
Figure 4.17:
PMOS LDD dose for 10/0.13 device accuracy plot between measured
and simulated.
4.2.2.2
Boron Di-Fluoride (BF2) energy splits
Since suggested dose to be used for BF2 has been determined, the implant energy for
BF2 has to be analyzed in order to find the right energy. As stated in Table 4.2, 3
different energies will be used in this section, 3.0 KeV, 3.5 KeV and 4.0 KeV.
TSUPREM-4 was run for process simulation analysis. In this section, the comparison
between 3 different energies was made with the current implant process energy that
used boron species with 0.7 KeV implant energy.
Figure 4.18 shows the three different BF2 implant energy compared with boron species
that used 0.7 KeV implant energy. It can be seen clearly that BF2 species used higher
energy, as it is much heavier species than boron. From the analysis plot, it shows that
even BF2 is implanted using much more higher implant energy; the concentration stays
more at the upper part of the transistor source and drain. This profile proves that BF2,
although it is much more heavier and implanted with a high energy than boron, but with
the fluorine incorporation, it will make the boron concentration diffuse laterally. This is
a very important aspect for a shallow junction device that was used today.
In order to strengthen the claim that fluorine incorporation gives great advantages to
device performance, a cutline is done all through the drain to justify this. Figure 4.19
shows PMOS device boron concentration cutline. From this cutline, it proves BF2 gives
great advantage for a shallow device process, as it will stop boron from diffusing further
into the drain. This boron penetration or diffusion will make the electrical
characteristics of the device change, such as shifting Vt and Idsat.
y (µm)
x (µm)
Figure 4.18:
Doping profile for three different BF2 energy, (a) BF2-PE1 (3.0 KeV),
(b) BF2-PE2 (3.5 KeV) and (c) BF2-PE3 (4.0 KeV) compared to boron
(0.7 KeV).
Figure 4.19:
Vertical cutline on boron concentration profile for 3 different BF2
energy, (a) BF2-PE1 (3.0 KeV), (b) BF2-PE2 (3.5 KeV) and (c) BF2-PE3
(4.0 KeV) compared with non-fluorine corporation doping, boron (0.7
KeV).
After characterizing process simulation profile, device simulator, MEDICI will continue
this analysis. Current flow lines will be check in order to match with boron species with
0.7 KeV implant energy. Figure 4.20 shows the current flow and electric potential
profile for PMOS device. It can be seen clearly that the predicted energy to be used in
order to replace boron with BF2 for PMOS LDD implant is by using BF2 with 3.5 KeV
implant energy. The current flow line from BF2 with 3.5 KeV implant energy matches
well with boron profile. This implant energy gives the value that can meet the Silterra
specification target.
y (µm)
x (µm)
Figure 4.20:
Current flow cutline profile and electric potential for three different BF2
energy, (a) BF2-PE1 (3.0 KeV), (b) BF2-PE2 (3.5 KeV) and (c) BF2-PE3
(4.0 KeV) compared with boron (0.7 KeV).
To support this prediction, the total current cutline is done on this device. One cutline is
done just under the gate for each device as shown in Figure 4.21. The reason to do this
cutline is to see which of the split match with the current from 0.7 KeV boron implant
energy. From Figure 4.22, it can be predicted that the best energy that matches well
with the current process using 0.7 KeV boron implant energy is by using 3.5 KeV BF2
implant energy. The 3.5 KeV energy curve is the nearest to the current process. So this
strengthens the prediction to suggest that in order to replace the current PMOS LDD
process with BF2, 3.5 KeV implant energy for BF2 should be used.
The comparison between simulation and measured data is presented in Figure 4.23.
From this plot, the simulated data shows a good agreement with measured data.
Hypothesis can be made that the predicted energy (3.5 KeV) matches well with the
measured data. This energy is suggested to be used as it matches well with the
measurement data and it gives a value that can meet the targeted value in the Silterra
specification.
y (µm)
x (µm)
Figure 4.21:
Total current profile with the vertical cutline under the gate edge for
three different BF2 energy, (a) BF2-PE1 (3.0 KeV), (b) BF2-PE2 (3.5
KeV) and (c) BF2-PE3 (4.0 KeV) compared with non-fluorine
corporation doping, boron (0.7 KeV).
Figure 4.22:
PMOS total current cutline profile with different LDD energy, (a) BF2PE1 (3.0 KeV), (b) BF2-PE2 (3.5 KeV) and (c) BF2-PE3 (4.0 KeV)
compare with boron (0.7 KeV).
-250
Measured
-260
Simulated
Idsat (uA/u m)
-255
-265
-270
-275
-280
-285
2.9
3.1
3.3
3.5
3.7
3.9
4.1
PMOS LDD Energy (KeV)
Figure 4.23:
PMOS LDD energy for 10/0.13 µm device accuracy plot between
measured and simulated data.
4.2.3 NMOS Simulation Results
As the gate length of MOS device is scaled down, issues related to short channel effects
become increasingly important. Some new LDD are designed for better control of short
channel effects and hot carrier injection. Shallow junction is required to control short
channel effects. A simple method is to replace phosphorus with arsenic in LDD implant
for shallow junction. Actually, the reduction of short channel roll-off due to arsenic
LDD cannot compensate the roll-off caused by channel length scaling. On the other
hand, sharper grading, which arises at the edge of arsenic LDD junction, can degrade
hot carrier reliability. Hence profile optimization becomes essential to achieve
performance improvement.
NMOS LDD performance is evaluated by comparing different dose for this implant.
Since NMOS device is widely known as a stable device compared to PMOS,
characterization in order to optimize this process is done just by varying the dose for
LDD implant. As shown is Table 4.3, 2 different arsenic dose is used in order to tune
this process to match with the measured data without disturbing 2D simulation results
and electrical characteristics.
Table 4.3:
Dose process split for NMOS LDD implant using arsenic species.
Lightly Doped Drain (LDD) Implant
Samples
(Splits)
Dose
(atom/cm2)
Energy
(KeV)
Tilt Angle
(0)
As-NLDD1
Arsenic,
1.5E+15
3.5
7
As-NLDD2
Arsenic,
1.3E+15
3.5
7
(a) Dose Splits
From Figure 4.24 below, lightly doped drain structure is clearly visible in the
TSUPREM-4 2D simulation profile. LDD junction will form just at the edge of the
device gate, and under the spacer is the source/drain junction implant. As stated in
literature, this is the cross section of the drain end of an LDD device, showing the
sidewall spacer, the gate overlap length (Lg) and the length of the lightly doped drain
region (Ln-). LDD structure can reduce the maximum electric field along the channel
significantly and can also change the position of the peak lateral electric field. The
lifetime of LDD MOSFET will increased accordingly.
(a) As-NLDD1
(b) As-NLDD2
Gate
Gate
y (µm)
x (µm)
Figure 4.24:
LDD structure
Doping profile for two different arsenic doses, (a) As-NLDD1 (1.5E+15
atom/cm2) and (b) As-NLDD2 (1.3E+15 atom/cm2).
From the figure above, vertical cutline is done just under the gate edge of the NMOS
device. From this cutline, arsenic concentration can be analyzed between these two
different doses. From Figure 4.25, it is clearly shown that there is no significant effect
between this two dose used for this analysis. The higher dose shows higher
concentration and the concentration curve nearly overlap or act similarly at the channel.
This shows that arsenic species doesn’t change much the doping concentration profile.
The correct dose to be used for this implant will be verified in the next analysis.
Figure 4.25:
Vertical cutline under gate for two arsenic concentrations, (a) AsNLDD1 (1.5E+15 atom/cm2) and (b) As-NLDD2 (1.3E+15 atom/cm2).
Since from the Figure 4.25, no suitable dose has been proposed, the MEDICI profile is
analyzed. Figure 4.26 shows the current flow line for two different doses used.
Hypothesis can be made that using different dose can change the pattern of the current
flow lines. Arsenic with a higher dose have a better current flow lines just at the
junction, but using the lower dose arsenic, the flow lines seems to be distorted. Vertical
cutline is done under the gate of the device and plotted as in Figure 4.27. It can be seen
from the plot that can be noted that by using higher dose, it can change the current
density drastically and from this, it can be conclude that the higher dose has a better
performance as it produce a better linear current flow line compared with lower dose.
(a)
(b)
y (µm)
x (µm)
Gate
Source
Gate
Drain
Source
Drain
Figure 4.26:
Current flow line profile for different arsenic dose used, (a) As-NLDD1
(1.5E+15 atom/cm2) and (b) As-NLDD2 (1.3E+15 atom/cm2).
Figure 4.27:
Current flow lateral cutline profile for different NMOS LDD dose, (a)
As-NLDD1 (1.5E+15 atom/cm2) and (b) As-NLDD2 (1.3E+15
atom/cm2).
In order to support the simulated data, the comparison of simulated and measured data
for Idsat comparing both two doses was plotted in Figure 4.28. It can be observed that by
using As-NLDD1 with 1.5E+15 atom/cm2 arsenic doses; the Idsat value is near to the
measured data. It is suggested that best dose to be used in NMOS LDD flow is by using
arsenic with 1.5E+15 atom/cm2 concentrations, as it is also the right dose in order to
meet Silterra specification range.
Idsat (uA/um )
535
530
Measured
525
Simulated
520
515
510
505
500
495
490
1.25E+15
1.3E+15
1.35E+15
1.4E+15
1.45E+15
1.5E+15
1.55E+15
NMOS LDD dose (atom/cm2)
Figure 4.28:
NMOS LDD dose for 10/0.13 µm device accuracy plot between
measured and simulated data.
4.2.4 Summary
The usage of BF2 in PMOS LDD implant step is discussed in this chapter with all the
advantages of using this dopant species is described. The best BF2 energy and dose that
matches well with Silterra specification is recommended for this process. The best
energy is at 3.5 KeV with the dose 2.8E+14 atom/cm2. As for NMOS LDD step,
different arsenic dose is discussed and described. It is recommended that the best dose
to be used is 1.5E+15 atom/cm2 with 3.5 KeV implant energy.
4.3
Investigation of Source/Drain (S/D) Implant in PMOS and
NMOS Device
4.3.1 Simulation Procedure
As stated in the previous chapter, this chapter will discuss source/drain implant in
CMOS device.
The source/drain implantation is a high current, low energy
implantation process. It is probably the last implantation process in the IC chip
fabrication processes. One of the significant differences from the LDD implantation is
that the dosage of the source/drain implantation is much higher, and it is performed
after the sidewall spacer formation. The sidewall spacer separates the heavily doped
source/drain slightly from the channeling area right underneath polysilicon gate and
helps to suppress the hot electron effect. As stated in the previous section, the same
procedure will be done on source/drain implantation process. The same splits will be
ran in the TSUPREM-4 process simulator and also in the real wafer fabricated in
Silterra. The workflow for the procedure is as in Figure 4.29.
Figure 4.29: Workflow of experimental procedure for source/drain process simulation.
Obtain Silterra’s 0.13 µm
source/drain process splits
for NMOS and PMOS
Simulate all the source/drain
process splits using
TSUPREM-4
Analyzed source/drain doping
profiles from TSUPREM-4
Repeat the step
for NMOS
Simulate using
device simulator,
MEDICI
Compared and match the
measured data with simulation
data
Analyzed and find the
optimized source/drain
process
4.3.2 Simulation Results
For source/drain analysis, different boron dose will be tuned to fine the best dose that
should be used for PMOS source/drain implant. In other hand, for NMOS device, the
characterization is only done on tuning up the energy, as it is too difficult to find the
correct energy for arsenic implant. The parameter values that are used in this
characterization is summed up in Table 4.4.
Table 4.4:
Process split for PMOS and NMOS source/drain implant with various
implant parameters.
Samples
(Splits)
PMOS
S/D1
S/D2
S/D3
NMOS
S/D_energy1
4.3.2.1
S/D_energy2
S/D_energy3
Source/drain Implant
Dose
(atom/cm2)
Boron,
2.6E+15
Boron,
2.7E+15
Boron,
2.8E+15
Arsenic,
2.7E+15
Arsenic,
2.7E+15
Arsenic,
2.7E+15
Energy
(KeV)
Tilt Angle
(0)
2.5
7
2.5
7
2.5
7
40
7
45
7
50
7
PMOS Source/Drain Analysis
PMOS device is simulated using TSUPREM-4. The adjust parameter is as shown in
Table 4.4. Boron dose is varied from 2.6E+15 atom/cm2 to 2.7E+15 atom/cm2 and
2.8E+15 atom/cm2. The same energy and tilt angle is used for the splits to eliminate any
effect on these parameters. Energy used in PMOS simulation is 2.5 KeV and implant tilt
angle is at 70. Boron dose is tune up because the electrical characteristics will be
affected if the wrong dose is used. Results obtained from TV2D in TSUPREM-4 are
presented in Figure 4.28 and will be discussed further in analysis section in chapter 5.
Figure 4.30 shows the net doping and depletion region that was plotted using TV2D.
The distribution of doping is quite similar between three doses used but the depletion
region seems to change. At boron dose 2.6E+15 atom/cm2, the depletion region is wider
and this will affect the current flowing at the junction of PMOS device. This will lead to
device degradation, as the I-V characteristics for PMOS device changes. For boron
dosage 2.8E+15 atom/cm2, the doping concentration is concentrated at the channel of
the device as shown in the figure below. The suggested dose to be used in this analysis
is at 2.7E+15 atom/cm2 as the doping profile and depletion is in the right condition. I-V
characteristics will be discussed after the following figure.
y (µm)
(a) 2.6E+15
atom/cm2
(b) 2.7E+15
atom/cm2
(c) 2.8E+15
atom/cm2
x (µm)
Figure 4.30:
Net doping and depletion region line for three different boron doses for
PMOS source/drain process, (a) S/D1 (2.6E+15 atom/cm2), (b) S/D 2
(2.7E+15 atom/cm2) and S/D 3 (2.8E+15 atom/cm2).
After simulating the device, the electrical characterization of the device is analyzed.
Figure 4.31 shows the Id-Vd curve for PMOS device with different dosage used. In this
plot, Idsat value is taken at Vd=1.2 V. Idsat value for different dose for PMOS device is in
the range from 268 µA/µm to 283 µA/µm. This value is slightly higher compared to
Silterra PMOS Idsat typical value. The best dose to be used in this process is predicted
from the closest value of Idsat, which is 254 µA/µm at Vd=1.2 V. This value is for boron
at dose 2.7E+15 atom/cm2. This result also agrees with the simulation result above that
predicts to use boron at this dose. Too high dose or too low will affect the Idsat and will
effect the device performance. It will degrade PMOS device and short channel effect
will occur.
-4.00E-03
Drain Current, Id (uA/um)
-3.50E-03
-3.00E-03
-2.50E-03
-2.00E-03
Boron 2.6E+15 atom/cm2
-1.50E-03
Boron 2.7E+15 atom/cm2
-1.00E-03
Boron 2.8E+15 atom/cm2
-5.00E-04
0.00E+00
0
-0.5
-1
-1.5
-2
-2.5
Drain Voltage, Vd (V)
Figure 4.31:
Id-Vd curve for PMOS source/drain implant process with different
dosage used for this process, (a) S/D1 (2.6E+15 atom/cm2), (b) S/D 2
(2.7E+15 atom/cm2) and S/D 3 (2.8E+15 atom/cm2).
These results will be clarified by comparing simulation data with the real silicon data
measured in Silterra. Figure 4.32 shows the comparison plot. At boron dose 2.7E+15
atom/cm2, the percentage difference for simulation and measured data is only 0.08%.
This is the lowest percentage error compared with the other doses, 2.6E+15 atom/cm2
and 2.8E+15 atom/cm2, which have 0.13% and 0.18% respectively.
-213
Measured
Idsat (uA/um)
-212.5
Simulated
-212
-211.5
-211
-210.5
1
-210
-209.5
-209
2.55E+15 2.60E+15 2.65E+15 2.70E+15 2.75E+15 2.80E+15 2.85E+15
2
PMOS Source/Drain dose (atom/cm )
Figure 4.32:
PMOS S/D dose for 10/0.13 µm device accuracy plot between measured
and simulated data.
From the percentage error values, suggestion can be made to use boron for PMOS
source/drain implant with the dose 2.7E+15 atom/cm2 as it is also the dose that can meet
the Silterra specification range. It can be noticed that the Idsat value for 2.7 E+15 is low
compared to the other doses. In this case, it can be concluded that there is no significant
effect can be seen within a 1% percentage error.
4.3.2.2
NMOS S/D Analysis
For NMOS source/drain implantation process, different arsenic implant energy is used.
Three splits are done for this step, which are 40, 45 and 50 KeV. In this splits, the
arsenic dose and tilt angle used is at 4.72E+15 atom/cm2 and 70 respectively. This is the
normal condition for NMOS source/drain implant step. Tilt angle can gives significant
difference to the value of Idsat and threshold voltage, which will be discussed further in
this work.
The same procedure to run this experiment for source/drain splits is implemented. The
process simulation in TSUPREM-4 is run using the same process recipe as in the
process running in Silterra fab. For electrical characterization, MEDICI is still used in
order to plot the I-V characteristics. These results will then be clarified with the
measurement silicon data.
Figure 4.33:
Current flow profiles for 0.13 µm NMOS device with 3 different
source/drain implant energy, (a) S/D_energy1 (45 KeV), (b)
S/D_energy2 (50 KeV) and S/D_energy3 (40 KeV).
Figure 4.33 above shows the current flow profile for 0.13 µm NMOS device with
different implant energy applied. The similar trend of current flow is shown here. There
is a slightly small difference between those three energies used. For arsenic with
implant energy 50 KeV, the simulation shows that there is a huge current flowing at the
device drain. But for 40 and 50 KeV, the current flow line looks smaller. This is also
proved by the current density cutline profile that is done along the poly gate as in Figure
4.34. It can be noted here that only small differences can be detected when different
energy is varied for source/drain implant.
Figure 4.34:
Current density cutline profiles for 0.13 µm NMOS device with 3
different source/drain implant energy, (a) S/D_energy1 (45 KeV), (b)
S/D_energy2 (50 KeV) and S/D_energy3 (40 KeV).
The prediction of which implant energy that should be used for NMOS source/drain
process will further be analyzed by looking at the I-V characteristics that was simulated
using MEDICI.
Drain Current, Id (uA/um)
8.00E-03
7.00E-03
6.00E-03
5.00E-03
4.00E-03
3.00E-03
40 KeV
2.00E-03
45 KeV
1.00E-03
50 KeV
0.00E+00
0
0.5
1
1.5
2
Drain Voltage, Vd (V)
Figure 4.35:
Drain current, Id versus drain voltage, Vd for NMOS device simulated
using MEDICI for 3 different implant energy, (a) S/D_energy1 (45
KeV), (b) S/D_energy2 (50 KeV) and S/D_energy3 (40 KeV).
Figure 4.35 above shows the simulated drain current versus drain voltage (Id vs Vd)
plots. In this plot, Idsat value can be determined and will be compared with measurement
data. Idsat value is taken at Vd=1.2 V. In this experiment, the value of Idsat varied from
570 µA/µm to 623 µA/µm. This value for Idsat is still in the Silterra NMOS Idsat range,
which is (455 µA/µm – 635 µA/µm). Idsat value for 50 KeV is slightly out of the range,
which it is assume that this device that was simulated is catastrophic. This is because,
Idsat will play a major role in determining the device performance, and if the Idsat is too
high, it will results in device degradation. Conclusion can be made that the best
source/drain implant energy that can be used for NMOS is between 40 and 45 KeV. The
Idsat value for this two energy is 507 µA/µm and 603 µA/µm respectively.
To further clarify this problem, the comparison of Idsat between simulation and
measurement is presented in Figure 4.36. In this figure, the correct energy for
source/drain process can be suggested. The best energy shall be determined by the
percentage error between simulation and measurement. Simulation data must agree with
measurement data in order to implement this suggestion in the real process. From this
figure, the percentage error for 40 and 45 KeV is 0.32% and 0.15% respectively. From
this error, suggestion to used 45 KeV implant energy for source/drain can be verified.
574
572
Idsat (uA/um)
570
568
566
564
562
560
Measured
558
Simulated
556
39
41
43
45
47
49
51
NMOS S/D Energy (KeV)
Figure 4.36:
NMOS S/D energy for 10/0.13 µm device accuracy plot between
measured and simulated data.
4.3.3 Summary
In this section, the source/drain implant process has been discussed thoroughly. For
PMOS device, implant dose is varied to tune and find the optimum dose for this step.
The suggested dose to be used for PMOS source/drain step is 2.7E+15 atom/cm2. For
NMOS device, a split is done on various implant energy. From the results shown above,
it is suggested to used implant energy at 450. The best S/D implant dose and energy that
suggested here, is the one that meets Silterra specification target.
CHAPTER 5
ANALYSIS AND DISCUSSION
5.1
Introduction
This chapter explains the complex results obtained in Chapter 4 in terms of basic
principles. The first section will cover halo implant for PMOS and NMOS transistors.
Discussion of the lightly doped drain (LDD) for PMOS and NMOS transistor will be in
the second section and the last section will analyze the source/drain implant for PMOS
and NMOS.
5.1.1 Analysis and Discussion of Halo Implant Experiment results in
PMOS and NMOS Transistors
A process called “pocket implant” or “halo implant” was introduced in 1985 [50]. The
halo implant is a quad implant that creates a high doping concentration in the channel
near the source/drain junctions. This process improves the short channel performance of
deep submicron MOSFETs. It is widely used to reduce Vt roll-off and punch-through
[40]. But if the dose is too high, it will cause undesirable reverse short channel effect
(RSCE) [41]. Hence, careful tuning of the halo implant parameters is always necessary
in order to obtain the desired electrical performance. PMOS and NMOS halo implant
effects will be explained in this section including simulated and measured TSUPREM-4
profiles and electrical characterization.
5.1.1.1
PMOS Transistor
The purpose of this section is to explain how halo implant parameters influence the
performance of a 130 nm physical gate length PMOSFET. The dose, tilt angle and
implant energy will effect the Vt roll-off and drain saturation current, Id. As in literature,
halo implant is employed in the advanced “conventional” MOSFETs in order to
improve the transistor performance. This halo dopant species is introduced only in a
selected local region; namely at the edge of the drain-extension region.
Figure 5.1:
Two different transistors size with halo implant. It is shown here that
when the gate length becomes small, the two halo implants will overlap
and therefore Vt will increase. This is called the “reverse” short channel
effect, RSCE. Normally (without halo) Vt should decrease when the gate
length becomes smaller.
As shown in Figure 5.1, halo can affect Vt and Vt roll off when the gate length is small.
Halo will overlap each other and increase Vt. In other hand, halo will have very little
effect on Vt in a large gate length transistor. Figure 5.2 shows the relation of Vt with
gate length. As the gate length is reduced, the two halo implants will start to overlap on
each other and Vt will roll up. Eventually, Vt will roll off as the punchthrough effect
comes into play, where LDD implants start to overlap on each other.
Vt
Left and right
halo overlap
(double dose)
Begin
punchthrough
Gate Length, L
Figure 5.2:
Threshold voltage, Vt versus gate length. This shows the effect of halo to
Vt with a different gate length.
Next, the effect of halo on junction capacitance will be briefly discussed. Figure 5.3
shows junction capacitance, Cj, value that changes due to different depth of halo
implant. Halo will increase Cj value a lot if halo is deeper than source/drain implant. For
halo that is shallower, Cj value is not affected.
Gate
Source
Cj
Drain
Deep halo
Shallow halo
Cj
P-sub
Figure 5.3:
Transistor with different halo depth. Note that for a shallower halo,
junction capacitance, Cj will not be affected. For halo deeper than
source/drain implant, Cj will increase.
Table 4.1 in the previous chapter gives the arsenic halo implant dose splits for PMOS
transistors. In this section, further analysis has been made to analyze and find the effect
of this dose to the transistor performance. It can be observed from Figure 5.4, which is
the simulated Vt roll-off curve for different doses used in PMOS halo, that too much
halo implant dose will produce excessive RSCE, which is undesirable for circuit design.
-0.5
RSCE
Threshold Voltage (Vt)
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
As 3.3E+13 atom/cm2
As 3.1E+13 atom/cm2
As 3.5E+13 atom/cm2
-0.1
-0.05
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Drawn Gate Le ngth (um)
Figure 5.4:
PMOS halo Vt roll-off curve for different arsenic doses, (a) HaloPD1
(3.3E+13 atom/cm2), (b) HaloPD2 (3.1E+13 atom/cm2) and (c) HaloPD3
(3.5E+13 atom/cm2). The bumps in the curve happen because each point
is simulated with different gate length, so it is a grid or numerical error.
Figure 5.5 below shows threshold voltage (Vt) that was measured using a tester (Agilent
4072 and Keithley S680) and prober (Tokyo Electron Limited, TEL P-8 and Electro
Glass, EG). In this plot, with lower halo dose, Vt is roll-off speedily as the channel
lengths become shorter. Here, the Vt is defined as the gate voltage, Vg, at which the
drain current, Id, reaches 0.1 µA per µm of gate width. Although the Vt roll-off can be
improved at higher halo implant dose, nevertheless such a high Vt will not meet the
performance requirements. With halo implant dose 3.3E+13 atom/cm2, it can effectively
improve Vt roll-off and hold the threshold voltage at about 0.38 V, which is desirable
for 0.13 µm transistors.
Figure 5.5:
Measured PMOS threshold voltage (Vt) curve for 10/0.13 µm transistor.
Measured data and Simulation Program with Integrated Circuit Emphasis
(SPICE) model are shown.
Table 5.1 shows the threshold voltage (Vt) value for measured data and simulated data
for the same wafer that is run with the same recipe.
Table 5.1:
Threshold voltage simulated using MEDICI and measured value for
different PMOS halo implant dose at L=0.13 µm.
Doses
Measured
threshold voltage,
Vt (V)
Simulated
threshold voltage,
Vt (V)
3.1E+13
atom/cm2
3.3E+13
atom/cm2
3.5E+13
atom/cm2
0.376
0.387
0.409
0.301
0.393
0.433
Threshold voltage (V t)
0.5
0.45
0.4
0.35
0.3
Measured
0.25
Simulated
0.2
3E+13
3.1E+13
3.2E+13
3.3E+13
3.4E+13
3.5E+13
3.6E+13
PMOS halo dose (atom/cm2)
Figure 5.6:
Measured and simulated PMOS threshold voltage, Vt for three different
halo doses. The smallest difference is seen at halo dose 3.3E+13
atom/cm2.
It can be seen in Figure 5.6, the measured value for arsenic with 3.3E+13 atom/cm2
implant dose are in good agreement with the simulated value using MEDICI.
Percentage error between these two values is 1.5%. This value is suggested as it is the
right dose that can meet the specification target.
There are 3 independent input parameters; dose, tilt angle/rotation and energy. Above
studies are based on a single variable, implant dose. The other 2 variables implant tilt
angles/rotation and implant energy have also been studied. It is assumed that the
variables are independent (no interactions) in this work, so only single-variable
experiments are implemented. Figure 5.7 shows Vt roll-off curve for different halo
implant energy. This split only ran on 2 energy splits, 90 and 110 KeV, in the real wafer
fabrication process. For simulation, 70 KeV is introduced to see the effect of the halo
using the lowest implant energy. This curve has a similar trend to the dose splits. In this
experiment, the best energy to meet the Vt target as in Silterra’s specification is at 90
KeV. This is because by using 90 KeV energy, threshold voltage value obtained is in
Silterra specification range. This is the desired threshold voltage for this device as
higher Vth value may affect the device performance. The summary for energy tuning is
shown is Table 5.2 and the comparison graph between measured and simulated is
plotted in Figure 5.8. The evaluations are continued by tuning the tilt angle to see how it
can affect the Vt for the transistor.
Threshold voltage (Vth)
-0.35
70KeV
90KeV
110KeV
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Drawn Gate Length (um)
Figure 5.7:
PMOS Vt roll-off for different halo implants energy, 70, 90 and 110
KeV.
Table 5.2:
Measured and simulated data for Vt with different PMOS halo implant
energy at L=0.13 µm.
Implant Energy
70 KeV
90 KeV
110 KeV
Measured threshold
voltage, Vt (V)
Not Available
0.254
0.300
Simulated threshold
voltage, Vt (V)
0.230
0.248
0.296
It can be seen in this plot that the simulation data is far off from the measured value.
Measured Vt value for 70 KeV is not available in Silterra split table obtained. In spite of
that, the Vt trend can be seen in the plot. As the implant energy is increased, Vt value is
also increased.
0.34
Threshold voltage (V t)
0.32
0.3
0.28
0.26
0.24
Measured
Simulated
0.22
0.2
60
70
80
90
100
110
120
PMOS halo implant energy (KeV)
Figure 5.8:
Measured and simulated PMOS threshold voltage, Vt for different halo
implants energy, 70, 90 and 110 KeV.
As for different tilt angle splits, Vt data that obtained from measurement is compared
with simulation data. Table 5.3 shows the Vt measurement for halo implant with
different tilt angle. By using different tilt angle, it gives no significant change of the
threshold voltage. As for simulated data, the same trend is shown. There is only a small
change in threshold voltage for each tilt angle used as shown in Figure 5.9.
Table 5.3:
Measured and simulation data for Vt with different halo implant tilt angle
at L=0.13 µm.
Tilt Angle (0)
Measured
threshold voltage,
Vt (V)
Simulated
threshold voltage,
Vt (V)
20
25
30
0.288
0.285
0.281
0.261
0.259
0.251
Threshold voltage (V t)
0.34
Measured
0.32
Simulated
0.3
0.28
0.26
0.24
0.22
0.2
18
20
22
24
26
28
30
32
0
PMOS halo tilt angle ( )
Figure 5.9:
Measured and simulated PMOS threshold voltage, Vt with different halo
implants tilt angle 200, 250 and 300 with rotation=0.
Figure 5.9 above shows the difference of threshold voltage, Vt between measured and
simulated. The difference between the measured value and simulated value is in the
range of 9%. The trend for this work can be seen, as the halo implant tilt angle is
increased, Vt value will decrease. This is because as the tilt angle decreased, the halo
will be formed too far away from the channel. This will not affect the Vt value. In other
hand, if too high tilt angle is used, halo will form too close to the channel, thus effecting
Vt value. This can be illustrated clearly in Figure 5.10.
Figure 5.10 shows different implant tilt angle that can affect transistor threshold
voltage, Vt. It is shown here that too high tilt angle for example, 800 will make the halo
formed too close to the channel. For too low tilt angle, the halo will form too far away
from the channel. When the halo is form too far from the channel, it will not give any
effect to the transistor.
Figure 5.10:
Transistor with different halo implant tilt angle and rotation=0. Normal
tilt is at 300.Too high tilt angle (800) resulting halo forming too close to
the channel. Too low tilt angle (50), halo is too far from the channel.
The structure is then characterized by using TV2D in TSUPREM-4. The results are
shown in Figure 5.11 and 5.12. There are significant changes that can be seen at the
PMOS channel when low tilt angle (200), medium tilt angle (250) and high tilt angle
(300) are used. The doping concentration spreads all over the channel as this can effect
the current flowing, as the main purpose of halo implant is to stop the leakage current
from drain to source when the transistor is off.
From this figure, it is shown that at a higher tilt angle value, resist shadowing problem
occurs. The halo implant can’t form perfectly at the channel. The halo overlaps each
other in the channel. This can be explained from Figure 5.13, which explains more
about the resist shadowing problem.
y (µm)
x (µm)
Figure 5.11:
PMOS net doping profile for different implant tilt angle (200, 250 and
300).
y (µm)
x (µm)
Figure 5.12:
PMOS halo doping profile for different implant tilt angle, (200, 250 and
300). The halo formed too closed to the channel when the implant tilt is
too high and halo is too far from the channel when the implant tilt angle
is too low.
Figure 5.13:
Transistor showing resists shadowing problem. Noted that if the tilt
angle is larger than 270, there will be no halo in the transistor. Photoresist
thickness is 0.60 µm and space from gate is 0.30 µm.
Figure 5.13 above shows the resist shadowing effect that happens when ions is
implanted on a transistor. Before implant, photoresist is used to block any implant to be
implanted in the wrong place. High-energy implant requires thick photoresist to mask
the penetration of high-energy ions. In most cases, the ion will be implanted into a
wafer at a tilt angle to minimize channeling. It is common practice to implant with 70
tilt angle, with 20 degrees rotation to avoid dopant channeling. However, halo implant
must be done with a larger angle so shadowing from photoresist will not be a potential
problem. As in the figure above, the shadowing creates shadow region at the channel. If
tilt angle is larger than ~270, there will be no halo in the transistor. Table 5.4 below
summarizes halo effect on Vt and Id for PMOS.
Table 5.4:
Effects of halo implant parameters on threshold voltage, Vt and saturated
drain current, Id for PMOS.
Implant Parameters
Threshold voltage, Vt
Saturated Drain
Current, Id
Higher dose
Higher
Lower
Higher implant energy
Higher
Lower
Larger tilt angle
Higher
Lower
5.1.1.2
NMOS Transistor
Extensive studies of varying implant dose, tilt angle and energy have also been taken
for NMOS transistors. The experiments were single variable, without combinations. As
stated in Table 4.1 in chapter 4, three different Boron doses are used for characterizing
NMOS transistors. Figure 5.14 shows the simulated Vt roll-off curve when different
dose is used to tune NMOS halo implant process.
0.45
Threshold Voltage (V)
0.4
0.35
0.3
0.25
0.2
0.15
Boron 1.0E+13
0.1
Boron 1.3E+13
0.05
Boron 1.6E+13
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Drawn Channel Length (um)
Figure 5.14:
NMOS Vt roll-off for three different halo implant doses, (a) HaloND1
(1.0E+13 atom/cm2), (b) HaloND2 (1.3E+13 atom/cm2) and (c)
HaloND3 (1.6E+13 atom/cm2).
NMOS halo implant dose shows results similar to PMOS halo implant. Higher dose will
lead to higher threshold voltage; Vt. Too high dose can make the halo catastrophic and
will lead to RSCE and junction leakage. Too much halo dose will not only make the
junction leak, but will produce low breakdown voltage or band-to-band tunneling also
called Zener effect leakage. This can be illustrated in Figure 5.15 below.
Figure 5.15:
(a)
(b)
High dose halo doping on a PMOS transistor, (a) breakdown voltage
versus doping concentration [51] and (b) band-to-band tunneling or
Zener effect leakage [51].
In this case, by using boron with 1.3E+13 will give the Vt that is closest to the target of
Silterra specifications. Figure 5.16 shows the measured silicon data. In this plot,
1.3E+13 atom/cm2 boron will have the Vt value closest to the Silterra target. The
comparison between these two data is shown in Table 5.5.
NMOS Threshold Voltage (Vth @
VD=0.1V)
0.38
Vtlin_HP(1.0E+13)
0.36
Vtlin_HP(1.3E+13)
0.34
Vtlin_HP(1.6E+13)
0.32
0.3
0.28
0.26
0.24
0.22
0.2
0.1
Figure 5.16:
1
Length (um)
10
Measured NMOS Vt roll-off for different halo implants doses, (a)
HaloND1 (1.0E+13 atom/cm2), (b) HaloND2 (1.3E+13 atom/cm2) and
(c) HaloND3 (1.6E+13 atom/cm2).
As in Table 5.5, it is shown that the measured silicon data for 1.3E+13 atom/cm2 boron
is comparable with the simulated data. The percentage difference is only 1.76%
compared to other dose that is used in this experiment.
Table 5.5:
Measured and simulation data for Vt with different NMOS halo implant
dose at L=0.13 µm.
Doses
1.0E+13 atom/cm2
1.3E+13 atom/cm2
1.6E+13 atom/cm2
Measured threshold
voltage, Vt (V)
0.320
0.341
0.364
Simulated threshold
voltage, Vt (V)
0.310
0.335
0.347
Threshold voltage, (V t)
0.41
0.39
0.37
0.35
0.33
0.31
Measured
0.29
Simulated
0.27
0.25
9.0E+12 1.0E+13 1.1E+13 1.2E+13 1.3E+13 1.4E+13 1.5E+13 1.6E+13 1.7E+13
2
NMOS halo dose (atom/cm )
Figure 5.17:
Measured and simulated NMOS threshold voltage, Vt with different halo
implants dose, HaloND1 (1.0E+13 atom/cm2), HaloND2 (1.3E+13
atom/cm2) and HaloND3 (1.6E+13 atom/cm2).
In order to fine-tune the halo step, halo implant tilt angle splits and halo implant energy
splits are also tuned accordingly on NMOS transistors in single-variable experiments.
The results for NMOS transistor are similar to PMOS transistor. Figure 5.18 shows the
simulated Vt roll-off for different NMOS halo implant energies, while Table 5.6 shows
measured and simulated threshold voltage, Vt values for different implant tilt angles and
implant energies.
Table 5.6:
Measured and simulation data for Vt with different NMOS halo implant
energy at L=0.13 µm.
Implant Energy
10 KeV
12 KeV
15 KeV
Measured threshold
voltage, Vt (V)
0.311
0.338
0.357
Simulated threshold
voltage, Vt (V)
0.313
0.369
0.374
Threshold voltage (V t)
0.39
0.38
0.37
0.36
0.35
0.34
0.33
0.32
Measured
0.31
Simulated
0.3
9
10
11
12
13
14
15
16
NMOS halo implant energy (KeV)
Figure 5.18:
Measured and simulated NMOS threshold voltage, Vt with different halo
implant energy, 10, 12 and 15 KeV.
As shown in figure above, the average percentage difference between simulated and
measured value is 4.86%. The best implant energy to match with the targeted
specification is at 10 KeV with the smallest percentage difference (0.64%) . Figure 5.19
below shows the simulated threshold voltage that is obtained from MEDICI simulator.
0.4
Threshold voltage (V)
0.38
0.36
0.34
0.32
0.3
0.28
10 KeV
0.26
12 KeV
0.24
15 KeV
0.22
0.2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Drawn Channel Length (um)
Figure 5.19:
Simulated NMOS Vt roll-off for different halo implants energy, 10, 12
and 15 KeV.
Table 5.7 shows the measurement and simulation data for NMOS halo with different
implant tilt angles. The average percentage difference between simulation and
measurement value is slightly bigger with the difference of 7.11%. The data is tabulated
in Figure 5.20. The expected value that can match with the specification is at 250, which
have 5% percentage difference.
Table 5.7:
Measured and simulation data for Vt with different NMOS halo implant
tilt angle at L=0.13 µm.
Tilt Angle (0)
15
25
35
Measured threshold
voltage, Vt (V)
0.288
0.320
0.351
Simulated threshold
voltage, Vt (V)
0.311
0.339
0.377
Threshold voltage (V t)
0.43
0.41
0.39
0.37
0.35
0.33
0.31
0.29
Measured
0.27
Simulated
0.25
12
17
22
27
32
37
0
NMOS halo tilt angle ( )
Figure 5.20:
Measured and simulated NMOS Vt roll-off for different halo implants tilt
angle, 150, 250 and 350. This shows that larger tilt angles increase the
threshold voltage.
In this section, simulated results of how the halo implants doses, tilt angles and energy
influences the characteristics of sub-micron MOSFET is reported. The conclusion is
that properly tuned halo implant can effectively suppress the short channel effect (SCE)
in MOSFETs with 130 nm physical gate length and maintain the desired level of
threshold voltage. Measured data have been taken to compare with this simulation data
and the results are summed up in tables at the end for each section.
5.1.2 Analysis and Discussion of Lightly Doped Drain (LDD) Implant
in PMOS and NMOS Transistor
Lightly doped drain (LDD) is another commonly used structure that can reduce hot
electron problems in sub-micron transistors by lowering the peak longitudinal electric
field.
We can form the LDD junction by using low energy, low current ion
implantation. It is a shallow junction with a very low dopant concentration, extended
just underneath the gate. In this section, PMOS and NMOS LDD structures will be
analyzed further from the results obtained in chapter 3. Simulated data will be compared
with measured silicon data for verification.
5.1.2.1
PMOS Transistor
As stated in Figure 4.3 in chapter 4, dose split and energy split has been done for PLDD
process in order to meet the Id and Vt specification targets. Before using boron difluoride (BF2) as indicated in Figure 4.3, previous process used boron for this step. In
this section, PLDD species changes from boron to BF2 will be further analyzed. It is
reported that, to achieve higher throughput and better negative bias temperature
instability (NBTI) lifetime, BF2 species usage is promising [52].
Figure 5.21:
Threshold voltage, Vt for 1.2 V 10/0.13 µm PMOS LDD for boron difluoride (BF2) and boron (B11). This shows that B11 and BF2 can
produce very similar Vt.
The comparison of threshold voltage between boron (B11) and boron di-fluoride (BF2)
is shown in Figure 5.21. There is almost no difference between using boron in the
former process and by using BF2 in the current process. Threshold voltage for 1.2 V
PMOS 10/0.13 µm for both BF2 and boron are quite similar. The analysis will go
further in investigating the difference of using BF2 and boron. Figure 5.22 shows the
zoom-in for threshold voltage value between BF2 and boron species. It can be seen
clearly that ~5 mV lower threshold voltage is observed for BF2 implant. From this,
conclusion can be made that different species (BF2 and boron) did not give much effect
on threshold voltage. BF2 can be used to replace boron species in PMOS LDD process
as it can give many advantages as well as disadvantages to the transistor performance.
Silterra is changing the process technology from boron to BF2 is PMOS LDD step in
order to reduce Negative Bias Temperature Instability (NBTI) effect and BF2 is useful
to form ultra-shallow junction in small-scale device. The boron penetration effect that
happen when BF2 is applied can be stop by co-implanting BF2 with higher dose of
phosphorus. This is done to retard the boron penetration thus eliminating the device
degradation effect.
Table 5.8:
Advantages and disadvantages of BF2 implant in CMOS transistor.
Advantages
1
Improves NBTI performance [52].
2
Reduces oxide leakage current in
polyoxide [53].
Used for ultra-shallow junction
formation [54].
3
Figure 5.22:
Disadvantages
Formation of silicide is worse on BF2
implanted surface [52].
Junction leakage is generally higher
for BF2 implanted surface [52].
Enhances boron diffusion into
SiO2/Si [30].
Threshold voltage, Vt difference for 1.2 V 10/0.13 PMOS for both boron
di-fluoride (BF2) and boron (B11). The difference is about 5 mV.
To continue the analysis, Idsat is measured from the wafer and was plotted box plot as in
Figure 5.23 for 10/0.13 µm PMOS. It is shown in this plot that Id values between this
two species have the same characteristics. Analysis goes further and found that a
marginal of (~ 4 µA/µm) degradation of Idsat observed on changing thin PLDD species
from boron to BF2 as shown in Figure 5.24. This is also assumed to be a minor impact
on the saturation drain current and it will give no big effect on the transistor. Conclusion
can be made that the used of BF2 will be implemented in current PLDD process and as
many wafers have been evaluated, the results obtained are excellent.
Figure 5.23:
Saturation drain current, Idsat for 1.2 V 10/0.13 PMOS for both boron difluoride (BF2) and boron (B11). The average difference between BF2 and
B11 is only 4 µA.
After determination of BF2 usage as the standard species in PLDD process, simulation
of different dose and energy of BF2 is done as in Section 4.2.3 in chapter 4. Results and
analysis has been done and the best dose and energy that meets the specification target
is already determined as in previous chapter.
Figure 5.24:
Idsat comparison for 1.2 V 10/0.13 PMOS for both BF2 and boron. It can
be noted Idsat degrades (~ 4 µA/µm) after changing to BF2 species.
5.1.2.2
NMOS Transistor
Since in the measured silicon data, only two splits were done on NLDD, simulation is
done on different implant energy and implant tilt angle in order to see any effect that
can change the transistor performance by tuning these parameters. In chapter 4, it had
been shown that the arsenic splits for NMOS LDD implant can change the current flow
line and furthermore, it will affect the drain current, Id, for the transistor. The best dose
to meet the spec target is 1.5E+15 atom/cm2.
In this analysis, tilt angle and energy will be tuned by using the TCAD simulator and
the threshold voltage obtained for these splits shall be analyzed in order to find the right
tilt angle and implant energy that should be used in this process. The splits that have
been done are shown in Table 5.9.
Table 5.9:
Tilt angle and energy splits for NMOS transistor simulation using
TCAD. Fixed parameters: dose at 1.5E+15 atom/cm2, rotation = 0
degrees.
Samples
(Splits)
Tilt Angle (0)
0
3
7
Energy (KeV)
2
3
4
Figure 5.25 below shows the Vt roll-off curve for different tilt angles used in the NMOS
LDD process. From this graph, the best tilt angle can be predicted according to the
threshold voltage value obtained. The higher the tilt angle causes Vt to shift up and can
cause degradation to the transistor performance. The best tilt angle that is matched with
Silterra specification is by using 70 tilt angle. This result is further verified by the
existing works [30], which stated that larger tilt angle of LDD implant should be
adopted to get reduced parasitic capacitance and enhanced transistor performance, but
with a proper dose adopted.
Threshold voltage (V)
0.5
0.45
0.4
0.35
0.3
0 degree
3 degree
0.25
7 degree
0.2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Drawn Channel Length (um)
Figure 5.25:
Simulated NMOS Vt roll-off for different LDD implants tilt angle, 00, 30
and 70. Higher angle causes higher Vt.
0.4
Threshold voltage (V)
2 KeV
3 KeV
0.35
4 KeV
0.3
0.25
0.2
0.15
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Drawn Gate Length (um)
Figure 5.26:
Simulated Vt roll-off curves comparing 3 different implant energy used
for NMOS LDD process, 2, 3 and 5 KeV. Higher energy causes higher
Vt.
From Figure 5.26 above, 3 different implant energies are used to tune the LDD process.
In this work, 2, 3 and 4 KeV implant energies are used. From the Vt roll-off curve, it is
clearly shown that the Vt value shifts tremendously when 4 KeV energy is used to
implant arsenic to create an LDD channel. Too high energy can degrade the transistor
performance [29]. At higher arsenic LDD implantation energies, deep source/drain
junction regions were locally implanted with arsenic, resulting in larger junction depth.
In this study, the best LDD NMOS implant energy should be used is in between 3 to 4
KeV. Too low energy resulting in Vt value did not match with the Silterra specification.
In this case, my conclusion is to use 3 KeV implant energy as it can give Vt value 0.28
V for L=0.13 µm, which is in the Silterra’s specification range of Vt for NMOS
(Min=0.27 V, Typ=0.33 V, Max=0.40 V).
5.1.3 Analysis and Discussion of Source/Drain (S/D) Implant in PMOS
and NMOS Transistor
Source/drain implant is commonly known also as highly doped drain (HDD) implant. It
is implanted after the sidewall spacers step. Sidewall spacers will be used alongside the
poly gates to prevent the higher source/drain (S/D) implant from penetrating too close
to the channel where S/D punch through could occur. In order to complement the
retrograde well implant techniques, medium-dose implants are made to penetrate the
silicon slightly beyond LDD junction depth, but not as deep as the original twin-well
implants. Retrograde well is an approach to well formation in CMOS structures; highest
concentration of dopant (implanted) in the well is located at a certain distance from the
surface. The result is a denser circuit and less susceptible to latch-up. The objective of a
retrograde well is to get a minimum doping in the channel, so that better mobility
caused by less collisions can be achieved. It also can stop the punchthrough effect. In
the S/D implant step, the spacer oxide from the previous step will protect the channel
from the dopant atoms during the implant process.
5.1.3.1
PMOS Transistor
S/D implant is a medium energy implant step that penetrates the silicon deeper than the
LDD junction depth. Spacer oxide prevents the boron dopant that is used in PMOS
transistor from encroaching into the channel. For PMOS source/drain analysis, as
shown in Table 4.4 in chapter 4, boron dose is split into 3 experiments: 2.6E+15
atom/cm2, 2.7E+15 atom/cm2 and 2.8E+15 atom/cm2. Different dose of boron can give
a slight impact on Idsat (as shown in chapter 4) and in threshold voltage, Vt that is be
discussed in this chapter. The main effect is on the sheet resistance of the source and
drain.
In analyzing source/drain implant, all the other implants (Vt adjust implant, halo and
LDD) are included. Simulation results in Figure 5.27 below show with the help of Vt
implant and the correct dose of halo implant, indicates that the source/drain implant
dose can be correctly determined.
From this result, it is suggested to use boron at 2.7E+15 atom/cm2 dose. Although the Vt
value looks significantly higher compared to the other two doses, but at this dose only
the Vt value is comparable to Silterra’s specification. The existence of halo/pocket
implant can act as a stopper that effectively resists the punchthrough from drain to
source.
-0.35
Threshold voltage (V t)
Boron 2.6E+15 atom/cm2
Boron 2.7E+15 atom/cm2
-0.3
Boron 2.8E+15 atom/cm2
-0.25
-0.2
-0.15
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Drawn Gate Length (um)
Figure 5.27:
Simulated Vt roll-off curve comparing 3 different implant doses used for
NMOS S/D process, 2.6E+15 atom/cm2, 2.7E+15 atom/cm2 and 2.8E+15
atom/cm2.
The sidewall of LDD region is not surrounded by n-type dopant, thus less p-dopant is
compensated. Source/drain series resistance does not increase much and the transistor
will suffer less current degradation. On the other hand, the depth of p-extension region
is typically less than half of the source/drain junction depth and contributes less to short
channel because the depletion region in the vertical direction has no impact on short
channel effect as shown in Figure 5.28. At the overlap region where PMOS S/D and nhalo implant meet, the concentration of the n-region is 2 to 3 orders of magnitude lower
than that of p+ region. Then at S/D, compensation by n-halo is not significant and the
increase in parasitic S/D junction capacitance is negligible, which would otherwise be a
serious problem.
(a)
(b)
Gate
Gate
y
(µm)
x
(µm)
Depletion
region
1) Boron 2.7E+15 atom/cm2
Gate
Gate
y
(µm)
x
(µm)
Depletion
region
2) Boron 2.6E+15 atom/cm2
Gate
y
(µm)
x
(µm)
Gate
Depletion
region
3) Boron 2.8E+15 atom/cm2
Figure 5.28:
Simulated PMOS structure showing (a) net doping profile and depletion
region and (b) electric potential and current flow lines for three different
S/D implant doses.
5.1.3.2
NMOS Transistor
The steps of creating the NMOS source/drain region are similar to PMOS S/D
formation. After the S/D implant, the implanted wafer is annealed in a rapid thermal
process (RTP) tool. This step is important to activate the dopants while preventing
structures from spreading by diffusion. In this experiment for NMOS transistors, 3 splits
were done using different implant energy values (40, 45 and 50 KeV) as shown in Table
4.4 in chapter 4. In chapter 4, only a small significant change at the transistor profile is
detected. In this analysis chapter, Vt roll-off characteristic will be characterized in order
to see if any short channel effect occurs in the NMOS transistor.
In Figure 5.29 below, it is shown that low implant energy (40 KeV), combined with a
proper halo implant and Vt adjust in the earlier process step gives excellent Vt roll-off
characteristics. This Vt value is also within our Silterra specification.
0.38
Threshold voltage (V)
0.36
0.34
0.32
0.3
0.28
VTN1(40)
0.26
VTN2(45)
0.24
VTN3(50)
0.22
0.2
0
0.1
0.2
0.3
0.4
Draw n Gate Length (um)
0.5
0.6
Figure 5.29:
Simulated NMOS Vt Roll-off curves for three different source/drain
implant energies, (a) 45 KeV (b) 40 KeV (c) 50 KeV. Higher energy
gives higher Vt.
Figure 5.30:
Simulated NMOS structure showing depletion region for three different
source/drain implant energies, 40, 45 and 50 KeV.
When the transistor is off (i.e., zero gate bias), the channel region under the gate is
depleted to a certain depth. Low NMOS implant energy is used. The junction depth of
the n-region under the gate is less than half of the depth of depletion region. Thus, the
charge in n-region under the gate will contribute less to the charge sharing effect with
the channel, which is the origin of short-channel effect. Under such condition, charges
in NMOS source/drain play a dominant role on short-channel effect. Vertical cutline is
done on this transistor in order to see the dopant distributions when low and higher
energy is used. Cutline profile is shown in Figure 5.31. From this figure, it shows that
higher energy will produce deeper junction and will create larger depletion region for
the transistor. From this explanation, the perfect implant energy that can meet Silterra
specification is suggested, that is 40 KeV.
Figure 5.31:
Net doping vertical cutline profile for NMOS source/drain implant with
different implant energy. When higher energy is used, dopant will
diffuse further to the drain and creates deeper junction.
5.2
Summary
In this chapter, all halo, LDD and S/D implant results that were presented in chapter 4 is
extensively analyzed and explained. The best parameter that should be used is
determined by the impact that it gives to the NMOS and PMOS transistor. Electrical
characteristics especially Vt roll-off is discussed further in order to find the limits of the
implant parameters used. All the suggested work is applied to Silterra 0.13 µm CMOS
current process and it is proved to improve the transistor performance.
CHAPTER 6
CONCLUSION AND RECOMMENDATION FOR FUTURE WORK
This chapter is divided into 3 parts. The first part describes the conclusion of the
research followed by the second part, which deals with the recommendation for future
work. The last part is the summary of this work.
6.1
Conclusion
Process and device simulation are extensively used in this study. The TCAD simulator
that was used in this work must be calibrated before quantitatively accurate results can
be obtained. In this work, the drain engineering work in CMOS 130 nm technology is
discussed and analyzed. It covers all PMOS and NMOS halo implant, lightly doped
drain (LDD) and lastly source/drain (S/D) implant. All simulated data is compared with
the measured silicon data on the wafer that is fabricated in Silterra.
From the simulation results for PMOS halo implant that used arsenic with different
doses, it is suggested that in order to get a better Idsat value and match with the measured
data, arsenic with dose 3.3E+13 atom/cm2 is used. On the other hand, for NMOS
device, it is suggested that the boron dose to be used in halo implant is at 1.3E+13
atom/cm2. This dose also agrees with the measured data as shown in Figure 4.8, with
the percentage error ~0.2%.
As for the lightly doped drain implant step, the same analysis is done for PMOS and
NMOS device. There are two sets of results used to compare the usage of the previous
implant dopant, boron (B11) with boron di-fluoride (BF2). BF2 is introduced in this step
since it has many advantages to the quarter-micron technology, such as it can reduce the
NBTI and increase the device lifetime [26, 36-37]. All the consequences and differences
of changing these two dopants are described in chapter 4 and 5. The result from the
simulation and also supported with measured data suggest that, BF2 can be used in
PMOS LDD implant step to replace boron that was implemented in the previous
process. The variations of Id and Vt from these two processes are in the same manner.
The suggested BF2 dose that can meet the specification target is 2.8E+14 atom/cm2,
with fixed energy at 3.5 KeV. Implant energy that should be used in this similar step is
also analyzed and compared with boron. The suggested energy to be used is at 3.5 KeV.
By using high energy as suggested by other work, NBTI effect and short channel effect
that always happen in short channel devices can be reduced. For NMOS LDD step, only
two arsenic doses is used and analyzed. Since NMOS transistor is a stable device in
Silterra, the tuning process for this device is only to determine the suitable arsenic dose
in NMOS LDD step. The proposed arsenic dose is 1.5E+15 atom/cm2, with fixed
energy at 3.5 KeV.
Source/drain implant (S/D) is a heavier implant compared to LDD. It has less impact
compared to LDD as it is located further away from the device channel and contributes
less effect to the short channel device. But tuning up this process step is still important,
as it is one of the main implant which creates source and drain junction in the PMOS
and NMOS device. For PMOS device, various boron doses are used to tune up this
process step. Medium dose is suggested for this step as it can give better Idsat value and
also this value is comparable to Silterra specification. The suggested boron dose is at
2.7E+15 atom/cm2. Different energy is used to characterize NMOS S/D process step. 45
KeV implant energy is suggested to be used for this implant, as the Idsat value produced
is comparable to Silterra specification.
In this work, 0.13 µm TCAD deck is calibrated using SIMS data for both PMOS and
NMOS device. The TSUPREM-4 and MEDICI is then validated to be use further in this
work. Halo, lightly doped drain (LDD) and source/drain (S/D) implant is simulated
using the same process recipe splits that runs in the real wafer fabricated in Silterra.
Electrical characteristics, Idsat and Vt are then characterized in order to see the effect that
occur by changing the implant parameters such as dose, energy and implant tilt angle to
the PMOS and NMOS devices. The implant parameter is then tuned and optimized in
order to match with Silterra specification target. An optimized implant parameters for
each of the implant step; halo, lightly doped drain (LDD) and source/drain (S/D) are
then suggested to the process engineer for future used in Silterra. The objectives for this
work is achieved by having a calibrated 0.13 µm TCAD deck and the optimized implant
parameters to be used further in sub micrometer CMOS. It is also understood that by
using TSUPREM-4 and MEDICI as the process and device simulator in this work, the
behavior of the finished structure under multitude of process recipe and biasing
conditions can be analyzed.
6.2
Limitation and Recommendation
The result of this work is limited by a few factors. As mention earlier, the accuracy of
the simulated results is reduced since some models used in the simulation are
uncalibrated. Thus, further calibration of simulator is necessary to ensure reliable
simulation results. A simple yet useful methodology can be adopted to calibrate the 2D
profiles. Since SIMS profiles are expensive and measured device characteristics are
relatively easier to obtain, it is possible to calibrate the impurity profiles by matching
short channel and reverse short channel effects.
Another source of error that need to be deal with for future work in TCAD calibration is
to accurately measure poly line width and oxide thickness to the necessary resolution.
Many important MOSFET electrical characteristics are first-order related to these
parameters (e.g., a 1% change in either Lgate or Tox will result in approximately a 1%
change in Idsat), thus these parameters need to be characterized thoroughly to get
accurate results.
Grid factor is also a limitation. In this work the experiment is initially used a grid factor,
which is not dense enough. This cause simulation results to be inaccurate, especially at
short channels. Consequently, device performance parameters for 0.13 µm and 0.18 µm
could not be obtained and for other channel lengths, values were illogical. Thus, a new
experiment, with a better grid factor can be simulated and corresponding result will be
more meaningful. A comparison of the two grid factors is shown in Figure 6.1.
The next limitation of this work is that the analysis is only based on a few variations of
implant dose, energy and tilt. However, the advantage of using TCAD simulator is that
a new experiment can be easily duplicated and simulated for other values of implant
dose, energy and tilt.
Figure 6.1:
6.3
(a) Denser grid factor, (b) less dense grid factor.
Summary
In summary, TSUPREM-4 and MEDICI for 0.13 µm Silterra’s Process Technology in
TCAD deck has been calibrated and can be further used by the process engineer to
analyzed and verify Silterra’s process variations. Three engineering structure; halo
implant, lightly doped drain (LDD) implant and source/drain (S/D) implant has been
simulated and characterized. By implementing certain value of implant dose, implant
energy and implant tilt angle gives the best saturation drain current, Idsat and threshold
voltage, Vth value that also meet the Silterra’s specification range. By using process and
device simulator such as TCAD, it is proved that the correct process parameter can be
determined by using TCAD. The inner part of a transistor can also be seen and analyzed
to debug the transistor performance and speed; hence the device performance can be
upgraded as the channel length shrink in the future.
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27 K.Y. Kam, Y.M. Son (2000), TCAD Synthesis Approach to Deep Submicron
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36 Hani Noorashiqin Abd. Majid, Albert Victor Kordesch, Muhamad Rasat
Muhamad, (2006) “Process Optimization of p+LDD in 130 nm Process
Technology using TCAD Simulation”, IEEE International Conference on
Semiconductor Electronics (ICSE), Kuala Lumpur, Malaysia, 29 Nov – 1 Dec,
2006.
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Kluwer Academic Publishers, 1998.
45 Fiory A.T. and Bourdelle K. K., "Activation of Implanted Poly Gates by Short
Cycle Time Annealing", Mat. Res. Soc. Symp, Vol. 610, 2000, pp. B3.3.1-B3.3.6.
46 Yu Bin, Wan Yun, Wang Haihong, Xiang Qi, Riccobene Concetta, Talwar
Somit, Lin Min-Ren, "70nm MOSFET with Ultra-Shallow, Abrupt, and SuperDoped S/D Extension Implemented by Laser Thermal Process (LTP)", IEDM
1999, 1999, pp 20.4.1-20.4.4.
47 M.E. Law, (2002). Process Modeling for Future Technologies, IBM J.Res &
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48 A. Narain (1993). MOSFET Models for VLSI Circuit Simulation, Theory and
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49 H.C. Chooi (2002), Modeling of Nanoscale MOSFETs, Stanford University.
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52 A. Scarpa, D. Ward, J. Dubois, M. Leo, G. Steven, C. Richard, Y. S. Kwang, C.
Antonio, K. Ramun, B. Mike, (2006) ”Negative-Bias Temperature Instability
Cure by Process Optimization”, IEEE Trans. Electron Devices, Vol.53, NO. 6.
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LIST OF PUBLICATIONS
1 Hani Noorashiqin Abd. Majid, Albert Victor Kordesch, Muhamad Rasat
Muhamad, (2006) “Process Optimization of p+LDD in 130 nm Process
Technology using TCAD Simulation”, IEEE International Conference on
Semiconductor Electronics (ICSE), Kuala Lumpur, Malaysia, 29 Nov – 1 Dec,
2006.
2 Hani Noorashiqin Abd. Majid, Albert Victor Kordesch, Muhamad Rasat
Muhamad, (2006) “Optimization of Lightly Doped Drain (LDD) process in
130nm PMOS using TCAD Simulation”, 2nd Mathematical and Physical
Science Graduate Conference (MPSGC), National University of Singapore,
Singapore, 12 Dec – 14 Dec, 2006.
3 Hani Noorashiqin Abd. Majid, Albert Victor Kordesch, Muhamad Rasat
Muhamad, (2007) “Optimum Halo Structure for 0.13 µm CMOS Technology
using TCAD”, UNITEN Student’s Conference on Research and Development
(UNITEN SCOReD), College of Graduate Studies, UNITEN, Malaysia, 14 – 15
May, 2007.
4 Hani Noorashiqin Abd. Majid, Albert Victor Kordesch, Muhamad Rasat
Muhamad, (2007) “Optimization of Halo Structure for 0.13 µm PMOSFET
using TCAD Simulation”, International Conference on Advancement of
Material and Nanotechnology (ICAMN), The City Bayview Hotel, Langkawi,
Malaysia, 29 May – 1 June, 2007.
APPENDIX A
Periodic Table of the Elements
Group**
Period
1
IA
1A
2
1.008
3
4
H
5
6
7
8
9
2
He
4.003
10
B C N O F Ne
6.941 9.012
10.81 12.01 14.01 16.00 19.00 20.18
12
Na Mg
22.99 24.31
19
4
13 14 15 16 17
IIIA IVA VA VIA VIIA
3A 4A 5A 6A 7A
Li Be
11
3
8A
2
IIA
2A
1
1
18
VIIIA
20
8
9 10 11 12 13 14 15 16
3
4 5 6
7
IIIB IVB VB VIB VIIB ------- VIII --- IB IIB Al Si P S
---3B 4B 5B 6B 7B
1B 2B 26.98 28.09 30.97 32.07
------- 8 ------21
22
23
24
25
26
27
28
29
30
31
32
33
34
17
18
Cl Ar
35.45 39.95
35
36
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
39.10 40.08 44.96 47.88 50.94 52.00 54.94 55.85 58.47 58.69 63.55 65.39 69.72 72.59 74.92 78.96 79.90 83.80
37
5
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
85.47 87.62 88.91 91.22 92.91 95.94 (98) 101.1 102.9 106.4 107.9 112.4 114.8 118.7 121.8 127.6 126.9 131.3
55
6
56
57
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Cs Ba La* Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
132.9 137.3 138.9 178.5 180.9 183.9 186.2 190.2 190.2 195.1 197.0 200.5 204.4 207.2 209.0 (210) (210) (222)
87
7
110 111 112
114
116
118
Fr Ra Ac~ Rf Db Sg Bh Hs Mt --- --- ---
---
---
---
()
()
()
(223)
88
(226)
Lanthanide
Series*
89
104 105 106
107
108
109
(227) (257) (260) (263) (262) (265) (266)
58
59
60
61
62
63
64
()
()
()
65
66
67
68
69
70
71
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu
140.1 140.9 144.2 (147) 150.4 152.0 157.3 158.9 162.5 164.9 167.3 168.9 173.0 175.0
90
91
92
93
94
95
96
97
98
99
100
101 102 103
Actinide Series~ Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
232.0 (231) (238) (237) (242) (243) (247) (247) (249) (254) (253) (256) (254) (257)
APPENDIX B
$driver ts4
$module NTub_PTub:0
$step load
init in.f=STI:0_0 tif
method unrefine=0
material mat=poly grasz.0=0.02 gamma.0=5.6e-5
impurity mat=poly imp=phosphorus q.sites=8e15 gseg.ini=25
impurity mat=poly imp=gb_phosphorus cm.sec dix.0=6e3
impurity mat=poly imp=boron q.sites=2e16 gseg.ini=25
impurity mat=poly imp=gb_boron cm.sec dix.0=420
$step Variables
assign name=device c.val="n"
assign name=gox c.val="thin"
assign name=region c.val="2d"
assign name=Lgate n.val=0.13
assign name=Lpolywin n.val=0.10
assign name=Lwin n.val=0.38
assign name=Lwintox n.val=0.1
assign name=Liso n.val=0.28
assign name=includeSTI n.val=0
$step Method
Method pd.full act.full itrap
source bas.inp
$step NTUB1-L05
deposit photo thick=2.00
if ("@device"=="p")
etch photo all
if.end
$step NTUB1-IMP
$moment fitted to UT-MARLOWE
assign name=NW1ds n.val=6e12
assign name=NW1en n.val=600
assign name=NW2ds n.val=6e12
assign name=NW2en n.val=380
$ Nwell 1st Implant
implant phos dose=@NW1ds/4 ener=@NW1en tilt=4 rota=0 damage +
taur.mod=DUALPEARSON taur.exe=tauruss4 print
implant phos dose=@NW1ds/4 ener=@NW1en tilt=4 rota=90 damage +
taur.mod=DUALPEARSON taur.exe=tauruss4 print
implant phos dose=@NW1ds/4 ener=@NW1en tilt=4 rota=180 damage +
taur.mod=DUALPEARSON taur.exe=tauruss4 print
implant phos dose=@NW1ds/4 ener=@NW1en tilt=4 rota=270 damage +
taur.mod=DUALPEARSON taur.exe=tauruss4 print
$ Implant 2
implant phos dose=@NW2ds/4 ener=@NW2en tilt=4 rota=22 damage +
taur.mod=DUALPEARSON taur.exe=tauruss4 print
implant phos dose=@NW2ds/4 ener=@NW2en tilt=4 rota=112 damage +
taur.mod=DUALPEARSON taur.exe=tauruss4 print
implant phos dose=@NW2ds/4 ener=@NW2en tilt=4 rota=202 damage +
taur.mod=DUALPEARSON taur.exe=tauruss4 print
implant phos dose=@NW2ds/4 ener=@NW2en tilt=4 rota=292 damage +
taur.mod=DUALPEARSON taur.exe=tauruss4 print
$step PTHRU2-IMP
implant arse dose=5e12 ener=150 tilt=7 rota=22 damage taur.mod=DUALPEARSON +
taur.exe=tauruss4 print
$step PVT1-IMP
implant arsenic dose=5e12 ener=150 tilt=7 rota=22 damage
taur.mod=DUALPEARSON +
taur.exe=tauruss4 print
$step NTUB1-CSTR
etch photo all
$step PTUB1-L15
deposit photo thick=1.7125
if ("@device"=="n")
etch photo all
if.end
$step PTUB1-IMP
assign name=PW1ds n.val=8e12
assign name=PW1en n.val=260
assign name=PW2ds n.val=5e12
assign name=PW2en n.val=120
$ High Energy Pwell Implant
$ PWELL IMPLANT
IMPLANT Boron DOSE=@PW1ds/4 ENERGY=@PW1en
taur.mod=DUALPEARSON tilt=4 +
rotation=0 damage taur.exe=tauruss4 print
IMPLANT Boron DOSE=@PW1ds/4 ENERGY=@PW1en
taur.mod=DUALPEARSON tilt=4 +
rotation=90 damage taur.exe=tauruss4 print
IMPLANT Boron DOSE=@PW1ds/4 ENERGY=@PW1en
taur.mod=DUALPEARSON tilt=4 +
rotation=180 damage taur.exe=tauruss4 print
IMPLANT Boron DOSE=@PW1ds/4 ENERGY=@PW1en
taur.mod=DUALPEARSON tilt=4 +
rotation=270 damage taur.exe=tauruss4 print
$ 2ND IMPLANT
IMPLANT Boron DOSE=@PW2ds/4 ENERGY=@PW2en
taur.mod=DUALPEARSON tilt=4 +
rotation=0 damage taur.exe=tauruss4 print
IMPLANT Boron DOSE=@PW2ds/4 ENERGY=@PW2en
taur.mod=DUALPEARSON tilt=4 +
rotation=90 damage taur.exe=tauruss4 print
IMPLANT Boron DOSE=@PW2ds/4 ENERGY=@PW2en
taur.mod=DUALPEARSON tilt=4 +
rotation=180 damage taur.exe=tauruss4 print
IMPLANT Boron DOSE=@PW2ds/4 ENERGY=@PW2en
taur.mod=DUALPEARSON tilt=4 +
rotation=270 damage taur.exe=tauruss4 print
$step NTHRU-IMP
implant boron dose=5e12 ener=60 tilt=7 rota=22 damage taur.mod=DUALPEARSON
+
taur.exe=tauruss4 print
$step NVT1-IMP
implant boron dose=5e12 ener=20 tilt=7 rota=22 damage taur.mod=DUALPEARSON
+
taur.exe=tauruss4 print
implant imp=indium dose=1e13 ener=120 tilt=7 rota=22 damage impl.t=tr.indium +
print
$step PTUB1-CSTR
etch photo all
$step Doping
select z=phos
print x.v=0 layers
$step save
save out.f=NTub_PTub:0_0 tif