A NEAR UNITY POWER FACTOR INPUT STAGE WITH MINIMUM
CONTROL REQUIREMENTS FOR AC DRIVE APPLICATIONS
Navid R. Zargari
Geza Joos
Concordia University
Department of Elec. & Comp. Engineering
1455 De Maisonneuve Blvd. West
Montreal, Que H3G 1M8 Canada
Tel: (514) 848-3116
FAX: (514) 848-2802
Email: navidz@ece.concordia.ca
Absfracf. Conventional a c induction motor drives use
P W M voltage source inverter PSI) fed from a diode
rectifier. In retrofit applications, due to voltage drops and
the inverter voltage gain, six-step operation of the inverter
is required at rated speed, resulting in large low order
harmonic current and torque components. To allow the
inverter to operate in the P W M mode of rated speed, a
synchronous rectifier is used in this paper to boost the de
bus voltage slightly. The resulting converter system
presents a11 the advantages associated with active frontend rectifiers. However, since the dc bus control
requirements a r e not stringent, a simple control structure
is used to ensure unity power factor operation.
Furthermore, optimized P W M patterns and pattern
synchronization are used to reduce the switching
frequency of the rectifier. The paper presents an analysis
and design guidelines for the complete drive system.
Simulation and esperimental results on a 5 KVA induction
motor drive confirm the feasibility and advantages of the
proposed structure.
L INTRODUCTION
Typical induction motor drives employ a rectifier-inverter
structure consisting of a diode rectifier, an L-C dc bus filter
and a PWM voltage source inverter, Fig. 1. The inverter has
been the subject of many improvements over the past years
[ 1,2]. However, most systems are based on a diode front-end
rectifier, which has the well-documented drawbacks: (a) large,
low frequency harmonics in the input current, particularly
with discontinuous conduction; (b) no regeneration
capabilities. Furthermore, in retrofit applications, due to
voltage drops and the inverter ac gain, the maximum output
voltage across the motor is less than the rectifier ac input
voltage in the normal PWh4 mode. This requires that the
inverter be operated in the six-step mode (over modulation)
at rated speed, and this results in large low order harmonics
across the motor. The purpose of this study is to replace the
diode rectifier by an input stage capable of delivering the
slightly higher dc voltage required to avoid operation of the
inverter in the over modulation region.
Active front-end rectifier, as a replacement for diode
rectifiers, are mentioned in the literature, [3-lo]. These
rectifiers are receiving more attention as the requirements on
line harmonic minimization are becoming more stringent.
Advantages of the active front-end rectifiers include: (a) near
sinusoidal ac input currents, (b) near unity power factor, (c)
regenerative capabilities. Of the two main structures available,
the synchronous link converter is the one capable of
producing the required boost in the dc bus voltage.
The proposed ac drive system, Fig. 2 , has all the features
mentioned above. In addition, to maintain a simple control
structure for the rectifier and optimize the operation of the
system, the following strategies are used:
(a) The rectifier is operated at a fixed modulation index, close
to one, and power transfer is controlled by pattern phaseshifting [ l l ] . @) Advantage is taken of the symmetrical
nature of the complete structure in terms of carrier
synchronization. (c) Since the rectifier is operated at a fixed
modulation index with a value near unity, optimized
switching patterns with reduced switching frequency can be
used [ 121.
The analysis of the complete system is presented. Design
guidelines are given. The system is implemented with an
induction motor to confirm the feasibility and advantages of
the proposed solution.
Fig. 1 Conventional ac drive system.
0-7803-1 456-5194 $4.00 0 1994 IEEE
387
IL DESCRIPTION OF THE PROPOSED A C DRIVE SYSTEM
The main blocks of interest in the system are (a) the load
inverter, (b) the synchronous rectifier power circuit, (c) the
control loop for the synchronous rectifier, (d) the P W
pattem generator.
tracking by reducing the instantaneous error between the
reference and the actual current. The output line impedance
determines the slope of current and therefore the existence of
the intersections required to create the PWM pattem. The
existence ofintersections is guaranteed through satisfying the
following condition:
V& + 21rfIp
A. Load inverter
The output inverter stage is current controlled. The
current error is fed to a PI controller and its output is
compared with a triangular camer which dictates the
operating switching frequency. The integral term improves the
4v.
2LO
where V,, f, are the amplitude and frequency of the camer, 4
is the amplitude of the output current reference, V, is the dc
bus voltage ,and Lois the output line inductance. The open
loop current transfer function is given by:
GAS) = TJs) . T,
1
.SL, to
+
where T, is given by:
and typical transfer function of a PI is given by:
TJS) = kl(-
1 +sr)
sr
(4)
dya
where k, is the gain and T is the time constant. The block
diagram of the inverter control loop is shown in Fig. 3(a).
The PI regulator can be designed by one of the following two
procedures. (a) To obtain a desired overshoot in the current
step response. (b) To achieve a desired phase margin. The
damping factor of the closed loop current transfer function is
given by:
VOLTAQE u)(IP
Fig. 2 The proposed ac drive system.
I
I
Fig.3 Block diagram of the control loops. (a) Cumnt-controlledoutput
invnter. @) DC bua voltage loop.
388
where V, is the dc bus voltage and M is the modulation
index of the input rectifier module. From the above equation,
the integral gain of the PI regulator can be designed to obtain
desired overshoot in the step response. Dependency of
damping factor on the modulation index 0,and on the PI
time constant (t), is shown in Fig. 4. From Fig. 4, the time
constant of the PI regulator was designed to obtain a damping
factor of 0.7. The bode plots of the open loop current transfer
function are shown in Fig. 5 , where it is seen that with a
design based on procedure (a), a phase margin of 60 degrees
is obtained. Therefore, it is concluded that the two methods
result in similar designs.
LFm
(@)
-:'a
V&
=
2Jz v
,
-
M
_ _ _ .... ............. ............. ....- ........
where ,
V is the rectifier input voltage. It is Seen that the
output dc voltage is proportional to the inverse of the
modulation index M. In the proposed scheme, the modulation
index is fixed and the dc bus voltage is therefore proportional
to the ac input voltage. The modulation index would be set
to M=l if both converters use the same type of pattern
generator and losses are neglected. The value will have to
adjust to a lower value, typically M=0.9 to account for losses.
In order to properly start the system, the six anti-parallel
diodes must be reverse-biased in the beginning. Thls means
that the dc link capacitor must be initially charged to a value
higher than output of a three-phase diode bridge rectifier. The
dc capacitor can be charged to this value with the use of a
variac, through the existing front-end diode rectifier.
ModJaicmeM
0.0
Fig. 4 (a) Damping factor vs modulation index @) Damping factor VS PI
time constant
1
10
Fm=q,ws
100
loo0
Fig. 5 Design of the current loop. ( inverter,T
system
loo00
PI regulator and designed
Gi.)
phase,
Fig. 7 Design of the control loop of the synchronous rectifier.
C. Control of the synchronous rectifier
Fig. 6 Phasor diagram of the input synchronous rectifier.
B. Svnchronous recti'jier
A voltage source topology is used on the line side. This
topology has a boost characteristic and provides a dc voltage
higher than that of a diode bridge rectifier. The output dc
voltage is obtained from:
389
In order to maintain near unity power factor, the rectifier
ac input voltage is made equal to the ac line voltage.
Assuming the link reactor is less than 0.4 pu, the resulting
power factor is greater than or equal to 0.98 (for a load angle
6 = 24 Deg. and a current phase shift 0 = 12 Deg., Fig. 6).
Under rated conditions, and for a given modulation index M,
this yields a given value of the dc bus voltage. Therefore,
rather than measure the ac input ac voltage, the base
equivalent dc voltage is computed and used as a reference for
the control loop. The error between the reference and the
actual dc bus voltage provides the error or control signal to
the load angle or phase shift generator, Fig. 2. The speed of
response of the dc bus voltage control loop is not critical
since the inverter will compensate for variations under
transient conditions. Therefore, the time constant of the PI
regulator in the voltage loop can be chosen to be 10 times
larger than that of the current loop. However, a more precise
design is achievable using the transfer function of the input
rectifier. The transfer function is obtained with the help of
dqo transformation technique and linearization of the
equations with small signal method. The following
assumptions are made: (a) ideal switches, (b) high frequency
switching and (c) all losses lumped in the line resistance. The
time invariant state space dynamic model for the input
synchronous rectifier is derived as:
X;
=AX&
+
BU
for the rectifier and inverter stages. In particular, patterns with
dead-bands, that result in an effective reduction of the
switching frequency by one third, are particularly well suited
for operation at a high modulation index. Furthermore, these
camer techniques give superior performance to stored patterns
under transient conditions since: (a) Response to changes in
reference are instantaneous. (b) There is no risk of producing
dc components in the pattem during transitions. The
advantages of using same camer for input and output
converters can be seen from Fig. 6, where it is clear that the
high frequency harmonics are attenuated. The reason being
that the inverter and rectifier currents contain similar
harmonic frequencies with the same sign.
(7)
IIL DESIGN OF THE DC BUS CAPACITOR
where A, X and BU are defined in the Appendix. The transfer
function is given by the following:
-v,(-s) a@)
C.D(s) + E
G(s)
m).Do
=
Tb
(8)
+
where C, D(s), E, F(s) and G(s) are given in the Appendix.
The block diagram of the voltage loop is depicted in Fig.
3(b). The bode plots of the open loop voltage transfer
functions are shown in Fig. 7. A PI regulator is designed to
obtain a stable system with a phase margin close to 60
degrees. The bode plots of the PI and the overall open loop
transfer function, T, are also shown (Fig. 7).
The dc bus capacitor must be designed to satisfy the
following criteria:
- To comply with the minimum ripple requirement of the dc
bus voltage.
- To limit the dc bus voltage fluctuations during transients.
It is concluded that the size of the capacitor is mainly limited
by the second condition. Dc bus voltage fluctuations can be
due to the inverter current transients or the ac mains
transients, such as switching capacitors or other loads on the
ac bus). The dc voltage fluctuations generated by the inverter
current transients can be calculated from:
(9)
D.PWM pattern generator
Since the modulation index is fixed, any pattern generator
can be used, including the off-line optimized and stored
patterns. However, advantage can be taken of carrier based
optimized techniques, if it is desired to synchronize carriers
where I, and I, are the inverter and rectifier dc currents
respectively. However, the main role of the capacitor during
ac transients is to maintain the balance of power during one
switching period. Assuming the input ac voltage is halved,
the minimum value of the capacitor is obtained from:
where AV is the maximum voltage drop allowed in the dc bus
without loss of control. The input synchronous link rectifier
is controllable as long as the anti-parallel diodes are reversed
biased. Therefore, the maximum voltage drop is obtained
from:
From 10,1 I the minimum value of the capacitor is calculated.
Fig. 8 Dc link currents. (a) dc capacitor current, (b) invcrkr input dc
cumnt, (c) rectifier output dc current
390
Table I
IV. DESIGN EXAMPLE, RESULTS AND COMMENTS
The specifications of the designed ac drive system are
given in Table I. The complete system is simulated and
results for steady state and different transient conditions are
obtained.
A . Steady state
Steady state operation for rated motor speed and rated
current is illustrated in Figs. 9,lO. The followings can be
concluded: (a) The dc bus voltage ripple is small and the
average value is 30% higher than the normal diode rectifier
voltage. (b) The output motor current is sinusoidal and has no
low frequency components. (c) The input ac line current is
sinusoidal and nearly in phase with the phase voltage,
resulting in nearly unity power factor.
B. Inverter current transients
The current reference waveforms of the output inverter
are increased by 25% and the effect on the dc bus voltage is
shown in Fig. 1 I . It is seen that 6 loop is not fast, however,
the output inverter has fast response due to current control.
The dc bus voltage ripple/fluctuations is rejected in the output
currents. The step-up inverter transient is depicted in Fig. 12.
The voltage variation is limited to f 1OV.
C. Ac mains transients
The ac mains transients are due to the line switching.
These will create overvoltage/undervoltage on the dc link.
The loss of control happens when the input voltages are high
enough to forward bias the diodes. However, the
controllability is regained when the ac transient is diminished.
If the dc bus voltage becomes lower than that of a diode
rectifier, it is necessary to recharge the dc capacitor to a value
higher than diode bridge output. Figure 13 shows a case
where switching of the other loads at PCC has resulted in a
10% decrease in the line voltage.
D. Operation with unbalanced input voltages
The ac mains with 10% amplitude unbalance is simulated
and results are shown in Fig. 14. The second harmonic
generated is very small. The input power factor remains near
unity.
V. CONCLUSIONS
A near unity power factor input stage with minimum
control requirements is proposed for ac drive applications. A
synchronous rectifier is used to boost the dc bus voltage
slightly. The output inverter is current-controlled, therefore,
n
V,= 377V. M
k = 1. k= 1.2.
=
0.9
n
7.= 0.001, ?=
. 0.012
~~~
~
~~
the dc bus control requirements are not stringent. This allows
for a simple control scheme on the input synchronous rectifier
to ensure near unity power factor operation. Analysis and
design guidelines are presented. The switching frequency can
be reduced by pattern synchronization of the inputloutput
converter. Feasibility and advantages of the proposed
structure is confirmed by simulation and experimental results.
REFERENCES
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tracking scheme for high dynamic performance," in IEEE-IECON C o d .
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485-495, Oct 1990.
B.T. Ooi, J.W. Dixon, AB. Kulkami and M. Nishimoto, "An integrated
ac drive system using a controlled current PWM rectifiedinverter link,"
in IEEE Trans.on Power Elec., vo1.3, No. 1, pp. 64-70. Jaa. 1988.
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pp. 706-71 1, Oct. 1988.
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Appendix
The followings specify the dynamic model of the
391
synchronous rectifier.
X = [id iq
vd', BU
--Lr
A =
0
= [0
V
L
01'
M
--siaa,
-0
2L
--r
--I
I
-M
Pa,
L
1
Rc
4c
Fig. 9 (a) Dc bus voltage. @) Inverter output current. (c) Input line current
(scaled) and line voltage.(d) Rectifier input voltage.
D(s) = (s+L)2
F(s)
1
= 2c(s+-)
Rc
as)= -3M2
(s+-)
4L
E =
o2
+
L
r
L
3 M 2 0 V,
4L
where:
L = line inductance, r = line resistance, R = equivalent
resistance of the output inverter referred to dc bus, c = dc
capacitor, 6, = phase angle for the operating point, M =
modulation index, V, = dc bus voltage, V, = peak value of
the input ac mains.
392
Fig. 10 Steady state waveforms. Input line current I,
voltage V
, dc bus voltage ,V
(scaled), input ac
:
V&
:
........................................
..
-1
9(h
Fig. 13 Ac transients. 10% step down in the ac line voltages.
Fig. 1 1 Step down in the ouput inverter current The currents are scaled
(X10).
(4
mi
I
: I
: . . V&
. . . . . . . .: . . . . . . . . . . . . . . . . . .
7
:
:
I
I
-1
4
0)0
Fig. 12 Step up in the output inverter c-t.
The currents are scaled ( X 5 ) .
4
37sy . . . . . . . . . v & . . . ' . . . . . . . . ' . . . . ' . . . .
. . . . . . . . .
I,
. . . . . . . .
. . . . . . . .
Fig. 14 Operation with unbalanced input voltages. (a) Dc bus voltage. @)
Input line current and voltage.
393