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1
A PLL Exploiting Sub-Sampling of the VCO
Output to Reduce In-band Phase Noise
Xiang Gao, Eric A. M. Klumperink, Mounir Bohsali, and Bram Nauta
jitter PLL based on sub-sampling. It uses a phasedetector/charge-pump (PD/CP) that sub-samples the
VCO output with the reference clock. In contrast to
what happens in a classical PLL, the PD/CP noise is not
multiplied by N2 in this sub-sampling PLL. Moreover,
no frequency divider is needed in the locked state and
hence divider noise and power can be eliminated. A
frequency locked loop guarantees correct frequency
locking without degenerating jitter performance. The
PLL implemented in a standard 0.18-µm CMOS
process consumes 4.2 mA from a 1.8 V supply and
occupies an active area of 0.4 × 0.45 mm2. The in-band
phase noise at 200 kHz offset is measured to be -126
dBc/Hz and the rms PLL output jitter integrated from
10 kHz to 40 MHz is 0.15 ps.
filter (LF) and a frequency divider divide-by-N. Both the
VCO
100
14 Bits
X. Gao, E. A. M. Klumperink and B. Nauta are with the IC-Design
Group, CTIT, University of Twente, 7500 AE, Enschede, The Netherlands
(e-mail: X.Gao@utwente.nl).
M. Bohsali is with National Semiconductor, Santa Clara, California.
0.5
2p
s
clo
70
50
ck
jitt
e
0.1
25
ps
ps
12 Bits
r
10 Bits
10
100
1000
Signal frequency (MHz)
Fig. 1. Achievable ADC signal-to-noise ratio (SNR) with a certain signal
frequency limited by jitter in the sampling clock.
Ref
LF
PD/CP
VCO
Out
Div
÷N
φref ,n
[Фref ]
(a)
φPD,n
+
+
∑
-
iCP ,n
+
Kd
φVCO,n
vLF ,n
+
FLF(s)
+
KVCO/s
+
[Фout ]
β CP = K d / N
A
clock with low jitter or phase noise is a prerequisite
for a variety of applications like high performance
analog-to-digital converters (ADCs), wireline and optical
serial links and radio transceivers. Fig. 1 shows the
achievable signal-to-noise ratio (SNR) of an ADC for a
certain signal frequency, limited by the amount of jitter in
the sampling clock. We see that for an ADC with higher
resolution and higher frequency, the requirement on the
sampling clock jitter is more stringent.
To the present time, many different PLL architectures
have been developed [1]. However, the core of most PLLs
is the same: the “classical PLL” architecture as shown in
Fig. 2. In a classical PLL, a voltage controlled oscillator
(VCO) is locked to a reference clock Ref by a feedback
loop with a phase-detector/charge-pump (PD/CP), a loop
80
60
Index Terms—clocks, clock generation, clock multiplier,
frequency multiplication, frequency synthesizer, low jitter,
low phase noise, low power, jitter, phase detector, phase
locked loop, PLL, sub-sampling phase detector, phase noise,
timing jitter.
I. INTRODUCTION
16 Bits
90
SNR (dB)
Abstract— In this paper, we present a 2.2-GHz low
+
φdiv,n
1/N
(b)
Fig. 2. Classical PLL (a) architecture; (b) phase domain model.
and the loop components contribute to PLL phase noise,
with the VCO noise dominating the out-of-band and the
loop noise dominating the in-band. In an optimized PLL,
the two types of noise contribute equally to the output jitter
[1, 2] and thus are equally important. The VCO phase noise
has been extensively studied in literature. The focus of this
paper is on reducing the loop noise, i.e., the PLL in-band
phase noise.
In a classical PLL, the CP and the divider are often the
main sources of loop noise. The in-band CP noise, when
transferred to the PLL output, is suppressed by the
feedback gain from the PLL output to the CP output [1, 2],
denoted as βCP. A larger βCP is preferred as it suppresses
more CP noise. In a PLL using a conventional 3-state
PFD/CP, the CP feedback gain is: βCP,3state=ICP/(2π·N), with
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ICP the CP current and N=fVCO/fRef. Due to the existence of
the divide-by-N, we see that βCP is reduced by N and
therefore the CP noise (in power) is amplified by N2 when
transferred to the PLL output, which is often the bottleneck
for a classical PLL to achieve low in-band phase noise. In
this paper, we will propose a new divider-less PLL
architecture based on sub-sampling phase detection which
can break this bottleneck.
2
requiring smaller loop filter capacitors. Therefore, a larger
βCP could also reduce chip area if the CP dominates the
loop
VsamP
Pulser
Ref
II. SUB-SAMPLING PLL
gmVsamP
Sampler
VCOP
Pul
Iout
Iout
VCO
Sampler
Vsam
IUP=gmVsam
= VDC + AVCO sin(2πfVCOt +φVCO)
Iout
Ref
fref
VDC
β CP , SSPD =
AVCO gm
−π
IDN=gmVDC
π
φVCO
VsamN
Sampler
VCON
gmVsamN
ideal locking point
- AVCO gm
Fig. 4. Sub-sampling PD/CP with pulse width control
Δ I out
= AVCO ⋅ g m
ΔφVCO
Ref
Fig. 3. Principle and characteristic of a sub-sampling based voltage
controlled PD/CP
The sampling based PD was known for its high detection
gain [3]. Still drawbacks like difficulty of integration (big
filter capacitor) and limited pull-in range have kept it from
wide use in PLLs [3]. Fig. 3 shows the concept of our subsampling PD (SSPD) proposal with a CP added. The key
idea is to exploit the high dV/dt of the high frequency
VCO. The sine wave VCO with amplitude AVCO and DC
value VDC is directly sub-sampled by Ref, without using
divider. The sampler output Vsam controls a current
IUP=gmVsam, while a reference voltage VDC controls another
current IDN=gmVDC. If N is an integer and the VCO and Ref
are phase aligned, the sub-sampling renders Vsam=VDC. The
CP then outputs no current and phase locking is achieved.
If there are phase errors, they will be converted to voltage
changes in Vsam around VDC, and then to current changes by
the voltage controlled CP. The ideal characteristic of the
SSPD/CP has same shape as the VCO output (see Fig. 3).
In a PLL with this SSPD/CP, the CP feedback gain
becomes βCP,SSPD=AVCO·gm. Assuming for simplicity squarelaw MOS transistors to implement gm, we find:
βCP,SSPD=AVCO·(2ICP/Vgs,eff), where Vgs,eff is the transistor’s
effective
gate-source
voltage.
Comparing
to
βCP,3state=ICP/(2π·N), we see that βCP,SSPD can easily be one
order of magnitude larger as usually N >>1 and AVCO>Vgs,eff.
In other words, for the same ICP, a PLL using a SSPD/CP
has a much larger βCP than a PLL using a 3-state PFD/CP
and thus suppresses CP noise more. Moreover, a PLL
using a SSPD/CP does not need a divider in the locked
state, which eliminates the noise and power contribution of
the divider. As a result, the loop noise is greatly improved
which leads to a PLL design with very low in-band phase
noise at low power.
In a PLL, the optimal bandwidth for minimum jitter fc,opt
is where the spectrum of the VCO and the loop noise
intersects [1, 2]. For lower loop noise, fc,opt is higher,
Sampler
gm/CP
Pulser
Pul
PFD
DZ
VCO
R1
C1
VCO
C2
CP
Div
÷N
FLL
Fig. 5. Sub-sampling PD/CP with pulse width control
noise. However, if other loop components start dominating
or if fc,opt reaches fRef/10, increasing βCP further can not
increase fc,opt, but does require a larger filter capacitor to
stabilize the PLL. Such “unnecessarily high” βCP will not
improve the loop noise but will make full integration
difficult. In a PLL using a SSPD/CP, βCP can easily be
“unnecessarily high”. Therefore, some way of gain control
is desired.
Fig. 4 shows the proposed SSPD/CP, now extended with
pulse width control. It uses differential sampling of antiphase VCO outputs to eliminate the reference voltage VDC
and alleviate charge injection and charge sharing issues. A
block called “Pulser” is added. It generates a pulse with a
duty ratio of DRpul, which connects or disconnects the
current sources from the CP output. In this way, the
effective CP output current and thus βCP is reduced by
DRpul. By a careful choice of DRpul, the high gain feature of
the SSPD/CP can be explored without paying unnecessary
filter capacitor area. The Pulser can be designed to have no
overlap with the sampling clock, so that the sampler can
simply be a track and hold.
Fig. 5 shows the sub-sampling PLL architecture utilizing
the proposed SSPD/CP. Since a SSPD has limited pull-in
range and may lock to any possible integer multiple of fRef,
a frequency-locked-loop (FLL) is added to ensure correct
PLL locking over the entire VCO tuning range. Similar to
the classical PLL, the FLL uses a divider and a 3-state
PFD/CP, except that a dead zone creator (DZ) is inserted
between the PFD and CP. During locking, the FLL has
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higher gain than the core loop and over-rules it. In the
locked state, the phase error between Ref and the divider
output Div is small and falls inside the dead zone. The CP
in the FLL will output no current. The FLL and the divider
then have no influence on the PLL and do not add noise.
After locking is achieved, the FLL can be disabled to save
power.
In a sub-sampling PLL where CP noise is greatly
suppressed and divider noise is eliminated, the sampling
clock noise becomes critical. Fig. 6 shows the schematic of
the SSPD/CP. The differential sampler simply consists of
two NMOS transistors and two 60fF capacitors. An inverter
chain is used to boost the Ref sampling edge steepness.
Two source follower buffers isolate the sampler from the
LC VCO. The sampling path is made as short and clean as
possible. The SSPD/CP characteristic (sine-shape) is fairly
linear when phase error is small in the locked state. The
Pulser is implemented with a delay cell and an AND gate,
with a 1.5nS pulse width.
3
Fig. 8. Measured PLL output phase noise.
Vbias
VsamP
VCOP
VBP
VsamN
VsamP
Pul
Pul
Iout
Vdum
Ref
VCON
Pul
Pul
VBN
VsamN
VBN
Fig. 6. Schematic of the sub-sampling PD/CP
III. EXPERIMENTAL RESULTS
0.45 mm
VCO
0.4
mm
50Ω buf.
bias
Fig. 7. Chip microphotograph.
PD,buf.
Loop
Filter
FLL
CP
pul.
FLL
VBN
Fig. 9. Measured PLL output spectrum.
To verify the ideas presented in this paper, a prototype
chip was fabricated in a standard 0.18-µm CMOS process.
Fig. 7 shows a die micrograph. The total chip area
including the pads is 0.8 x 0.8 mm2, while the active area is
0.4 x 0.45 mm2 and is dominated by the LC VCO. The IC
was tested in a 24 pin Quad LLP package. Excluding the
50Ω CML buffer for measurement, the PLL core consumes
4.2mA from a 1.8-V supply. The VCO dissipates 1 mA and
the loop components 3.2 mA. The FLL consumes 0.8mA
and is disabled after locking is achieved to save power.
The reference clock of the PLL is generated by an offchip 55.25-MHz high quality crystal oscillator from Wenzel
Associates. The amplitude of the crystal oscillator is
attenuated before it is fed into the chip such that the clock
arrived on-chip has an amplitude of 1.8 Vp-p. The phase
noise spectrum of the 2.21-GHz PLL output measured from
an Agilent E5501B phase noise measurement setup is
shown in Fig. 8. The in-band phase noise is -126 dBc/Hz at
200-kHz offset and out-of-band phase noise is -141 dBc/Hz
at 20-MHz offset. The PLL output rms jitter can be related
to the phase noise as:
fh
σ =
2
t
2 × ∫ L ( f )df
fl
(2πf out ) 2
(1)
where [fl, fh] is the specified integration region. Integration
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of the phase noise spectrum from 10 kHz to 40 MHz yields
a total phase noise power of -56.8 dBc, which translates to
an rms-jitter of 0.15 ps at the 2.21-GHz output frequency.
The reference spur was measured with an Agilent
Spectrum Analyzer E4440A to be -46 dBc at 55.25 MHz
offset as shown in Fig. 9. This spur is caused by
insufficient isolation between the VCO and the sampler,
and can be improved in a re-design.
Fig. 10 summarizes the PLL performance. Compared
with [4-6], this design achieves the lowest jitter while
consuming several times less power as well as active area.
To make a fair comparison between in-band phase noise £inband in PLL designs, the dependency of £in-band on fRef and N
should be normalized out [7]. The normalized £in-band of this
design is >12dB lower than that of [4-6], at a low loop
power.
This Work
Output Frequency
[6]
[5]
[4]
2.2 GHz
3.67 GHz
3.125 GHz
10 GHz
Ref. Frequency fRef
55 MHz
50 MHz
RMS Output Jitter
0.15ps(10k-40M) 0.2ps(1k-40M)
0.56ps(1k-50M) 0.22ps(10k-20M)
62.5 MHz
2.5 GHz
In-band Phase
Noise £in-band
-126 dBc/Hz
@ 200kHz
-108 dBc/Hz
@ 400kHz
-108 dBc/Hz
@ 100kHz
-109 dBc/Hz
@ 600kHz
Normalized In-band
-235 dBc/Hz2
Phase Noise [6]
@ 200kHz
=£in-band-20logN-10logfRef
-222 dBc/Hz2
@ 400kHz
-220 dBc/Hz2
@ 100kHz
-215 dBc/Hz2
@ 600kHz
Power Consumption
7.6 mW
39 mW
25 mW
81 mW
Active Area
0.18 mm2
0.95 mm2
0.43 mm2
0.71 mm2
Technology
0.18-μm CMOS
0.13-μm CMOS 0.13-μm CMOS 0.18-μm CMOS
ACKNOWLEDGMENT
The authors would like to thank A. Djabbari, G. Socci,
K.Y. Wong for useful discussions, G. Wells for layout
assistance, G. J. M. Wienk, H. de Vries, for practical
assistance, and X. Wang for impractical assistance.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1
10
FO
M
Jitter Variance σt2 (ps)2
FO
M
0
10
FO
M
=-
=-
=-
FOM = 10 log[(
22
0d
B
1s
)2 ⋅
P
]
1mW
’98_23.5
23
0d
B
24
0d
B
σt
’06_32.5[5]
’07_17.1
’00_12.5
-1
10
FO
M
’08_19.1[6]
=-
’04_5.5
’03_10.3[4]
This work
25
0d
B
-2
10
0
10
10
1
2
Power P (mW)
10
4
3
10
Fig. 10. Jitter and power comparison between this work and the classic
PLLs.
IV. CONCLUSION
The design and measurement of a fully integrated 2.21GHz PLL in a standard 0.18-µm CMOS process has been
presented. This PLL employs a sub-sampling based PD/CP
that sub-samples the high frequency VCO output with the
low frequency reference clock. It is shown that, different
from the classical PLL, the PD/CP noise is not multiplied
by N2 in this sub-sampling PLL, resulting in a low noise
contribution from the PD/CP. Moreover, no frequency
divider is needed in the locked state thus divider noise and
power are eliminated. Operating under 1.8V, the PLL core
consumes 4.2 mA. With a 55.25MHz reference, the
measured in-band phase noise of the 2.21 GHz PLL is -126
dBc/Hz at 200 kHz offset. The rms output jitter integrated
from 10 kHz to 40 MHz is 0.15 ps.
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