Design and Phase Noise Analysis of a Multiphase
6 to 11 GHz PLL
George von Bueren, David Barras, Heinz Jaeckel
Alex Huber
Electronics Laboratory, ETH Zürich
CH-8092 Zürich, Switzerland
University of Applied Sciences Northwestern Switzerland
CH-5210 Windisch, Switzerland
Christian Kromer
Marcel Kossel
Aprius Inc.
CA 94085 Sunnyvale, USA
IBM Zurich Research Laboratory
CH-8803 Rüschlikon, Switzerland
Abstract—This paper presents the design, the phase noise
analysis and measurement results of a fourth-order phaselocked loop (PLL) circuit. The PLL is composed of a four-stage
inductorless ring oscillator, a 1/16-divider, phase-frequency
detector (PFD), charge pump and loop filter, which all are fully
differential circuits. A tuning range of 6 to 11 GHz is achieved
using delay interpolation elements in the ring oscillator. For
jitter minimization, we analyze the noise contribution of each
building block, identify the largest noise contributors, and
evaluate the total PLL phase noise in s- and z-domain. The
measured RMS jitter of 18 mUI agrees well with the predicted
value of 15 mUI from our noise analysis. The PLL is fabricated
in 90-nm bulk CMOS, consumes a current of 45mA at 1.1V and
occupies an area of 0.1 mm2.
Keywords: CMOS analog integrated circuits, jitter, phase
locked loops, phase noise, voltage controlled oscillators.
I.
INTRODUCTION
Multiphase PLLs are often used for reference-clock
multiplication in transmitters and receivers of serial I/O-links
[1], [2]. Ring oscillators provide multiple clock phases [1]-[3],
consume less area and typically achieve a larger tuning range
than LC oscillators. However, ring oscillators suffer from
increased phase noise compared to LC oscillators. In
applications where a low-noise reference clock is available, a
high PLL bandwidth helps to reject the phase noise of the
voltage controlled oscillator (VCO) over a wide bandwidth.
To avoid stability problems, the well-known rule-of-thumb is
to choose the PLL closed-loop bandwidth fPLL to be less than
one tenth of the reference frequency fREF [4]. As a
consequence, the multiplication factor N of multiphase PLLs
with ring oscillator and large PLL bandwidth is generally
lower than 10 [1], [2]. For example, a 2-GHz PLL employing
a ring oscillator and N = 5 achieved a root mean square (RMS)
jitter of 4.2 mUI [1]. For higher multiplication factors N, the
in-band phase noise increases and the maximum possible PLL
bandwidth decreases. Reported RMS jitter values of
multiphase ring oscillator PLLs with multiplication factors of
This work was supported by the Swiss Federal Office for Professional
Education and Technology, contract/grant number KTI 7995.1
eight [2] and sixteen [3] and operating ranges of 4.3-7.4 GHz
and 9.6-12.8 GHz are 10 mUI and 20 mUI, respectively. Both
PLLs were implemented in 90-nm SOI CMOS and
incorporate a three-stage differential ring oscillator that
provides six clock phases. In this paper, we present a PLL
with an inductorless four-stage differential ring oscillator that
operates between 6 and 11 GHz. Our paper discusses the
design of this ring oscillator using delay interpolation as well
as of other PLL blocks such as the differential charge pump.
This PLL design was then used for a detailed phase noise
analysis of each building block in the s- and z-domain. Our
analysis enables the determination of the largest noise
contributors and a precise prediction of the PLL phase noise
and RMS jitter.
II.
PLL DESIGN AND PHASE NOISE ANALYSIS
The block diagram of the PLL realized is shown in Fig. 1.
The four-stage differential ring oscillator generates eight clock
phases Ψ0…Ψ7 spaced by 45°. Depending on the phase
difference between reference and divided clock, an amount of
charge is pumped into or out of the passive loop filter, which
has an impedance ZLF = (R+(sC1)-1) || (sC2)-1. All circuit blocks
use differential signaling to generate less noise on the supply
voltage and to have a higher immunity to common-mode noise
such as supply and substrate noise.
REFERENCE
RIP
RIN
DIP
DIN
P
F
D
ZLF
UPP
UPN
VFAST
iCPP
CP
DNP
DNN
VCPP
VCPN
iCPN
loop filter
ZLF
V-Vconverter
DE
VSLOW
ringBUF2
oscillator
Ψ0
:2
:2
:2
divider
DE
DE
DE
BUF2
BUF2
BUF2
Ψ4 Ψ1
Ψ5 Ψ2
Ψ6 Ψ3
:2
OUTPUT
dummy loads
Fig. 1 Architecture of the multiply-by-16 PLL
Ψ7
A. Four-stage Differential Ring Oscillator
Ring oscillators based on differential amplifiers using
NMOS differential pairs and PMOS loads provide a tuning
range larger than one octave. However, the delay of one stage
can alter significantly because of process variations, and thus
the maximum oscillation frequency might be lower than the
required 10±1 GHz. Another approach for tuning ring
oscillators with lower dependence on process spread is based
on delay variations by interpolation [5]. Each delay element
(DE) consists of a CML buffer (BUF1) and an interpolator
(INT) as shown in Fig. 2(a),(b). If the differential control
voltage VFAST – VSLOW is at its upper limit, only the fast path is
active and the slow path is disabled [Fig. 2(a)], yielding the
maximum oscillation frequency of fosc,max. At the other
extreme as shown in Fig. 2(b), the minimum oscillation
frequency is fosc,min. As shown in Fig. 1, a voltage-to-voltage
(V-V) converter is inserted between the charge pump and the
ring oscillator. This converter circuit, depicted in Fig. 2(c),
adjusts VFAST and VSLOW, which define the currents in the
interpolator in Fig. 2(d). The simulated tuning ranges for
nominal, worst-case (R large, NFET slow) and best-case
(R small, NFET fast) process conditions taking wiring R and C
parasitics into account are 6-12, 5-11, and 8-14 GHz,
respectively. The VCO transfer function KV(s) includes a pole
ωVCO due to the V-V-converter.
The SSB phase noise power spectral density (PSD) LVCO(f)
has been simulated with SpectreRF Pnoise (periodic noise)
small-signal analysis based on the periodic steady-state
solution and predicted by analytical calculations based on [6].
LVCO(f) for the fast and the slow path are depicted in Fig. 3(a)
and (b), respectively. The simulated phase noise contribution
due to thermal noise only has been determined by forcing
SpectreRF to turn off flicker noise, while the control voltages
VSLOW, VFAST and v2 are connected to constant voltage sources.
As shown in Fig. 3(a), the simulated (SpectreRF, solid line)
and the analytically predicted (Eq. (60) in [6], dotted line)
results for the thermal noise contribution only match exactly in
the case where the fast path is active. The simulated and
predicted phase noise including flicker noise of the transistor
iFAST
INT
INT
INT
INT
BUF1
BUF1
BUF1
INT
INT
INT
BUF1
BUF1
BUF1
VFAST
BUF1
Mf
(a)
V-V-conv.
iSLOW
INT
VSLOW
BUF1
Ms
V-V-conv.
v2noise
v2
(b)
(d)
(c)
due to
replica
Replica
BUF1
RI
300Ω
ion
VCPP
VCPN
iSLOW
VSLOW
Ms
fp
iop
Mdf
fn sp
Mds
sn
iFAST
v1
VFAST
VFAST
VSLOW
Mtf
Mts
Mf
Fig. 2. Simplified schematic of the delay interpolating ring oscillator:
(a) fast path, (b) slow path. (c) V-V-converter. (d) interpolator (INT).
(a) L
VCO
0
[dBc/Hz], fast path
0
simulated
← SPECTRE-RF
← predicted
↑
(analytic)
-100 thermal noise only
10
5
6
7
8
10
10
10
Frequency [Hz]
← with noise on v2 (sim.)
← v : no noise (sim.)
-50
-50
-150 4
10
(b) LVCO [dBc/Hz], slow path
2
↑
-100
thermal noise only
9
10
-150 4
10
10
5
6
← predicted
(analytic)
7
10
10
10
Frequency [Hz]
8
9
10
Fig. 3. Predicted(dotted) and simulated LVCO(f): (a) Fast and (b) slow path.
Mf, Eq. (60) + Eq. (64) in [6], are also in good agreement. For
the slow path, the predicted (modified analytical expressions
of [6], dotted) and simulated (solid) phase noise due to flicker
noise of Ms and the thermal noise of the delay stages are in
good agreement as well. The total simulated phase noise
(dash-dotted line) is 4 dB higher because of the additional
noise on v2 generated by the replica bias circuit, as can be seen
in Fig. 2(b). The above analysis allows a precise calculation
and prediction of the noise contribution of the ring oscillator
due to the V-V-converter, the buffers and interpolators at
fosc,min and fosc,max. Therefore, to reduce the phase noise the
analysis above suggests that one needs to reduce the flicker
noise in the diode-connected FETs in the V-V-converter,
minimize the current mirror multiplication factors mslow, mfast,
decrease the load resistors RI and RB, increase the tail currents,
and lower the transconductances of the tail current sources.
B. Asynchronous 1/16-Divider
The phase noise of the asynchronous 1/16 divider
consisting of four 1/2 static CML frequency dividers
accumulates after each stage. This behavior becomes an issue
especially when correlated noise affects every stage.
Therefore, the noise on the common bias line of all divider
stages has to be kept as low as possible. To determine the PSD
of the phase noise of the 1/16 divider SΦ,DIV(f), each 1/2 stage
is characterized individually by performing SpectreRF strobed
PNoise simulations and combined by accounting for the
increasing period of the signal after each stage [7].
C. Differential PFD and Charge Pump
To obtain zero systematic timing mismatch between the up
and down pulses the PFD is designed symmetrically and
differentially. The schematic of the fully differential charge
pump employing current steering is illustrated in Fig. 4. Since
the supply voltage is only 1.1 V the use of thick-oxide MOS
transistors or cascode current sources is precluded. To adjust
the output common-mode voltage, a half-replica bias circuit
(M1r, M2r, M3r) is used instead of a common-mode feedback
(CMFB) circuit. This approach has two benefits. First, the
loop filter ZLF has no influence on the replica bias feedback
loop. In a CMFB implementation, any change of ZLF would
alter the loop behavior of the CMFB loop and could create
stability problems. Second, the replica feedback loop
bandwidth can be chosen independently of the PLL
bandwidth. The realization of the differential-in differentialout charge pump is simplified and enables the implementation
of a low-area-consuming replica bias circuit (M1r, M2r, M3r,
M7, M8) without the need for any compensation capacitance.
M4
VCPN
iCPP
ICPN
UPP
UPN DNN
M2a
M2b
M1a
M2r
M7b
M7a
M2d
vb1
M1b
2
Si,CPcalc
↓
Si,CP [A2/Hz]
↓
-22
M1
M3
M4
M5
M6
-24
10
-26
10
2
10
3
10
M1 M3
↓ ↓
KPLL x 1015
6
4
2 LPLL ( f )df
0.0 0 .016
2
2
4
-1
ωz
fw
1MHz
JRMS=15mUI
2
s-domain
z-domain
s-domain with T , T
6 8
x 10 -8
(d) f PLL [MHz]
8
6
fPLL=50MHz
60
4
2
20
2
4
-1
ωz
40
fb
10MHz
50
6 8
x 10-8
(e) Phase margin [º]
8
6
4
Phase
margin: 42º
40
2
2
4
-1
ωz
30
6 8
x 10-8
Fig. 6. (a) Equations: SSB phase noise PSD LPLL and RMS jitter JRMS.
(b) Continuous-time and discrete-time noise transfer functions.
Countour plots: (c) RMS jitter, (d) PLL bandwidth, (e) Phase margin
D. Phase Noise Analysis in s- and z-Domain
The loop filter parameters R, C1 and C2 can be chosen to
achieve minimal RMS jitter, which is important for this
application. Other PLL characteristics, e.g., lock time,
sideband spurs, and amount of jitter peaking are not critical in
this application. Knowing the different PSDs of the PLL noise
sources, the PSD of the PLL phase noise LPLL and RMS jitter
JRMS can be predicted with the continues-time or discrete-time
noise transfer functions [8]. The equations are given in
Fig. 6(a). The detailed analysis about minimizing RMS jitter
of third-order PLLs [9] concluded that the RMS jitter depends
on the loop gain KPLL, the zero frequency ωz = (RC1)-1, the
ripple pole ωp2 ≈ (RC2)-1 and the loop delay. In our analysis,
we included the forward delay Tfw, feedback delay Tfb and in
addition the pole ωVCO due to the V-V-converter, which is not
present in [9]. This additional pole increases the order of our
PLL to four. Fig. 6(b) shows the continuous-time and discretetime closed-loop transfer function HREF. This clearly
demonstrate that the loop delay effects, modeled by the terms
exp(-sTfw) and exp(-sTfb) in the s-domain, have to be taken
into account to determine the phase margin and phase noise
correctly. The contours of the calculated RMS jitter JRMS, PLL
closed-loop bandwidth fPLL and phase margin for various
values of ωz and KPLL for the specific cased N = 16 are
illustrated in Fig. 6(c), (d) and (e), respectively. The smallest
integrated RMS jitter between 1 kHz and 100 MHz keeping a
phase margin > 40° amounts to 15 mUI as illustrated by the
round markers. The PLL bandwidth fPLL is around 50 MHz. In
addition, predicted RMS jitter values of PLLs with
multiplication factor N = 4, 8 or 16, fixed ripple pole
fp2 = fref/12 and a phase margin > 40° are listed in Table 1. As
expected, the RMS jitter is lower for larger fPLL and smaller N.
M6 →
↑
M2
M4,M5 →
TABLE I.
Rs
↓
4
8
24dB
50
Si,CPsim
10
f Low
15
0.0
-20
∫
f High
(c) RMS jitter [UI]
The current noise at the output of the charge pump due to
the PFD/CP circuit also contributes to the PSD of the PLL
phase noise LPLL. As its PSD Si,PFD/CP(f) is low-pass-filtered,
the most important noise contributors are flicker and thermal
noise, whereas induced gate noise can be neglected. The PSD
Si,PFD/CP is determined numerically by a SpectreRF Pnoise
analysis. To identify the largest noise contributors, the PSD of
the current noise Si,CP(f) of the charge pump alone is
determined by conventional noise analysis techniques using
analytic descriptions of the noise sources involved and the
noise transfer functions. Furthermore, the relative contribution
to LPLL due to the simulated combined PFD/CP noise and the
analytically calculated charge pump noise alone is compared.
By inspecting the small-signal-equivalent circuit of the
simplified charge pump circuit, we recognize that in6, the noise
source of the current mirror reference, is low-pass-filtered by
the capacitance at node vb1, which is the reference voltage of
the mirror. Furthermore, noise contributions in4 and in5 are
filtered by the capacitance at node vb2. The analysis showed
that the current sources M1, M3-M6 are the dominant noise
contributors of the charge pump. Their individual
contributions towards lower frequencies have nearly equal
PSDs as shown in Fig. 5. The influence of M2 is by a factor of
10 lower than that of M1 although the flicker noise current of
M2 is 500 times higher than the one of M1 because of the
difference in transistor size. This behavior is due to the fact
that transistor M2 and the output resistance of M1 and M3
form a common-source stage with source degeneration. Fig. 5
also compares the calculated Si,CPcalc(f) (solid line) with the
simulated Si,CPsim(f) (dashed line, small signal noise
simulation). The noise analysis of the charge pump
demonstrated that the most important noise contributor to
charge pump noise are the current sources M1a,b and M3a,b
(Fig. 4). Thus, large transistors for M1 and M3 can be justified
because the flicker noise PSD and also the systematic error
between iCPP and iCPN will be reduced.
10
2
1
J RMS [ UI ] =
2π
Fig. 4. Schematics of the charge pump.
| (4th-order)
REF
2
+ H CP Si,PFD/CP + H LF S v,LF
LPLL (f ) = SΦ ,PLL (f ) 2
VrefCM
2
|H
2
+ H VCO SΦ ,VCO + H DIV SΦ ,DIV
M6
M1r
M5
(b)
28dB
2
SΦ ,PLL = H REF SΦ ,REF
ICPB
0.11mA
M8b
M8a
DNP
M2c
(a)
M3r
VrefCM
KPLL x 1015
M3b
KPLL x 1015
vb2
M3a
VCPP
5
6
10
10
10
Frequency f [Hz]
7
10
8
10
Fig. 5. Calculated and simulated PSDs of the charge pump current noise.
N
4
8
16
PREDICTED RMS JITTER FOR PLLS WITH N = 4, 8 AND 16.
fref
2.5 GHz
1.25 GHz
625 MHz
JRMS (fPLL = 0.05·fref)
6 mUI
10 mUI
15 mUI
JRMS (fPLL = 0.1·fref)
6 mUI
9 mUI
14 mUI
SSB Phase Noise [dBc/Hz]
-80
L
PLL
flow ...fhigh[Hz] 103...105 105...107
JPFD/CP 1.1mUI 3.8mUI
JDIV 1.4mUI 2.3mUI
JVCO 0.05mUI 4.3mUI
7
10 ...10
8
3
10 ...10
7mUI
1.2mUI
10mUI
8
8mUI
3.2mUI
11mUI
draws 45 mA from a 1.1 V supply. The die area is
300×350 μm2. The measured RMS jitter value of the presented
work is comparable with the one with N = 16, three
differential stages and half the tuning range [3]. The predicted
RMS jitter value of this CMU with N = 8 is equal to that of the
PLL with N = 8 and three differential stages [2].
-100
L
L
-120
10kHz
IV.
↑
PFD/CP
L
VCO
↓
L
100kHz
↑
↑
L
DIV
↑
LF
REF
1MHz
10MHz
Fig. 7. Measured and predicted (LPLL) SSB phase noise PSD at 10 GHz.
III.
MEASUREMENT RESULTS
The measured phase noise of the implemented PLL, the
predicted phase noise contributions from all the circuit blocks,
and the analytically calculated RMS jitter values of the
PFD/CP, divider and VCO are shown in Fig. 7. The
contributions of the reference clock LREF and the thermal noise
of the resistance of the passive loop filter LLF are very small as
the multiplication factor N = 16 still is small. As expected, the
phase noise of the VCO is the largest and predominant
contributor, with a jitter contribution JVCO = 11 mUI. But also
the noise sources of the divider (JDIV = 3.2 mUI) and PFD/CP
(JPFD/CP = 8 mUI) are of significance and cannot be neglected.
One reason is the high value of the flicker noise corner
frequency of deep submicron CMOS devices. Flicker noise is
of particular issue for this charge pump topology because the
output of the charge pump is connected to the passive loop
filter for the entire reference period. Another reason for the
high noise content in the current sources is the relatively small
values of VGS - VTH of the current sources due to the low supply
voltage. The difference of LPLL at smaller offset frequencies
(<400 kHz) has practically no influence on the resulting RMS
jitter. The integrated RMS jitter between 1 kHz and 100 MHz
of the measured LPLL is 16 mUI, which is 1 mUI higher than
predicted. The jitter histogram measured with a sampling
scope is shown in Fig. 8. The RMS jitter of the oscilloscope
alone is lower than 0.2 ps thanks to a precision time base. The
RMS and peak-to-peak jitter of the PLL are 18 mUI and
0.13 UIpp, respectively. Hence, the reference spurs of –
41 dBc (not shown) cause less than 2 mUI out of the total
18 mUI RMS jitter. The PLL alone without the 50 Ω buffer
The purpose of this work was to demonstrate a 6-11 GHz
four-stage ring oscillator locked to a clean reference clock.
The proposed inductorless interpolation delay element in the
ring oscillator allows the delay of each stage to be varied over
a large range between 11 and 20 ps. As the jitter in a PLL is
accumulated we performed a detailed noise analysis of each
circuit block to identify the noise sources that have an
uncorrelated and a correlated impact, e.g. on all stages of the
ring oscillator. Noise power spectral densities of the ring
oscillator and the charge pump that have been predicted by
analytical calculations are in good agreement with simulation
results. PLL phase noise and RMS jitter have been evaluated
accurately and optimized with classical phase domain
analysis, including loop delay and parasitic poles for PLLs
with multiplication factors N = 4, 8 and 16. The experimental
results of the integrated 10-GHz PLL with a clean reference
frequency of 625 MHz showed excellent agreement with the
predicted power spectral density of the PLL phase noise LPLL
and RMS jitter, confirming the validity and quality of the
models.
ACKNOWLEDGMENT
The authors thank C. Menolfi, T. Morf, L. Rodoni,
T. Toifl, M. Schmatz, S. Wehrli and J. Weiss for fruitful
discussions, and U. Egger and M. Lanz for designing and
manufacturing the test substrate.
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[3]
[4]
[5]
[6]
[7]
[8]
[9]
Fig. 8. Jitter histogram at 10 GHz.
Horizontal scale: 10 ps/div. Vertical scale: 50 mV/div
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