Vol. 34, No. 4
Journal of Semiconductors
April 2013
Analysis of the dV /dt effect on an IGBT gate circuit in IPM
Hua Qing(华庆)1; Ž , Li Zehong(李泽宏)1 , Zhang Bo(张波)1 , Huang Xiangjun(黄祥钧)2 ,
and Cheng Dekai(程德凯)2
1 State
Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology
of China, Chengdu 610054, China
2 Midea Air-Conditioning & Refrigeration Research Institute, Foshan 528311, China
Abstract: The effect of dV /dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is
shown that a voltage slope applied across the collector–emitter terminals of the IGBT can induce a gate voltage spike
through the feedback action of the parasitic capacitances of the IGBT. The dV /dt rate, gate–collector capacitance,
gate–emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher
dV /dt rate, gate–collector capacitance, gate resistance and lower gate–emitter capacitance is more prone to dV /dt
induced self turn-on. By optimizing these parameters, the dV /dt induced voltage spike can be effectively controlled.
Key words: IGBT; dV /dt ; voltage spike; IPM
DOI: 10.1088/1674-4926/34/4/045001
EEACC: 2570
1. Introduction
The intelligent power module (IPM) is nowadays widely
used as the power inverter circuit for appliance motor drive
systems such as frequency-alterable air-conditioners, washing
machines, and refrigerators. It is an advanced hybrid integrated
circuit (IC) which contains power devices, driver IC and protection circuits. Due to their excellent performance, insulated
gate bipolar transistors (IGBTs) are commonly employed as the
power switching devices of the IPM, where they are required to
switch on and off at high frequencies in order to reduce switching dissipation and improve system performanceŒ1 . However,
this fast switching transient can lead to problemsŒ2 5 . One of
the main issues caused by this switching transient that should
be considered to properly design the IPM is the dV /dt problemŒ3; 5 11 . In the three-phase full-bridge IGBT inverter stage
of the IPM, during the turn on transient of the high-side IGBT,
there will be an abrupt voltage slope (dV /dt) applied across the
collect–emitter terminals of the low-side IGBT. This dV /dt can
cause a current that flows into the gate drive circuit through the
parasitic capacitances of the low-side IGBT, which leads to the
increase of the gate–emitter voltageŒ9; 11 . Even worse, if this
unwanted voltage spike exceeds the threshold voltage of the
low-side IGBT, an arm shoot through will occur, which threatens the reliability of the IGBT and IPM.
In order to improve dV /dt immunity, increase the reliability of both the IGBT and IPM itself, it is therefore necessary to
explore the theory behind the dV /dt induced problem.
In this paper, an IGBT-based IPM which is used in a
frequency-alterable air-conditioner system is proposed as the
research subject and the dV /dt effect on the IGBT gate circuit with respect to the real application circuit is investigated.
Moreover, discussions are conducted for the analyzed results,
working principle and causes of the problem, which provide
a design reference to improve the reliability of the IGBT and
IPM.
2. Circuit schematic and principal analysis
Figure 1 illustrates the simplified circuit schematic of the
three-phase full-bridge inverter of the IPM and the corresponding photograph of the IPM is shown in Fig. 2. The inverter employs IGBT1–IGBT6 as the power switching devices which
are arranged in three legs: U (IGBT1, IGBT4), V (IGBT3,
IGBT6), W (IGBT5, IGBT2), each with its own anti-parallel
free-wheeling diode (FWD) FWD1–FWD6.
In order to analyze the dV /dt performance, a relevant circuit is shown in Fig. 3. In this Figure, the dV /dt generated
circuit is formed by V1 , V2 , R1 , R2 and M2. Also, a PSpice
model for IGBT is introduced. Since the IGBT is essentially a
power MOSFET with an added semiconductor layer in series
with the collector, it is suitable to emulate the basic function of
the IGBT by a power MOSFET M1 in series with a PNP transistor Q1 connected as in Fig. 3. The collector–emitter diode,
collector–emitter capacitance and breakdown features of the
IGBT are emulated by D1 and D2. RC and RE indicate the collector and emitter resistances of the IGBT respectively. CGC
and CGE are the parasitic gate–collector capacitance and gate–
emitter capacitance of the IGBT respectively. RG is the gate
resistance and RDS.on/ indicates the resistance of the driver IC.
In addition, stray inductance in the circuit from PCB tracks and
die bonding wires of the IGBT are lumped together and represented by LS .
Referring to the circuit shown in Fig. 3, when the M2 turns
on, there will be a sudden voltage slope (i.e. dV /dt ) applied
across the collector–emitter terminals of the IGBT. In this case,
* Project supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (No.
2011ZX02504).
† Corresponding author. Email: huaqing2014@126.com
Received 13 August 2012, revised manuscript received 23 October 2012
© 2013 Chinese Institute of Electronics
045001-1
J. Semicond. 2013, 34(4)
Hua Qing et al.
Fig. 1. Simplified circuit schematic of three-phase full-bridge inverter.
power dissipation. Moreover, if this voltage spike exceeds the
threshold voltage of the IGBT, the device may self turn on,
then the high-side IGBT and low-side IGBT will conduct simultaneously, resulting in an arm short through and threaten
the reliability of the IGBT and IPMŒ9 .
From the equivalent circuit shown in Fig. 3, the circuit
equations are given as follows:
CGC
dVCE
dt
CGC
dVGE
dt
CGE
dVGE
dt
iG D 0;
(1)
diG
iG RDS.on/ D 0;
(2)
dt
where iG is the gate current of the IGBT. So, the gate–emitter
voltage VGE of the IGBT can be deduced from the above expressions and is given as follows:
VGE
iG RG
LS
Fig. 2. Photograph of the IPM.
VGE
D
VCE
1
exp
s.RG C RDS.on/ /CGC
:
RG C RDS.on/
C s.RG C RDS.on/ /.CGC C CGE /
LS
(3)
When the value of the parasitic inductance LS is very small
compared with that of the gate resistance RG CRDS.on/ , the VGE
can then be simplified by:
VGE D .RG C RDS.on/ /CGC
1
Fig. 3. Simulation-assisted circuit to analyze the dV /dt performance.
the dV /dt can coupling into the gate circuit induces a current
that flows in CGC , RG , LS and RDS.on/ as shown in Fig. 3, and
leads to a transitory voltage spike across the gate–emitter terminals of the IGBT. The voltage spike between the gate–emitter
terminals of the IGBT is related to many parameters such as
the applied dV /dt across the collector–emitter terminals, the
parasitic capacitances of the IGBT and the impedance of the
gate drive circuit. This voltage spike can cause an increase of
exp
dVCE
dt
t
.RG C RDS.on/ /.CGC C CGE /
: (4)
In the above equation, it can be noted that the VGE is directly affected by dVCE /dt , CGC and RG , which could also be
seen in Figs. 4–6. If the gate driver resistance RG of the IGBT is
too high, then during the dVCE /dt transient, there will be a high
voltage spike between the gate–emitter terminals of the IGBT
and it is getting worse by the fact that the dVCE /dt is changing
fast or CGC is high. So, the value of these parameters should be
chosen carefully.
In the case that the value of RG is very low, then a resonant
circuit will be formed by RG , RDS.on/ , LS , CGC and CGE , which
045001-2
J. Semicond. 2013, 34(4)
Hua Qing et al.
Fig. 6. Simulated voltage spike versus RG .
Fig. 4. Simulated voltage spike versus dV /dt rate.
Fig. 5. Simulated voltage spike versus CGC .
causes a voltage oscillation of the gate drive circuit as could be
seen in Fig. 6.
A numerical simulation has been carried out with PSpice
software to qualitatively analyze the dV /dt effect. Several primary factors dV /dt , CGC and RG that influence the gate voltage spike were analyzed and the simulation results are shown
in Figs. 4–6.
The dV /dt induced gate voltage spikes for different dV /dt
rates were simulated when RG D 100 , LS D 100 nH, RDS.on/
D 1 m, CGC D 10 pF and CGE D 700 pF. The simulation
results are illustrated in Fig. 4. Obviously, the dV /dt itself has
a direct impact on the voltage spike. If a rapid dV /dt is applied
across the collector–emitter terminals of the IGBT, since the
higher dV /dt rate always generates a larger displace current,
there is a quick rise rate of the voltage spike. It can be seen
from Fig. 4 that the gate voltage spike is proportional to the
dV /dt rate. A lower dV /dt rate leads to a lower voltage spike.
When the collector–emitter voltage variation rate dV /dt of the
IGBT is 200 V/s, there is a high voltage overshoot of about
2.25 V between the gate–emitter terminals of the IGBT, but the
voltage spike duration time is very short, about 0.2 s. When
dV /dt D 50 V/s, the voltage spike decreases to appropriately
1.15 V and the duration time becomes 0.4 s. When dV /dt D
20V/s, there is a significant reduction of the voltage spike,
which is about 0.5V and the duration time increases to about
0.6 s. Therefore, slowing down the dV /dt rate can reduce the
gate voltage spike, but on the other hand, the duration time of
the voltage spike will increase accordingly.
Figure 5 shows the impact of the parasitic capacitances
CGC on the voltage spike when dV /dt D 200 V/s, RG D 100
, CGE D 700 pF, LS D 100 nH and RDS.on/ D 1 m. It is
shown that by reducing CGC from 160 to 10 pF, the gate voltage spike can be reduced by as much as 30%.
In Fig. 6, the simulated results for the dV /dt induced gate
voltage spikes at different gate resistances RG are displayed
when dV /dt D 200V/s, CGC D 10 pF, CGE D 700 pF, LS D
100 nH and RDS.on/ D 1m. It is shown that this parameter
has a significant influence on the behavior of dV /dt . When the
gate resistance RG D 100 , there is an obvious voltage spike
between gate–emitter terminals of the IGBT during the dV /dt
transient, with a gate resistance of only 3 , the gate–emitter
voltage spike is significantly reduced to about 0.5V. However,
the large reduction in RG can produce a ringing in the circuit.
As has been mentioned before, this is due to the resonance of
the gate circuit resistances, parasitic capacitances and stray inductances. Hence, RG is the key factor for achieving optimized
design, it is possible to control the dV /dt induced voltage spike
by choosing an appropriate value of gate resistance RG .
3. Experimental results
According to the previous theoretical analysis and simulation results of the dV /dt effect on the IGBT gate circuit, an
experimental study has been developed to inspect the performance of the dV /dt. Several IGBT devices were investigated
and the parameters of the tested IGBTs are shown in Table 1.
The dV /dt induced gate voltage spikes were tested when dV /dt
D 200 V/s, 50 V/s, 20 V/s, RG D 100 , 20 , 3  and
LS D 100 nH, RDS.on/ D 1 m for devices A, B and C, respectively. The experimental results are given in Figs. 7–12.
Device A and B are non-punch through (NPT) trench IGBTs
and device C is a punch through (PT) planar IGBT. Vth is the
threshold voltage of the IGBT.
It can be seen that the experimental results are similar to
the simulation results shown in the above section. As could be
seen from Figs. 7, 9 and 11, the dV /dt rate has a direct influence on the voltage spike. A higher dV /dt rate leads to a higher
045001-3
J. Semicond. 2013, 34(4)
Table 1. Device parameters.
Device Type
CGE (pF) CGC (pF)
A
NPT700
10
trench
B
NPT1500
92
trench
C
PT-planar
3715
27
Hua Qing et al.
Vth (V)
4.32
3.87
5.65
Fig. 9. Measured voltage spike versus dV /dt rate of device B.
Fig. 7. Measured voltage spike versus dV /dt rate of device A.
Fig. 10. Measured voltage spike versus RG of device B.
Fig. 8. Measured voltage spike versus RG of device A.
voltage spike but a lower duration time. Taking device A as
an example, Figure 7 illustrates the tested waveforms according to changes in the dV /dt rate. The amplitude of the voltage
spike is approximately 1.85 V when dV /dt is 200 V/s, and
it could be very much reduced as the dV /dt rate reduces to 20
V/s. Meanwhile, the duration time of the voltage spike also
increased accordingly. Also, device A features the highest voltage spike compared to the other two devices B and C under the
same conditions and the voltage spike of device C is lowest.
This is because the voltage spike is proportional to the CGC and
inversely proportional to the CGE as is shown in the simulation
results.
The voltage spikes as a function of RG for devices A, B and
C are plotted in Figs. 8, 10 and 12. As seen from these figures,
the experimental results agree with the simulation results that
both the voltage spike and duration time are proportional to the
RG . The higher the RG increases, the higher the gate voltage
Fig. 11. Measured voltage spike versus dV /dt rate of device C.
spike and the wider the duration time. When RG D 100 ,
device A has a very high voltage spike about 1.85 V with a
duration time of about 0.65 s and the voltage spike is observed
reducing to a very small value of about 0.4 V when RG D 3 ,
but at the same time the ringing starts rising rapidly as seen in
Fig. 8. Device B and C have the same changing trend compared
to device A, but it was obvious that device C has the lowest
voltage spike, this is also due to the fact that device C has a
045001-4
J. Semicond. 2013, 34(4)
Hua Qing et al.
54% when the dV /dt rate changes from 200 to 20 V/s at RG
D 100 . In addition, when dV /dt D 200 V/s, decreasing RG
from 100 to 3 , a large reduction of voltage spike in the range
of 79% is expected. Furthermore, since device C has a much
lower CGC and higher CGE compared with device B, its voltage
spike is 66% lower than devices B under the same conditions
dV /dt D 200 V/s, RG D 100 .
Therefore, with the appropriate optimization of these parameters the dV /dt induced voltage spike can be effectively controlled and the research results of this paper could be used as
practical guidance for the design of the IGBT and the IPM.
References
Fig. 12. Measured voltage spike versus RG of device C.
different CGE and CGC compared to devices A and B.
However, we would like to point out that there could be a
difference between the simulation results and experimental results due to the precision of the circuit model and the parameter
dispersion of the IGBTs and other elements. Although the actual situation is much more complicated, this study still gives
some insight for further improvement in the design. Nevertheless, the trends of the simulation results clearly agree with the
experimental results.
4. Conclusion
This paper studies the dV /dt induced voltage spike behavior, the relationship between this voltage spike and the dV /dt
rate, parasitic capacitances CGC , CGE and gate resistance RG
is investigated theoretically, numerically and experimentally.
An analytical formula describing the relationships between the
voltage spike and dV /dt rate, CGC , CGE and RG is derived.
Based on the simulation results it has been verified that the
voltage spike of the low-side IGBT that are caused by the
dV /dt is proportional to the dV /dt rate, gate resistance RG and
gate–collector capacitance CGC of the IGBT, but is inversely
proportional to gate–emitter capacitance CGE of the IGBT. This
conclusion is also validated by the experiment on three IGBT
samples, devices A, B and C. Take device A as an example, the
voltage spike caused by the dV /dt can be reduced by around
[1] Ranstad P, Nee H P. On dynamic effects influencing IGBT losses
in soft-switching converters. IEEE Trans Power Electron, 2011,
26(1): 260
[2] Letor R, Aniceto G C. Short circuit behavior of IGBT’s correlated to the intrinsic device structure and on the application circuit. IEEE Trans Industry Applications, 1995, 31(2): 234
[3] Park S, Jahns T M. Flexible dv/dt and di /dt control method
for insulated gate power switches. IEEE Trans Industry Applications, 2003, 39(3): 657
[4] Takizawa S, Igarashi S, Kuroki K. A new di /dt control gate drive
circuit for IGBTs to reduce EMI noise and switching losses. IEEE
PESC, 1998, 2: 1443
[5] Igarashi S, Takizawa S, Tabata M, et al. An active control gate
drive circuit for IGBT’s to realize low-noise and snubberless system. Proc ISPSD, 1997: 69
[6] Bryant A, Yang S, Mawby P, et al. Investigation into IGBT
dV /dt during turn-off and its temperature dependence. IEEE
Trans Power Electron, 2011, 26(10): 3019
[7] Idir N, Bausiere R, Franchaud J J. Active gate voltage control
of turn-on di /dt and turn-off dv/dt in insulated gate transistors.
IEEE Trans Power Electron, 2006, 21(4): 849
[8] Wu W, Held M, Umbricht N, et al. dv/dt induced latching failure
in 1200 V/400 A halfbridge IGBT modules. IEEE IRPS, 1994:
420
[9] Murata K, Harada, K. Analysis of a self turn-on phenomenon
on the synchronous rectifier in a DC–DC converter. INTELEC,
2004: 199
[10] Yedinak J, Gladish J, Brockway B, et al. A 600 V quick punch
through (QPT) IGBT design concept for reducing EMI. Proc
ISPSD, 2003: 67
[11] Musumeci S, Pagano R, Raciti A, et al. A novel protection technique devoted to the improvement of the short circuit ruggedness
of IGBTs. IECON, 2003, 2: 1733
045001-5