leading
edge
A matter of trust
“No one trusts the
simulation except
the engineer who
By Warren Webb
ontron based its new CP306 CompactPCI
K
Everyone trusts the
processor. Kontron’s new board requires only pas-
test except the
sive cooling methods and touts approximately
engineer who ran
50% lower power dissipation
than its predecessors. The
vendor soldered both the
processor and the memory directly to the CompactPCI
board; thus, the CP306 is suitable for use in harsh environments, such as robotics, mobile data-acquisition systems,
aircraft cockpits, and traindriver cabins. Additionally,
the 1.1-GHz CP306 variant
can operate in the extendedtemperature range of 40 to
85°C.
—Mike Santori,
Business and Technology
fellow and head of softwareproduct strategy
for National Instruments,
in Desktop Engineering,
August 2003
Edited by
Fran Granville
CompactPCI CPU features
low-power M processor
ran the simulation.
the test.”
What’s hot
in the
design
community
3U CPU board on the new Intel Pentium M
In addition to the 1.6-GHz
processor clock rate, the
CP306 design includes a 1Mbyte Level 2 cache, a 333MHz memory-clock rate, and
a 400-MHz system bus. Onboard communications interfaces include Gigabit Ethernet, Fast Ethernet, four USB
2.0 ports, and as many as four
COM channels. The board
also includes a dual ATA100
interface and a CompactFlash
socket. Memory options include a maximum of 512
The CP306 CompactPCI singleboard computer offers a high-performance CPU in a rugged configuration requiring only passive-cooling methods.
Mbytes of DDR-SDRAM/
PC333. The board is available
in single-slot- or two-slotwide versions. The CP306
supports Windows, Linux,
and VxWorks operating systems, and prices start at $3300
(small quantities).
䉴 Kontron America, 1-858677-0877, www.kontron.com.
Two bus converters in quarter-brick space deliver 400W
Vicor’s V•I Chip packaging for dc/dc converters and related products delivers more
power from a smaller volume than do most competitive products. The BCMs (busconverter modules) in this series are isolated dc/dc converters that normally produce
unregulated nominal 12V-dc outputs to power nonisolated POL (point-of-load) converters. Each BCM occupies less than half the pc-board area of and is substantially
thinner than a quarter-brick module resulting in power density as high as 800W/in3.
Now, Vicor has created a product that you can describe as a natural: a pc board
that occupies a quarter-brick footprint and accommodates two BCMs, enabling you
to pull a total of 400W from two 12V outputs that are isolated from the input and
from each other. Because each module delivers almost 17A, the isolation offers the
possibility of reduced voltage drops and I2R losses in the network that distributes the
BCM outputs to the POL devices and can also reduce noise through grounding of
the two BCM outputs at a single point. Prices start at 13 cents/watt (OEM quantities).—by Dan Strassberg
䉴 Vicor, 1-800-735-6200, www.vicorpower.com.
This quarter-brick-format pc
board accommodates two of
Vicor’s bus-converter modules,
enabling you to put two isolated,
200W-output, 12V (nominal) dc
supplies into a pc-board area that
usually accommodates only one
such supply.
www.edn.com
September 4, 2003 | edn 13
leading
edge
Software aims at ending erroneous
and poorly documented calculations
athSoft, publisher of MathCAD, which
M
the company calls the largest selling (based
on number of copies sold) mathematical-software
application for engineers and scientists, has
trademarked the term “calculation management.”
Before you say “so what?” and
complain that EDN shouldn’t
waste your time with such
trivia, read on.
The company points to the
fact that nearly all product designs are based on calculations
and that hardly any companies keep good records of the
formulas they use in their calculations. Therefore, when
product problems develop
and, among other things, the
possibility of recalls and lawsuits arises, designers experience major problems with attempts to reverse-engineer the
calculations.
Moreover, the most popular software for performing
engineering calculations is the
spreadsheet, and MathSoft’s
research shows that virtually
all spreadsheets for this purpose contain at least one error.
A key reason for this problem,
the company asserts, is that
spreadsheets hide the formulas embedded in them, and,
when you make the formulas
visible, they look almost nothing like the equivalent formulas you would write down
with pencil and paper.
Allen Razdow, MathSoft’s
senior vice president of strategic planning, has written a
white paper on the subject,
and you can download it at
www.mathsoft.com/news.
Once you read the paper, you
will understand why MathSoft believes that calculation
management constitutes an
important market that it is
uniquely qualified to serve.
Although MathSoft has introduced products that support calculation management, the company’s latest
product, MathCAD Application Server, offers capabilities
that MathSoft says are unavailable in any other commercial-software package.
Specifically, with the aid of
the Application Server, users
who have on their computers
no special software other than
a standard Web browser without special plug-ins, can view,
modify, and manipulate
MathCAD worksheets. Mathematical formulas appear in
these worksheets as they
would if you wrote them with
pencil and paper, and you can
plug in values to observe their
effect. The Application Server transforms the worksheets
on the fly from MathCAD
.MCD files into interactive
HTML files.
The initial market for the
Application Server, whose
prices start at $13,750, is in
large companies whose products depend heavily on engineering calculations. Aerospace, automotive, and pharmaceutical manufacturers are
examples but are far from the
only ones.
—by Dan Strassberg
䉴 MathSoft Engineering and
Education Inc, 1-617-4448040, www.mathsoft.com.
REFERENCE DESIGN
MONITORS MONITOR POWER
Using the DAK-33 reference
design from Power
Integrations, you can accelerate your design for a lowstandby-power supply for LCD
and CRT monitors. The design
provides an ac/dc flyback
power supply providing power
to 45W yet with standbypower consumption of less
than 1W. Vishay based the
product on its Topswitch-GX
power-conversion IC, and the
12V, 3.75A adapter operates
from a line supply of 90 to
265V ac. Full power efficiency
is better than 83%. This reference design sells for $45.95;
for lower power applications,
the $31.95 DAK-34 provides
an 80%-efficient, 30W, 12V,
2.5A supply.—by Bill Schweber
䉴 Power Integrations Inc, 1408-414-9200, www.powerint.
com.
DILBERT By Scott Adams
Control your power to the
people with the high-efficiency, low-standby-power DAK33 reference design for a linepowered supply yielding as
much as 12V at 3.75A.
䉴 The number of Bluetooth chip-set units will swell from 35.8 million to 575 million from 2002 to 2007, for a five-year compound-annual
growth rate of 74%, according to InStat/MDR. Meanwhile, silicon revenue will rise to $1.7 billion in 2007.
14 edn | September 4, 2003
www.edn.com
leading
edge
Communication consortiums craft new conventions
n recent communications news, the Home-
I
PNA (Home Phoneline Networking Alliance)
finalized HomePNA 3.0, which specifies that
equipment operates at 128 Mbps with optional extensions to 240 Mbps. Key to
the new specification are enhancements to quality of
service, allowing users to assign time slots for individual
data streams for delivery of
real-time data that multimedia applications require. The
alliance is preparing to submit
3.0, which it based on the 2.0
physical layer and which is
fully backward-compatible
with the older spec, to the ITU
(International Telecommunication Union) for adoption.
In other news, the RapidIO
Trade Association announced
plans to expand its application focus to cover data-plane
applications for telecommunications networks. Doing so
targets the spec at applications that had previously been
the domain of HyperTransport or one of the high-speed
flavors of PCI. In a separate
effort, the PICMG 3.5 Subcommittee is reorganizing to
map the RapidIO protocols
onto the AdvancedTCA platform architecture.
In addition, the IEEE approved standard 802.3af-2003
for delivering POE (powerover-Ethernet) cables. The
standard defines legacy installation, ensuring the safe delivery of power to both currently installed devices and
power-enabled terminals;
preservation of the cabling infrastructure by avoiding alteration of wiring; and data integrity, ensuring no loss of
data or degradation because
of power delivery. The standard will support both endspan devices, such as those
embedded in switches, and
stand-alone midspan hubs,
allowing the use of power-enabled terminals without the
need for upgrading currently
installed switches.
In another development,
the PCI-SIG (PCI Special Interest Group) finalized the
PCI Express Mini Card companion specification, outlining a Mini Card form factor
for PCI Express designs in
mobile applications.
Also, the Bluetooth SIG announced that Bluetooth 1.2 is
in the final testing phases.
Backward compatible with
Version 1.1, the new specification features adaptive frequency hopping to reduce interference with other wireless
technologies in the 2.4-GHz
spectrum and enhanced voice
processing to improve quality
of voice in noisy environments using error-detection
methodologies. It also offers
enhanced quality of service to
increase performance of multipoint applications in which
one radio can serve several
clients and an anonymity
mode to increase the security
of Bluetooth links by masking
the physical address of radios
to prevent identity attacks and
snooping.
IBpak, a new multisource
agreement, creates common
specifications for hot-pluggable 4 copper-cable transceivers and 4/12 fiber-optic transceivers that support
InfiniBand-defined ports.
The specification incorporates the electrical, cable, and
fiber-attachment requirements in Volume 2, Release
1.1 of the InfiniBand Architecture specification and adds
definitions for the electricalconnector, package-outline,
guide-rail, hot-swap, test, and
control features. Transceivers
based on this multisource
agreement should function as
transparent, retiming repeaters for board-to-board
and interchassis interconnections.—by Nicholas Cravotta
䉴 Home Phoneline Networking Alliance, www.
homepna.org.
䉴 RapidIO Trade Association, www.rapidio.org.
䉴 PCI-SIG, www.pcisig.com.
䉴 Bluetooth SIG, www.
bluetooth.com.
䉴 IBpak, www.ibpak.org.
TCP terminator takes on 2 million connections
The SW5000 network-content processor from Seaway Networks provides 5-Gbps, full-duplex, full-TCP (Transfer
Control Protocol) byte-stream reconstruction, termination,
or both for applications requiring Layer 4 to Layer 7 processing at multigigabit rates. Applications include firewalls,
intrusion-detection systems, SSL (Secure Sockets Layer) accelerators, virtual-private-network gateways, and content
filters. The device supports zero-copy data management, as
many as 64,000 contexts, and 2 million simultaneous connections. Per-second processing specs are 66 million accesscontrol-list comparisons, 300,000 connection setups,
240,000 Layer 7 switching decisions, or 17-Gbps Layer 5 to
Layer 7 pattern-matching searches.
Software-development tools include a C/C Gnu tool
with an API library based on a sockets interface. They also
include a board-level simulation with cycle-accurate simulation of SW5000. A 6U CompactPCI chassis with SW5000
processor board and four open CompactPCI slots is also
available. The device is currently available for sampling, and
production is scheduled for the third quarter. The SW5000
comes in a 1157-ball BGA package and sells for $645
(1000). The SW5000 development platform, also available
in the third quarter, costs $21,495 and includes one systemI/O module and a two-port Gigabit Ethernet module.
—by Nicholas Cravotta
䉴 Seaway Networks Inc, www.seawaynetworks.com.
䉴 Retail prices for plasma displays have gone from approximately $14,000 in 1998 to approximately $4500 in 2003.—The New York Times,
Aug 18, 2003.
16 edn | September 4, 2003
www.edn.com
leading
edge
Deep-memory, 6-GHz-bandwidth scopes now take
20G samples/sec on four channels simultaneously
eCroy, whose WaveMaster 8600A won every
L
test in EDN’s “Scopes Trial” (Feb 6, 2003, pg
44), has now upgraded the sampling rate of its topof-the-line, 6-GHz-bandwidth scopes. Like the
similar-bandwidth TDS6604
from Tektronix (www.tek
tronix.com), LeCroy’s original
6-GHz units could sample
full-bandwidth signals in real
time only in the two-channel
mode. LeCroy’s newest models, the WM 8620A and the
SDA 6020 join Agilent’s
(www.agilent.com) Infiniium
54855A in the ability to simultaneously sample four
full-bandwidth signals in real
time. Moreover, like the Agi-
lent scope, the LeCroy scopes,
when equipped with four differential active probes, can simultaneously sample four
full-bandwidth differential
signals in real time.
In accordance with LeCroy’s tradition of offering
the industry’s deepest memory options, the 8620A and the
SDA 6020 are available with
memory depths as great as 48
million samples/channel. This
deep memory is available at
all sample rates. The Agilent
scope offers memory as great
as 32M samples/channel, but
you can use that memory
depth only when the scope
samples at less than 10% of its
maximum rate. At higher
sampling rates, the maximum
memory depth is 1M sample/channel. Even with only
the basic memory, the LeCroy
scopes can capture records as
long as 2 million samples/
channel (8620A) or 8 million
samples/channel (SDA 6020).
Prices for the 8620A begin at
$69,500 and for the SDA 6020
at $77,500.
—by Dan Strassberg
䉴 LeCroy Corp, 1-800-4532769, www.lecroy.com.
The WaveMaster 8620A is the
second digital scope to be able to
simultaneously capture four 6-GHz
signals in real time at 20G samples/sec but, with optional memory, is the first scope to be able to
capture four 48 million-sample
records in real time at 20G
samples/sec.
Vendor bucks trend, touts VXI’s overlooked advantages
Bustec is marching to the beat of a different drummer
from that of its best known competitors in modular instrumentation. The company insists that it is traveling the right
road, whereas its competitors are not. At issue is VXI—once
the crown jewel of modular instrumentation and still a major factor in the market, pulling in, according to Bustec,
more than $600 million in equipment sales last year. Nevertheless, companies promoting newer, more charismatic
technologies, such as PXI, have succeeded in implanting the
message that the time for VME-based VXI is over; it’s too
slow, too expensive, and too large to compete in new
applications.
Bustec officials insist that such statements fly in the face
of the fact that VXI is a good match for the most demanding
applications, especially in systems that use USB 2.0 to interface VXI card cages to an external host PC, thus obviating
the need for specialized interface boards in the host. Bustec
officials say that using such a setup with its new Slot-0 VXI
controllers, they have measured sustained transfer rates as
high as 32M bytes/sec from the host, through the backplane,
and to the modules. This figure includes all of the delays associated with the Windows operating system. Moreover,
Bustec points out that its proprietary architecture makes
each module a system in its own right, enabling a single Csized VXI cage to accommodate, for example, thousands of
analog inputs, making VXI’s packaging density much
18 edn | September 4, 2003
greater than that of allegedly more compact architectures.
The Slot-0 controllers the company used in the speed tests
carry prices as low as $2150 for a module that works with a
stand-alone PC host. A combination Slot-0 controller and
1.3-GHz Pentium III-based host with 256 Mbytes of RAM
and an 80-Gbyte hard drive costs $9845. The company also
offers a combination Slot-0 controller and PowerPC-compatible host.
The company has also announced unusual delta-sigma
ADC modules. By implementing the converters’ DSP functions in a high-speed PLD, the company synthesized a converter with a FIR filter instead of the IIR filters that are common in such ADCs. This approach, say Bustec spokesmen,
greatly reduces aliasing problems, which produce anomalies
in certain reconstructed digitized signals. A type of signal
that has always been problematic is a square wave. Despite
oversampling at many times the square wave’s repetition
rate, a typical delta-sigma converter can introduce overshoot
on the signal’s edges. Using a FIR filter in the ADC minimizes the overshoot without requiring an antialiasing filter
that would distort the rise time. The results are digitized signals that you can correctly analyze in the time domain and
that don’t force you to use frequency-domain analysis.
Prices for the four-channel, 16-bit ADC modules start at
$3300.—by Dan Strassberg
䉴Bustec Inc, 1-440-826-4156, www.bustec.com.
www.edn.com
leading
edge
Tools focus on high-speed-pc-board design
adence is taking a system approach to the
C
pc-board market by focusing its tools to serve
the needs of high-speed-pc-board designers. The
company reasons that advanced ICs will need highspeed pc boards, so it is aiming its pc-board tools to
support their development. It
has introduced the Cadence
15.0 pc-board- and IC-packaging-design environment.
The suite of products provides engineers with an environment for designing and
implementing gigabit serial
interfaces in high-speed-pcboard systems. It supports the
simulation and implementation of constraint-driven, differential interconnect from
die to die across IC dies, IC
packages, and pc boards.
New features in the Allegro
layout editor and the SpecctraQuest signal-design and
-analysis environment enable
the simulation and management of differential signals
throughout the entire design
flow. Engineers can design a
comprehensive set of rules
within a constraint-manage-
ment system and then use
those rules to drive layout and
routing.
Designing integral die stacks
helps designers to reduce the
product footprint, integrate
disparate technologies, and reduce time to market. The Advanced Package Designer provides an environment that
allows engineers to design and
edit multiple stacked-die packages and to automatically create wire bonds.
New capabilities in PCB Librarian Expert address electrical-component-library development and management
by using XML for data-driven symbol generation, management, and portability. The
tool also supports the ability
to directly import pin and
package data from data sheets
in .PDF and .CSV formats.
Engineers can validate a part
according to user-definable
company standards, and the
library-management system
tracks changes between part
versions, providing detailed
reporting of differences between revisions.
Designers commonly use
outer-layer ground planes for
shielding, reducing, and supplying selective power to sensitive subcircuits. Because of
their complex manufacturability requirements, creating
and modifying these layers
can be time-consuming. Allegro 15.0 provides an easy-touse, real-time, copper-pouring capability that allows for
dynamic plowing and healing
during interactive or automatic routing. Designers can
edit shapes at any time without the need for re-creating or
postprocessing the layer.
A new Spice-to-Ibis Model
Integrity module in the
SpecctraQuest SI Expert tool
helps users to create Ibis models from Spice models. Model
Integrity identifies IV and
voltage-time tables for typical,
maximum, and minimum
corner cases from the Spice
run file. It employs a best
curve-fitting algorithm to
provide accurate Ibis models
from Spice simulations that
contain more solution points
than the Ibis models allow.
The new release runs on
Solaris, HP-UX, IBM-AIX,
Windows 2000, and XP-Pro.
The PCB Design Studio bundle sells for $4000 for a oneyear-use license. It includes
Concept HDL schematic or
Capture CIS schematic, library management, Allegro
for interactive layout, and the
Specctra autorouter. The PCB
Design Expert for high-speed
design has a yearly license of
$26,000. The bundle includes
Concept HDL Expert or Capture CIS schematic, constraint
and topology management, library management, Allegro
Expert for interactive pcboard layout, and the Specctra
Expert autorouter.
SpecctraQuest SI Expert
has a one-year license price of
$24,200. It provides preroute
and postroute topology extraction and exploration, simulation and verification, constraint and topology management, virtual floorplanning, and interconnect routing.—by Gabe Moretti
䉴 Cadence, 1-408-943-1234,
www.cadence.com.
Virtual-silicon prototyping targets FPGA designs
FPGA designers using the most up-to-date devices must
solve a number of new problems, including the inability to
achieve performance requirements, unpredictable routing
results, routing congestion, tightly packed designs, critical
paths spanning various levels of hierarchy, and heavily constrained interconnect wires. Although digital-ASIC designers can now use virtual-silicon prototyping to address these
problems, FPGA designers have had to solve them using expensive design iterations. To address these problems, Hier
Design has introduced its first product, PlanAhead, a hierarchical floorplanner for FPGA designs.
The tool allows designer to quickly inspect the results of
placing-and-routing logic blocks on an FPGA fabric. It pro-
vides a hierarchical, block-based, and incremental design
methodology, allowing engineers to incrementally change
portions of the design. Working with smaller portions of
the design helps engineers to maintain performance requirements, because results of iterative place-and-route
functions are often unpredictable, particularly when
designers perform them on flattened netlists of the entire chip.
PlanAhead supports the Xilinx Virtex-II and Spartan3
device families. The price for a one-year, time-based license
is $25,000. The product is available on Solaris 5.8, Linux
7.3, and Windows XP operating systems.—by Gabe Moretti
䉴 Hier Design, 1-408-982-8240, www.hierdesign.com.
䉴 The average retail prices for standard DVD players decreased from just over $600 to less than $100 from 1997 to 2003.—The New York
Times, Aug 18, 2003.
20 edn | September 4, 2003
www.edn.com
Fading emulator challenges 3G radios
By Graham Prophet
anufacturers of mobile communications
M
products can now perform comprehensive
evaluation of their designs in response to realworld signal conditions with Spirent’s SR5500
wireless channel emulator.
The 5500 controllably reproduces effects such as time
varying multipath delay
spread, fast fading, slow shallow-signal fading, and channel loss. It provides 24 independent paths and can
evaluate systems based on
CDMA2000, W-CDMA, and
wireless-LAN standards. The
company designed the new
unit in response to the more
complex fading/multipath
testing requirements, including dynamic fading, that
come with the 3G standards—making it “an order
www.edn.com
of magnitude more complex
than for GSM,” according to
Spirent’s business-development director Richard Catmur. It is, he adds, no longer
feasible for even the largest
operators to develop labbased testing solutions inhouse, hence the devolution
of a single-box option in the
5500.
Spirent designed the 5500
as an impairment generator,
not a signal generator that applies impairment to the signal
path. It generates the complete signal, then mixes down
to baseband. A DSP engine
applies calculated impairments, then the signal is returned to RF and applied to
the air interface of the system
under test. In this way, you
can create completely reproducible long pseudorandom
sequences of fading and multipath effects and precisely return to any condition that is
recognised as presenting a
problem. The entire system
is housed in one chassis including local oscillators and
power meters. Channel bandwidth exceeds 25 MHz; cascaded systems can model 48
channels to a timing accuracy
of 0.1 nsec. The frequency
range is to 2.7 GHz, and you
can use a doubler to cover the
802.11a band. The SR5500
costs around $125,000.
Spirent, ⫹1 732 544 8700,
www.spirent.com
September 2003 | edn europe 13
leading
edge
JTAG tool checks out pc boards at first power-up
ou most likely associate
JTAG—IEEE1149.1—with
testing your product in the
late stages of its design cycle;
you may use the test access that
JTAG provides for production
test, and you may therefore be
involved in test generation and
writing test routines. But, according to test-solution vendor
XJTAG, the principles of JTAG
can be useful much earlier in
the design process—in the first
stages of powering up a new
board and getting it to be functional, for example. XJTAG sells
a development system, with
both hardware and software
components, that allows a high
level of verification and circuit
testing of a board before, say, its
host microprocessor is even
running. This practice, the
company says, is becoming ever
more valuable as more devices
move to high-density BGA
packaging and more of the circuit nodes become inaccessible
to physical probing.
To use the system, you design
your board with attention to interconnecting the JTAG chain
for all devices that have JTAG
ports. Normally, you then forget JTAG until it is time to write
the test routines for production
test. XJTAG’s software can take
a BDSL (boundary-scan description language) and netlist
description of the board and
Y
create scripts that allow you to
view information about the
board via a hardware link between its JTAG port and a PC.
XJAnalyser is a circuit-visualisation tool that provides a
graphical view of the state of all
JTAG pins; you can verify the
JTAG chain and set values on
pins or buses of devices in the
chain. This ability allows you to
verify and test more of the devices on a typical board—connecting only power and the
“XJLink” interface module.
You need not run microprocessor software to exercise
may of the parts connected to
the processor, which can circumvent the problem you face
when a board doesn’t start because of a manufacturing fault
or a software problem with the
initial boot-up routines.
A comprehensive connection
test is a built-in feature of the
system.You can also manipulate
non-JTAG devices on the board
using a high-level language
called XJEase. The language is
device-centric; you write scripts
to exercise specific parts in given interconnection scenarios,
and those scripts are reusable in
subsequent designs. The tool
uses the access it has to interconnected non-JTAG parts, via
the pins of JTAG-enabled parts,
to load circuit values and check
functions; reading and writing
14 edn europe | September 2003
memory patterns is a simple example. As with any JTAGenabled board, you can also
use the system to program
EPROMs, flash memory, or
FPGAs.
XJTAG chief technology officer Dominic Plunkett explains
how the company’s approach
differs from the more conventional use of JTAG, noting that
the company seeks to “change
the mindset from thinking of
something you do for [the
downstream use of] the test engineer, to [thinking of] something you do for yourself that is
of great value in the early stages
of hardware design.” Plunkett
says the approach also provides
test engineers with a head start
because you can hand over the
scripts you create to the test department. And it goes a long
way in forming the core of a
production test suite. The
XJRunner product supports
this process.
XJTAG began as a design
consultancy (and maintains
that role). It created the XJTAG
concept as an aid to commissioning complex new circuit
boards. In bringing up a new
board now, Plunkett says, he
uses the system more than either a scope or a logic analyser.
A demonstration board (XJDemo) completes the development package (Ease/Analyser/
Link), which sells for €13,500;
you can evaluate it free for a 30day trial.—by Graham Prophet
XJTAG, ⫹44 1954 211244,
www.xjtag.com
www.edn.com
leading
edge
One-stop for audioprocessing IP
ensaura is a software house that spe-
S
cialises in the physics of spatial hearing; over
several years, it has developed a set of algorithms
that reproduce exact audio environments and
simulate the effect of hearing any given sound at
a chosen position in three-dimensional space.
The company’s software IP (intellectual property) is widely integrated into
multimedia PCs and games
platforms such as Xbox and is
supplied as middleware for
platforms such as PlayStation.
Now, Sensaura is developing an IP-brokering service for
its own and third-party audio
IP with proven performance,
building on its expertise in developing software-based audio solutions on a consultancy basis. A portfolio of audio
IP already contains more than
55 patent filings. Applications
will target the consumer, automotive, and communica-
tions spaces. The business
model will be similar to a standard semiconductor-industry
format of licence fee and royalty; Sensaura aims to act as a
worldwide broker for audio
expertise while developing
commercial solutions for
next-generation products.
The company will charge an
initial development consultancy fee and a quarterly licence fee based on product
sales; it claims to be unusual in
having both engineering and
licensing expertise in one operation.
Minimal modem
further minimised
You can reduce the component count of an integrated
modem to a new minimum with the latest members of
Silicon Laboratories’ ISOmodem device family. You
might use such modems in point-of-sale devices, settop-boxes, or digital televisions, which require the integrated ability to make dial-up data connections.
The new parts (Si2457, 34, 15, and 04) integrate Silicon Labs’ silicon DAA technology to simplify direct connection to a phone line. They give you a one-chip solution for a system that might have required a DSP data
pump, a modem controller, a codec, a transformer, relays, optoisolators, and a two- to four-wire hybrid (depending on the generation of modem chip set). They
also integrate a 27-MHz clock input and PLL, eliminating a crystal. You can design modems that comply in all
territories and operate at 2.4 to 56 kbps. Packaging is in
24-pin TSSOPs, and pricing starts at $7.85 (10,000). An
evaluation board is also available.—by Graham Prophet
Silicon Laboratories, ⫹44 118 965 7670, www.silabs.
com
In particular, Sensaura will
assist in the migration of audio solutions from ASIC platforms to software solutions
running on standard DSPs;
the company has announced a
specific agreement with Texas
Instruments, but it says it also
has experience in all of the
mainstream DSP architectures.—by Graham Prophet
Sensaura, ⫹44 208 848
9779, www.sensaura.com
Leadfree’s long-term impact
Consumer products sold in the European market must change to leadfree
solders by July 2006. More and more
leadfree components are becoming
available, and leadfree processes are
becoming better understood, even if
many companies have yet to use
them. According to research group
TWI, leadfree alloys and the altered
process parameters needed to work
with them may have long-term effects
16 edn europe | September 2003
on the reliability of components and
systems. TWI is setting up a groupsponsored project to investigate these
effects in association with the United
Kingdom’s Open University and University of Greenwich; it will focus on
the leadfree mandate’s impact on
long-life and high-reliability products
and will aim to develop specific testing and modelling methods. The
group will feed results back to spon-
soring companies over a two-year period. TWI (formerly The Welding Institute) is a research organisation specialising in all forms of materials
joining, and has previously researched
soldering techniques.
—by Graham Prophet
TWI, ⫹44 1223 891162, www.twi.
co.uk, or go direct to www.twi.co.uk/
j32k/unprotected/band_1/research_gs
ppr7360_intro.html
www.edn.com