Islamic University – Gaza
Engineering Faculty
Department of Computer Engineering
ECOM 3010: Computer Architecture Discussion
Chapter 5
Exercises with solutions
Eng. Eman R. Habib
December, 2013
2
Computer Architecture Discussion
Exercise 1: (5.1 from book)
Combinational logic only: a, b, c, h, i
Sequential logic only: f, g, j
Mixed sequential and combinational: d, e, k
Exercise 2: (5.2 from book)
3
Computer Architecture Discussion
a. RegWrite = 0: All R-format instructions, in addition to lw, will not work because these
instructions will not be able to write their results to the register file.
b. ALUop1 = 0: All R-format instructions except add will not work correctly because the
ALU will perform addition instead of the required ALU operation.
c. ALUop0 = 0: beq instruction will not work because the ALU will perform addition instead
of subtraction, so the address of branch may be wrong.
d. Branch (or PCSrc) = 0: beq will not execute correctly. The branch instruction will always
be not taken even when it should be taken.
e. MemRead = 0: lw will not execute correctly because it will not be able to read data from
memory.
f. MemWrite = 0: sw will not work correctly because it will not be able to write to the data
memory.
Exercise 3: (5.3 from book)
a. RegWrite = 1: sw and beq should not write results to the register file. sw (beq) will
overwrite a random register with either the store address (branch target) or random
data from the memory data read port.
b. ALUop0 = 1: All R-format instructions except subtract, in addition to lw and sw will not
work correctly because they will always perform subtraction.
c. ALUop1 = 1: lw and sw and beq will not work correctly. they will perform a random
operation depending on the least significant bits of the address field instead of addition
operation necessary for address calculation in lw and sw, or subtraction for beq.
d. Branch = 1: Instructions other than branches (beq) will not work correctly if the ALU
Zero signal is raised. An R-format instruction that produces zero output will branch to a
random address determined by its least significant 16 bits.
‫‪Computer Architecture Discussion‬‬
‫‪e. MemRead = 1: All instructions will work correctly. (Data memory is always read, but‬‬
‫)‪memory data is never written to the register file except in the case of lw.‬‬
‫‪f. MemWrite = 1: Only sw will work correctly. The rest of instructions will store their‬‬
‫‪results in the data memory, while they should not.‬‬
‫)‪Exercise 4: (5.8 from book‬‬
‫‪jr $rs‬‬
‫‪000000 / rrrrr / 00000 /00000 / 00000 / 001000‬‬
‫لما بدنا نضٌف انستركشٌن على السٌنجل ساٌكل اول شً نتزكر شو بتعمل االنستركشٌن و شو فورماتها‪ jr rs ,‬بتعمل‬
‫جمب على االدرٌس المخزن بالرٌجٌستٌر ‪ rs‬و االنستركشٌن تعتبر ‪ R-format‬اول ‪ 6‬بتات حٌكونو اصفار و ال‪ 5‬بتات‬
‫الً بعدهم حٌكونو ‪ rs‬و الباقً كلو اصفار و مش الزمٌن و اخر ‪ 6‬بتات بتحدد الفنكشٌن ‪.‬‬
‫بعدٌن بنشوف شو الزم نعدل على الداتا باث عشان تعمل هً االنستركشٌن‪ ,‬ال ‪ jr‬بتاخد الداتا الموجودة بال ‪ rs‬الً هٌا رح‬
‫تطلع من الرٌجٌستر فاٌل اول رٌجٌسٌتر (‪ ) Read Data 1 port‬و تودٌها على ‪ٌ PC‬عنً الزم نغٌر االنبت اللً جاي‬
‫على ‪ PC‬بدل ما كان من الملتبلٌكسٌر اللً بحدد ناخد من ‪ PC+4‬او ادرٌس البرانش‪ ,‬الزم نضٌف بعدو كمان ملتٌبلكسٌر‬
‫و نحط االنبت االول الو هوا اوتبت الملتبلٌكسٌر القدٌم و االنبت التانً الداتا اللً جاٌة من ‪ Read Data 1 port‬و‬
‫السٌلكشٌن الٌن للمتلٌبلكسٌر بدو ٌكون كنترول سٌجنال جدٌد نسمٌه ‪ JumpReg‬بس مش حنقدر نطلع هاد الكنترول‬
‫سٌجنل من الكنترول ٌونت النو انبت الكنترول ٌونت بس ال)‪ OP (6bits‬و النو ‪ jr‬من ‪ R-type‬فحتكون زي باقً‬
‫االنستركشٌنز اللً ب ‪ R-type‬كلهم اصفار فمش حقدر احدد من ‪ 6 bits‬انها ‪ jr‬و بدل ما نكبر الكنترول ٌونت و نضٌف‬
‫علٌها ‪ function 6 bits‬ممكن ناخد هاد الكنترول سٌجنل من ‪ ALU control‬النو هً بفوت علٌها ‪function 6‬‬
‫‪ bits‬اما االوبٌرشٌن مش رح تهمنً النو ما بدي استخدم ‪ ALU‬فحنضٌف على تٌبل ‪ ALU control‬هاد الالٌن‪:‬‬
‫‪JumpReg‬‬
‫‪1‬‬
‫‪Operation‬‬
‫‪xxx‬‬
‫‪Function field‬‬
‫‪001000‬‬
‫‪ALUOp0‬‬
‫‪0‬‬
‫‪ALUOp1‬‬
‫‪1‬‬
‫‪4‬‬
‫‪Computer Architecture Discussion‬‬
‫و التعدٌل على السٌنجل ساٌكل حٌكون هٌك‪:‬‬
‫)‪Exercise 5: (5.9 from book‬‬
‫‪sll $rd, $rt, SA‬‬
‫‪000000 / 00000 / ttttt / ddddd / sssss / 000000‬‬
‫بدي اضٌف ‪ sll‬اول شً االنستركشٌن ‪ sll $rt, $rd, SA‬بتعمل شٌفت للرٌجسٌتر ‪ $rt‬بقٌمة ‪ SA‬و بتخزن النتٌجة ب‬
‫‪ $rd‬و االنستركشٌن تعتبر ‪ R-format‬اول ‪ 6‬بتات حٌكونو اصفار و ال‪ 5‬بتات الً بعدهم حٌكونو غٌر مستخدمٌن و ال‬
‫‪ 5‬بتات الً بعدهم بكونو ‪ $rt‬بعدٌن ‪ 5‬بتات ‪ $rd‬بعدٌن ‪ 5‬بتات ‪ Shift amount‬و اخر ‪ 6‬بتات بتحدد الفنكشٌن ‪.‬‬
‫بعدٌن بدنا نشوف شو الزم نعدل على الداتا باث عشان تعمل هً االنستركشٌن‪ ,‬بٌلزمنا نعدل على ‪ ALU‬و نحط فٌها‬
‫‪ shifter‬و نزٌد علٌها بورت لل ‪ SA‬عشان تاخد المدخل التانً لل‪ ALU‬و تعملو شٌفت بقٌمة ‪ SA‬ولهٌك الزم اعدل‬
‫على ‪ ALU control‬انو لما ٌكون ‪ ALUOp = 10‬و بتات الفٌنكشٌن ‪ٌ 000000‬عنً ‪ sll‬تطلع ‪ٌ 0000‬عنً الزم‬
‫نضٌف بت جدٌد الوتبت ال ‪ ALU control‬لما ٌكون ‪ 0‬رح ٌاخد اوتبت ال ‪ .Shifter‬و التعدٌل على الداتا باث انو الزم‬
‫اخد بتات ال ‪ Instrection[10-6] SA‬و اودٌهم على البورت للجدٌد لل ‪ .ALU‬و ما رح ٌلزم كنترول سٌجنل جدٌد‪.‬‬
‫وبما انها ‪ R-type‬ما رح ٌكون فً زٌادة على تٌبل ‪. Control unit‬‬
‫‪5‬‬
‫‪Computer Architecture Discussion‬‬
‫و حنضٌف على تٌبل ‪ ALU control‬هاد الالٌن‪:‬‬
‫‪Operation‬‬
‫‪1000‬‬
‫‪Function field‬‬
‫‪000000‬‬
‫‪ALUOp0‬‬
‫‪0‬‬
‫‪ALUOp1‬‬
‫‪1‬‬
‫و التعدٌل على السٌنجل ساٌكل حٌكون هٌك‪:‬‬
‫)‪Exercise 6: (5.10 from book‬‬
‫‪lui $rt, immediate‬‬
‫‪001111 / 00000 / ttttt / iiiiiiiiiiiiiiii‬‬
‫بدي اضٌف ‪ lui‬اول شً االنستركشٌن ‪ lui $rt, immediate‬بتخزن االٌمٌدٌت باخر ‪ 06‬بت من الرٌجٌستر ‪ $rt‬و‬
‫االنستركشٌن تعتبر ‪ I-format‬اول ‪ 6‬بتات بحددو االنسترٌكشٌن و ال‪ 5‬بتات الً بعدهم حٌكونو غٌر مستخدمٌن و ال ‪5‬‬
‫بتات الً بعدهم بكونو ‪ $rt‬بعدٌن ‪ 06‬بت ‪.immediate‬‬
‫‪6‬‬
‫‪Computer Architecture Discussion‬‬
‫ممكن اخد ال‪ 06‬بت اللً باالخر افوتهم على الساٌن اكستٌنشٌن بعدٌن افوتهم على ‪ ALU‬و اخلٌها تعمل شٌفت ‪ 06‬هٌك‬
‫بصٌر االٌمٌدٌت بال‪ 06‬بت اللً باالخر و ال‪ 06‬بت اللً باالول اصفار‪.‬‬
‫بعدٌن بدنا نشوف شو الزم نعدل على الداتا باث عشان تعمل هً االنستركشٌن‪ ,‬بٌلزمنا نعدل على ‪ ALU‬و نحط فٌها‬
‫‪ shifter‬و نزٌد علٌها بورت لل ‪ SA‬نفوت علٌه رقم ‪ “10000” 06‬عشان تاخد المدخل التانً لل‪ ALU‬و تعملو‬
‫شٌفت ‪ 06‬بت ولهٌك الزم اعدل على ‪ ALU control‬انو لما ٌكون ‪ ALUOp = 11‬تطلع ‪ٌ 0000‬عنً الزم نضٌف‬
‫بت جدٌد الوتبت ال ‪ ALU control‬لما ٌكون ‪ 0‬رح ٌاخد اوتبت ال ‪ .Shifter‬و ما رح ٌلزمنً تعدٌل على الداتا باث‪.‬‬
‫و حنضٌف على تٌبل ‪ ALU control‬هاد الالٌن‪:‬‬
‫‪Operation‬‬
‫‪1000‬‬
‫‪Function field‬‬
‫‪xxxxxx‬‬
‫‪ALUOp1‬‬
‫‪1‬‬
‫‪ALUOp0‬‬
‫‪1‬‬
‫وعلى تٌبل ‪ Control unit‬رح نضٌف هاد الالٌن‪:‬‬
‫‪Branch ALUOp‬‬
‫‪11‬‬
‫‪0‬‬
‫‪Mem‬‬
‫‪Write‬‬
‫‪0‬‬
‫‪Mem‬‬
‫‪Read‬‬
‫‪0‬‬
‫‪Reg‬‬
‫‪Write‬‬
‫‪1‬‬
‫‪MemtoReg‬‬
‫‪ALUSrc‬‬
‫‪0‬‬
‫‪1‬‬
‫‪Instruction RegDst‬‬
‫‪0‬‬
‫‪lui‬‬
‫‪ RegDst‬الزم تكون ‪ 0‬النو بدي اخزن نتٌجة الشٌفت بالرٌجٌستر ‪Instrection[20-16] rt‬‬
‫‪ ALUSrc‬الزم تكون ‪ 1‬النو المدخل التانً لل ‪ ALU‬الزم ٌكون اوتبت ‪Sign extend‬‬
‫‪ MemtoReg‬الزم تكون ‪ 0‬النو ما بدي اخد من المٌموري بدي اخد اوتبت ال ‪ ALU‬الً رح تعمل الشٌفت و اخزنو‬
‫بالرٌجٌستٌر فاٌل‬
‫‪ RegWrite‬الزم تكون ‪ 0‬النو بدي اكتب على الرٌجٌستٌر فاٌل‬
‫‪ MemRead, MemWrite‬بحطهم زٌرو النو مش رح استخدم المٌموري ال رح اقرأ منها و ال رح اكتب علٌها‬
‫‪ Branch‬الزم تكون زٌرو النو مش رح اعمل برانش و بدي ال‪ٌ PC‬صٌر ‪PC+4‬‬
‫‪ ALUOp‬رح احطها ‪ 00‬النو رح تعمل شً جدٌد ”‪ “sll‬بدون ما تتطلع على بتات الفنكشٌن‬
‫‪7‬‬
‫‪Computer Architecture Discussion‬‬
‫و التعدٌل على السٌنجل ساٌكل حٌكون هٌك‪:‬‬
‫)‪Exercise 7: (5.11 from book‬‬
‫هنا رح ٌلزمنً اضٌف كمان ‪ write port‬على الرٌجٌستٌر فاٌل النو الزم اكتب على رٌجٌسترٌن و بدي اضٌف كنترول‬
‫سٌجنل اسمٌه ”‪ٌ “Regwrite2‬كون ‪ 0‬لما بدي اكتب على الرٌجٌستر التانً و رح اعتبر انو الراٌت بورت التانً رح‬
‫تتخزن الداتا الً رح تفوت علٌه داٌما بنفس الرٌجٌستر ‪ instruction[25-21] rs‬و هٌك بضل اضٌف‬
‫‪ incrementer‬عند الراٌت بورت التانً و ٌكون فاٌت علٌه ‪.Read Data 1‬‬
‫و ما رح ٌكون فً تعدٌل على ‪.ALU control‬‬
‫‪8‬‬
9
Computer Architecture Discussion
:‫ رح نضٌف هاد الالٌن‬Control unit ‫ورح اضٌف على تٌبل‬
Instruction RegDst ALUSrc
l_inc
0
1
Memto
Reg
1
Reg
Write
1
Mem
Read
1
Mem Branch ALUOp
Write
0
0
00
Reg
Write2
1
‫ رح‬RegWrite2 ‫ بس رح ٌكون زٌادة الكنترول سٌجنل الجدٌد‬lw ‫كل الكنترول سٌجنلز حٌكونو نفسهم النستركشٌن‬
.write data 2 port ‫ عشان اكتب على‬0 ‫ٌكون‬
:‫و التعدٌل على السٌنجل ساٌكل حٌكون هٌك‬
10
Computer Architecture Discussion
Exercise 8: (5.12 from book)
This instruction requires two writes to the register file. The only way to implement it is to
modify the register file to have two write ports instead of one.
Such a modification of the register file architecture may not be required for a multiple- cycle
implementation, since multiple writes to the same port can occur on different cycles.
Exercise 9: (5.13 from book)
‫ يعني‬don’t care ‫ نفس انقيم و انباقي‬lw ‫ و‬R-format ‫ النو باننسبة نم‬ALUSrc ‫ ب‬MemtoReg ‫ممكن استبدل‬
.0 ‫ او‬0 ‫ما رح يفرق اذا‬
don’t care ‫ نفس انقيم و انباقي‬lw ‫ و‬R-format ‫ النو باننسبة نم‬MemRead ‫ ب‬MemtoReg ‫ممكن استبدل‬
.0 ‫ او‬0 ‫يعني ما رح يفرق اذا‬
‫ انقيم‬sw ‫ نفس انقيم اما‬lw ‫ و‬R-format ‫ او انعكس النو باننسبة نم‬ALUSrc ‫ ب‬MemRead ‫ما بينفع استبدل‬
.‫بتختهف‬
11
Computer Architecture Discussion
Exercise 10: (5.14 from book)
swap $rs,$rt can be implemented by:
addi $rd,$rs,0
addi $rs,$rt,0
addi $rt,$rd,0
if there is an available register $rd
or:
sw $rs,temp($r0)
addi $rs,$rt,0
lw $rt,temp($r0)
if not.
Exercise 11: (5.31 from book)
MemRead ‫ او‬ALUSrc ‫ او‬MemtoReg ‫ او‬ALUOp1 ‫ ب‬RegDst ‫ممكن استبدل‬
MemRead ‫ او‬ALUSrc ‫ او‬ALUOp1 ‫ او‬RegDst ‫ ب‬MemtoReg‫ممكن استبدل‬
‫‪Computer Architecture Discussion‬‬
‫ممكن استبدل ‪ Branch‬و ‪ ALUOp0‬ببعض‬
‫‪Exercise 12:‬‬
‫‪Add bne to single cycle.‬‬
‫بدي اضٌف ‪ bne‬رح تشتغل نفس ‪ beq‬انو بدي احسب االدرس بانً اعمل شٌفت لٌفت ‪ 2‬بعدٌن اجمعو ل ‪ PC+4‬و رح‬
‫اخلً ال ‪ ALU‬تطرح الرٌجٌسترٌن بس رح تختلف بانو اذا كان الزٌرو سٌجنل بٌساوي ‪ٌ 0‬عنً مش متساوٌٌن هنا بعمل‬
‫ا لبرانش و هٌك رح ٌلزمنً اعدل على السٌلٌكشن الٌن للملتبلٌكسٌر اللً بحدد اذا حعمل برانش او الء بانو اضٌف ‪and‬‬
‫بفوت علٌها ‪ not zero‬و كنترول سٌجنل جدٌد بسمٌه ‪ BranchnotEq‬و االند القدٌمة مع االند الجدٌدة بفوتو على‬
‫‪ٌ or‬عنً اذا اجت ‪ beq‬و تحققت او ‪ bne‬و تحققت ٌعمل برانش على االدرس اللً حسبو‪.‬‬
‫و ما رح ٌكون فً تغٌٌر على ‪ ALU control‬النو ‪ ALU‬رح تعمل نفس لو اجت ‪.beq‬‬
‫و تٌبل ‪ Control unit‬رح نضٌف هاد الالٌن‪:‬‬
‫‪Branch‬‬
‫‪notEq‬‬
‫‪ALUOp‬‬
‫‪Jump‬‬
‫‪Branch‬‬
‫‪Mem‬‬
‫‪Write‬‬
‫‪Mem‬‬
‫‪Read‬‬
‫‪Reg‬‬
‫‪Write‬‬
‫‪Memto‬‬
‫‪Reg‬‬
‫‪ALUSrc‬‬
‫‪RegDst‬‬
‫‪Ins‬‬
‫‪1‬‬
‫‪01‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪x‬‬
‫‪0‬‬
‫‪x‬‬
‫‪bne‬‬
‫‪ RegDst, RegWrite, MemtoReg‬هدول كلهم ما بهمونً النو ما رح اخزن شً على الرٌجٌستٌر فاٌل‬
‫‪ ALUSrc‬الزم تكون ‪ 0‬النو المدخل التانً لل ‪ ALU‬الزم ٌكون ‪ Read Data 2‬من الرٌجٌستر فاٌل‬
‫‪ MemRead, MemWrite‬بحطهم زٌرو النو مش رح استخدم المٌموري ال رح اقرأ منها و ال رح اكتب علٌها‬
‫‪ Branch, Jump‬ما بدي اعمل برانش و ال جمب فحٌكونو ‪0‬‬
‫‪ ALUOp‬الزم احطها ‪ 00‬النو بدي اعمل ‪subtract‬‬
‫‪ BranchnotEq‬السٌجنل الجدٌد بحطو ‪ 0‬عشان تعمل برانش لما ٌكون السٌجنل زٌرو = ‪0‬‬
‫‪12‬‬
‫‪Computer Architecture Discussion‬‬
‫و التعدٌل على السٌنجل ساٌكل حٌكون هٌك‪:‬‬
‫‪Exercise 13:‬‬
‫‪Add jal to single cycle.‬‬
‫‪jal address‬‬
‫)‪000011 / 26 bit (address‬‬
‫بدي اضٌف ‪ jal‬اول شً االنستركشٌن ‪ jal address‬بتعمل شغلتٌن اول شً بتعمل جمب و بنحسب بنفس طرٌقة ال ‪j‬‬
‫انو ٌعمل شٌفت لٌفت ‪ 2‬بعدٌن ٌضٌف باالخر اخر ‪ 4‬بت من ‪ PC+4‬و الشغلة التانٌة انها بتحط االدرس للنٌكسٌت‬
‫انستركشٌن ب ‪ٌ $ra‬عنً رح تحط ‪ PC+4‬ب‪.$ra‬‬
‫والزم نعدل على الداتا باث انو اضٌف ملتٌبلٌكسر عند ‪ Write data‬بالرٌجسٌتر فاٌل بعد المٌلتبلٌكسٌر اللً بحدد اذا بدي‬
‫اكتب الداتا الً جاٌة من ال‪ ALU‬او من المٌموري و ٌكون السٌلٌكشٌن الٌن الو كنترول سٌجنل جدٌد اسمٌه ‪ jal‬و االنبت‬
‫االول للمتلٌبلٌكسر ٌكون الملتٌبلكسٌر القدٌم و االنبت التانً ‪ PC+4‬فلما تكون ‪ jal=1‬رح ٌكتب بالرٌجٌستر فاٌل ‪PC+4‬‬
‫كمان الزم اقلو ٌكتب الداتا بالرٌجستر ‪ $ra‬فالزم اضٌف كمان ملتبلٌكسٌر عند ‪ Write register‬بعد الملتٌبلكسٌر اللً‬
‫بحدد اخد ‪ rt‬او ‪ rd‬و ٌكون السٌلكشٌن الكنترول سٌجنل الجدٌد ‪ jal‬و ٌكون االنبت االول الملتٌبلكسٌر القدٌم و االنبت‬
‫التانً "‪ "00000‬رقم الرٌجٌستٌر ‪ $ra‬النو رقمو ‪ 10‬فلما تكون ‪ jal=1‬رح ٌكون الرٌجٌستٌر الدٌستٌنٌشن هوا ‪.$ra‬‬
‫و ما رح ٌلزم تعدٌل على ‪ ALU control‬النو ما رح استخدم ‪.ALU‬‬
‫‪13‬‬
‫‪Computer Architecture Discussion‬‬
‫و على تٌبل ‪ Control unit‬رح نضٌف هاد الالٌن‪:‬‬
‫‪Jal‬‬
‫‪ALUOp‬‬
‫‪Jump‬‬
‫‪Branch‬‬
‫‪Mem‬‬
‫‪Write‬‬
‫‪Mem‬‬
‫‪Read‬‬
‫‪Reg‬‬
‫‪Write‬‬
‫‪Memto‬‬
‫‪Reg‬‬
‫‪ALUSrc‬‬
‫‪RegDst‬‬
‫‪Ins‬‬
‫‪1‬‬
‫‪xx‬‬
‫‪1‬‬
‫‪0‬‬
‫‪0‬‬
‫‪0‬‬
‫‪1‬‬
‫‪x‬‬
‫‪x‬‬
‫‪x‬‬
‫‪jal‬‬
‫‪ RegDst‬ما رح تهمنً النو مش رح اخد اوتبت الملتبلٌكسٌر هاد‬
‫‪ ALUSrc‬ما بتهمنً النو مش رح استخدم ‪ALU‬‬
‫‪ MemtoReg‬ما رح تهمنً النو مش رح اخد اوتبت الملتبلٌكسٌر هاد‬
‫‪ RegWrite‬الزم تكون ‪ 0‬النو بدي اكتب على الرٌجٌستٌر فاٌل على ‪$ra‬‬
‫‪ MemRead, MemWrite‬بحطهم زٌرو النو مش رح استخدم المٌموري ال رح اقرأ منها و ال رح اكتب علٌها‬
‫‪ Branch‬ما بتهمنً النو ما رح اعمل برانش بحطها ‪0‬‬
‫‪ Jamp‬الزم تكون ‪ 0‬النو رح اعمل جمب و رح اخد ادرٌس الجمب‬
‫‪ ALUOp‬ما بتهمنً النو مش رح استخدم ‪ALU‬‬
‫‪ Jal‬الكنترول سٌجنل الجدٌد الزم ٌكون ‪ 0‬عشان ٌختار الداتا ‪ PC+4‬و الرٌجسٌتر ‪$ra‬‬
‫و التعدٌل على السٌنجل ساٌكل حٌكون هٌك‪:‬‬
‫‪14‬‬
15
Computer Architecture Discussion
Exercise 14: (5.29 from book)
a. RegWrite = 0: All R-format instructions, in addition to lw, will not work because these
instructions will not be able to write their results to the register file.
b. MemRead = 0: None of the instructions will run correctly because instructions will not
be fetched from memory.
c. MemWrite = 0: sw will not work correctly because it will not be able to write to the data
memory.
d. IRWrite = 0: None of the instructions will run correctly because instructions fetched
from memory are not properly stored in the IR register.
e. PCWrite = 0: jump instructions will not work correctly because their target address will
not be stored in the PC. beq will not work correctly because the PC+4 will not written
into PC so the addition with the sign extended will be wrong. And the next instruction
will not execute because the PC will not incremented.
f. PCWriteCond = 0: Taken branches will not execute correctly because their target
address will not be written into the PC.
Exercise 15: (5.30 from book)
a. RegWrite = 1: Jump and branch will write their target address into the register file. sw
will write the destination address or a random value into the register file.
b. MemRead = 1: All instructions will work correctly. Memory will be read all the time, but
IRWrite and IorD will safeguard this signal.
16
Computer Architecture Discussion
c. MemWrite = 1: All instructions will not work correctly. Both instruction and data
memories will be written over by the contents of register B.
d. IRWrite = 1: lw will not work correctly because data memory output will be translated as
instructions.
e. PCWrite = 1: All instructions except jump will not work correctly. This signal should be
raised only at the time the new PC address is ready (PC + 4 at cycle 1 and jump target in
cycle 3). Raising this signal all the time will corrupt the PC by either ALU results of Rformat, memory address of lw / sw, or target address of conditional branch, even when
they should not be taken.
f. PCWriteCond = 1: Instructions other than branches (beq) will not work correctly if they
raise the ALU's Zero signal. An R-format instruction that produces zero output will
branch to a random address determined by their least significant 16 bits.
Exercise 16: (5.32 from book)
We use the same datapath, so the immediate field shift will be done inside the ALU.
1. Instruction fetch step: This is the same
(IR <= Memory[PC]; PC <= PC + 4)
2. Instruction decode step: We don't really need to read any register in this stage if we
know that the instruction in hand is a lui, but we will not know this before the end of
this cycle. It is tempting to read the immediate field into the ALU to start shifting next
cycle, but we don't yet know what the instruction is. So we have to perform the same
way as the standard machine does.
A <= 0 ($r0); B <= $rt; ALUOut <= PC + (sign-extend(immediate field));
3. Execution: Only now we know that we have a lui. We have to use the ALU to shift left
the low-order 16 bits of input 2 of the multiplexor. (The sign extension is useless, and
sign bits will be flushed out during the shift process.)
ALUOut <= sll {sign-extend(IR[15:0]),16}
4. Instruction completion: Reg[IR[20-16]] = ALUOut.
17
Computer Architecture Discussion
The first two cycles are identical to the FSM of Figure 5.38. By the end of the second cycle the
FSM will recognize the opcode. We add the Op='lui', a new transition condition from state 1 to
a new state 10. In this state we perform the left shifting of the immediate field: ALUSrcA = x,
ALUSrcB = 10, ALUOp = 11 (assume this means left shift of ALUSrcB). State 10 corresponds to
cycle 3. Cycle 4 will be translated into a new state 11, in which RegDst = 0, RegWrite = 1,
MemtoReg = 0. State 11 will make the transition back to state 0 after completion.
As shown above the instruction execution takes 4 cycles.
From state 1
Op = 'lui'
10
ALUSrcA = x
ALUSrcB = 10
ALUOp = 11
11
RegDst = 0
RegWrite = 1
MemtoReg = 0
To state 0
Exercise 17: (5.33 from book)
18
Computer Architecture Discussion
This solution can be done by modifying the data path to extract and shift the immediate field
outside the ALU. Once we recognize the instruction as lui (in cycle 2), we will be ready to store
the immediate field into the register file the next cycle. This way the instruction takes 3 cycles
instead of the 4 cycles of Exercise 5.32.
1. Instruction fetch step: Unchanged.
2. Instruction decode: Also unchanged, but the immediate field extraction and shifting will
be done in this cycle as well.
3. Now the final form of the immediate value is ready to be loaded into the register file.
The MemtoReg control signal has to be modified in order to allow its multiplexor to
select the immediate upper field as the write data source. We can assume that this
signal becomes a 2-bit control signal, and that the value 2 will select the immediate
upper field.
19
Computer Architecture Discussion
The first two cycles are identical to the FSM of Figure 5.38. By the end of the second cycle, the
FSM will recognize the opcode. We add the Op = 'lui', a new transition condition from state 1 to
a new state 10. In this state we store the immediate upper field into the register file by these
signals: RedDst = 0, RegWrite = 1, MemtoReg = 2. State 10 will make the transition back to state
0 after its completion.
From state 1
Op = 'lui'
10
RegDst = 0
RegWrite = 1
MemtoReg = 10
To state 0
Exercise 17: (5.34 from book)
We can use the same datapath.
1. Instruction fetch: Unchanged (IR <= Memory[PC]; PC<= PC + 4).
2. Instruction decode: Unchanged
(A <= Reg[IR[25-21]]; B<=REG[IR[20-16]]; ALUOut<=PC+(sign-extend(IR[15-0])<<2).
3. Load immediate value from memory (MDR <= Memory[PC]; PC <= PC + 4).
4. Complete instruction (Reg[IR[20-16]] (dependent on instruction format) <= MDR).
The first two cycles are identical to the FSM of Figure 5.38. We add the Op='ldi', a new
transition condition from state 1 to a new state 10. In this state we fetch the immediate value
from memory into the MDR: MemRead = 1, ALUSrcA = 0, IorD = 0, MDWrite = 1, ALUSrcB = 01,
ALUOp = 00, PCWrite = 1, PCSource = 00. FSM then makes the transition to another new state
11. In this state we store the MDR into the register file by these signals: RedDst = 0 (actually
depends on the instruction format), RegWrite = 1, MemtoReg = 1. State 11 will make the
transition back to state 0 after its completion.
Four cycles to complete this instruction, in which we have two instruction memory accesses.
20
Computer Architecture Discussion
From state 1
Op='ldi'
10
11
MemRead = 1,
ALUSrcA = 0,
IorD = 0,
IRWrite = 0,
ALUSrcB = 01,
ALUOp = 00,
PCWrite = 1,
PCSource = 00
RedDst = 0,
RegWrite = 1,
MemtoReg = 1
To state 0
Exercise 18: (5.35 from book)
Many solutions are possible. In all of them, a multiplexor will be needed as well as a new
control signal (e.g., RegRead) to select which register is going to be read (i.e., using IR[25-11] or
IR[20-16]). One simple solution is simply to add a write signal to A and break up state 1 into two
states, in which A and B are read. Alternatively, you could decide to read A first because it may
be needed to calculate an address. You could then postpone reading B until state 2 and avoid
adding an extra cycle for the load and store instructions. An extra cycle would be needed for
the branch and R-type instructions.
Step 1: Instruction Fetch:
IR <= Memory[PC];
PC <= PC + 4;
21
Computer Architecture Discussion
Step 2: Instruction Decode and Register Fetch:
A <= Reg[IR[25:21]];
ALUOut <= PC + (sign-extend(IR[15:0]) << 2);
Step 3: (instruction dependent):
• Memory Reference:
ALUOut <= A + sign-extend(IR[15:0]);
• R-type and Branch:
B <= Reg[IR[20:16]];
Step 4: (Branch or R-type or memory-access):
• Loads and stores access memory
MDR <= Memory[ALUOut];
or
Memory[ALUOut] <= B;
• R-type instructions
ALUOut <= A op B;
• Branch:
if (A==B) PC <= ALUOut;
Step 5: (Write-back step):
• Load:
Reg[IR[20:16]] <= MDR;
• R-type instructions
Reg[IR[15:11]] <= ALUOut;
22
Computer Architecture Discussion
23
Computer Architecture Discussion
Exercise 19: (5.50 from book)
The exception cause can be represented through the status "cause" register, which records the
reason code for the exception. The instruction position at which the exception occurs is
identified by saving it in the Exception Program Counter (EPC) register.
Execution can be restarted for some exceptions like overflow, system call request, or external
I/O device interrupt by restarting execution at the EPC after handling the exception.
Other exceptions are not restartable and program has to terminate. Examples of this are invalid
instructions (which can actually be restartable if defined as NOP by the hardware),
power/hardware failure, and divide by zero. In such a case, an error message can be produced,
and program termination takes place.
Exercise 20: (5.51 from book)
a. Divide by zero exception can be detected in the ALU in cycle 3, before executing the
divide instruction.
b. Overflow can be hardware detected after the completion of the ALU operation. This is
done in cycle 4.
24
Computer Architecture Discussion
c. Invalid opcode can be detected by the end of cycle 2.
d. This is an asynchronous exception event that can occur at any cycle. We can design this
machine to test for this condition either at a specific cycle (and then the exception can
take place only in a specific stage), or check in every cycle (and then this exception can
occur at any processor stage).
e. Check for instruction memory address can be done at the time we update the PC. This
can be done in cycle 1.
f. Check for data memory address can be done after address calculation at the end of
cycle 3.
 Best Wishes 