N
Comlinear CLC425
Ultra Low Noise Wideband Op Amp
General Description
Features
The Comlinear CLC425 combines a wide bandwidth (1.9GHz
√Hz, 1.6pA/√
√Hz) and low
GBW) with very low input noise (1.05nV/√
µV VOS, 2µ
µV/°C drift) to provide a very precise, wide
dc errors (100µ
dynamic-range op amp offering closed-loop gains of ≥10.
■
■
■
■
■
Singularly suited for very wideband high-gain operation, the CLC425
employs a traditional voltage-feedback topology providing all the
benefits of balanced inputs, such as low offsets and drifts, as well
as a 96dB open-loop gain, a 100dB CMRR and a 95dB PSRR.
■
■
■
■
The CLC425 also offers great flexibility with its externally adjustable
supply current, allowing designers to easily choose the optimum
set of power, bandwidth, noise and distortion performance.
Operating from ±5V power supplies, the CLC425 defaults to a
15mA quiescent current, or by adding one external resistor, the
supply current can be adjusted to less than 5mA.
Applications
■
■
■
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■
The CLC425's combination of ultra-low noise, wide gain-bandwidth, high slew rate and low dc errors will enable applications in
areas such as medical diagnostic ultrasound, magnetic tape & disk
storage, communications and opto-electronics to achieve maximum
high-frequency signal-to-noise ratios.
1.9GHz gain-bandwidth product
1.05nV/√Hz input voltage noise
0.8pA/√Hz @ Icc < 5mA
100µV input offset voltage, 2µV/°C drift
350V/µs slew rate
15mA to 5mA adjustable supply current
Gain range ±10 to ±1,000V/V
Evaluation boards & simulation
macromodel
0.9dB NF @ Rs = 700Ω
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Comlinear CLC425
Ultra Low Noise Wideband Op Amp
August 1996
Instrumentation sense amplifiers
Ultrasound pre-amps
Magnetic tape & disk pre-amps
Photo-diode transimpedance amplifiers
Wide band active filters
Low noise figure RF amplifiers
Professional audio systems
Low-noise loop filters for PLLs
Equivalent Input Voltage Noise
10
CLC425AJP
CLC425AJE
CLC425AIB
CLC425A8B
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
CLC425ALC
-40°C to +85°C
CLC425AMC
-55°C to +125°C
CLC425AJM5
-40°C to +85°C
DESC SMD number : 5962-93259.
8-pin PDIP
8-pin SOIC
8-pin CERDIP
8-pin CERDIP,
MIL-STD-883, Level B
dice
dice, MIL-STD-883, Level B
5-pin SOT
Voltage Noise (nV/√Hz)
The CLC425 is available in the following versions:
1.05nV/√Hz
1
100
1k
Pinout
SOT23-5
Vo
 1996 National Semiconductor Corporation
Printed in the U.S.A.
10M
100M
Pinout
DIP & SOIC
VCC
VEE
Vnon-inv
10k
100k
1M
Frequency (Hz)
Vinv
NC
1
8 Rp
Vinv
2
-
7 +Vcc
Vnon-inv
3
+
6 Vout
-Vcc
4
(optional)
5 NC
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CLC425 Electrical Characteristics
PARAMETERS
Ambient Temperature
Ambient Temperature
CONDITIONS
CLC425 AJ/AI
CLC425 A8/AM/AL
Ω; Rg = 26.1Ω
Ω; RL = 100Ω
Ω;
(VCC = ±5V; AV = +20; Rf =499Ω
TYP
+25°C
+25°C
MIN/MAX RATINGS
-40°C
+25°C
+85°C
°
°
-55 C
+25 C
+125°C
UNITS
unless noted)
SYMBOL
FREQUENCY DOMAIN RESPONSE
gain bandwidth product
Vout < 0.4Vpp
✝-3dB bandwidth
Vout < 0.4Vpp
Vout < 5.0Vpp
gain flatness
Vout < 0.4Vpp
✝peaking
DC to 30MHz
✝rolloff
DC to 30MHz
linear phase deviation
DC to 30MHz
1.9
95
40
1.5
75
30
1.5
75
30
1.0
50
20
GHz
MHz
MHz
GBW
SSBW
LSBW
0.3
0.1
0.7
0.7
0.7
1.5
0.5
0.5
1.5
0.7
0.7
2.5
dB
dB
°
GFP
GFR
LPD
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.2%
overshoot
slew rate
3.7
22
5
350
4.7
30
12
250
4.7
30
10
250
7.0
40
12
200
ns
ns
%
V/µs
TRS
TSS
OS
SR
48
65
48
65
46
60
dBc
dBc
dBm
HD2
HD3
IMD
1.05
1.6
0.9
1.25
4.0
1.25
2.5
1.8
2.5
nV/√Hz
pA/√Hz
dB
VN
ICN
NF
96
± 100
±2
12
- 100
± 0.2
±3
95
100
15
77
± 1000
8
40
- 250
3.4
± 50
82
88
18
86
± 800
86
± 1000
4
20
- 120
2.0
± 25
86
90
16
dB
µV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
AOL
VIO
DVIO
IB
DIB
IIO
DIIO
PSRR
CMRR
ICC
2
6
1.5
1.9
5
± 3.8
± 3.4
± 3.8
90
90
0.6
1.6
1
3
2
2
3
3
50
10
± 3.5
± 3.7
± 2.8
± 3.2
± 3.4
± 3.5
60/70
70
40/45
55
1.6
3
2
3
10
± 3.7
± 3.2
± 3.5
70
55
MΩ
kΩ
pF
pF
mΩ
V
V
V
mA
mA
RINC
RIND
CINC
CIND
ROUT
VO
VOL
CMIR
IOP
ION
0.4V step
2V step
0.4V step
2V step
DISTORTION AND NOISE RESPONSE
✝2nd harmonic distortion
1Vpp, 10MHz
✝3rd harmonic distortion
1Vpp, 10MHz
10MHz
3rd order intermodulation intercept
equivalent noise input
voltage
1MHz to 100MHz
current
1MHz to 100MHz
noise figure
Rs = 700Ω
STATIC DC PERFORMANCE
open-loop gain
*input offset voltage
average drift
*input bias current
average drift
input offset current
average drift
✝power supply rejection ratio
common mode rejection ratio
*supply current
DC
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance
common-mode
differential-mode
input capacitance
common-mode
differential-mode
output resistance
closed loop
output voltage range
RL= ∞
RL=100Ω
input voltage range
common mode
output current
source
-55°C/-40°C
sink
-55°C/-40°C
- 53
- 75
35
____
20
____
2.0
____
88
92
16
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Miscellaneous Ratings
Absolute Maximum Ratings
Vcc
Iout
±7V
Recommended gain range
150mA
±Vcc
±25mA
+175°C
Notes:
*
AJ,AI
✝
AJ
✝
AI
*
A8
✝
A8
*
AL, AM
±10 to ±1,000V/V
short circuit protected to ground, however maximum reliabiliy
is obtained if I out does not exceed...
common-mode input voltage
differential input current
diode protected
maximum junction temperature
operating temperature range
AJ/AI
A8/AM/AL:
storage temperature range
lead temperature (soldering 10 sec)
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-40°C to +85°C
-55°C to +125°C
-65°C to +150°C
+300°C
2
:
:
:
:
:
:
100% tested at +25°C, sample at +85°C.
Sample tested at +25°C.
100% tested at +25°C.
100% tested at +25°C, -55°C, +125°C.
100% tested at +25°C, sample at -55°C, +125°C
100% wafer probed +25°C to +25°C min/max specs.
3
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4
+Vcc
Vin
Total Input Noise vs. Source Resistance
In order to determine maximum signal-to-noise ratios
from the CLC425, an understanding of the interaction
between the amplifier's intrinsic noise sources and the
noise arising from its external resistors is necessary.
6.8µF
7
3
0.1µF
Rs
Vs
6
CLC425
RT
Vout
2
6.8µF
Figure 3 describes the noise model for the non-inverting
amplifier configuration showing all noise sources. In
addition to the intrinsic input voltage noise (en) and
current noise (in=in+=in-) sources, there also exists thermal voltage noise ( et = 4kTR ) associated with each of
the external resistors. Equation 1 provides the general
form for total equivalent input voltage noise density (eni).
Equation 2 is a simplification of Equation 1 that assumes
4
-Vcc
Rseq = Rs ||R T
0.1µF
Rf
Rg
Av = 1 +
Rf
Rg
Figure 1: Non-inverting Amplifier Configuration
Introduction
The CLC425 is a very wide gain-bandwidth, ultra-low
noise voltage feedback operational amplifier which enables application areas such as medical diagnostic ultrasound, magnetic tape & disk storage and fiber-optics to
achieve maximum high-frequency signal-to-noise ratios.
The set of characteristic plots located in the "Typical
Performance" section illustrates many of the performance trade-offs. The following discussion will enable
the proper selection of external components in order to
achieve optimum device performance.
en
Rseq
√4kTRseq
√4kTRf
@
25° C
Figure 3: Non-inverting Amplifer Noise Model
eni =
(
en2 + in + Rs
eq
)
2
+ 4 kTRs
eq
( (
+ in − R f || Rg
))
2
(
+ 4 kT R f || Rg
)
Equation 1: General Noise Equation
Rf||Rg = Rseq for bias current cancellation. Figure 4
illustrates the equivalent noise model using this assumption. Figure 5 is a plot of eni against equivalent
source resistance (Rseq) with all of the contributing voltage noise sources of Equation 2 shown. This plot gives
the expected eni for a given Rseq which assumes Rf||Rg =
Rseq for bias current cancellation. The total equivalent
output voltage noise (e no) is e ni∗Av.
√4kT2Rseq
en
6.8µF
Av
2Rseq
7
0.1µF
CLC425
Rb
Rf
√4kTRg
4 kT = 16.4e − 21 Joules
As seen in Figure 2, bias current cancellation is accomplished for the inverting configuration by placing a resistor (R b) on the non-inverting input equal in value to the
resistance seen by the inverting input (Rf||(Rg+Rs)). Rb is
recommended to be no less than 25Ω for best CLC425
performance. The additional noise contribution of Rb can
be minimized through the use of a shunt capacitor.
3
Rg
in-
Bias Current Cancellation
In order to cancel the bias current errors of the noninverting configuration, the parallel combination of the
gain-setting (Rg) and feedback (Rf) resistors should equal
the equivalent source resistance (Rseq) as defined in
Figure 1. Combining this constraint with the non-inverting gain equation also seen in Figure 1, allows both Rf
and Rg to be determined explicitly from the following
equations: Rf=AvRseq and Rg=Rf/(Av-1). When driven from
a 0Ω source, such as that from the output of an op amp,
the non-inverting input of the CLC425 should be isolated
with at least a 25Ω series resistor.
+Vcc
CLC425
in+
2
in
√2
Vout
6
6.8µF
4
Figure 4: Noise Model with Rf||Rg = R seq
Vin
Rs
-Vcc
Rg
0.1µF
Rf
eni =
Vs
Av = - Rf
Rg
Figure 2: Inverting Amplifier Configuration
(
en2 + 2 in Rseq
)
2
(
+ 4 kT 2 Rseq
)
Equation 2: Noise Equation with Rf||Rg = R seq
5
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As seen in Figure 5, eni is dominated by the intrinsic
voltage noise (en) of the amplifier for equivalent source
resistances below 33.5Ω. Between 33.5Ω and 6.43kΩ,
eni is dominated by the thermal noise ( et = 4kTR seq ) of
the external resistors. Above 6.43kΩ, eni is dominated by
the amplifier's current noise ( 2inRseq ). The point at
which the CLC425's voltage noise and current noise
contribute equally occurs for Rseq=464Ω (i.e. en / 2in ).
As an example, configured with a gain of +20V/V giving
a -3dB of 90MHz and driven from an Rseq=25Ω, the
CLC425 produces a total equivalent input noise voltage
( eni ∗ 1.57∗90MHz ) of 16.5µVrms.
The noise figure is related to the equivalent source
resistance (Rseq) and the parallel combination of Rf and
Rg. To minimize noise figure, the following steps are
recommended:
• Minimize Rf||Rg
• Choose the optimum Rs (ROPT)
ROPT is the point at which the NF curve reaches a
minimum and is approximated by:
ROPT ≅ (en/in)
Figure 6 is a plot of NF vs Rs with Rf||Rg = 9.09 (Av = +10).
The NF curves for both Unterminated and Terminated
systems are shown. The Terminated curve assumes Rs
= RT. The table indicates the NF for various source
resistances including Rs = ROPT.
Figure 5: Voltage Noise Density vs. Source Resistance
If bias current cancellation is not a requirement, then
Rf||Rg does not need to equal Rseq. In this case, according
to Equation 1, Rf||Rg should be as low as possible in
order to minimize noise. Results similar to Equation 1
are obtained for the inverting configuration of Figure 2 if
Rseq is replaced by Rb and Rg is replaced by Rg+Rs. With
these substitutions, Equation 1 will yield an eni refered to
the non-inverting input. Refering eni to the inverting input
is easily accomplished by multiplying eni by the ratio of
non-inverting to inverting gains.
Figure 6: Noise Figure vs Source Resistance
Supply Current Adjustment
The CLC425's supply current can be externally adjusted
downward from its nominal value by adding an optional
resistor (Rp) between pin 8 and the negative supply as
shown in Figure 7. Several of the plots found within the plot
pages demonstrate the CLC425’s behavior at different
supply currents. The plot labeled “Icc vs. Rp” provides the
means for selecting Rp and shows the result of standard IC
process variation which is bounded by the 25°C curve.
Noise Figure
Noise Figure (NF) is a measure of the noise degradation
caused by an amplifier.
+Vcc
 eni 2 
 S / Ni 
NF = 10LOG  i
 = 10LOG  2 
 So / N o 
 et 
3
2
)
(
2
 2
e + in 2  Rseq + R f | | Rg  + 4kTRseq + 4kT R f | | Rg


 n
NF = 10LOG 
4kTRseq


4
Vout
-Vcc
Figure 7: External Supply Current Adjustment
Non-Inverting Gains Less Than 10V/V
Using the CLC425 at lower non-inverting gains requires
external compensation such as the shunt compensation
as shown in Figure 8. The quiescent supply current must
also be reduced to 5mA with Rp for stability. The compensation capacitors are chosen to reduce frequency
response peaking to less than 1dB. The plot in the
"Typical Performance" section labeled “Differential Gain
and Phase” shows the video performance of the CLC425
with this compensation circuitry.
) 



Rseq = Rs for Unterminated Systems
Rseq = Rs II RT for Terminated Systems
Equation 3: Noise Figure Equation
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6
8
Rp
The Noise Figure formula is shown in Equation 3. The
addition of a terminating resistor RT, reduces the
external thermal noise but increases the resulting NF.
The NF is increased because RT reduces the input signal
amplitude thus reducing the input SNR.
(
7
CLC425
6
Cf
Icc=5mA
Rs = 75Ω
Cin
75Ω
Rin
75Ω
39pF
+Vcc
Rf
CLC425
75Ω
Rf = 124Ω
Rg = 124Ω
CLC425
Cf = 10pF
Av = − I in ∗ R f
Rb
Figure 8: External Shunt Compensation
Figure 11: Transimpedance Amplifier Configuration
Inverting Gains Less Than 10V/V
The lag compensation of Figure 9 will achieve stability
for lower gains. Placing the network between the two
input terminals does not affect the closed-loop nor noise
gain, but is best used for the invering configuration
because of its affect on the non-inverting input impedance.
Vin
Rg
Rf
Vout
R
CLC425
Rout
C
RL
Figure 12: Transimpedance Amplifier Frequency Response
Rb
Figure 9: External Lag Compensation
Single-Supply Operation
The CLC425 can be operated with single power supply
as shown iin Figure 10. Both the input and output are
capacitively coupled to set the dc operating point.
Vcc
R
Vcc
2
Vcc
Vout = Vcc + AvVac
2
Vac
C
CLC425
R
C
Rout
RL
Figure 13: Current Noise Density vs. Feedback Resistance
Rf
Rg
 en 
4 kT
+
 + R
R
 f
f
2
C
i ni =
Figure 10: Single Supply Operation
Low Noise Transimpedance Amplifier
The circuit of Figure 11 implements a low-noise transimpedance amplifier commonly used with photo-diodes.
The transimpedance gain is set by Rf. The simulated
frequency response is shown in Figure 12 and shows
the influence Cf has over gain flatness. Equation 4
provides the total input current noise density (ini) equation for the basic transimpedance configuration and is
plotted against feedback resistance (Rf) showing all
contributing noise sources in Figure 13. This plot indicates the expected total equivalent input current noise
density (i ni) for a given feedback resistance (Rf). The total
equivalent output voltage noise density (eno) is i ni∗Rf.
2
in
Equation 4: Total Equivalent Input Refered Current
Very Low Noise Figure Amplifier
The circuit of Figure 14 implements a very low Noise
Figure amplifier using a step-up transformer combined
with a CLC425 and a CLC404. The circuit is configured
with a gain of 35.6dB. The circuit achieves measured
Noise Figures of less than 2.5dB in the 10-40MHz
region. 3 rd order intercepts exceed +30dBm for frequencies less than 40MHz and gain flatness of 0.5dB is measured
in the 1-50MHz pass bands. Application Note OA-14 provides
greater detail on these low Noise Figure techniques.
7
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40kΩ
Vin
R = 681Ω
Vo
Pi
50Ω
10Ω
600Ω
Av=+10
CLC425
R1 = 45.3Ω
200Ω
1:4
CLC425
806Ω
50Ω
0.1µF
180Ω
20Ω
Mini-Circuits
T16-6T
C1 = 2200pF
Po
CLC404
1pF
50kΩ
Av=-3
20Ω
50Ω
Rg = 50Ω
Rf = 1kΩ
C = 470pF
Ko = 1 +
R2 = 200Ω
L = 0.1µH
Gain = Po = 35.6dB
Pi
Rf
Rg

 sC R + 1
 Rf 
sLRg
Vo
1 1
= Ko 
−


2
Vin
 sC1 ( R1 + R) + 1  R f + Rg  s LCR2 Rg + sL R2 + Rg + R2 Rg 
Figure 14: Very Low Noise Figure Amplifier
(
Low Noise Integrator
The CLC425 implements a deBoo integrator shown in
Figure 15. Integration linearity is maintained through
positive feedback. The CLC425's low input offset
voltage and matched inputs allowing bias current
cancellation provide for very precise integration. Stability is maintained through the constraint on the circuit
elements.
Rf
Ko
Vo ≅ Vin
;
Ko = 1 +
sRa C
Rg
)
Figure 17: Low Noise Magnetic Media Equalizer
Rb
Ra
Vo
Vin
C
CLC425
R
50Ω
50Ω
Figure 18: Equalizer Frequency Response
Rf
Rg
Low-Noise Phase-Locked Loop Filter
The CLC425 is extremely useful as a Phase-Locked
Loop filter in such applications as frequency synthesizers and data synchronizers. The circuit of Figure 19
implements one possible PLL filter with the CLC425.
Rf
Rb
≥
, R >> Ra
Ra || R Rg
Rf
Figure 15: Low Noise Integrator
Vin
High-Gain Sallen-Key Active Filters
The CLC425 is well suited for high-gain Sallen-Key type
of active filters. Figure 16 shows the 2nd order Sallen-Key
low pass filter topology. Using component predistortion
methods as discussed in OA-21 enables the proper
selection of components for these high-frequency filters.
Figure 19: Phased-Locked Loop Filter
Decreasing the Input Noise Voltage
The input noise voltage of the CLC425 can be reduced
from its already low 1.05nV / Hz
by slightly increasing
the supply current. Using a 50kΩ resistor to ground on
pin 8, as shown in the circuit of Figure 14, will increase the
quiescent current to ≈17mA and reduce the input noise
voltage to < 0.95nV / Hz
.
CLC425
Rf
Rg
Printed Circuit Board Layout
Generally, a good high-frequency layout will keep power
supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes
to ground will cause frequency response peaking and
possible circuit oscillation, see OA-15 for more information. Comlinear suggests the 730013 (through-hole) or the
730027 (SOIC) evaluation board as a guide for high-frequency
layout and as an aid in device testing and characterization.
Figure 16: Sallen-Key Active Filter Topology
Low Noise Magnetic Media Equalizer
The CLC425 implements a high-performance low-noise
equalizer for such applications as magnetic tape
channels as shown in Figure 17. The circuit combines an
integrator with a bandpass filter to produce the lownoise equalization. The circuit's simulated frequency
response is illustrated in Figure 18.
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CLC425
Rb
R2
C2
Vout
Rg
C1
R1
Cf
8
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Comlinear CLC425
Ultra Low Noise Wideband Op Amp
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
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of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
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Tel: 1(800) 272-9959
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circuitry and specifications.
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12
Lit #150425-006