ULTRA LOW VOLTAGE CURRENT MULTIPLIER/DIVIDER
Yngvar Berg and Tor Sverre Lande
Dept. of Informatics, University of Oslo, Gaustadalleen 23, P.O.Box 1080, Blindern,
N-0316 Oslo, Norway. Fax: +47 22 85 24 01. Email:yngvarb@ifi.uio.no
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Standard transistor
-8
max
I ds
-9
Weak inversion model
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[A]
Exact current
ds
I. Introduction
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I
Abstract— In this paper we are presenting novel
current multiplier/divider circuits utilizing the
power of FGUVMOS transistors. Even for ultra low
supply voltages a proper operation is achieved with
threshold shifting using post-fab. tuning. Measured
results are provided of a multiplier working over a
large magnitude in current at 0.7V power supply.
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I bec
C1
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As the current-mode approach to analog circuit
design [1] is gaining interest due to better performance, another compelling reason for current-mode
circuits is the decreasing power supply of digital
microelectronics. The upside of sharing both silicon and power with digital electronics challenges
the analog designer to come up with solutions. As
the power supply is lowered, the available headroom
is shrinking, so current-mode design techniques provides some kind of relief by demanding much less
headroom (compressed voltage-mode).
Looking into the future, ultra low supply voltage
(ULV) Vdd < 1V is coming. Improved precision in
production will permit a reduced threshold voltage
with improved matching, but still the threshold voltage will “steal” an increasing part of the available
headroom.
One possible solution to the matching problem is
post-fabrication tuning like laser-trimming. Techniques requiring individual tuning of each poweredup circuit are slow and expensive. Another approach
to threshold matching is to use MOS transistors
with capacitive coupling to a floating gate as indicated in figure 1. A change in the stored charge
of the floating gate will effectively shift the threshold voltage seen from the capacitively coupled input
terminal. The success of this approach is clearly
dependent on both the accuracy and the overhead
penalty in terms of silicon area and production cost.
We have developed a novel and very simple approach [2], [3] to program the floating gate of MOStransistors, called FGUVMOS transistors, available
in any double-poly CMOS process. By exposing the
circuit to short-wave UV-light, the threshold voltage
of both PMOS and NMOS transistors can be tuned
simply by reverse-biasing the power-rails.
In the following, we will apply FGUVMOS transistors to design a current-mode multiplier/divider
circuit for ULV operation, but in order to understand the design, we have to explain some more details about FGUVMOS circuits in general. There
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in
fg
I
ds
Cm
min
I ds
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0
0.1
0.2
0.3
0.4
0.5
V in [V]
Fig. 1.
Multiple input n-channel Floating-gate UVMOS
(FGUVMOS) transistor.
is always one PMOS stacked on top of one NMOS
transistor. The height is always two with a common
drain-node, but of course additional MOS transistors may be added in parallel (both Ps and Ns).
However, each floating gate may have several inputs
connected through floating capacitors, compensating for the limited stacking. All FGUVMOS circuits
must be tuned or programmed using short-wave UVlight (UV-C) [2], [4]. Note that all transistors on a
chip, or even a wafer, can be programmed simultaneously without using any additional programming
circuitry, except the power-rails. Two important
conditions are established during the tuning process:
1. The threshold voltage of all PMOS transistors is
typically programmed to a small negative voltage
relative to the Vdd supply rail, while the threshold
voltages of all NMOS transistors are typically tuned
to a small positive voltage relative to the Vss supply rail (substrate). By reverse biasing the supplyrails, the source and drain of all transistors are interchanged. The nodes between the PMOS and NMOS
are strongly driven by a source-follower configuration to a equilibrium voltage, Vbe (≡ VDD /2), maintained also under normal biasing conditions. The
current flowing through the stacked transistors is
matched and will result in a balanced equilibrium
current, Ibec , under normal biasing.
2. A useful consequence of the current matching is
the equalized transconductances [2], due to shifting of the threshold voltage. We have that is
gmN /gmP = 1 in weak inversion and gmN /gmP =
p
µN /µP in strong inversion. In other words the
difference in mobility between N-type and P-type
transistors is compensated without altering transistor dimensions.
The symmetry is another important property of
FGUVMOS circuits and will compensate for systematic errors like the Early effect and mobility differences between PMOS and NMOS.
Po
I in1
I in2
C po
I Po
V po
V in2
V in1
V no
I No
C i1
C i3
C no
C i2
Ni1
No
Ni2
II. FGUVMOS circuits
In spite of the design restrictions imposed by
the tuning scheme, it is possible to make powerful circuits. A crucial design parameter is the sizing of the coupling capacitors. For a multiple input
FGUVMOS transistor each input has by design an
effective coupling capacitance, Ci , to the floating
gate. The input signal is attenuated with a factor
ki = Ci /CT , where CT is the total load capacitance
seen from the input. This load capacitance will increase with the number of inputs and may even be
non-linear.
For FGUVMOS circuits it is convenient to express the behavior as modulation of the equilibrium
condition. For simplicity, we will model the weak
inversion behavior knowing that a similar analysis may be done for strong inversion as well. The
input modulation of the drain current as a function of the ith input terminal may be expressed as
1
exp{ nU
(Vi − Vdd /2)ki }. The accumulated drain
t
current modulation
of m inputs is expressed as the
Qm
1
(Vi −Vdd /2)ki }. The effective
product i=1 exp{ nU
t
drain current of a FGUVMOS transistor may then
be written as
Ids = Ibec
m
Y
i=1
exp{
1
(Vi − Vdd /2)ki }.
nUt
Furthermore, we may express the min and max
currents in terms of the balanced equilibrium current and current modulation
max
Ids
min
Ids
1
= Ibec exp{
Vdd ki }
2nUt
Pm
= Ibec R i=1 ki
Pm
= Ibec R i=1 −ki
Ibec
=
max ,
Ids
1
Vdd } and the maximum dywhere R = exp{ 2nU
t P
m
namic range, assuming i=1 ki = 1, of the transis2
tor current is R .
Although this is an expression for a m-input FGUVMOS NMOS transistor, the number of inputs are
usually kept small in order to maintain a sufficient
SNR. The expression for PMOS transistors are very
similar.
Fig. 2. Minch’ current divider (original without the PMOS).
III. Current multipliers and dividers
We are now equipped with the required tools for
FGUVMOS circuit design.
Although these kind of circuits are kind of exotic,
the basic idea of the circuit in figure 2 is reported
earlier in [5].
The input currents may be expressed as
Iin1
Iin2
1
(Vin1 − Vdd /2)ki1 }
nUt
1
= Ibec exp{
(Vin1 − Vdd /2)ki1 }
nUt
1
· exp{
(Vin2 − Vdd /2)ki2 }.
nUt
= Ibec exp{
In our equilibrium analysis the output current IN o
may be expressed as
IN o
1
(Vin2 − Vdd /2)kno }
nUt
kno
Iin2
ki2
= Ibec (
.
(1)
ki3
ki3 )
1−
(Ibec ) ki1 (Iin1 ) ki1
= Ibec exp{
If ki3 /ki1 = 1 equation 1 reduces to IN o =
Ibec (Iin2 /Iin1 )kno /ki2 which demonstrates the dividing and scaling property of the circuit.
For the output current of the PMOS transistor,
IP o , we obtain
IP o
= Ibec (
Iin1 kkpo
) i2 .
Iin2
(2)
Again if kno /ki2 = kpo /ki2 equation 2 reduces to
IP o = IN o giving us the inverse output. In fact the
inverse of any FGUVMOS circuit may be obtained
by adding the opposite type of MOS device. We
have added the PMOS giving the inverted output.
The simulated output currents of the current divider
are shown in figure 3. The circuit behaves reasonably well within two order of magnitude. A feature
of FGUVMOS circuits is the low supply voltages of
only 0.7V in these simulations.
The symmetry properties of FGUVMOS circuits
may be used to change the current divider into a
current multiplier. By flipping the Ni2 transistor
−7
10
Ino, Iin2=Imax
Po
I in2
I in1
Ino, Iin2=Ibec
C o3
−8
10
Iout
Ipo, Iin2=Imax
C o4
V in2
V in1
I Po
V po
V no
Ino, Iin2=Imin
I No
C i1
−9
C i2
C o1
C o2
10
No
Ipo, Iin2=Imax
−10
10
Ni2
Ni1
Ipo, Iin2=Ibec
−10
−9
10
−8
10
Fig. 6. Improved FGUVMOS current multiplier.
−7
10
10
Iin1
−7
10
Fig. 3. Current divider characteristics.
Pi
I in1
Ipo, Iin2=Imin
Ipo, Iin2=Ibec
Po
−8
10
I Po
C po
C i2
V po
Ino, Iin2=Imax
Iout
C i3
V in2
V in1
Ipo, Iin2=Imax
V no
I No
−9
10
C no
C i1
Ino, Iin2=Ibec
I in2
Ni
No
Ino, Iin2=Imin
−10
10
Fig. 4. Current multiplier.
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−9
10
−8
10
10
−7
10
Iin1
in figure 2 and make it a PMOS transistor, we get a
current multiplier as shown in figure 4. The output
current IP o may be written as
IP o
= Ibec (
(Iin1 )
ki3
ki1
Iin2
k
1+ ki3
(Ibec )
)
kpo
ki2
.
(3)
i1
If ki3 /ki1 = 1 equation 3 reduces to IP o =
Ibec (Iin2 Iin1 /(Ibec )2 )kpo /ki2 .
Again we may read out an inverted version of
our transfer function through the PMOS transistor.
The simulated current multiplier characteristics are
shown in figure 5 and are very similar to the current
−7
10
Ino, Iin2=Imin
Fig. 7. Improved FGUVMOS current multiplier characteristics.
divider regarding dynamic range.
IV. Improved multiplier/divider circuits
A current multiplier with extended dynamic range
and better symmetry may be implemented as a
FGUVMOS circuit. By using two coupling capacitors to the output stages, the effective coupling from
each input terminal is reduced giving an increased
dynamic range. In addition we get symmetrical input stages improving linearity of the multiplier. The
circuit is shown in figure 6. Applying our equilibrium analysis we find the output current, IN o , may
be expressed as
IN o
Ipo, Iin2=Imax
= Ibec (
Iin1 kko1 Iin2 kko2
) i1 (
) i2 .
Ibec
Ibec
(4)
−8
10
Iout
Ino, Iin2=Ibec
Ipo, Iin2=Ibec
−9
10
Ino, Iin2=Imax
Ipo, Iin2=Imin
−10
10
−10
10
−9
−8
10
10
−7
10
Iin1
Fig. 5. Simulated output current of the current multiplier.
Again if ko1 /ki1 = ko2 /ki2 we have that IN o =
Ibec {(Iin2 Iin1 )/(Ibec )2 }ko1 /ki1 . In figure 7 the simulated output of the current multiplier is shown. As
expected the dynamic range is increased to three orders of magnitude and might be increased further by
capacitive division limited by the acceptable SNR.
An interesting feature is to play with the terms
rx and ry . If we let rx = ry = 1/2 in equation 4 we
get
p
Iin1 Iin2
IN o =
−5
10
Pi
Po
I n1
−6
10
C o4
C i2
C o3
I Po
−7
10
V po
V in2
−8
V in1
10
V no
C i1 C o2
I in2
Iout (A)
I No
C o1
Ni
−9
10
No
−10
10
−11
10
Fig. 8. Improved FGUVMOS current divider.
−12
10
−7
10
−13
10
Ipo, Iin2=Imax
−9
10
−8
10
Iin (A)
−7
10
−6
10
Fig. 10. Measured performance of the current multiplier.
The output current as a function of the input current
was measured for different multiplication factors (voltages).
Ipo, Iin2=Ibec
−8
10
Ino, Iin2=Imin
Iout
−10
10
Ipo, Iin2=Imin
−9
10
Ino, Iin2=Ibec
Ino, Iin2=Imax
−10
10
−10
−9
10
−8
10
10
−7
10
Iin1
Fig. 9. Hspice simulation of the improved FGUVMOS current divider output.
IP o
=
I2
√ bec .
Iin1 Iin2
As illustrated, different compressive or expansive
functions might be added just by changing capacitive ratios.
To make the picture complete, we present the improved FGUVMOS current divider.
The output current IN o in figure 8 may be expressed as
IN o
= Ibec (
Iin1 kko1 Ibec kko2
) i1 (
) i2 .
Ibec
Iin2
The measured performance of a current multiplier
is shown in figure 10 with a supply voltage of 0.7V .
The output current is measured as a function of
the input current while varying the multiplying input voltage. Note that a pure current-mode version
of this circuit would not achieve a dynamic range
of this magnitude, but with one voltage-mode input terminal, we could exceed the 0.7V power supply voltage. For higher current-levels transition to
strong inversion may be observed, but for weak inversion the linearity is exceptional.
VI. Conclusion
Novel current-mode multipliers and dividers have
been proposed exploring the power of the FGUVMOS transistor. Low supply voltage is combined
with minimum sized transistors to form a working
current multiplier/divider circuit at 0.7V . The feasibility of our approach is proven through measured
results of a test circuit implemented in standard
double-poly CMOS.
References
If ko1 /ki1 = ko2 /ki2 we have that IN o =
Ibec (Iin1 /Iin2 )ko1 /ki1 . The simulated output currents of the improved current divider are shown in
figure 9. We have our dividing function with improved linearity and dynamic range.
[1]
V. Measured results
[4]
A slightly simplified version of the circuit in figure 7 was implemented in AMS 0.8µ CMOS using minimum transistors. One of the input-current
branches was removed and replaced with a direct
capacitive coupling to a NMOS output transistor.
Before testing the circuits a tuning was done using
a standard 4W UV-eraser according to the procedure required for FGUVMOS transistors [2], [3], [6].
[2]
[3]
[5]
[6]
Analogue IC Design: The Current-mode Approach, Edited book by Toumazou C. et. al., Peter Penegrinus, 1990
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june. 1997.
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Current Mirrors., ASIC97, october. 1997.
R.G. Benson and D.A. Kerns. UV-Activated Conductances Allow For Multiple Scale Learning., IEEE
Transactions on Neural Networks, vol. 4, no. 3, may 1993.
B.A. Minch, C. Diorio, P. Hasler and C.A. Mead.
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and Signal Processing, 9, pp.167-179, Kluwer Academic
Publishers, 1996.
Y. Berg and T.S. Lande. Tunable Current Mirrors
for Ultra Low Voltage., ISCAS99, may-june. 1999.