TI Designs
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit
Ethernet Reference Design
TI Designs
Design Features
TI Designs provide the foundation that you need
including methodology, testing and design files to
quickly evaluate and customize the system. TI Designs
help you accelerate your time to market.
•
Design Resources
•
TIDA-00204
Design Folder
DP83867IR
LM46002
AM3359
TPS65910A3
TPS51200
LMZ10501
TPS720
TPS737
TPD4E05U06
TPS717
TPD4S012
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
Product Folder
•
•
•
•
ASK Our E2E Experts
WEBENCH® Calculator Tools
EMI- and EMC-Compliant Design With Wide Input
Voltage Range (17 to 60 V) Using Two DP83867IR
Gigabit Ethernet PHYs and AM3359 Sitara™
Processor to Work in Harsh Industrial
Environments
Exceeds CISPR 11 / EN55011 Class A Radiated
Emission Requirement by > 4.3 dB
Exceeds IEC61800-3 EMC Immunity
Requirements:
– ±6-kV ESD CD per IEC 61000-4-2
– ±4-kV EFT per IEC 61000-4-4
– ±2-kV Surge per IEC 61000-4-5
Sitara AM3359 Firmware, Including UDP and
TCP/IP Stack and HTTP Web Server Examples,
Boots From Onboard SD-Card Allowing Easy
Standalone Operation
Access to DP83867IR Registers Through USB
Virtual COM Port Allows for Custom Specific PHY
Configurations Such as RGMII Delay Mode
Hardware Support for Start-of-Frame (SOF) Detect
Allows Implementation of IEEE 1588 PTP
Featured Applications
•
•
•
•
Micro
USB
Boot application
firmware from
SD-Card
Micro
SD
DDR3
Reset
button
24-MHz
clock
JTAG/
UART
Sitara PMIC
DDR3 P/S
Application firmware
- IPv4 TCP/IP
- UDP
- IP address:
192.168.1.10
- HTTP webserver
example
Host processor
Sitara AM3359
Gigabit PHY P/S
10/100/
1000 Mb/s
Ethernet
PHY1
DP83867IR
10/100/
1000 Mb/s
Ethernet
PHY2
DP83867IR
25-MHz
crystal/clock
Status LEDs
Magnetics
Optional access
DP83867IR
registers through
virtual COM port
24-V to 5-V
DC/DC
RJ45
Port 1
RJ45
Port 2
25-MHz
crystal/clock
Status LEDs
Magnetics
Input: 24 V
(17 to 60 V)
Industrial Drives
Factory Automation and Control
Industrial Networks
Test and Measurement
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
All trademarks are the property of their respective owners.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
1
System Description
www.ti.com
1
System Description
1.1
TI Design Overview
This TI design supports dual-port Gigabit Ethernet communication through twisted pair copper cable as
defined in IEEE 802.3ab. It is designed to be evaluated for harsh industrial environment with regards to
standard compliance to CISPR 11 / EN55011 Class A radiated immunity requirements and EMC immunity
requirements for ESD according to 61000-4-2, fast transient burst (EFT) according to IEC61000-4-4, and
surge according to IEC61000-4-5.
The design implements dual-port Gigabit Ethernet using two DP83867IR Gigabit Ethernet PHYs, which
are connected through the Reduced Gigabit Media Independent Interface (RGMII) to AM3359 Sitara
processor with integrated Ethernet MAC and Switch. It offers a wide input voltage range from 17 to 60 V
with nominal 24-V input voltage and meets industrial requirements for EMI and EMC.
For easy standalone operation, the host processor is configured to boot the pre-installed application
firmware from an onboard SD-Card. The application firmware implements a driver for the DP83867IR,
UDP and TCP/IP stack, and HTTP web server examples, based on TI’s SYS/BIOS Industrial SDK and TI’s
Networking Development Kit NDK. A USB virtual COM port offers optional user access to read or write to
DP83867IR registers for custom configurations like RGMII Delay Mode, if required. A JTAG interface on
the AM3359 provides the option for custom software development, test, and debug.
Therefore, this design allows for performance evaluation of two DP83867IR Gigabit Ethernet PHYs and
AM3359 Sitara processor with integrated Ethernet MAC and Switch.
Micro
USB
Boot application
firmware from
SD-Card
Micro
SD
DDR3
Reset
button
24-MHz
clock
JTAG/
UART
Sitara PMIC
DDR3 P/S
Application firmware
- IPv4 TCP/IP
- UDP
- IP address:
192.168.1.10
- HTTP webserver
example
Host processor
Sitara AM3359
Gigabit PHY P/S
10/100/
1000 Mb/s
Ethernet
PHY1
DP83867IR
10/100/
1000 Mb/s
Ethernet
PHY2
DP83867IR
25-MHz
crystal/clock
Status LEDs
Magnetics
Optional access
DP83867IR
registers through
virtual COM port
24-V to 5-V
DC/DC
RJ45
Port 1
RJ45
Port 2
25-MHz
crystal/clock
Status LEDs
Magnetics
Input: 24 V
(17 to 60 V)
Figure 1. System Block Diagram of TIDA-00204
2
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
System Description
www.ti.com
1.2
Gigabit Ethernet Overview
Ethernet has heavily expanded usage over the years. Ethernet became an attractive option for industrial
networking applications. The opportunity to use open protocols (such as TCP/IP over Ethernet networks)
help replace proprietary communications in industrial control and factory automation applications. When
using Ethernet, there are several speeds available today: 10 Mb/s, 100 Mb/s (Fast Ethernet), 1000 Mb/s
(Gigabit Ethernet), and 10 Gb/s (10-Gigabit Ethernet).
Gigabit Ethernet uses the extended Ethernet MAC layer interface, connected through a Gigabit Media
Independent Interface (GMII) layer to physical layer entities (PHY sublayers) such as 1000BASE-LX,
1000BASE-SX, 1000BASE-CX, and 1000BASE-T. The topology for a 1000-Mb/s full-duplex operation is
comparable to the 100BASE-T full-duplex mode, and the minimum packet transmission time has been
reduced by a factor of ten. The resulting achievable topologies for the half-duplex 1000-Mb/s CSMA/CD
MAC are similar to those found in half duplex 100BASE-T.
Table 1. Gigabit Ethernet Standards
IEEE STANDARD
NAME
MEDIUM
IEEE 802.3ab
1000BASE-T
Twisted-pair copper cable
1000BASE-SX
Fiber optic cable
1000BASE-LX
Fiber optic cable
1000BASE-CX
Twinax
IEEE 802.3z
As previously mentioned. this TI design is using twisted pair copper cables as defined IEEE 802.3ab.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
3
System Description
1.3
1.3.1
www.ti.com
Gigabit Ethernet PHY Interfaces
Medium Dependent Interface: PHY Layer 1000BASE-T
The 1000BASE-T Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and baseband
medium specifications are intended for users who want a 1000-Mb/s performance over balanced twistedpair cabling systems.
The 1000BASE-T PHY supports full-duplex baseband transmission through four pairs of minimum CAT5
balanced cables. The 1000 Mb/s is achieved by transmitting through four wires pairs, each at 250 Mb/s.
Using hybrids and cancellers enable full duplex transmission by allowing symbols to be transmitted and
received on the same wire pairs at the same time. Baseband signaling with a modulation rate of 125 MBd
is used on each of the wire pairs. The transmitted symbols are selected from a four-dimensional five-level
symbol constellation (4D-PAM5). In the absence of data, idle symbols are transmitted.
The IEEE 802.3 specifies specify that a PHY with a MDI that is not a power interface (PI) should provide
electrical isolation between the port device circuits, including frame ground (if any) and all MDI leads. This
electrical isolation shall withstand at least one of the following electrical strength tests:
• 1500 VRMS at 50 to 60 Hz for 60 s
• 2250-V DC for 60 s
• A sequence of ten 2400-V impulses of alternating polarity, applied at intervals of not less than 1 s
To meet this requirement transformers are typically used for isolation. The typical transformer
configuration for 1000BASE-T can be seen in Figure 2 for a one differential pair.
MDI_1+
MDI_1to PHY
1:1
to RJ45
Figure 2. Gigabit Ethernet Transformer (One out of Four Pairs)
Depending on the PHY device, parallel termination might be needed for each of the MDI differential signal
pair. The termination impedance is typically 100 Ω differentially. Newer devices like the DP83867IR
include integrated termination so no external termination resistors are required.
4
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
System Description
www.ti.com
1.3.2
Medium Independent Interface: MAC Layer Interface
For the MAC layer interface to the Gigabit PHY, there are three different options defined in the IEEE
802.3ab standard: The standard Media Independent Interface (MII), the GMII, SGMII, or the RGMII.
1.3.2.1
GMII
The purpose of GMII is to make various physical media transparent to the MAC layer. The GMII accepts
either GMII or MII data, control, and status signals and routes them either to the 1000BASE-T, 100BASETX, or 10BASE-T modules, respectively.
The GMII provides full-duplex operation and is an 8-bit wide transmit and receive data path interface
clocked at 125 MHz defining speeds up to 1000 Mb/s. GMII is backwards compatible with the MII
specification, thereby supporting 10 (2.5 MHz) and 100 (25 MHz) Mb/s speeds. Data and delimiters are
synchronous to clock references. It also provides a simple management interface.
The transmit signals are GTX_CLK, TX_CLK, TX_D[7:0], TX_EN, and TX_ER. The GTX_CLK signal is
supplied to the PHY when it is operating in Gigabit mode. When this is done, the TX_D, TX_EN, and
TX_ER are synchronized to the GTX_CLK signal. For a 10/100-Mb operation, the TX_CLK is supplied to
the MAC, and the TX_CLK signal is used to synchronize the signals (TX_D, TX_EN, and TX_ER). The
receiver signals are RX_CLK, RX_D[7:0], RX_DV, RX_ER, COL, and CS. The GMII uses in total a
maximum of 25 pins.
1.3.2.2
RGMII
The RGMII is designed to reduce the number of pins required to interconnect the MAC and PHY (12 pins
for RGMII relative to 24 pins for GMII). With this optimization, the RGMII consists of 12 signals: 6 signals
for receive, which are RX_CTL, RX_CLK, RX_D[3:0], and 6 for transmit, which are TX_CTL,
TX_CLK,TX_D[3:0]. To accomplish this, the data paths and all associated control signals are reduced and
are multiplexed. Both rising and trailing edges of the clock are used. The TX_CTL and RX_CTL signal
carries data valid (DV) on the rising edge and DV XOR ERROR on the falling edge, for CTL signals there
is no change between 10/100Mb/s or 1000Mb/s operation.
For a Gigabit operation, the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and 100-Mb/s
operation, the clock frequencies are 2.5 MHz and 25 MHz, respectively.
1.3.2.3
SGMII
The SGMII differs from the GMII and RGMII by having a higher clock frequency and the 8b/10b (SerDes)
coded interface. It uses differential pairs at a 625-MHz clock frequency double data rate (DDR) for TX and
RX data and for TX and RX clock. The transmit and receive path uses one differential pair for data and in
some cases one for clock. TX and RX clocks must be generated on device output but are optional on
device input. With revision 1.8 of the SGMII standard, clock recovery can be used, removing the need for
the clock signal. This means that the SGMII can be a 4- to 8-pin solution.
1.3.3
Serial Management Interface
The serial management interface (SMI) consists of a Management Data Clock (MDC) and a Management
Data Input/Output (MDIO) signal. It provides access to the PHY’s internal register space for status
information and configuration. The MDC and MDIO signals can be shared amongst several PHYs due to
the serial communication protocol, where an address is used to identify the corresponding PHY slave. The
MDIO has a standard set of registers from 0 to 31 each containing 16 bits. In IEEE 802ah clause 45, an
extended register set was defined for extra functionality of the PHYs. The SMI is initially specified at a
2.5-MHz clock.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
5
System Description
1.4
www.ti.com
IEEE 1588v2
Precise time information is important, especially for distributed systems like in factory automation. The
IEEE 1588v2 is an IEEE standard for precision clock synchronization protocol for networked measurement
and control systems. The protocol is used to synchronize the time and clock frequency. It defines a way to
provide sub-microsecond precision synchronization.
To define this synchronization, the start of package detection is needed. Depending on which application
layer this detection happens, the timing error varies. The lower the layer, the smaller the error.
Processor
IEEE1588 code
(Application layer)
4
OS
3
Hardware assist
MAC
2
1
Ethernet PHY
Figure 3. Options 1 to 4 for Time Stamp versus Layer
The closer to the PHY the time stamp is set the better the time reference. The time stamp consists of two
signals the Ingress (RX) and Egress (TX) time stamp. Depending on when the time stamp is done, the
delay can vary from nanoseconds to microseconds.
6
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Features
www.ti.com
2
Design Features
This design allows for performance evaluation of two DP83867IR Gigabit Ethernet PHYs and AM3359
Sitara™ processors with an integrated Ethernet MAC and Switch. It meets industrial requirements for EMI
and EMC, supports industrial temperature grade, and offers a wide input voltage range with a default of 24
V.
To allow for easy standalone operation, the AM3359 Sitara boots the application firmware from SD-Card.
The application firmware implements the driver for the DP83867IR, UDP and TCP/IP stack, and HTTP
web server examples and is based on TI’s SYS/BIOS Industrial SDK. An additional option is provided to
access the DP83867IR Gigabit Ethernet PHY registers through USB virtual COM port. A JTAG interface
option is also provided to allow for custom software development with that board.
Table 2. TIDA-00204 Hardware Specification
FUNCTION
INFO
Number of ports
MDI
RGMII
EMAC and switch
Y
Status LED
Y
IEEE 1588v2
Y
Hardware enabled but not
tested
Separate transformer and
RJ45 jack
Y
Option to place protection
diodes on either side of the
magnetics, used for test
purpose
SMI
Integrated with Sitara AM3359
Y (2.5 MHz)
Configurable PHY address
(SMI)
Low power
DP83867IR
COMMENT
2
1000BASE-T (copper)
MAC interface
Gigabit Ethernet IEEE 802.3ab
SPECIFICATION
Y
Through strap resistors
565 mW
Integrated termination resistors
RGMII Delay Mode on RX/TX
Clock
Y
Programmable
25 MHz (< 50 ppm)
Input voltage
24 V (17 to 60 V)
Output voltage
5V
Output current
850 mA (nominal), 1.2 A
(maximum)
Indicator LED
Y
For 5 V, 3.3 V and 2.5 V
Point of load for all ICs
Y
PMIC for AM3359, 3.3 V (I/O),
2.5 V and 1.1 V for PHYs
Standalone operation
Boot from SD-Card interface
Y
USB virtual COM port
Access to PHY registers
Y
JTAG header
Y
Power
JTAG
Temperature range
EMI
EMC
Industrial
–40°C to 85°C
CISPR 11 / EN55011
IEC61800-3
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Intermediate voltage
Read and write operation to
both registers of PHY
supported
Selected devices support
industrial temperature range
Class A radiated emissions
IEC61000-4-2 ±4-kV ESD CD,
Criterion B
Shielded Ethernet cable
IEC61000-4-4 ±2-kV EFT,
Criterion B
Shielded Ethernet cable
IEC61000-4-5 ±1-kV Surge,
Criterion B
Shielded Ethernet cable,
min 20 m
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
7
Design Features
www.ti.com
Table 3. TIDA-00204 Firmware Specification (AM3359)
FUNCTION
INFO
SPECIFICATION
Boot loader
Boot application firmware from SD-Card
Y
DDR3 memory
Driver for DDR3
Y
USB virtual COM port
Driver for UART
Y
Driver for DP83867IR
Y
TI SYS/BIOS
Y
IPv4 protocol support
Y
PHY
RTOS
UDP and TCP/IP
Fixed IP
HTTP
8
COMMENT
Based on TI’s AM335x
industrial SDK and NDK
192.168.1.10
Web server example
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
Y
Based on TI’s AM335x
industrial SDK and NDK
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Block Diagram
www.ti.com
3
Block Diagram
Figure 4 shows the system block diagram. The major building blocks are the DP83867IR Gigabit Ethernet
PHY, the AM3359 Sitara Host Processor, and the power supplies.
Micro
USB
JTAG/
UART
Boot application
firmware from
SD-Card
Sitara PMIC
DDR3 P/S
Application firmware
- IPv4 TCP/IP
- UDP
- IP address:
192.168.1.10
- HTTP webserver
example
Micro
SD
DDR3
Reset
button
24-MHz
clock
Host processor
Sitara AM3359
Gigabit PHY P/S
10/100/
1000 Mb/s
Ethernet
PHY1
DP83867IR
10/100/
1000 Mb/s
Ethernet
PHY2
DP83867IR
25-MHz
crystal/clock
Status LEDs
Magnetics
Optional access
DP83867IR
registers through
virtual COM port
24-V to 5-V
DC/DC
RJ45
Port 1
RJ45
Port 2
25-MHz
crystal/clock
Status LEDs
Magnetics
Input: 24 V
(17 to 60 V)
Figure 4. System Block Diagram of TIDA-00204
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
9
Circuit Design and Component Selection
www.ti.com
4
Circuit Design and Component Selection
4.1
DP83867IR 10/100/1000-Mb/s Gigabit Ethernet PHY
The DP83867IR was selected due to following features:
• IEEE 802.3ab 1000BASE-T compliant
• Operating temperature range –40°C to 85°C
• 8-kV IEC 61000-4-2 ESD protection (direct contact)
• RGMII with software (register) programmable and hardware configurable (strap resistors) clock skew
• Integrated termination resistors
• Low power: 565 mW
• SOF detect for IEEE 1588 time stamp
In
•
•
•
4.1.1
addition to the above features, the DP83867IR also offers the following features:
Low deterministic TX and RX latency
Wake on LAN (WoL)
Synchronized clock output to synchronize multiple PHYs using one crystal (or clock)
DP83867IR Gigabit Ethernet PHY Configuration
When configuring the DP83867IR, this can be done using either a SMI or a strap configuration through the
four-level strap pins. A pull-up resistor and a pull-down resistor of suggested values may be used to set
the voltage ratio of the four-level strap pin input and the supply to select one of the possible selected
modes. The device should feature four-level strap pins, each supporting at least four selectable options,
as shown in Figure 5 and Table 4. Strap resistors with 1% tolerance are recommended.
VDDIO
RHI
Strap (GPIO)
RLO
Figure 5. Strap Circuit
Table 4. Four-Level Strap Resistor Ratios
MODE
RESISTOR RHI (kΩ)
RESISTOR RLO (kΩ)
1
OPEN
OPEN
2
11
2.49
3
6.04
2.49
4
2.49
OPEN
Because this design employs two DP83867IR, the SMI will have two DP83867IR slaves addresses. This
means that the SMI address of the two DP83867IR have to differ to ensure a valid communication. To set
the DP83867IR SMI address a strap configuration option can be used on one DP83867IR to change the
default address from 0x00. In this design, it was chosen to use the pin RX_D4 to set the SMI address, as
this pin is not used for the RGMII.
10
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
A strap configuration option was chosen so the RGMII is always enabled to ensure the RGMII is enabled
when as the RX_D6 pin is used as input pin on the AM3359 Sitara processor.
As the clock out option of the device is not used by default, RX_D7 strap configuration option was done to
disable the clock out of the device. This feature is default on if this strap on is not done and if it needs to
be disabled without strap configuration. It would have to be done using the SMI.
RGMII2_RXCTRL
Vddio
RGMII2_RXCLK
RGMII2_RXCTRL_R
0
R44
RGMII2_RXCLK_R
0
R46
R47
0
R50
0
R51
0
0
R49 RGMII2_RXD0
11.0k RGMII2_RXD1
RGMII2_RXD2
RGMII2_RXD3
Vddio
R56
R57
2.49k
R43
RGMII2_RXD0_R
RGMII2_RXD1_R
RGMII2_RXD2_R
RGMII2_RXD3_R
PHY2_RX1588
11.0k
Vddio
R60
560
R62
2.49k
1
R61
2.49k
RX_DV/RX_CTRL
RX_ER/GPIO
RX_CLK
44
45
46
47
48
49
50
51
RX_D0
RX_D1
RX_D2
RX_D3
RX_D4/GPIO
RX_D5/GPIO
RX_D6/GPIO
RX_D7/GPIO
R59
11.0k
PHY2_TX1588
53
54
43
GND
D12
Orange
COL/GPIO
CRS/GPIO
1
7
9
16
RESERVED
RESERVED
RESERVED
RESERVED
2
GND
55
56
DP83867IRPAPR
GND
Figure 6. Schematic for DP83867IR Strap Configuration on ETH2
Table 5. DP83867IR Strap on Resistor Chosen
DP83687IR PIN NAME
CONFIGURATION
MODE
RX_D4
Strap resistors
2 (PHY_ADD4 = 1, only ETH2)
RX_D6
Strap resistors
2 (RGMII enable)
RX_D7
Strap resistors
2 (Clock out disable)
2.49 NŸ
LED_0
Mode 1
470 Ÿ
470 Ÿ
VDDIO
Mode 4
LED_1
When using the strap configuration on a specific pin, ensure that the additional function mapped to this pin
is applicable. For example, due to this the TX_D0 to TX_D3 and RX_D0 to RX_D3 pins, which are used
by the RGMII, have not been used for strap configuration. This is because this strap resistor configuration
would have needed to be compensated with trace matching from the other RGMII pins used. Another
example is the LED indicator pins: When used with both LED functionality and strap configuration, take
caution on how to connect the LED with regards to the strap resistors. An example for strap mode 0 and
strap mode 4 with indicator LED is shown in Figure 7.
GND
Figure 7. Example Strap Connections With Indicator LEDs for Mode 1 and Mode 4
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
11
Circuit Design and Component Selection
4.1.2
www.ti.com
MAC Layer Interface
The MAC interface of this design was chosen according to minimum number of pins at lowest possible
clock frequency. See Table 6 of the pin definitions.
Table 6. MAC Interface Option Pinout for the Different Standards
DECISION CRITERION
Number of MAC interface signals
Clock frequency
GMII
RGMII
24
12
SGMII
4 or 8
125 MHz
125 MHz
625 MHz
With those considerations, the choice was to use the RGMII as it is running at a lower frequency than the
SGMII. Therefore, the RGMII allows for easier PCB routing of the signals, and the number of signals is
acceptable.
The RGMII signals are not differential but single-ended, and they are referenced to a clock signal of
125 MHz. It is crucial that length matching is done properly for all signals to avoid skew due to different
propagation delay between the clock and the data signals.
For this design, the following length matching was done on the RGMII signals.
Table 7. DP83867 RGMII Trace Length on TIDA-00204 PCB
RGMII SIGNAL
TX LENGTH (mm)
RX LENGTH (mm)
PHY1 CLK
29.9925
29.9984
PHY1 CTRL
29.9944
29.9937
PHY1 D0
29.9902
29.9941
PHY1 D1
29.9650
29.9918
PHY1 D2
29.9860
29.9918
PHY1 D3
29.9994
29.9918
PHY2 CLK
32.4950
32.4993
PHY2 CTRL
32.4659
32.5294
PHY2 D0
32.4924
32.4958
PHY2 D1
32.4877
32.4989
PHY2 D2
32.4937
32.4990
PHY2 D3
32.4676
32.4990
Here, it can be seen that the PHY1 RGMII traces are length matched with a maximum length difference of
0.034 mm, and for PHY2 with a maximum difference of 0.064 mm.
Additional considerations are to place each PHYs RGMII TX and RX on the same layer and add series
termination resistors close to the corresponding output pins. Because the DP83867IR has an integrated
50-Ω series impedance, a 0-Ω series termination has been placed at the DP83867 RGMII RX output pins.
This was a test and debug option and the termination resistor (array) can be removed in a production
design.
A 22-Ω series termination resistor was placed close to the RGMII1 and RGMII2 TX pins of the AM3359
Sitara.
12
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
4.1.3
Interface From PHY to RJ-45
The transformer used in the MDI connection provides DC isolation between local circuitry and the network
cable. The center tap of the isolated winding has a "Bob Smith" termination through a 75-Ω and a 1000-pF
capacitor-to-chassis ground. The termination capacitor should be voltage rated to at least 2 kV. The Bob
Smith termination reduces noise resulting from common mode current flows.
NOTE: A TVS diode has been placed each between the DP83867IR and the transformer and the
transformer and the RJ45 jack. This was a test and debug option only and the position
between the DP83876IR and the magnetics showed slightly better results in EMC and EMI,
as shown in Figure 8.
RBIAS
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_TRSTN
LED_0
LED_1
LED_2
MDC
MDIO
INT/PWDN
RESET
XI
XO
CLK_OUT
GND
PHY1_TD_B_P
PHY1_TD_B_N
10
11
PHY1_TD_D_N
PHY1_TD_D_P
PHY1_TD_C_N
PHY1_TD_C_P
GND
6
7
9
10
NC
NC
NC
NC
GND
1
2
PHY1_TD_B_N
PHY1_TD_B_P
PHY1_TD_A_N
PHY1_TD_A_P
R23
8
3
4
0.1µF
PHY1_TD_C_N
6
7
9
10
GND
6
PHY1_TD_C_P
D1+
D1-
D2+
D2-
NC
NC
NC
NC
GND
GND
4
5
PHY1_TD_B_P
PHY1_TD_B_N
0.1µF
PHY1_TD_B_N
60
R29
R25
560
10
0.1µF
PHY1_TD_A_N
D4
Yellow
PHY_RESETn
19
18
R35
DNP
22
22
65
R26
560
11
12
R27
560
MX1+
TD1-
MX1-
TCT2
MCT2
TD2+
MX2+
TD2-
MX2-
19
TCT3
MCT3
18
TD3+
MX3+
TD3-
MX3-
23
D5
Red
GND
GND
MCT4
TD4+
MX4+
TD4-
MX4-
PHY1_X_D_N
75.0
22
21
20
17
PHY1_X_D_P
R24
PHY1_X_C_N
75.0
J4
PHY1_X_C_P
R32
PHY1_X_B_N
75.0
16
15
14
1
2
3
4
5
6
7
8
9
10
11
12
PHY1_X_B_P
R37
PHY1_X_A_N
75.0
43202-8916
13
PHY1_X_A_P
C33
1000pF
C34
DNP
D6
Green
GND
TCT4
R22
HX5008FNL
4.7k
PHY1_INTPWDN
59
MCT1
TD1+
C30
TPD4E05U06DQA
Vddio
8
9
PHY1_TD_B_P
8
3
PHY1_TD_A_P
MDIO_CLK_1
MDIO_DATA_1
5
7
GND
20
21
24
TCT1
C29
PHY1_TD_A_P
PHY1_TD_A_N
4.7k
2
3
U9
10.0k
63
62
61
0.1µF
PHY1_TD_D_N
C28
GND
GND
GND
R21
15
PHY1_TD_D_P
PHY1_TD_D_N
TPD4E05U06DQA
PHY1_TD_D_P
PHY1_TD_D_N
28
26
25
27
24
4
5
PHY1_TD_D_P
PHY1_TD_C_P
PHY1_TD_C_N
13
14
D2+
D2-
1
TD_P_D
TD_M_D
5
6
1
D1+
D1-
2
TD_P_C
TD_M_C
C26
1000pF
PHY1_TD_A_P
PHY1_TD_A_N
T1
C27
U7
1
2
PHY1_TD_C_P
PHY1_TD_C_N
1
TD_P_B
TD_M_B
2
3
V18phy
R18
DNP
0
2
TD_P_A
TD_M_A
GND
R17
DNP
0
17
64
1
VDDA1P8
VDDA1P8
C25
1000pF
V11phy
8
29
42
58
2
VDD1P1
VDD1P1
VDD1P1
VDD1P1
PHY1_EARTH
1000pF
GND
GND
PHY1_EARTH
PHY1_EARTH
R36
PHY1_CLKOUT
1.00M
1
Y1
2
ABM3-25.000MHZ-D2Y-T
25 MHz
GND
C31
27pF
C32
27pF
GND
Figure 8. Schematic of Media Dependent Interface of ETH1
The trace length that needs to be considered is from RJ45 to magnetic and from magnetic to DP8867IR,
for these signals they are differential pairs. This means that the signals needs to be routed differentially as
long as possible without making the traces longer than necessary. To ensure data integrity, the trace’s
difference should be below 10 mil (0.254 mm).
Table 8. Differential Signal Trace Length From PHY to Magnetic and Magnetic to RJ45 Jack
MEDIA DEPENDENT INTERFACE
RJ45 TO MAGNETIC (mm)
MAGNETIC TO DP8867IR (mm)
PHY1 Differential pair A (N,P)
13.0123 (N), 13.0708 (P)
10.0302 (N), 10.0302 (P)
PHY1 Differential pair B (N,P)
13.1709 (N), 13.3115 (P)
10.0223 (N), 10.0223 (P)
PHY1 Differential pair C (N,P)
13.1321 (N), 13.0146 (P)
10.0175 (N), 10.0082 (P)
PHY1 Differential pair D (N,P)
13.0804 (N), 13.0003 (P)
10.0163 (N), 10.0163 (P)
PHY2 Differential pair A (N,P)
12.9469 (N), 13.0056 (P)
13.3910 (N), 13.4938 (P)
PHY2 Differential pair B (N,P)
12.9398 (N), 13.0815 (P)
13.1988 (N), 13.1047 (P)
PHY2 Differential pair C (N,P)
13.0899 (N), 13.0409 (P)
13.0679 (N), 13.1622 (P)
PHY2 Differential pair D (N,P)
13.1864 (N), 13.1063 (P)
13.3252 (N), 13.2272 (P)
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
13
Circuit Design and Component Selection
www.ti.com
To ensure no unnecessary stubs, all traces are routed on the top layer. The only exception is the pins
D2_P and D2_N. Due to the RJ45 jack pin assignment without integrated transformer, this differential pair
changed the layer to minimize the overall differential trace length of the four pairs.
Table 9. RJ45 Connector Pinout
4.1.4
PIN
SIGNAL
PIN
SIGNAL
1
D1_P
5
D3_N
2
D1_N
6
D2_N
3
D2_P
7
D4_P
4
D3_P
8
D4_N
DP83867IR Input Clock Selection
For the input clock, either a crystal or an external clock source can be used. For both cases, the clock
needs to be 25 MHz with a tolerance of less than ±50 ppm. For more details, refer to the DP83867IR
datasheet, Sections 8.2.1.2 and 8.2.1.3 [1]. For this design, a 25-MHz crystal was chosen (see Section 4.4
for more details).
The DP83867IR has a clock out pin CLK_OUT too. This allows to route the 25-MHz clock from one
DP83867IR PHY to the second DP83867IR PHY and eliminates the need for a crystal at the second PHY,
reducing costs. The TIDA-00204 design has been prepared for this configuration by adding series 0-Ω
resistors.
4.1.5
Power and Ground Pins
For each of the three power rails on the DP83867IR, decoupling capacitors are recommended as follows.
A 1-nF capacitor is recommended be placed close to each supply pin of the DP83867IR. A 10-nF and a
10-µF capacitor are recommended per supply rail.
4.1.6
PHY RESET
The DP83867IR PHYs are automatically reset after power-up, through signal SYS_RESETn. Additionally,
the DP83867IR hardware reset signal PHY_RESETn can be issued by the Sitara AM3359 GPIO pin with
the signal GPIO_PHY_RESETn, which offers a software option to reset the PHYs if needed.
Vddio
C35
0.01µF
GPIO_PHY_RESETn
1
4
2
3
SYS_RESETn
GND
5
R38
10.0k
PHY_RESETn
U11
SN74AHC1G08DCK
GND
Figure 9. PHY Reset Option During Power Up (SYS_RESETn) and Software Reset (GPIO_PHY_RESETn)
14
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
4.1.7
Not Connected Pins on DP83867
Table 10. DP83867IR Not Connected Pins
4.2
PINS
REASON
TXD4:7
Internal pull-down
TX_ER
Internal pull-down
TX_CLK
Output
COL
Internal pull-down
CRS
Internal pull-down
Reserved
Reserved
JTAG (TDI, TMS, TCLK)
Internal pull-up
JTAG (TDO)
Output
Host Processor
The Sitara AM3359 was chosen as it has a 2-Gb Ethernet MAC with switch layer supporting RGMII to
both DP83867IRs. The MAC switch layer inside the AM3359 is supporting several features of passing
messages from one PHY to the other without the use of the core. To achieve deterministic and very low
transmit and receive latency, the ICSS/PRU subsystem can be used to capture the start of frame for IEEE
1588 time stamp. The TIDA-00204 hardware is provisioned for this feature but not tested.
4.2.1
AM3359 Boot Mode Configuration
The AM3359 internal ROM code selects the corresponding peripheral based on the level of the SYSBOOT
configuration at power on reset of the device. For the full details of this boot procedure, read Sections
26.1.5 to 26.1.8 of the Technical Reference Manual of the AM335x Sitara processors.
For easy standalone operation, the AM3359 has been configured to boot from MMC1/SD-Card. This
configuration requires the SYSBOOT[15:0] pins to be "0100 0000 0001 1100". This is achieved by setting
the corresponding pull-up and pull-down resistors as per the schematics in Figure 10.
Vaux2
R83
DNP
10k
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k
R94
10k
R95
10k
R96
R97
R98
10k DNP
10k DNP
10k
SYS_BOOT0
SYS_BOOT1
SYS_BOOT2
SYS_BOOT3
SYS_BOOT4
SYS_BOOT5
SYS_BOOT6
SYS_BOOT7
SYS_BOOT8
SYS_BOOT9
SYS_BOOT10
SYS_BOOT11
SYS_BOOT12
SYS_BOOT13
SYS_BOOT14
SYS_BOOT15
R101 R102 R103 R104 R105
100kDNP
100k 100k 100k 100k
R106 R107
100k 100k
R108 R109 R110
100k 100k 100k
R111 R112 R113 R114
100kDNP
100kDNP
100kDNP
100k
R115
100k
R116
100k
GND
Figure 10. AM3359 SYSBOOT Pin Configuration for MMC1/SD-Card Boot Mode
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
15
Circuit Design and Component Selection
4.2.2
www.ti.com
AM3359 GPIO Pin Assignment
When using the Sitara before starting the design, ensure that the peripherals functions required for the
design can be assigned to the specific GPIO pins without a mux conflict. For this purpose, there is a pin
mux tool utility for TI processors called PINMUXTOOL-V3. The tool can be downloaded from the TI
website (www.ti.com). There are specific versions pending the device, part, and package. This tool is a
huge help for AM3359 pin assignment.
This design uses the following peripherals: EMAC with RGMII1 and RGMII2, UART, MMC0 and MMC1,
MDIO, SDRAM/DDR3, I2C, and ECAP.
The pin mux tool was used to find the optimum pin assignment for the different peripherals used in the
TIDA-00204 reference design.
Table 11. AM3359 Pin Assignment
SIGNAL
PINS (GPIO MODE)
AMOUNT OF PINS
RGMII1
J16-J18, K15-K18, L15-L18, M16 (Mode 2)
12
RGMII2
R13-14, V14-V17, U14-U16, T14-T16 (Mode 2)
12
UART
G15-G16(Mode 3)
2
MMC
U9, V9 (Mode 2), U7, V7, R8, T8 (Mode 1)
6
MDIO
M17-M18 (Mode 0)
2
JTAG
Fixed pins not available with mux
8 to 11
SDRAM (DDR3)
Fixed pins not available with mux
52
C16-C17 (Mode 0)
2
U13 (Mode 5), C15 (Mode 2), C18 (Mode 0), E15 (Mode 4)
4
I2C
ECAP
The remaining pins could be used in GPIO mode or assigned to unused peripherals on the AM3359
device.
16
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
4.2.3
MMC1 Micro SD-Card
Figure 11 shows the micro SD-Card interface including ESD protection device on the TIDA-00204. The
TPD6E001 is a low-capacitance ±15-kV ESD-protection diode array designed to protect sensitive
electronics attached to communication lines. Each channel consists of a pair of diodes that steer ESD
current pulses to VCC or GND. The TPD6E001 protects against ESD pulses up to ±15-kV human-body
model (HBM), ±8-kV contact discharge (CD), and ±15-kV air-gap discharge, as specified in
IEC 61000-4-2.
Vmmc
R120
10k
R121 R122
10k
10k
R123 R124
10k
10k
R125
10k
C202
10µF
C203
0.1µF
J6
GND
MMC1_DAT2
MMC1_DAT3
MMC1_CMD
1
2
3
4
5
6
7
8
MMC1_CLK
MMC1_DAT0
MMC1_DAT1
10
11
U18
1
2
3
4
Vmmc
10
IO1
IO2
IO3
IO4
IO5
IO6
NC
NC
VCC
GND
6
7
8
DAT2
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1
S1
S2
S3
S4
CD
SW
9
12
13
14
502774-0891
GND
9
5
MicroSD_case
TPD6E001RSER
C205
C206
0.01µF
GND
0.1µF
GND
MicroSD_case
Figure 11. MMC1 Micro SD-Card Interface With ESD Protection
4.2.4
I2C Communication to PMIC and EEPROM
The I2C module 0 is used for communicating with both, the EEPROM, and the Power Management IC
(PMIC). The PMIC I2C is hardcoded to the I2C address equal to 0101101 binary or 0x2D in hex.
The EEPROM was given the binary address 1010000 equal to 0x50 in hex. This is done by setting the A2,
A1, and A0 pin. This then forms the 7-bit address as "1010A2A1A0".
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
17
Circuit Design and Component Selection
4.2.5
www.ti.com
DDR3 RAM
For this design, the MT41J128M16JT-125K TR DDR3 RAM was chosen to leverage experience from the
TI AM3359 Industrial Communications Engine development platform with part number TMDSICE3359.
This memory requires a 1.5-V supply with a rise time better than 200 ms. During this time a VTT supply
needs to be provided as this rail is a system supply for signal termination resistors. Once powered, the
device needs to be reset before going into the initialization state. Then the memory is ready for operation.
Due to the speed of the signals to the DDR3 RAM, length matching and termination are important to
ensure performance. For the data lines, length matching was done by defining different net classes with
specific considerations. The concept of defining different net classes is important when routing high speed
signals, as they can insure timing constraints or timing relationships. When defining these groups, it is
important to understand the basics of the DDR3 memory signals. For DDR3, the signals can be divided
into four different groups that have similar requirements.
Table 12. DDR3 Net Class Definitions
NET CLASS
Data
Address/Command
Control
Clock
SIGNALS
DDR_D[15:0],DDR_DQM[1:0], DDR_DQS0[_P and _N], DDR_DQS1[_P and _N]
DDR_A[13:0],DDR_BA[2:0], DDR_CASN, DDR_RASN, DDR_WEN
DDR_CKE, DDR_CSN, DDR_ODT, DDR_RESETN
DDR_CLK_N,DDR_CLK_P
For the different groups, it is possible with either software or hardware to shift the sampling point. Even
with this feature of DDR3 RAM, it is still needed to do a timing budget calculation. With this calculation, it
is possible to have an estimation of how the length matching needs to be. Length matching is needed due
to the fact that the typical propagation delay for the FR4 PCB is approximately 6.5 ps/mm and so a length
mismatch would lead to a delay of the signal compared to the other signal lines. As an example the net
class data has been matched as seen in Table 13.
Table 13. DDR3 Trace Length on PCB for Net Class Data
18
SIGNAL
TRACE LENGTH (mm)
SIGNAL
TRACE LENGTH (mm)
DDR_D0
27.4776
DDR_D8
25.3669
DDR_D1
27.6777
DDR_D9
25.2680
DDR_D2
27.4567
DDR_D10
25.4147
DDR_D3
27.2947
DDR_D11
25.6113
DDR_D4
27.4070
DDR_D12
25.6584
DDR_D5
27.5413
DDR_D13
25.3574
DDR_D6
27.4398
DDR_D14
25.5648
DDR_D7
27.3044
DDR_D15
25.4486
DDR_DQM0
27.3479
DDR_DQM1
25.4907
DDR_DQS0_N
27.4755
DDR_DQS1_N
25.4209
DDR_DQS0_P
27.4726
DDR_DQS1_P
25.4285
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
Termination was done with parallel termination of 47 Ω to improve performance. Arrays were chosen here
to minimize size.
Further general considerations are:
• All nets in the address and command fly-by groups shall have the same number of vias in each lengthmatched segment. Ground vias are placed to ensure a proper current return path. Minimize use of vias
on signal traces as they negatively impact signal integrity.
• The single-ended Address/Command net class and the control net class needs external termination to
VTT.
• For the data net class within a byte lane, the data bits can be swapped to simplify routing.
• Organize the power, ground, and signal planes to eliminate or significantly reduce the number of split
or cut planes present in the design (no splits are allowed under any DDR3 routes).
• Maintain an acceptable level of skew across the entire DDR3 interface (by net class).
• It is strongly recommended that all nets be simulated to assure proper design, performance, and signal
integrity.
• Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints. All long routes should be stripline to reduce EMI and timing skew, and
any microstrip routed for BGA breakouts should be as short as possible.
• Routes along the same path and routing segment must have the same number of vias. Vias can be
blind, buried, or HDI microvia for improved signal integrity, but are not required for standard data rates.
Similarly, back drilling vias is not required for standard data rates but can be used to eliminate via
stubs.
• For this design, the DDR3 layout was copied from the TI AM3359 Industrial Communications Engine
development platform with part number TMDSICE3359 to leverage a working and fully tested design
with the peripheral settings for the DDR3 interface.
4.2.6
AM3359 Clocking Options
For the clock, either a crystal or a digital clock source can be used. For both cases, the clock needs to be
19.2, 24, 25, or 26 MHz with a tolerance of ±50 ppm. For more details, see Section 6.2.2 of the AM3359
datasheet [5]. For this design, a 24-MHz crystal was chosen as used with the TMDSICE3359 AM3359
Industrial Communications Engine development platform.
4.2.7
Power Supply Pins
For the decoupling capacitors on the different power rails of the AM3359, see Section 5.9 of the AM3359
datasheet [5].
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
19
Circuit Design and Component Selection
4.2.8
www.ti.com
USB Virtual COM Port and JTAG Interface
An FTDI chip connects to a micro USB port. This FTDI chip can be used for both JTAG (XDS100) and
Virtual COM port functionality. A separate JTAG header is available too.
To use the FTDI chip, the onboard EEPROM, which is connected to the FTDI chip, needs to be
programmed as follows:
• To program the EEPROM connected to the FTDI chip, get the tool "Mprog". To find this tool, go to the
following webpage for the download link.
http://processors.wiki.ti.com/index.php/XDS100#How_to_make_an_XDS100
• The EEPROM needs to be programmed in a specific way. To find an example image also called a
*.ept file to write in the EEPROM, go to the following webpage:
http://processors.wiki.ti.com/index.php/XDS100
A .ept file for the Mprog tool is available for the specific XDS100 version needed. Download a .ept file,
which includes both JTAG and Virtual COM port functionality.
To verify the image is programmed correctly, power the board and connect the micro USB to the PC. Now
go into the start menu and open the menu Devices and Printers for Windows® 7. The following connection
should now be found (see Figure 12).
Figure 12. XDS100v2 Driver in Windows 7 Devices and Printers Menu
If Figure 12 does not appear, retry the previous steps.
When this is done properly, Code Composer Studio™ v6 can be used to connect to the AM3359 core
through JTAG using the XDS100v2 driver.
20
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
4.3
Power Supplies
The power supplies are realized in three stages. The first stage is a 24-V to 5-V DC/DC to provide an
intermediate 5-V rail to the other two stages. The second stage is a PMIC supplying the host processor,
and the last stage is supplying the two Gigabit PHYs.
24-V input
Stage 1
DC/DC
5 V: LM46002
5V
Stage 3
Stage 2
Enable
signal
Host processor
Vrtc: TPS71718
PMIC: TPS65910A3
Enable
signal
Gigabit PHY I/O rail
Gigabit PHY rails
2v5: LMZ10501
1v1: TPS72011
3v3: TPS73733
DDR3 termination
regulator
TPS51200
Figure 13. TIDA-00204 Power Supply Stages
4.3.1
24-V to 5-V DC/DC Buck Converter
For this stage, the LM46002 SIMPLE SWITCHER® regulator was chosen. It is an easy-to-use
synchronous step-down DC-DC converter capable of driving up to 2 A of load current from an input
voltage ranging from 3.5 to 60 V. The LM46002 provides exceptional efficiency, output accuracy, and
drop-out voltage in a very small solution size. The family requires few external components. Pin
arrangement allows for a simple, optimum PCB layout.
An extended family is available in various load current options with pin-to-pin compatible packages,
including LM46001.
The schematic of the LM46002 is shown in Figure 14.
L2
U1
13
14
R2
453k
12
8
C11
10µF
11
R4
100k
DNPC12
0.022µF
7
R5
80.6k
6
VIN
VIN
SW
SW
CBOOT
EN
BIAS
PGOOD
FB
SS/TRK
VCC
RT
AGND
PGND
PGND
PAD
SYNC
1
2
MSS1260-153MLB
C1
10µF
C4
3
5
C2
10µF
C3
10µF
C10
1µF
0.47µF
GND
9
GND
4
10
15
16
17
C13
4.7µF
R6
1.00M
C14
8.2pF
LM46002PWP
GND
GND
GND
GND
GND
GND
GND
0402 footprint
R7
249k
GND
Figure 14. Schematic of 24-V to 5-V DC/DC Buck Converter With LM46002
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
21
Circuit Design and Component Selection
4.3.1.1
www.ti.com
Passive Components Calculations
The first step is to decide and set the switching frequency of the regulator. In the TIDA-00204, the
switching frequency (FSW) is set to 500 kHz thanks to R5. Equation 1 indicates that R5 should be 79.8 kΩ.
80.6 kΩ is then used as value for R5.
40200
R5 =
- 0.6
F sw
(1)
with
• FSW in kHz and R5 in kΩ
The default frequency is also 500 kHz, due to the internal oscillator precision of 20% it was chosen to use
a resistor for the 500-kHz frequency. This gives a 10% precision. Secondly, during EMI test it can be
useful for fine tuning to move the frequency up or down to change the harmonic spectrum of the
converter.
Once the switching frequency is set, the size of inductance needed it chosen. For most buck converters,
this value is chosen to achieve the wanted peak-to-peak ripple current that flows in the inductor along with
the DC load current. A higher inductance gives lower ripple current, which then gives a lower output
voltage ripple with the same output capacitors. An inductance that gives a ripple current of 20% to 40% at
the maximum current is normally a good starting point. The minimum inductor value is calculated based
on input voltage range (17 to 60 V), output voltage (5 V), maximum output current (2 A) and the switching
frequency (500 kHz) as set in the previous step. The duty cycle (D) can be approximated as D = VOUT/VIN,
assuming no loss power conversion.
(V IN - V OUT ) ´ D
(V IN - V OUT ) ´ D
£ L min £
0.4 ´ F sw ´ I OUT
0.2 ´ F sw ´ I OUT
(2)
The calculation gives that the inductor needs to be between 9 and 23 μH; for this design, 15 μH was
chosen.
Besides the inductor size, the rated saturation current needs to be specified as per Equation 4.
I RIPPLE =
(VIN - V OUT )´ D
L 2 ´ F sw
I L -peak = I OUT +
(3)
I RIPPLE
2
(4)
The inductor peak current is 2.305 A according to Equation 3 and Equation 4. A good practice is to use an
inductor with the saturation current around 1.5 to 2 times higher than calculated.
The LM46002 has both valley current limit and peak current limit. During an instantaneous short, the peak
inductor current can be high due to a momentary increase in duty cycle. The inductor current rating should
be higher than the peak current limit. Select an inductor with a larger core saturation margin and
preferably a softer roll off of the inductance value over load current.
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But a
too low inductance can generate too large inductor current ripple such that over current protection at the
full load could be falsely triggered. It also generates more conduction loss because the RMS current is
slightly higher relative that with lower current ripple at the same DC current. Larger inductor current ripple
also implies larger output voltage ripple with the same output capacitors. With peak current mode control,
it is not recommended to have too small of an inductor current ripple. Enough of an inductor current ripple
improves the signal-to-noise ratio on the current comparator and makes the control loop more immune to
noise.
22
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
The maximum desired output voltage ripple and the transient response to load changes are the
parameters to take into account for selecting the value of the output capacitors.
C OUT >
F sw
ææ r
1
ö
´ çç
´ (1 + (1 - D ))÷ +
´ r ´ DV OUT / DI OUT
ø
è è 12
ö
((1 - D ) ´ (1 + r ))÷
ø
(5)
with
• ΔIOUT equal load current (2 A)
• ΔVOUT equal target output voltage undershoot (0.5 V)
• r the inductor ripple ratio (ΔIL/IOUT)
Equation 5 indicates that COUT should be higher than 10.0 μF. A general guideline would be to pick COUT
between the minimum required output capacitance, calculated in Equation 6, and multiply this minimum
required capacitance by 10. Two 10.0 μF in parallel were chosen to fit the COUT requirements.
The second requirement is the maximum ESR of the capacitor, which can be found using Equation 6.
(1 - D )
æ1
ö
ESR <
´ ç + 0.5 ÷
F sw ´ C OUT
r
è
ø
(6)
Equation 6 calculates the maximum ESR of the output capacitor to meet the maximum output ripple
required. The equivalent ESR of the output capacitors C3 and C4 should be lower than 0.288 Ω.
The LM46002 requires high quality ceramic (X5R or X7R) input decoupling capacitors. The recommended
value is between 4.7 to 10 μF. A good practice for ceramic capacitors is to choose a voltage rating of
twice the maximum input voltage. If the placement of the LM46002 additional bulk capacitance is needed,
this additional capacitor dampens voltage spikes caused by the lead inductance of the trace. The value is
not critical but it must be rated to fit the voltage requirements.
The output voltage is externally adjusted with a resistor divider network. The divider network is comprised
of top feedback resistor R6 and bottom feedback resistor R7. Equation 7 is used to determine the output
voltage of the converter.
V FB
R7 =
´ R6
V OUT - V FB
(7)
R6 is chosen to be 1 MΩ to minimize quiescent current, which improves light load efficiency in this
application. With the desired output voltage set to be 5 V and the VFB is equal to 1.01 V, the R7 value can
then be calculated using Equation 7. The equation gives the value 253.4 Ω. The chosen value for this
design is a 249-kΩ resistor. For more details on the adjustable output voltage, see the LM46002
datasheet [11].
The LM46002 is internally compensated and the internal R-C values are 400 kΩ and 50 pF, respectively.
Depending on the VOUT and the frequency FS, if the output capacitor COUT is dominated by low ESR
(ceramic types) capacitors, it could result in low-phase margin. To improve the phase boost, an external
feed forward capacitor C14 can be added in parallel with R6. C14 is chosen such that the phase margin is
boosted at the crossover frequency without C14. A simple estimation for the crossover frequency without
C14 (FX) is shown in Equation 8.
4.35
fX =
V OUT ´ C OUT
(8)
The following equation for C14 was tested:
1
1
C 14 =
´
2 ´ p ´ FX
R 6 ´ (R 6 || R 7 )
(9)
Equation 9 indicates that the crossover frequency is geometrically centered on the zero and pole
frequencies caused by the C14 capacitor.
For designs with higher ESR, C14 is not needed. When COUT has medium ESR, C14 calculated from
Equation 9 should be reduced. With Low ESR used the calculated value. Table 2 of the LM46002
datasheet can be used as a starting point. The calculated value is 8.2 pF, and an 8.2-pF COG capacitor
was selected for C14.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
23
Circuit Design and Component Selection
www.ti.com
The LM46002 needs a bootstrap capacitor C4. The recommended bootstrap capacitor is 0.47 μF and rated
at 6.3 V or higher. The bootstrap capacitor must be a high quality ceramic type with X7R or X5R grade
dielectric for temperature stability.
The VCC pin is the output of an internal LDO for the LM46002. The input for this LDO comes from either
VIN or bias. To ensure stability of the part, place a minimum of a 2.2-μF, 10-V capacitor from this pin to
ground.
For an output voltage of 3.3 V or higher, the BIAS pin can be connected to the output in order to increase
efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO will
be internally connected into VIN. Because this is an LDO, the voltage differences between the input and
output will affect the efficiency of the LDO. If necessary, a capacitor with the value of 1 μF can be added
close to the BIAS pin as an input capacitor for the LDO.
The soft start capacitor (C12) determines the minimum amount of time it will take the output voltage to
reach its programmed value during start up. This also allows limiting the inrush current in the LM46002
(current require to charge the output capacitors to the programmed value). If this pin is left unconnected,
the soft start time is 4.1 ms typically. Longer soft start times can be set by an external soft start capacitor
per Equation 10.
C 12 = I ssc ´ t ss
(10)
with
• C12 equal the soft start capacitor value (μF)
• ISSC the soft start charging current (μA)
• tSS equals the desired soft start times
The ISSC current is 2.2 μA, defining a soft start time of 10 ms would equal a soft start capacitor of 0.022 μF.
The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R2 and R4. R2 is
connected between the VIN pin and the EN pin of the device. R4 is connected between the EN pin and the
GND pin. The UVLO has two thresholds: one for power up when the input voltage is rising, and one for
power down or brown outs when the input voltage VIN is falling. Use Equation 11 to determine the
VUVLO-Falling level.
æ V UVLO -Falling
ö
- 1÷ ´ R 4
R2 = ç
ç
÷
V ENL
è
ø
(11)
The enable falling edge threshold (VENL) for the LM46002 is 1.8 V. R4 was chosen to 100 k to minimize
input current from the supply. If the desired VIN UVLO falling level is 10 V, the value of R2 can be
calculated using Equation 12. That is equal to 455.6 k. R2 was chosen to be 453 k.
V UVLO -Ri sin g = V ENH ´
(R 4 + R 2 )
R4
(12)
The enable rising edge threshold (VENH) for the LM46002 is 2.1 V. Equation 12 can be used to calculate
the required input voltage to meet the rising threshold to enable the converter. With the above chosen
resistors, the LM46002 will enable at 11.6 V.
24
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
4.3.2
Power Supply for Two Gigabit Ethernet PHYs
The PHY power supplies need to provide three power rails. The 3.3-V VDDIO power rail is sequenced from
the 3.3-V PMIC rail (see Section 4.3.2.1). When the VDDIO power rail is enabled, it will enable the
remaining two rails 2.5 V and 1.1 V as seen in Figure 15. The information on the power consumption of
the Gigabit Ethernet PHY can be seen in Section 6.5 of the DP83867IR datasheet [1].
5V
Enable
signal
Gigabit PHY I/O rail
Enable
signal
Gigabit PHY rails
2v5: LMZ10501
1v1: TPS72011
3v3: TPS73733
Figure 15. Power Stage for Two Gigabit Ethernet PHYs
4.3.2.1
DP83867IR Current Consumption
The DP83867IR has two power options. One option requires two rails for the core and one rail for the
VDDIO. In this setup, the PHY draws 565 mW. For the two-rail option, no sequencing is required. If power
dissipation on the DP83867IR is critical, the second option uses three rails for core and one rail for VDDIO.
In this setup, the PHY draws 545 mW. VDDIO can be 3.3, 2.5, or 1.8 V. See its datasheet for more details
on the current consumption per rail and if a voltage other than 3.3 V is used in the VDDIO rail [1].
Table 14. Power Consumption per Voltage Rail
RAIL
STANDARD POWER MODE (565 mW)
LOW POWER MODE (545 mW)
1.1 V
106 mA
106 mA
1.8 V
N/A
64 mA
2.5 V
157 mA
103 mA
VDDIO (3.3, 2.5, or 1.8 V)
31 mA (1.8 V)
31 mA (1.8 V)
For this design, the power supply was designed for the two-rail standard power mode option to fit two
DP83867IR PHYs.
The TPS72011 and LMZ105001 were chosen for the 1.1-V rail and the 2.5-V rail, respectively.
For the VDDIO 3.3 V, the TPS73733 was chosen. This rail is also used as supply rail for other interfaces on
board (for example, for the Gigabit Ethernet PHY LEDs and VDDIO voltage rail, the EEPROM, the debug or
JTAG circuitry, reset circuitry, and additional pull up resistors for data communication lines).
These parts were chosen because of their feature of industrial temperature range –40°C to 85°C and that
they could dissipate the needed power at 85°C. Here it is important to choose the correct package of the
device; several other part numbers could fit the electrical specification. However, their package would not
be able to dissipate the needed power at the full current and temperature range. Knowing the voltage drop
across the LDO and the power dissipation at 85°C, the maximum current that can be dissipated for the
decided voltage rail can be calculated.
Table 15. 3.3-V and 1.1-V LDO Power Dissipation per Package
MAX POWER
DISSIPATION
AT 85°C
AMBIENT
TEMPERATURE
DEVICE
INPUT
VOLTAGE
OUTPUT
VOLTAGE
VOLTAGE
DROP
TPS72011DRV
2.5 V
1.1 V
1.4 V
615 mW
65 K/W
439.29 mA
TPS73733DCQ
5V
3.3 V
1.7 V
790 mW (1)
53.1 K/W
464.71 mA (1)
(1)
RɵJA
MAX CURRENT
AT 85°C
Estimated power dissipation and max current at 85°C using junction-to-ambient thermal resistance.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
25
Circuit Design and Component Selection
www.ti.com
The 2.5-V rail at LMZ10501 was chosen due to the fact that an LDO with the current needed would be a
very expensive device and would dissipate a significant amount of power. When two PHYs are powered
approximately 526 mA is required, with margin the 1-A LMZ10501 was chosen.
Vddio
U2
1
Vaux2
C15
0.1µF
5
IN
2
OUT
EN
C16
1µF
4
NR
6
3
GND
TPS73733DCQ
V5_dc
R8
0
GND
R9
V25phy
0
R8
0
U3
7
C17
10µF
Vddio
R12
0
1
8
VIN
VOUT
EN
FB
VREF
R14
150k
GND
SGND
2
R16
110k
PGND
VCON
PAD
5
GND
C18
10µF
3
U5
6
4
GND
C22
0.1µF 4
V5_dc
V11phy
BIAS
OUT
1
R15
0
C23
2.2µF
9
6
LMZ10501SIL
C24
0.1µF
C21
470pF
GND
GND
3
IN
EN
NC
GND
PAD
2
5
7
TPS72011DRV
GND
Figure 16. Schematic of Power Supply for Two DP83867IR Gigabit Ethernet PHYs
Use Equation 13 to calculate the output voltage for the LMZ10501.
æ
V OUT
R 16 = ç
ç 5.875 V - V OUT
è
ö
÷ ´ R 14
÷
ø
(13)
R14 needs to between 80 and 300 kΩ and R16 can be calculated. R14 has to be minimum 80 kΩ to ensure
that the VREF output current loading is not greater than 30 μA and the reference voltage is maintained. This
design needed a 2.5-V output voltage and the R14 was decided to be 150 kΩ and the R16 is now calculated
to 111.1 kΩ. A 110-kΩ resistor was chosen. A small filter capacitor of 470 pF with a voltage rating of 6.3 V
or 10 V is connected in parallel to R16. The input and output capacitors are recommended to be X5R or
X7R.
26
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
4.3.3
Power Stage for AM3359 Host Processor
The power stage for the AM3359 Sitara is realized using the PMIC TPS65910A3 and a DDR3 terminator
regulator TPS51200. An additional TPS71718 LDO is used for the RTC circuit of the Sitara, as the
TPS65910A3 RTC circuit has been turned off.
The TPS65910A3 can be configured through I2C, this interface can be used to set internal registers of the
PMIC. For more details on these registers, see the TPS65910A3 user's guide. The TPS65910A3 have the
following power sources that can be used, each of the power supplies can be programmed to work at
several voltages. For the TPS65910A3, there are several boot modes depending on the device that needs
to be powered. Because the AM3359 is used, the EEPROM sequence has been chosen boot[1:0] = "10".
For more information on this topic, see Section 10.
Table 16. TPS65910A3 Default Voltage Rails per "10" EEPROM Sequence
RAIL NAME
TYPE
VIO
SMPS
VDD1
VOLTAGE OPTIONS
DEFAULT VOLTAGE
POWER
1.5, 1.8, 2.5, or 3.3 V
1.5 V
1000 mA
SMPS
0.6 to 1.5 V in 12.5-mV steps
Programmable multiplication factor: ×2, ×3
1.1 V
1.1 V
1500 mA
VDD2
SMPS
0.6 to 1.5 V in 12.5-mV steps
Programmable multiplication factor: ×2, ×3
1.1 V
1.1 V
1500 mA
VDD3
LDO
5 V or OFF
N/A
100 mA
VDIG1
LDO
1.2, 1.5, 1.8, or 2.7 V
1.8 V
300 mA
VDIG2
LDO
1, 1.1, 1.2, or 1.8 V
1.8 V
300 mA
VPLL
LDO
1.0, 1.1, 1.8, or 2.5 V
1.8 V
50 mA
VDAC
LDO
1.8, 2.6, 2.8, or 2.85 V
1.8 V
150 mA
VAUX1
LDO
1.8, 2.5, 2.8, or 2.85 V
1.8 V
300 mA
VAUX2
LDO
1.8, 2.8, 2.9, or 3.3 V
3.3 V
150 mA
VAUX33
LDO
1.8, 2.0, 2.8, or 3.3 V
3.3 V
150 mA
VMMC
LDO
1.8, 2.8, 3.0, or 3.3 V
3.3 V
300 mA
VRTC
LDO
1.8 V or OFF
OFF
OFF
The TPS51200 is used for the DDR3 ram as the sink/source termination regulator. The DDR memory
termination structure determines the main characteristics of the VTT rail, which is to be able to sink and
source current while maintaining acceptable VTT tolerances. The VTT accuracy has a direct impact on the
memory signal integrity, it is imperative to understand the tolerance requirements on VTT. The termination
current demand of the DDR3 is less than 1 A of burst current. The TPS51200 ensures the regulator output
voltage to be between VTTREF – 25 mV < VTT < VTTREF + 25 mV.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
27
Circuit Design and Component Selection
4.4
www.ti.com
System Clocks
There are several options to apply the clocks. For systems with distributed clocks, a clock distribution
circuit can be used too. The initial design leverages a crystal on each DP83867IR as well as on AM3359
Sitara. This was due to initial test and debug to allow individual component testing.
4.4.1
Individual Crystals
The crystal manufacturers define the load capacitance of their crystal in their datasheet. This load
capacitance CL is the sum of the PCB parasitic stray capacitance CS and the external load capacitors CX
and CY, respectively, as per Equation 14. Assuming that the external load capacitors are the same value,
they can be calculated with Equation 14.
C X = C Y = 2 ´ (C L - C S )
(14)
CS is the stray capacitance (device and PCB) this value can be assumed to a few pF as a rule of thumb.
The load capacitors need to be NPO/COG type. Table 17 shows the selected load capacitors per crystal
and per device on the TIDA-00204.
Table 17. Parallel Capacitors Needed for Oscillation Circuit
DEVICE
CL
CS
CX = CY
ABM3-25.000MHZ-D2W-T
CRYSTAL
DP83867IR
18 pF
4 pF
27 pF
ABM3-24.000MHZ-D2W-T
AM3359
18 pF
4 pF
27 pF
ABM3-12.000MHZ-D2Y-T
FT2232HL
18 pF
4 pF
27 pF
AM3359 (RTC)
12.5 pF
3 pF
19 pF
MC-306 32.7680K-A0:ROHS
In this design, the default configuration is one crystal at each DP83867IR PHY. However, the hardware is
prepared thanks to 0-Ω resistors to clock the second DP83867IR PHY from the PHY 1, as shown in
Figure 17. If desired, this configuration can be tested.
25 MHz
25 MHz
CY
XI
CLK_OUT
XO
XI
XO
CLK_OUT
CX
DP83867IR (PHY 1)
DP83867IR (PHY 2)
Figure 17. Crystal Configuration for DP83876IR and Option to Clock the Second DP83867IR PHY From the
First DP83867IR
28
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Circuit Design and Component Selection
www.ti.com
4.4.2
Clock Distribution Circuits
Alternatively to the XTAL clocking as implemented on the TIDA-00204 reference design, a more advanced
clocking solution is possible. The following section describes how this could be implemented.
Replace XTALs of the PHY and Sitara chips with a CDCE913 clock generator. If the layout allows, also
additional clocks on the board could be derived from the clock generator. The CDCE9xx device family is
available with various output and PLL counts.
The yields several advantages in general:
• Smaller component area used for clocking
• Possibility to enable spread spectrum (SSC)
• Potentially lower cost
• Possibility to extend easily
Figure 18 shows how a CDCE913 could be connected and used to provide three reference LVCMOS
clocks.
CDCE913
25 MHz
LVCMOS
to DP83867IR PHY 1
25 MHz
LVCMOS
to DP83867IR PHY 2
24 MHz
LVCMOS
to AM3359 Sitara
Figure 18. CDCE913 Clock Distribution Circuit Example
This new clocking source could be used to change the component floor plan as shown in Figure 19 with
an Altium 3-D PCB simulation.
Step 1: Remove the oscillator circuitry used for the two
DP83867 PHYs and the AM3359 Sitara as shown in the
picture.
Step 2: Place CDCE913 and its supporting
components on bottom side, between the
PHYs and close to AM3359. This allows
short routing distances.
X
X
X
PCB top view
PCB bottom view (flipped)
Figure 19. PCB Component Area Saving With a CDCE913 Clock Generator
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
29
Software Design
www.ti.com
5
Software Design
5.1
Sitara AM3359 Firmware
The goal of the software design was to provide an example application firmware for evaluating Gigabit
Ethernet, which boots from micro SD-Card automatically after the TIDA-00204 is powered. The application
firmware implements a driver for the DP83867IR, UDP and TCP/IP stack, and HTTP web server
examples. A USB virtual COM port offers optional user access to read or write to DP83867IR registers for
custom configurations like RGMII Delay Mode, if required.
5.1.1
Functional Overview
The host processor Sitara AM3359 is configured to boot from MMC1/SD-Card. The AM3359 copies the
TIDA-00204 example application binary file app from the SD-Card to DDR3 RAM and launches the
example application. The flowchart of the SD-Card boot load process is shown in Figure 20.
Start
ROM boot from
MMC1
micro SD card
Load app file from
micro SD card
Launch application
³DSS´
Figure 20. AM3359 Boot Load Process From MMC1 Micro SD-Card
30
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Software Design
www.ti.com
The TIDA-00204 example application app consists of three major functional blocks.
The first part initializes the AM3359 peripherals like the Ethernet MAC, Ethernet Switch (CPWS), and
UART. Then, the app initializes SYS/BIOS and sets up a UART task thread as well as an Ethernet task
thread. After that, the app starts SYS/BIOS. Then, both the UART thread and the Ethernet thread are
scheduled and run accordingly.
Start
Init EMAC,
Ethernet Switch,
and UART
Init SYS/BIOS and
setup UART and
Ethernet threads
Start SYS/BIOS
Ethernet
thread
UART
thread
Figure 21. AM3359 Initialization
The Ethernet thread initializes the configuration registers of both DP83867IR Gigabit PHYs through SMI.
For example, set RGMII mode, autonegotiation, indicator LEDs, and more. Then the thread enables the
network layer with fixed IPv4 address 192.168.1.10 and TCP and UDP transport layer. Additionally, a
HTTP web server example application is included.
The UART thread enables communication through virtual COM port and offers and additional option to
read and write to the individual registers of the DP83867 Gigabit PHYs through SMI. For example, the
user can adjust the RGMII Delay Mode according to the specific hardware, if desired.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
31
Software Design
www.ti.com
The flowcharts of both threads are shown in Figure 22 and Figure 23.
Gigabit
Ethernet
thread
UART
thread
Init PHY1 and PHY2
with MDIO interface
Init IPv4 with static IP
192.168.1.10
Init TCP and UDP
Enable UART
access to both
DP83867 devices
Init HTTP
Autonegotiate
Ethernet
Ethernet link
Yes
Port 1 cable
Disconnected
Port 2 cable
Disconnected
Port 1 cable
connected?
Cable
connected
No
No
Autonegotiate
Ethernet
Yes
Write data to
DP83867 PHY
register address
No
Thread
Ethernet link
Yes
Yes
Select DP83867
PHY MDIO
address
Yes
Print selected
register addresses
with data
Read register of
selected PHY
Port 2 cable
connected?
No
Enter DP83867
PHY Register
address and data
Yes
No
No
Yes
Thread
Select
all addresses
0x00 to 0x1F
No
Enter specific
register address
Figure 22. AM3359 Gigabit Ethernet Thread Flowchart
32
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
Figure 23. AM3359 UART Thread Flowchart
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Software Design
www.ti.com
5.1.2
Software Components
The "TIDA-00204 SD-Card Image" consists of two binary files. The AM3359 boot loader binary file called
"MLO" and the example application binary file called "app", as described in Section 5.1.1. Both binaries
were compiled in separate CCS 6 projects.
5.1.2.1
"MLO" Binary File
The TIDA-00204 boot loader binary file "MLO" was developed with the Texas Instruments
AM335x_SYSBIOS_Industrial_SDK_01_01_00_06 software package. This example project was modified
to the TIDA-00204 hardware with boot from MMC1/SD-Card. The binary file was renamed after
compilation to MLO to fit the AM3359 ROM boot loader and is part of the
TIDA-00204_Firmware_AM3359_SD-Card_Image.
5.1.2.2
"app" Binary File
The TIDA-00204 example application binary file app was developed with the following Texas Instruments
software packages:
• AM335x_SYSBIOS_Industrial_SDK 01_01_00_06:
http://downloads.ti.com/sitara_indus/esd/AM335x_SYSBIOS_Industrial_SDK/latest/index_FDS.html
• SYS/BIOS 6_40_03_39: http://softwaredl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_40_03_39/exports/bios_setupwin3
2_6_40_03_39.exe
• XDCtools 3_30_05_60: http://softwaredl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/rtsc/3_30_05_60/index_FDS.html
• NDK 2_24_00_11: http://softwaredl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ndk/2_24_00_11/index_FDS.html
• NSP 1_10_02_09 Product Download Page: http://softwaredl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ndk/nsp_1_10_02_09/index_FDS.html
The example application uses only a few example projects including the source and header files.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
33
Software Design
5.1.3
www.ti.com
Creating the Micro SD-Card Image
To create the TIDA-00204_Firmware_AM3359_SD-Card_Image to boot the demo application firmware
from the micro SD-Card, the following equipment is required:
• A pre-formatted micro SD-Card with FAT file system
• A PC with a micro SD-Card reader
• Win32 Disk Imager installed on PC
Copy the MLO and app binary file to the micro SD-Card. After that, invoke the Win32 Disk Imager. See an
example of the program shown in Figure 24.
Figure 24. Procedure to Create SD-Card Image With Win32 Disk Imager
Select Read to write the current inserted micro SD-Card into the name image in this example called
"test.img". This image was renamed to TIDA-00204_SD-Card_Image_rev1_0 and then included into the
TIDA-00204 software package.
5.2
PC Test Software for UDP Packet Transfer Based on TI’s NDK
The tests for the Gigabit Ethernet communication path developed with the Texas Instruments NDK
2_24_00_11 software package. From this software package, the following source file was used:
• c:\ti\ndk_2_24_00_11\packages\ti\ndk\winapps\testudp.c
For more information on the testudp files, see Section 2.2.3.3 of the NDK document [8].
With original executable testudp.exe, the utilization was around 1%, which was below the needs for this
design; therefore, modification was done. The original source was modified adding hyper threading to
enable higher utilization. To compile the source file, MinGW was used.
NOTE: To use the hyper threading on a Windows PC, add libwinpthread-1.dll in the same directory
as the executable. The library file libwinpthread-1.dll can be downloaded from the internet.
With hyper threading, 25% utilization was achieved on a single Gigabit Ethernet port and 20% each in
case of on dual Gigabit Ethernet port 1 and port 2.
Two variants were generated as explained in the following two sections.
34
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Software Design
www.ti.com
5.2.1
UDP Throughput Test
The example UDP test file is called "TIDA-00204_UDP_throughput_test.exe". The software flow of the
throughput example code can be seen in Figure 25.
Start
Enable Ethernet
socket for UDP
Open
thread
Initialize payload with
size of 1472 bytes
Receive UDP packet
Close thread
No
Send UDP packet to
socket
Increase packet
counter by 1
Packet
counter and
0xFFFF
= 0?
Stop
UDP packet
transfer
Yes
Print to console
packet counter
Yes
Print to console
number of packets sent,
time elapsed
Stop
Figure 25. Flowchart of UDP Throughput Test Software
Figure 26 is an example console output can be seen of the example UDP throughput test software.
Figure 26. Command Prompt UDP Throughput Print
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
35
Software Design
5.2.2
www.ti.com
UDP Packet Error Test
The example UDP test file is called "TIDA-00204_UDP_throughput_test.exe". Figure 27 shows the
software flow of the throughput example code can be seen.
Start software
Enable Ethernet
socket for UDP
Setup predefined
packet and size of
packet to send
Send UDP packet to
socket;
Increase packet
counter by 1
Stop
UDP packet
transfer
No
Packet
counter and
0x3FFF
= 0?
Print to console
packet counter
Receive UDP
from
TIDA-00204
Compare send and
received packet and
count errors
Print to console
error counter
Print to console
number of packets sent,
time elapsed, total errors
Stop
Figure 27. Flowchart of UDP Packet Error Test Software
The above example verifies, if the echoed back packets were corrupted. This functionality is needed
check the signal integrity of the connection. Note that with this functionality enabled on the PC, the
utilization of the Gigabit Ethernet connection was 5%.
An example console output of the example UDP packet error test can be seen in Figure 28.
Figure 28. Command Prompt UDP Packet Error Test Print
36
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Getting Started
www.ti.com
6
Getting Started
6.1
PCB Overview
A picture of the PCB with key functional blocks is shown in Figure 29.
Jumpers:
J1: 5 V enable
J3: PHY P/S enable
24-V to 5-V DC/DC
LM46002
Micro USB virtual COM port
24-V input
PHY P/S
2v5
1v1
LEDs (supply rails)
D2 (5 V)
D3 (2.5 V)
D14 (3.3 V)
Gigabit Ethernet PHY
DP83867IR
Reset button
Port 1
Ethernet status LEDs
Host processor
AM3359
Gigabit Ethernet PHY
DP83867IR
Port 2
Micro
SD-card
Ethernet status LEDs
Figure 29. TIDA-00204 PCB Picture With Key Functional Blocks
6.2
How to Run the Board
The next sections show the prerequisites and the steps to quickly start using the board.
6.2.1
Prerequisites
The following hardware equipment and software is required.
Table 18. Prerequisites
HARDWARE EQUIPMENT OR SOFTWARE
REQUIREMENTS
24-V power supply
24-V output power brick with at least a 250-mA output current
Output connector 2.1-mm I.D. × 5.5-mm O.D. × 9.5-mm Female
PC
PC or Laptop with USB port and Gigabit Ethernet port
Ethernet cable
Recommended CAT7 twisted pair cable
Micro USB cable
N/A
Micro SD-card
Big enough to fit the micro SD-card TIDA-00204 image
TeraTerm v4.76 or newer
Download from web, or use any other terminal program of your
choice
Win32 Disk Imager v0.9.5 or newer
Download from web
XDS100 v2 PC USB driver
To get this driver, install CCS 6.x
TIDA-00204 software package
Download from the TIDA-00204 web page
libwinpthread-1.dll
Download from web
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
37
Getting Started
6.2.2
www.ti.com
Jumper Settings
CAUTION
The following two jumpers need to be set: J1 and J3.
The J1 jumper powers the host processor power stage and the J3 jumper enables the Gigabit Ethernet
PHY power supply.
6.2.3
Prepare the Micro SD-Card
For easy standalone board operation, a micro SD-Card image is provided. The example image on the SDCard is configured so the AM3359 reads the boot loader MLO from the micro SD-Card and enables the
Sitara AM3359 in a mode. The Sitara AM3359 enables the needed peripherals to communicate with the
two PHYs over the MDI and sets those PHYs in autonegotiate 10/100/1000 mode. It also enables a UART
functionality where one can read out the PHY registers from the two DP83867 devices over virtual COM
port.
Write the image "TIDA-00204_SD-Card_Image_rev1_0.img" to a micro SD-Card. Use Win32 Disk Imager
to write the image to the SD-Card (see Figure 30).
Figure 30. Win32 Disk Imager Image Showing the Write Function
Select the provided TIDA-00204 firmware image and click Write to flash the image to the micro SD-Card.
CAUTION
Ensure that the micro SD-Card is selected at the Device tab.
If the image is not being written with the onboard PC SD-Card slot, try using an external SD-Card reader.
CAUTION
If the micro SD-Card is not prepared like above, but the individual binary files
MLO and app are copied to a preformatted micro SD-Card it might be that the
AM3359 does not boot properly. For further details on this topic, see the
Section 26.1.7.5.2 of the AM335x technical reference manual [6].
38
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Getting Started
www.ti.com
6.2.4
Powering the TIDA-00204 Reference Design
Insert the micro SD-Card with TIDA-00204 firmware image into the TIDA-00204 micro SD-Card cage.
Connect a 24-V power supply with at least a 250-mA output current. After that, the three green LEDs (D2,
D3, and D14) will turn on. If the LEDs does not turn on, one of the jumpers J1 and J3 are not connected.
Connect the micro USB cable from the TIDA-00204 reference design to the PC. Now the XDS100 v2 PC
USB driver is installed on the PC. If PC does not find this driver, install CCS 6 to get the driver.
Invoke a terminal program, like TeraTerm that can connect to the virtual COM port. Setup the terminal
program in Serial Console Mode and set the parameters as seen in Table 19.
Table 19. Terminal Program Serial Console Configuration
BAUD RATE
DATA
PARITY
STOP
FLOW CONTROL
115200
8-bit
None
1-bit
None
Afterwards, press the reset button on the board. For the location of the reset button, see Figure 29.
Now on the terminal program, the boot sequence of the TIDA-00204 reference design is printed. See
Figure 31 for terminal program printout.
Figure 31. Virtual COM Port Connection During Boot
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
39
Getting Started
6.3
www.ti.com
Evaluating the TIDA-00204 Dual-Port Gigabit Ethernet Reference Design
With the board powered up, the next step is to connect the Ethernet link partner.
Connect a link partner to either port 1 or port 2, depending on the link partner autonegotiate will setup
10/100/1000 network capability. Now the Ethernet LEDs will light up showing link status and Ethernet
speed.
The status LEDs have the following functionality see Table 20.
Table 20. DP83867 Gigabit PHY Port 1 and Port 2 Status LED Configuration
LED #
Function
D7 / D12
Not assigned to a
specific function on
TIDA-00204
D4 / D9
Receive or transmit
activity
D5 / D10
1000-Mb link
established
D6 / D11
Link established
The status LEDs are explained from left to right when looking at the board picture.
The reference design is setup to use the IP address 192.168.1.10, that is a static IP. It does not have
DHCP function enabled.
Setup the PC Network connection for static IP in the same address range as the TIDA-00204 reference
design with subnet mask 255.255.255.0. For example: 192.168.1.30.
To test the Ethernet connection there are several options: ping, provided UDP test software and a HTTP
web server. See examples below.
All Gigabit Ethernet examples demonstrated on both port 1 and port 2.
6.3.1
Ping
With the command prompt, the windows ping function can be used for initial connection test, see
Figure 32.
Figure 32. Command Prompt Ping Print
40
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Getting Started
www.ti.com
6.3.2
UDP Test Software
The two PC test programs as part of the TIDA-00204 software package can be used.
Insure that the libwinpthread-1.dll is located in the same folder as the TIDA-00204_throughput_test.exe
and TIDA-00204_packet_test.exe. This library can be downloaded from the internet.
To invoke these programs, use a Windows PC with the command prompt, see Figure 33 and Figure 34 for
example print outs.
Figure 33. Command Prompt UDP Throughput Print
Figure 34. Command Prompt UDP Packet Error Test Print
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
41
Getting Started
6.3.3
www.ti.com
HTTP Web Server Example
Open a browser and enter this address: http://192.168.1.10. See Figure 35 for a screenshot of the
TIDA-00204 webpage.
Figure 35. TIDA-00204 HTTP Web Server Example
42
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Getting Started
www.ti.com
6.3.4
Access to DP83867IR Registers Through USB Virtual COM Port
The virtual COM port connection can be used to read and write to both DP83867IR registers through SMI.
With this, it is possible to configure the DP83867IR registers in a different configuration than default for
additional test options.
CAUTION
All inputs are in decimal and all outputs are in hexadecimal.
Figure 36 shows an example screenshot for a register read from DP83867IR on Ethernet port 2.
Figure 36. Virtual COM Port Connection for DP83867IR (ETH1) Register Read
To find the Gigabit Ethernet PHY DP83867IR register addresses, see the DP83867IR datasheet [1].
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
43
Test Results
7
www.ti.com
Test Results
For the TIDA-00204 tests, the following test equipment was used:
Table 21. Test Equipment for the TIDA-00204 Gigabit Ethernet Signal Integrity Tests
TEST EQUIPMENT
24-V power brick
Power supply
Knürr-Heinzinger Polaris 125-5
Gigabit Ethernet adapter for PC
PC
DRAKA UC900 super screen 27 CAT7 with a CAT6A connector
Tektronix TDS794D, P6339A probes
Tektronix TDS2024B, P2220 probes
Oscilloscope
Electronic load
Multimeter
7.1.1
Digitus – USB 3.0 Ethernet adapter
Latitude E6540 with Windows 7 64-bit
Ethernet cable
7.1
PART #
V-Infinity 3A-621DN24
Chroma 63103 with Chroma 6314
FLUKE 179
Gigabit Ethernet Signal Integrity Tests
RGMII Signals
The RGMII signals between the MAC and the PHY are tested with a 1000-Mb connection on both PHY1
and PHY 2 RX and TX. Figure 37 through Figure 40 show the clock signal and corresponding RX_D1 and
TX_D1 data signal. The other data signals D0, D2, and D3 were measured too and exhibited the same
waveforms. This was expected because the design was optimized for impedance and matched length of
the clock and data lines.
Figure 37. ETH1 RGMII RX Clock and Data Signal During
Gigabit Ethernet Connection
44
Figure 38. ETH1 RGMII TX Clock and Data During
Gigabit Ethernet Connection
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
Figure 39. ETH2 RGMII RX Clock and Data Signal During
Gigabit Ethernet Connection
7.1.2
Figure 40. ETH2 RGMII TX Clock and Data Signal During
Gigabit Ethernet Connection
Serial Management Interface (SMI)
The maximum clock frequency of the SMI of the Sitara AM3359 is 2.5 MHz. This test does not need to
have an Ethernet connection running. Figure 41 and Figure 42 show the two signals MDC (Clock) and
MDIO (I/O) between the Sitara AM3359 and the two DP83867IR for Gigabit Ethernet ETH1 and ETH2.
Figure 41. SMI Clock and Data Signal at 2.5 MHz at
DP83867IR ETH1
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Figure 42. SMI Clock and Data Signal at 2.5 MHz at
DP83867IR ETH2
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
45
Test Results
7.2
www.ti.com
Power Supply Tests
7.2.1
24-V to 5-V DC/DC Power Supply
The LM46002 was configured in this design to work with an input voltage range between 17 and 60 V.
The nominal load current was defined for the following configuration. The Sitara AM3359 running at
600 MHz executing the application code from DDR3, with both DP83867IR connected in Gigabit Ethernet
mode with continuous UDP packet transfer at 20% network utilization on both ports. The minimum load
current is set to 500 mA, the nominal load to 850 mA, and the maximum load to 1.2 A.
5.5
5.5
5.4
5.4
5.3
5.3
5.2
5.2
Output Voltage (V)
Output Voltage (V)
Three tests where done: Output voltage versus input voltage (Figure 43), output voltage versus load
current (Figure 44), and the output voltage ripple (Figure 45).
5.1
5
4.9
4.8
5.1
5
4.9
4.8
4.7
4.7
4.6
4.6
4.5
10
20
30
40
Input Voltage (V)
50
60
4.5
500
600
D001
Figure 43. Output Voltage (VOUT) at 850 mA Nominal Load
Current With Varying Input Voltage (VIN)
700
800
900
1000
Load Current (mA)
1100
1200
D002
Figure 44. Load Regulation: VOUT at 24-V Input Voltage at
Varying Loads
Figure 45. VOUT Output Voltage Ripple at 850 mA Load Current and 24-V VIN Input Voltage
46
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
7.2.2
Power Supply for the DP83867IR Gigabit Ethernet PHYs Tests
The voltages have been verified as shown in Table 22. The startup of the 3v3, 2v5, and 1v1 rails are
shown in Figure 46.
Table 22. Measured Voltage Rails of the Gigabit Ethernet PHY
SUPPLY NAME PER SCHEMATICS
SPECIFIED VOLTAGE
MEASURED
3v3
3.3 V
3.31 V
2v5
2.5 V
2.47 V
1v1
1.1 V
1.10 V
Figure 46. PHY Power Supply Voltage Rails During Startup
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
47
Test Results
7.2.3
www.ti.com
PMIC for Sitara AM3359 Host Processor
The TPS65910A3 output voltages were verified and compared against the expected voltages based on
the TPS65910A3 EEPROM pin configuration.
Table 23. Measured Voltages on the PMIC TPS65910A3
SIGNAL
EXPECTED VOLTAGE
MEASURED VOLTAGE
VIO
1.5 V
1.52 V
VDD1
1.1 V
1.11 V
VDD2
1.1 V
1.11 V
VDD3
OFF
N/A
VDIG1
1.8 V
NC. VDIG1 pin was not connected in this design.
VDIG2
1.8 V
1.81 V
VPLL
1.8 V
1.82 V
VDAC
1.8 V
1.80 V
VAUX1
1.8 V
1.82 V
VAUX2
3.3 V
3.31 V
VAUX33
3.3 V
3.33 V
VMMC
3.3 V
3.32 V
VRTC
OFF
N/A
The sequencing has not been tested. Please see TPS65910Ax User's Guide For AM335x Processors for
further details [7].
48
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
7.3
Gigabit Ethernet Functional Tests
The following functions have been tested: autonegotiate, ping, UDP transfer, and web server.
Table 24. Functional Tests of TIDA-00204 Reference Design
7.3.1
FUNCTION
TEST RESULT
Autonegotiate
PASS
Ping
PASS
UDP
PASS
Web server
PASS
Autonegotiate
Testing the autonegotiate is done using a network connection which can be programmed into a specific
autonegotiate condition. Doing this ensures that the link negotiated is not going into a default setting
defined in the IEEE 802.3ab standard. This can happen if one partner of the link is forced and the other is
set to autonegotiate.
The default autonegotiate setting of the DP83867IR is set 10/100/1000-Mb half- or full-duplex mode. The
DP83867IR recognizes the data rate supported by partner and sets the highest data rate supported by
both.
Table 25 shows the different autonegotiate mode results.
Table 25. DP83867IR Autonegotiate Mode Test Results
DP83867IR SETTING
Autonegotiate: 10/100/1000 full
duplex or half duplex
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
LINK PARTNER SPEED
MODE SETTING
LINK PARTNER DUPLEX
MODE SETTING
LINK CONNECTION
ESTABLISHED
10/100/1000
Full duplex
1000 full duplex
10/100/1000
Half duplex
1000 half duplex
10/100
Full duplex
100 full duplex
10/100
Half duplex
100 half duplex
10
Full duplex
10 full duplex
10
Half duplex
10 half duplex
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
49
Test Results
7.3.2
www.ti.com
Ping
Ping is invoked from the command prompt using the TIDA-00204 static IP address 192.168.1.10.
Figure 47 presents a command prompt printout that shows the ping test.
Figure 47. Command Prompt Ping Print
Wireshark was used to log the packet transfer during the ping test. In Figure 48, the Wireshark printout
result can be seen.
Figure 48. Wireshark Log of TIDA-00204 Ping Test
50
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
7.3.3
UDP
The UDP throughput test is invoked from the command prompt using the TIDA-00204 static IP address
192.168.1.10. Figure 49 presents a command prompt printout that shows the UDP throughput test.
Figure 49. Command Prompt UDP Throughput Print
Windows Task Manager networking was used to log the packet transfer utilization during the UDP
throughput test. Figure 50 shows the Windows Task Manager printout.
Figure 50. Utilization of One Port Connection With UDP Throughput Test Running
With the throughput test file, it is possible to achieve around 25% utilization of the Gigabit bandwidth. The
slight change in the utilization on the curve is due to other network or CPU tasks.
When running this test on both ports simultaneously, the utilization will be 20% on each port.
For the UDP packet error test, the utilization is 5% independent of how many ports are connected, which
is a limitation of the UDP packet error test software running on the PC.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
51
Test Results
7.3.4
www.ti.com
HTTP Web Server
To test the HTTP web page example, the TIDA-00204’s static IP address http://192.168.1.10 is entered
into a browser (see Figure 51).
Figure 51. HTTP Web Server Example
For this test, Wireshark was used to log the traffic generated by initializing the web server and the loading
of the page.
Figure 52 shows the traffic log from Wireshark.
Figure 52. Wireshark Log of TIDA-00204 HTTP Web Server Example
52
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
7.4
EMC/EMI Test Results
The TIDA-00204 TI design has been tested for EMI according to CISPR 11 / EN55011 Class A radiated
emissions. For EMC immunity, the design has been tested according to IEC61800-3 and IEC61000-6-2 for
ESD, EFT, and Surge with reference to standards IEC61000-4-2, IEC61000-4-4, and IEC61000-4-5,
respectively.
The design is compliant to these standards and exceeds the voltage requirements according to
IEC61800-3 EMC immunity requirements. A summary is shown in the following tables and more details in
the following sections.
Table 26. CISPR 11 / EN55011 Class A Radiated Emission Requirements for Category 2 and
Measured Level
REQUIREMENTS
TIDA-00204 MEASUREMENTS
Phenomenon
Basic standard
Category 2 electric field
strength component quasipeak dB (µV/m)
Measured minimum margin to limit
Test
EMI
CISPR 11 / EN55011 Class
A
40 (30 to 230 MHz)
47 (230 to 1000 MHz)
Horizontal: 10.6 dB (125 MHz)
Vertical: 4.3 dB (125 Mhz)
PASS
Table 27. IEC61800-3 and IEC61000-6-2 EMC Immunity Requirements for Second Environment and
Measured Voltage Levels and Class
REQUIREMENTS
Port
Enclosure
ports
Level
Level
Performance
Criterion
Test
ESD
±4-kV CD or
IEC61000-4-2 8-kV AD, if CD
not possible
B
±6-kV CD
B
PASS
(EXCEED)
EFT
±2-kV/5-kHz,
IEC61000-4-4 capacitive
clamp
B
±4 kV
B
PASS
(EXCEED)
±1-kV; since
shielded cable
>20-m, direct
IEC61000-4-5
coupling to
shield (2
Ω/500 A)
B
±2 kV
A (1)
PASS
(EXCEED)
Ports for
control lines
and DC
auxiliary
Surge 1.2/50
supplies <60 V µs, 8/20 µs
(1)
Basic
standard
Phenomenon
TIDA-00204 MEASUREMENTS
Performance
(acceptance)
criterion
Class A is considered when there are less than two consecutive UDP packet losses and no major drop in network utilization.
One UDP packet loss will be tolerated by the system if the following UDP packet is echoed back successfully. The test has been
conducted with a UDP error packet test program at around 5% network bandwidth.
The performance (acceptance) criterion is defined as follows:
Table 28. Performance (Acceptance) Criterion
PERFORMANCE
(ACCEPTANCE)
CRITERION
DESCRIPTION
A
The module shall continue to operate as intended. No loss of function or performance even during the test.
B
Temporary degradation of performance is accepted. After the test, the module shall continue to operate as
intended without manual intervention.
C
During the test, loss of functions accepted, but no destruction of hardware or software. After the test, the
module shall continue to operate as intended automatically, after manual restart, or power off, or power on.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
53
Test Results
7.4.1
www.ti.com
Test Setup
The TIDA-00204 TI design has been tested at the testing laboratory of CSA Group Bayern in
Strasskirchen, Germany.
The TIDA-00204 with the test equipment is shown in the below picture. Each of the TIDA-00204 Gigabit
Ethernet ports 1 and 2 are connected to a PC or Laptop with an external Gigabit Ethernet to USB3
adapter. Two different test programs ran of the laptops.
The first test program "tida-00204_udp_throughput_test.exe" transmits and receives continuous UDP
packages with a payload size of 1472 bytes, yielding the maximum 1514 bytes per IPv4 packet. The
firmware of the Sitara AM3359 receives the UDP packets and echoes them back. Each of the two
Ethernet ports used around 20% of the network.
The second test program "tida-00204_udp_packet_error_test.exe" implements a UDP packet tester. It
compares the transmitted packet with the received packet (echoed back from Sitara AM3359) for the
corresponding Gigabit Ethernet port on the TIDA-00204. If a packet error is detected, it prints the number
of the packet to the console. The maximum bandwidth/network utilization achievable with this test software
was around 5% due to limitation on the PC test software "tida-00204_udp_packet_error_test.exe".
Figure 53. TIDA-00204 Test Equipment Overview for EMI/EMC Tests
The specific test setups for EMI (Section 7.4.2), ESD (Section 7.4.3), EFT (Section 7.4.4), and Surge
(Section 7.4.5).
54
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
7.4.2
CISPR 11 / EN55011 Radiated Emission Test Results
The TIDA-00204 meets EN55011 / CSPR 11 Class A requirements for category 2 with at least 4.3 dB of
margin (far-field measurements at 125 MHz, vertical polarization). The minimum margin in horizontal
polarization was 10.6 dB at 125 MHz as well.
An automatic pre-test with near-field measurement (3-m antenna distance to device under test [DuT]) was
used to identify the frequencies of maximum EMI in each horizontal and vertical polarization as
preparation for the final test with a 10-m antenna distance.
Figure 54 shows the test setup of the final measurement with a 10-m antenna distance to DuT.
Figure 54. CISPR 11 / EN55011 Test Setup for Far-Field With 10-m Antenna Distance to TIDA-00204 DuT
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
55
Test Results
www.ti.com
Figure 55 and Figure 56 show the measured spectral density with the final measurement with a 10-m
antenna at the critical frequencies identified during the pre-test. As mentioned earlier, the minimum margin
was 4.3 dB in vertical and 10.6 dB in horizontal polarization, each at 125 MHz.
Table 29. Measured EMI Spectrum (Quasi-Peak) According to EN55011;
10-m Far-Field, Horizontal Polarization
FREQUENCY
(MHz)
READING [dBµV]
(QP)
CORRECTION (dB)
VALUES [dBµV/m]
(QP)
LIMIT [dBµV/m]
(QP)
MARGIN [dB] (QP)
125
18.6
10.8
29.4
40
10.6
250
21.1
15.2
36.3
47
10.7
375
16.6
18.8
35.4
47
11.6
500
12.9
21.8
34.7
47
12.3
875
4.9
27.3
32.2
47
14.8
Figure 55. Measured EMI Spectrum (Quasi-Peak) According to EN55011;
10-m Far-Field, Horizontal Polarization
56
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
Measured EMI Spectrum (Quasi-Peak) According to EN55011;
10-m Far-Field, Vertical Polarization
FREQUENCY
(MHz)
READING [dBuV]
(QP)
CORRECTION (dB)
VALUES [dBuV/m]
(QP)
LIMIT [dBuV/m]
(QP)
MARGIN [dB] (QP)
125
24.9
10.8
35.7
40
4.3
250
20.4
15.2
35.6
47
11.4
375
12.6
18.8
31.4
47
15.6
500
8.5
21.8
30.3
47
16.7
875
1.2
27.3
28.5
47
18.5
Figure 56. Measured EMI Spectrum (Quasi-Peak) According to EN55011;
10-m Far-Field, Vertical Polarization
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
57
Test Results
7.4.2.1
www.ti.com
Pre-Test Results With 3-m Antenna Distance
CAUTION
Due to the shorter distance (3 m instead of 10 m), the threshold for EN55011
for radiated EMI is higher by 10 dB as well. The setup is shown in Figure 57.
Figure 57. Automatic Pre-Test Setup for EMI With 3-m Antenna Distance to DuT
(Left: Antenna, Right: TIDA-00204 DuT and Box With Shielded Laptops)
A pre-test was done to identify the critical frequencies on each polarization. This test has been done in a
chamber with a 3-m distance to the antenna.
Table 30. Pre-Test Equipment Setup
58
TYPE
NAME
Antenna
A5_VULB9168_24-14-007
Cable
A5_Cable_50-13-018
Cable
A5_Cable_50-13-019
Preamplifier
Ohm1_MTS TVV-695_50-01-059
Receiver
Ohm1_FSP7_11-05-002
Turntable
CO1000
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
The measured spectrum of the pre-test is shown in Figure 58 for horizontal and in Figure 59 for vertical polarization.
Figure 58. Measured EMI Spectrum According to EN55011;
3-m Near-Field, Horizontal Polarization (Pre-Test)
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Figure 59. Measured EMI Spectrum According to EN55011;
3-m Near-Field, Vertical Polarization (Pre-Test)
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
59
Test Results
7.4.3
www.ti.com
IEC-61000-4-2 ESD Test Results
Figure 60 shows the ESD test setup. The ESD strike was applied to the RJ45 case or shield of port 1 and
port 2. Both RJ45 cases were electrically connected with a conductive copper foil. During the ESD test,
both Gigabit Ethernet ports were connected with a 20-m cable to the far-end laptops. A UDP packet
transfer was launched on each Gigabit Ethernet link.
The test program "tida-00204_udp_throughput_test.exe" transmits and receives continuous UDP
packages with a payload size of 1472 bytes, yielding the maximum 1514 bytes per IPv4 packet. The
firmware of the Sitara AM3359 receives the UDP packets and echoes them back. The network utilization
was around 20% on each of the two Ethernet ports.
Figure 60. IEC61000-4-2 Test Setup for TIDA-00204 (Picture of 6-kV CD)
60
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
Table 31 shows the complete ESD test results for contact and air discharge (AD) at voltage levels, which
also exceed the requirements per IEC61800-3. This is marked accordingly.
Table 31. IEC-61000-4-2 ESD Test Results for TIDA-00204
(1)
PHENOMENON
BASIC
STANDARD
LEVEL
TIDA-00204
CONNECTOR
UNDER TEST
PERFORMANCE
CRITERION (1)
ESD
IEC61000-4-2
±4-kV CD
RJ45 port 1 and 2
B
ESD
IEC61000-4-2
±6-kV CD
RJ45 port 1 and 2
B
Not required per IEC61800-3
ESD
IEC61000-4-2
±8-kV CD
RJ45 port 1 and 2
C
Not required per IEC61800-3
ESD
IEC61000-4-2
±8-kV AD
RJ45 port 1 and 2
B
ESD
IEC61000-4-2
±15-kV AD
RJ45 port 1 and 2
B
COMMENT
Not required per IEC61800-3
See Table 28 for performance descriptions.
Class B was claimed when there was a network utilization reduction, but no link loss. Only for 8-kV ESD
CD was the link lost and a power-cycle of the boards was required. Figure 61 shows the network
utilization during the entire ESD test for ±6-kV CD ESD strikes. It can be seen that the network utilization
is reduced due to lost packets, but the link does not drop.
Figure 61. IEC61000-4-2 ±6-kV ESD CD: Network Utilization With UDP Packet Throughput Test on Port 1
and Port 2 (Measured on Two Separate Laptops)
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
61
Test Results
7.4.4
www.ti.com
IEC-61000-4-4 EFT Test Results
Figure 62 shows the EFT test setup. During the EFT test, both Gigabit Ethernet ports where connected
with a 3-m CAT7 cable to far end laptops. The capacitive clamp can be seen in the foreground of
Figure 62.
Figure 62. IEC61000-4-4 EFT Test Setup for TIDA-00204
During the EFT tests, a UDP packet transfer was launched on each Gigabit Ethernet port. Each test level
and Gigabit Ethernet port was tested with two different PC software programs running on a laptop for
analysis, as described earlier. The test results are shown in Table 32.
Table 32. IEC-61000-4-4 EFT Test Results for TIDA-00204
(1)
(2)
TIDA-00204
CONNECTOR
UNDER TEST
PERFORMANCE
CRITERION (1) (2)
±2-kV/5-kHz,
cap clamp
RJ45 port 1
B
IEC61000-4-4
±2-kV/5-kHz,
cap clamp
RJ45 port 2
B
EFT
IEC61000-4-4
±4-kV/5-kHz,
cap clamp
RJ45 port 1
B
Not required per
IEC61800-3
EFT
IEC61000-4-4
±4-kV/5-kHz,
cap clamp
RJ45 port 2
B
Not required per
IEC61800-3
PHENOMENON
BASIC STANDARD
EFT
IEC61000-4-4
EFT
LEVEL
COMMENT
See Section 7.4.1 for test setup description.
See Table 28 for performance descriptions.
To verify the number of packets lost the program during the EFT tests, a UDP packet transfer was
launched on each Gigabit Ethernet port. Each EFT voltage test level and gigabit Ethernet port was tested
with two different software programs running on the laptop for analysis of throughput and packet errors
during an EFT event.
62
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
Class B was claimed as there was no significant network utilization reduction, from the average of around
20% during the UDP packet throughput test as shown in Figure 63. During the packet error test, the
network utilization dropped from 5% to 1% due to a laptop issue when a packet lost was detected.
Figure 63. IEC61000-4-4 ±4-kV EFT: Network Utilization With UDP Throughput Test on Gigabit Ethernet
Port 1
Figure 64. IEC61000-4-4 ±4-kV EFT: Network Utilization With UDP Packet Error Test on Gigabit Ethernet
Port 1
During the test, the UDP packet error test program printed the packet number for every packet lost as well
as the total submitted packets. The total number of submitted packets during the EFT event was 60,680
packets (1526 bytes each). The number of lost packets was 100. However, there was not a single event
where two consecutive packets were lost. Therefore, every lost packet was re-submitted successfully.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
63
Test Results
7.4.5
www.ti.com
IEC-61000-4-5 Surge Test Results
Figure 65 shows the surge test setup. During the surge test, both Gigabit Ethernet ports where connected.
The port under test with a 20-m CAT7 cable and the other port, not under test with a 3-m cable to far end
laptops, respectively. The surge generator is on the left-hand side outside the picture.
Figure 65. IEC61000-4-5 Surge Test Setup for TIDA-00204
During the surge tests, a UDP packet transfer was launched on each Gigabit Ethernet port. Each test level
and Gigabit Ethernet port was tested with two different PC software programs running on a laptop for
analysis, as described earlier. The test results are shown in Table 33.
Table 33. IEC-61000-4-5 Surge Test Results for TIDA-00204
PHENOMENON
Surge
Surge
Surge
Surge
(1)
(2)
64
TIDA-00204
CONNECTOR
UNDER TEST
PERFORMANCE
CRITERION (1) (2)
IEC61000-4-5
±1-kV, 2-Ω/500-A
(20-m shielded
CAT7 Ethernet
cable)
RJ45 port 1
A
Exceeds IEC61800-3,
only Class B required
IEC61000-4-5
±1-kV, 2-Ω/500-A
(20-m shielded
CAT7 Ethernet
cable)
RJ45 port 2
A
Exceeds IEC61800-3,
only Class B required
IEC61000-4-5
±2-kV, 2-Ω/500-A
(20-m shielded
CAT7 Ethernet
cable)
RJ45 port 1
A
Exceeds IEC61800-3
IEC61000-4-5
±2-kV, 2-Ω/500-A
(20-m shielded
CAT7 Ethernet
cable)
RJ45 port 2
A
Exceeds IEC61800-3
BASIC
STANDARD
LEVEL
COMMENT
See Section 7.4.1 for test setup description.
See Table 28 for performance descriptions.
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Test Results
www.ti.com
Class A is considered when there are less than two consecutive UDP packet losses and no major drop in
network utilization. One UDP packet loss will be tolerated by the system, if the following UDP packet is
echoed back successfully. The test has been conducted with a UDP error packet test program at around
5% network bandwidth (see Figure 66).
To verify the number of packets lost the program during the surge tests, a UDP packet transfer was
launched on each Gigabit Ethernet port. Each surge voltage test level and Gigabit Ethernet port was
tested with two different software programs running on the laptop for analysis of throughput and packet
errors during a surge event.
Class A was claimed as there was no significant network utilization reduction, from the average of around
20% during the UDP packet throughput test. During the packet error test, the network utilization remained
5%. The total number of submitted packets during the surge event was 230,000 packets (1526 bytes
each). Only one packet was lost. Higher network utilization may yield more packet error losses; however,
this was not tested due to lack of test equipment.
Figure 66. IEC61000-4-5 ±2-kV Surge: Network Utilization With UDP Packet Error Test on Gigabit Ethernet
Port 1
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
65
Test Results
www.ti.com
Figure 67. IEC61000-4-5 ±2-kV Surge: Packet Error Analysis, Console Printout on Gigabit Ethernet Port 1
Additional tests were done with a modified board that did not have a TVS diode between the PHY and
transformer. During ±1-kV surge (as per IEC61800-3), no significant changes were observed with or
without TVS diode. However, at ±2-kV (exceeding the level required by IEC61800-3), the packet error
losses significantly increase by a factor of 10. Therefore, if higher surge immunity is desired the TVS diode
is recommend to be populated between the PHY and the transformer as per the TIDA-00204 schematics.
The TVS diode between the transformer and the RJ45 connector on ETH1 (port 1) was an initial test
option and not needed. It is marked DNP (not fitted) on the TIDA-00204 schematics.
66
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
8
Design Files
8.1
Schematics
To download the schematics, see the design files at TIDA-00204.
R1
J1
10
V5__DC_Sitara
C5
1µF
C6
0.1µF
C7
1000pF
C8
0.1µF
R2
453k
C9
1000pF
12
RAPC722X
8
GND
C11
10µF
11
R4
100k
DNPC12
0.022µF
7
R5
80.6k
6
VIN
VIN
SW
SW
CBOOT
EN
BIAS
PGOOD
FB
SS/TRK
VCC
RT
AGND
PGND
PGND
PAD
SYNC
1
2
V5_dc
MSS1260-153MLB
C1
10µF
C4
3
5
C2
10µF
C3
10µF
PEC02SAAN
V5_dc
C10
1µF
0.47µF
R3
750
GND
9
GND
4
10
15
16
17
1
MBRA160T3G
LPS3010-102MRB
1
2
13
14
1
3
2
L2
U1
C13
4.7µF
R6
1.00M
C14
8.2pF
D2
Green
2
L1
D1
J2
LM46002PWP
GND
GND
GND
GND
GND
GND
GND
0402 footprint
R7
249k
GND
GND
Figure 68. 24-V Input Power Supply
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
67
Design Files
www.ti.com
J3
1
2
PEC02SAAN
U2
1
Vaux2
C15
0.1µF
5
IN
EN
Vddio
2
OUT
C16
1µF
4
NR
6
3
GND
TPS73733DCQ
R8
0
U3
0
1
8
VOUT
EN
FB
VREF
R14
150k
GND
SGND
2
R16
110k
PGND
VCON
PAD
R11
DNP
0
5
C18
10µF
3
DNPC19
1µF
IN
3
EN
6
4
GND
V18phy
U4
1
OUT
DNP
GND
NC
V25phy
5
4
DNPC20
1µF 1v8 rail only used for
initial test/debug purpose
R15
0
R13
360
TLV70218DBVR
9
1
C17
10µF
VIN
LMZ10501SIL
D3
Green
C21
470pF
2
0
7
Vddio
R12
2
R10
V25phy
0
PHY is powered after vddio
V5_dc
GND
R9
GND
GND
GND
U5
C22
0.1µF 4
V5_dc
V11phy
BIAS
OUT
GND
1
C23
2.2µF
6
C24
0.1µF
GND
3
IN
EN
NC
GND
PAD
2
5
7
TPS72011DRV
GND
Figure 69. Power Supply for Dual DP83867IR PHYs
68
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
U8
1
2
PHY1_X_C_P
PHY1_X_C_N
PHY1_X_D_N
PHY1_X_D_P
PHY1_X_C_N
PHY1_X_C_P
U6
52
39
30
RGMII1_TXCTRL
RGMII1_TXD0
RGMII1_TXD1
RGMII1_TXD2
RGMII1_TXD3
R19
RGMII1_RXCTRL
38
37
36
35
34
33
32
31
RGMII1_RXCTRL_R
0
R20
1
2
3
4
5
6
7
8
RGMII1_RXCLK
RGMII1_RXD0
RGMII1_RXD1
RGMII1_RXD2
RGMII1_RXD3
Vddio
R28
11.0k
16
15
14
13
12
11
10
9
RGMII1_RXCLK_R
RGMII1_RXD0_R
RGMII1_RXD1_R
RGMII1_RXD2_R
RGMII1_RXD3_R
53
54
43
44
45
46
47
48
49
50
51
EXB-2HVR000V
0
PHY1_RX1588
PHY1_TX1588
Vddio
R31
2.49k
GTX_CLK
TD_P_A
TD_M_A
TX_EN/TX_CTRL
TX_ER
TX_CLK
TD_P_B
TD_M_B
TX_D0
TX_D1
TX_D2
TX_D3
TX_D4
TX_D5
TX_D6
TX_D7
TD_P_D
TD_M_D
13
14
RX_D0
RX_D1
RX_D2
RX_D3
RX_D4/GPIO
RX_D5/GPIO
RX_D6/GPIO
RX_D7/GPIO
R30
11.0k
55
56
R33
560
R34
2.49k
1
7
9
1
GND
16
D7
Orange
MDC
MDIO
20
21
RESET
COL/GPIO
CRS/GPIO
XI
XO
RESERVED
RESERVED
RESERVED
RESERVED
22
GND
65
PHY1_TD_D_N
PHY1_TD_D_P
PHY1_TD_C_N
PHY1_TD_C_P
D1+
D1-
4
5
PHY1_TD_D_P
PHY1_TD_D_N
6
7
9
10
NC
NC
NC
NC
3
1
2
PHY1_TD_A_P
PHY1_TD_A_N
GND
PHY1_TD_B_N
PHY1_TD_B_P
PHY1_TD_A_N
PHY1_TD_A_P
R23
6
7
9
10
GND
8
3
4
0.1µF
PHY1_TD_C_N
6
PHY1_TD_C_P
D1+
D1-
D2+
D2-
NC
NC
NC
NC
GND
GND
4
5
PHY1_TD_B_P
PHY1_TD_B_N
0.1µF
PHY1_TD_B_N
TD1+
MX1+
TD1-
MX1-
TCT2
MCT2
24
23
R25
560
10
0.1µF
PHY1_TD_A_N
R26
560
D4
Yellow
PHY_RESETn
D5
Red
8
3
TD2+
MX2+
TD2-
MX2-
GND
GND
TCT3
MCT3
TD3+
MX3+
TD3-
MX3-
TCT4
MCT4
TD4+
MX4+
TD4-
MX4-
PHY1_EARTH
PHY1_X_D_N
75.0
21
20
PHY1_X_D_P
R24
PHY1_X_C_N
75.0
J4
19
18
17
1
2
3
4
5
6
7
8
PHY1_X_C_P
R32
PHY1_X_B_N
75.0
16
15
14
9
10
11
12
PHY1_X_B_P
R37
43202-8916
PHY1_X_A_N
75.0
13
PHY1_X_A_P
C33
1000pF
C34
DNP
PHY1_EARTH
1000pF
GND
GND
PHY1_EARTH
PHY1_EARTH
U10
1.00M
Y1
GND
GND
PHY1_X_D_P
PHY1_X_D_N
DNP
TVS diode only used for
initial testing
R22
R36
PHY1_CLKOUT
4
5
HX5008FNL
D6
Green
GND
11
12
R27
560
4.7k
PHY1_INTPWDN
NC
NC
NC
NC
D2+
D2-
22
C30
TPD4E05U06DQA
Vddio
8
9
PHY1_TD_B_P
8
3
PHY1_TD_A_P
R35
DNP
22
5
7
GND
R29
MCT1
C28
GND
GND
U9
10.0k
MDIO_CLK_1
MDIO_DATA_1
2
TCT1
C29
DP83867IRPAPR
PHY1_X_A_P
PHY1_X_A_N
2
PHY1_X_B_N
PHY1_X_B_P
PHY1_X_A_N
PHY1_X_A_P
ABM3-25.000MHZ-D2Y-T
25 MHz
GND
0.1µF
PHY1_TD_D_N
PHY1_TD_D_P
GND
R21
4.7k
D2+
D2-
TPD4E05U06DQA
1
2
U7
1
2
PHY1_TD_C_P
PHY1_TD_C_N
GND
19
18
CLK_OUT
1
PHY1_TD_D_P
PHY1_TD_D_N
60
59
R18
DNP
0
T1
C27
PHY1_TD_C_P
PHY1_TD_C_N
15
63
62
61
INT/PWDN
PHY1_TD_B_P
PHY1_TD_B_N
28
26
25
27
24
LED_0
LED_1
LED_2
V18phy
C26
1000pF
PHY1_TD_A_P
PHY1_TD_A_N
5
6
TD_P_C
TD_M_C
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_TRSTN
RX_DV/RX_CTRL
RX_ER/GPIO
RX_CLK
2
3
10
11
RBIAS
GND
R17
DNP
0
17
64
1
40
RGMII1_TXCLK
VDDA1P8
VDDA1P8
D1+
D1-
TPD4E05U06DQA
2
VDDA2P5
VDDA2P5
C25
1000pF
V11phy
8
29
42
58
1
4
12
VDD1P1
VDD1P1
VDD1P1
VDD1P1
2
VDDIO
VDDIO
VDDIO
1
V25phy
23
41
57
2
Vddio
6
7
9
10
GND
C31
27pF
C32
27pF
1
2
D1+
D1-
6
7
9
10
NC
NC
NC
NC
D2+
D2-
4
5
GND
GND
8
3
PHY1_X_B_P
PHY1_X_B_N
DNP
TPD4E05U06DQA
TVS diode only used for
initial testing
PHY1_EARTH
GND
V25phy
Vddio
Vddio
C35
0.01µF
C36
10µF
C37
0.01µF
C38
1000pF
C39
1000pF
C40
10µF
C41
0.01µF
C42
1000pF
C43
1000pF
C44
1000pF
1
4
2
GND
V11phy
C45
10µF
C46
0.01µF
C47
1000pF
PHY_RESETn
U11
SN74AHC1G08DCK
3
SYS_RESETn
GND
5
R38
10.0k
GPIO_PHY_RESETn
GND
Place each 1000pF cap close to each supply pin of the PHY
C48
1000pF
C49
1000pF
C50
1000pF
GND
V18phy
C51
10µF
GND
C52
0.01µF
GND
Figure 70. DP83867IR PHY 1
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
69
Design Files
www.ti.com
D8
U12
40
RGMII2_TXCLK
52
39
30
RGMII2_TXCTRL
38
37
36
35
34
33
32
31
RGMII2_TXD0
RGMII2_TXD1
RGMII2_TXD2
RGMII2_TXD3
R43
RGMII2_RXCTRL
Vddio
0
R44
RGMII2_RXCLK
RGMII2_RXCLK_R
0
R46
R47
0
R50
0
R51
0
0
R49 RGMII2_RXD0
11.0k RGMII2_RXD1
RGMII2_RXD2
RGMII2_RXD3
Vddio
R56
R57
2.49k
RGMII2_RXCTRL_R
RGMII2_RXD0_R
RGMII2_RXD1_R
RGMII2_RXD2_R
RGMII2_RXD3_R
PHY2_RX1588
11.0k
Vddio
44
45
46
47
48
49
50
51
GTX_CLK
TD_P_A
TD_M_A
TX_EN/TX_CTRL
TX_ER
TX_CLK
TD_P_B
TD_M_B
TX_D0
TX_D1
TX_D2
TX_D3
TX_D4
TX_D5
TX_D6
TX_D7
TD_P_C
TD_M_C
TD_P_D
TD_M_D
RBIAS
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_TRSTN
RX_DV/RX_CTRL
RX_ER/GPIO
RX_CLK
RX_D0
RX_D1
RX_D2
RX_D3
RX_D4/GPIO
RX_D5/GPIO
RX_D6/GPIO
RX_D7/GPIO
LED_0
LED_1
LED_2
MDC
MDIO
INT/PWDN
R59
11.0k
PHY2_TX1588
53
54
43
VDDA1P8
VDDA1P8
R60
560
R61
2.49k
1
R62
2.49k
GND
D12
Orange
2
GND
55
56
1
7
9
16
RESET
COL/GPIO
CRS/GPIO
XI
XO
RESERVED
RESERVED
RESERVED
RESERVED
CLK_OUT
GND
GND
R39
DNP
0
17
64
2
3
PHY2_TD_A_P
PHY2_TD_A_N
5
6
2
5
3
4
PHY2_TD_C_N
V18phy
R40
DNP
0
GND
PHY2_TD_D_P
PHY2_TD_D_N
SRV05-4.TCT
5V
GND
PHY2_TD_C_P
PHY2_TD_C_N
13
14
PHY2_TD_D_P
PHY2_TD_D_N
R41
15
T2
C55
10.0k
28
26
25
27
24
1
GND
0.1µF
PHY2_TD_D_N
2
R45
4.7k
63
62
61
3
PHY2_TD_D_P
GND
20
21
MDIO_CLK_2
MDIO_DATA_2
60
R55
R52
560
Vddio
R53
560
5
6
PHY2_TD_C_P
D9
Yellow
D10
Red
D11
Green
GND
GND
GND
0.1µF
PHY2_TD_B_N
8
9
PHY2_TD_B_P
R63
DNP
0
22
65
PHY1_CLKOUT
MX1+
TD1-
MX1-
TCT2
MCT2
24
23
1.00M
Y2
2
TD2+
MX2+
TD2-
MX2-
TCT3
MCT3
TD3+
MX3+
10
TD3-
MX3-
TCT4
MCT4
0.1µF
PHY2_TD_A_N
11
TD4+
MX4+
12
PHY2_TD_A_P
ABM3-25.000MHZ-D2Y-T
25 MHz
TD4-
MX4-
20
PHY2_X_D_N
75.0
PHY2_X_D_P
R48
PHY2_X_C_N
75.0
J5
19
18
17
PHY2_X_C_P
R58
PHY2_X_B_N
75.0
16
15
14
C61
27pF
1
2
3
4
5
6
7
8
9
10
11
12
PHY2_X_B_P
R64
PHY2_X_A_N
75.0
43202-8916
13
HX5008FNL
C59
1000pF
GND
C60
27pF
R42
22
21
C58
R65
1
MCT1
TD1+
C57
7
PHY_RESETn
19
18
0.1µF
PHY2_TD_C_N
R54
560
4.7k
PHY2_INTPWDN
59
TCT1
C56
4
DP83867IRPAPR
GND
6
C54
1000pF
PHY2_TD_B_P
PHY2_TD_B_N
10
11
1
1
VDDA2P5
VDDA2P5
2
4
12
PHY2_TD_C_P
C53
1000pF
V11phy
8
29
42
58
1
V25phy
VDD1P1
VDD1P1
VDD1P1
VDD1P1
2
VDDIO
VDDIO
VDDIO
1
23
41
57
2
Vddio
C62
PHY2_X_A_P
DNP
1000pF
GND
GND
PHY2_EARTH
PHY2_EARTH
PHY2_EARTH
GND
V25phy
Vddio
D13
C63
10µF
C64
0.01µF
C65
1000pF
C66
1000pF
C67
10µF
C68
0.01µF
GND
V11phy
C69
1000pF
C70
1000pF
C71
1000pF
PHY2_TD_A_P
GND
Place each 1000pF cap close to each supply pin of the PHY
1
6
2
5
3
4
PHY2_TD_A_N
GND
PHY2_TD_B_P
V18phy
PHY2_TD_B_N
SRV05-4.TCT
5V
C72
10µF
C73
0.01µF
C74
1000pF
GND
C75
1000pF
C76
1000pF
C77
1000pF
C78
10µF
C79
0.01µF
GND
Figure 71. DP83867IR PHY 2
70
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
V5__DC_Sitara
V5__DC_Sitara
C80
10µF
V5__DC_Sitara
C82
4.7µF
V5__DC_Sitara
GND
C83
4.7µF
V5__DC_Sitara
C84
4.7µF
V5__DC_Sitara
C85
4.7µF
GND
GND
VCC2
3
VCC3
23
GND
6
GND
V5__DC_Sitara
28
GND
13
C89
10µF
VCC1
41
47
GND
C87
4.7µF
U13
36
SW3
VFB3
SW1
VCC5
VFB1
29
GND
C91
2.2µF
27
20
21
GND
GND
38
8
9
39
I2C0_SDA
I2C0_SCL
GND
11
10
45
37
33
19
26
1
40
PMIC_Vrtc
PMIC_PWR_EN
PMIC_RESETOUTn
R67
10.0k
18
C99
0.1µF
GND
25
17
Vdd1_smps
GND
35
VLCF5020T-2R2N2R6-3
C86
10µF
32
L4
VCC6
VCC7
SW2
VCCIO
VFB2
12
30
L3
VCC4
Vaux33
PMIC_Vrtc
31
GND
VLCF5020T-2R2N2R6-3
C88
10µF
44
L5
VDDIO
SWIO
VFBIO
OSC32KIN
VDIG1
OSC32KOUT
VDIG2
CLK32KOUT
VAUX33
SDA/SDI
SCL/SCK
GPIO/CKSYN
SCLSR/EN1
SDASR/EN2
INT1
SLEEP
PWRON
BOOT1
BOOT0
PWRHOLD
NRESPWRON
VMMC
GND
Vaux33
VLCF5020T-2R2N2R6-3
C90
10µF
16
VAUX2
VPLL
VDAC
Vdig2
5
Vaux33
GNDIO
TESTV
GND1
GND2
REFGND
PAD
C92
2.2µF
4
Vmmc
D14
Green
C93
2.2µF
2
46
C94
2.2µF
Vaux2
C95
2.2µF
48
Vpll
GND
GND
C96
2.2µF
24
Vdac
C97
2.2µF
22
C98
2.2µF
VREF
R66
560
GND
7
Vaux1
VAUX1
Vdds_DDR
14
VRTC
VBACKUP
Vdd2_smps
42
1
C81
10µF
2
V5__DC_Sitara
GND
15
GND
34
43
49
GND
TPS65910A3A1RSL
GND
V5__DC_Sitara
Vrtc
U14
6
C100
1µF
4
IN
OUT
EN
NR
NC
1
3
C101
1µF
5
2
GND
TPS71718DSER
GND
GND
Figure 72. Sitara AM3359 Power Supply
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
71
Design Files
www.ti.com
Vdd2_smps_am335x
Vaux2
U15C
Vdd2_smps
U15D
F6
F7
G6
G7
G10
H11
J12
K6
K8
K12
L6
L7
L8
L9
M11
M13
N8
N9
N12
N13
Vdd1_smps_am335x
Vdd1_smps
F10
F11
F12
F13
G13
H13
J13
A2
Vdig2
D9
H15
N15
N16
C134
0.01µF
C135
0.01µF
C136
0.01µF
C137
0.01µF
C138
0.01µF
C139
1µF
C140
1µF
C141
1µF
GND
E7
C142
0.01µF
E5
F5
G5
H5
J5
K5
L5
Vdig2
GND
Vdds_DDR
VDDSHV4
VDDSHV4
P7
P8
C102
0.01µF
C105
0.01µF
P10
P11
C106
0.01µF
C103
0.01µF
C104
10µF
C107
10µF
A1
A18
F8
G8
G9
G11
G12
H6
H7
H8
H9
H10
H12
J6
J7
J8
J9
J10
J11
Vmmc
GND
Vaux2
P12
P13
C108
0.01µF
C111
0.01µF
H14
J14
C112
0.01µF
C109
0.01µF
C110
10µF
C113
10µF
Vmmc
GND
Vaux2
VDDSHV5
VDDSHV5
K14
L14
C114
0.01µF
E10
E11
E12
E13
F14
G14
N5
P5
P6
C115
0.01µF
C116
10µF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K7
K9
K10
K11
L10
L11
L12
L13
M6
M7
M8
M9
M10
M12
N7
N10
N11
V1
V18
AM3359BZCZA80
GND
GND
GND
C117
0.01µF
C118
0.01µF
C119
0.01µF
C120
0.01µF
C121
0.01µF
C122
0.01µF
C123
0.01µF
C124
0.01µF
C125
0.01µF
C126 Vaux2
10µF
Vdac
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
E6
E14
F9
K13
N6
P9
P14
C127
0.01µF
C128
0.01µF
C129
0.01µF
C130
0.01µF
C131
10µF
VDDA _ADC
VSSA_USB
R15
R16
GND
VDDA3P3V_USB1
VDDA1P8V_USB1
VDDA_ADC
VSSA_ADC
N14
GND
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV6
VDDSHV3
VDDSHV3
VDDA3P3V_USB0
VDDA1P8V_USB0
M14
C133
0.01µF
VDD_MPU
VDD_MPU
VDD_MPU
VDD_MPU
VDD_MPU
VDD_MPU
VDD_MPU
VDD_MPU_MON
VDDSHV2
VDDSHV2
VDDS_SRAM_MPU_BB
CAP_VDD_SRAM_MPU
CAP_VBB_MPU
VDDS_SRAM_CORE_BG
Vaux1
C132
0.01µF
VDDSHV1
VDDSHV1
CAP_VDD_SRAM_CORE
VDDS_PLL_MPU
D10
D11
C10
E9
Vaux33
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VSSA_USB
VDDS_PLL_DDR
VPP
VDDS_PLL_CORE_LCD
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
VDDS_DDR
L6
D8
150 ohm
E8
GNDA_ADC
C143
0.01µF
Vrtc
VDDS_RTC
CAP_VDD_RTC
RTC_KALDO_EN
VDDS_OSC
RESERVED
D7
D6
B4
GND
Vdig2
L7
150 ohm
Vdig2
M5
R10
Vpll
GND
C144
0.01µF
GNDA_ADC
R11
A3
R68
10.0k
C145
1µF
C146
0.01µF
C147
0.01µF
AM3359BZCZA80
GND
GND_osc0
Vdds_DDR
C148
10µF
C149
10µF
C150
0.1µF
C151
0.1µF
C152
0.1µF
C153
0.1µF
C154
0.1µF
C155
0.1µF
C156
0.1µF
C157
0.1µF
C158
0.1µF
C159
0.1µF
C160
0.1µF
C161
0.1µF
C162
0.1µF
C163
0.1µF
C164
0.1µF
C171
10µF
C172
0.01µF
C173
0.01µF
C174
0.01µF
C175
0.01µF
C176
0.01µF
C166
0.1µF
C167
0.1µF
C168
0.1µF
C169
0.1µF
Place each 0.1uF cap close to each supply pin of the Sitara DDR I/F
GND
Vdd2_smps_am335x
C170
10µF
C165
0.1µF
C177
0.01µF
Vdd1_smps_am335x
C178
0.01µF
C179
0.01µF
C180
0.01µF
C181
0.01µF
C182
0.01µF
C183
0.01µF
C184
0.01µF
C185
10µF
C186
0.01µF
C187
0.01µF
C188
0.01µF
C189
0.01µF
C190
0.01µF
Place each 0.01uF cap close to each supply pin of the Sitara
GND
GND
Figure 73. Sitara AM3359 Supply Pins
72
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
C192
C191
0.01µF
PMIC_RESETOUTn
2
Vaux2
R69
GND
U15A
27pF
1
C193
Y3
ABM3-24.000MHZ-D2Y-T
24 MHz
V10
U11
V11
27pF
A6
A4
A5
C194
GND_osc0
18pF
Y4
2
3
DNC
DNC
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
1
4
MC-306 32.7680K-A0:ROHS
32.768kHz
C198
18pF
GND_rtc
DDR_BA0
DDR_BA1
DDR_BA2
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
RTC_XTALIN
M3
M4
N1
N2
N3
N4
P3
P4
J1
K1
K2
K3
K4
L3
L4
M1
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_ODT
DDR_RESETn
G1
G2
J3
R99
49.9 DDR_VREF
J4
EXTINT
XDMA_EVENT_INTR0
XDMA_EVENT_INTR1
RTC_XTALOUT
VSS_RTC
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14
DDR_A15
DDR_BA0
DDR_BA1
DDR_BA2
M2
P1
P2
J2
L1
L2
DDR_DQM0
DDR_DQS0_P
DDR_DQS0_N
DDR_DQM1
DDR_DQS1_P
DDR_DQS1_N
PWRONRST
WARMRST
RTC_PWRONRST
XTALOUT
VSS_OSC
F3
H1
E4
C3
C2
B1
D5
E2
D4
C1
F4
F2
E3
H3
H4
D3
C4
E1
B3
D2
D1
G3
H2
F1
G4
B2
DDR_CLK_P
DDR_CLK_N
DDR_CKE
DDR_CSn
DDR_CASn
DDR_RASn
DDR_WEn
XTALIN
TRST
TMS
TDI
TCK
TDO
EMU0
EMU1
GPMC_CLK
GPMC_CS0
GPMC_CS1
GPMC_CS2
GPMC_CS3
GPMC_WE
GPMC_OEN_RE
GPMC_ADV_ALE
GPMC_BE0_CLE
GPMC_BE1
GPMC_WAIT0
GPMC_WP
DDR_ODT
DDR_RESET
DDR_VTP
R13
V14
U14
T14
R14
V15
U15
T15
V16
U16
T16
V17
G18
G17
G16
G15
F18
F17
PMIC_PWR_EN
R71
SYS_WARMRESETn
VDDA_ADC
JTAG_TRSTn
JTAG_TMS
JTAG_TDI
JTAG_TCK
JTAG_TDO
JTAG_EMU0
JTAG_EMU1
C195
0.01µF
MMC1_CLK
MMC1_CMD
C196
0.01µF
GNDA_ADC
B9
A9
C197
1000pF
PHY1_RX1588
PHY2_TX1588
GPIO_PHY_RESETn
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
I2C0_SCL
I2C0_SDA
DDR_VTT_EN
PHY2_INTPWDN
PHY2_RX1588
RGMII2_TXCTRL_R
RGMII2_TXD3_R
RGMII2_TXD2_R
RGMII2_TXD1_R
RGMII2_TXD0_R
RGMII2_TXCLK_R
R77
22
RGMII2_TXCTRL
RGMII2_RXCTRL
R78
R79
R80
R81
R82
22
22
22
22
22
RGMII2_TXD3
RGMII2_TXD2
RGMII2_TXD1
RGMII2_TXD0
RGMII2_TXCLK
C6
C5
B6
C7
B7
A7
C8
B8
A8
C9
EMU2_GPIO0_19
EMU3_GPIO0_20
V12
V6
U9
V9
T13
U6
T7
R7
T6
U18
T17
U17
GPMC_A0
GPMC_A1
GPMC_A2
GPMC_A3
GPMC_A4
GPMC_A5
GPMC_A6
GPMC_A7
GPMC_A8
GPMC_A9
GPMC_A10
GPMC_A11
U15B
SYS_RESETn
0
RTC_PORZ
B10
C11
B11
A12
A11
C14
B14
U7
V7
R8
T8
U8
V8
R9
T9
U10
T10
T11
U12
T12
R12
V13
U13
MMC0_CMD
MMC0_CLK
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
R70
10k
B18
A15
D14
GPMC_AD0
GPMC_AD1
GPMC_AD2
GPMC_AD3
GPMC_AD4
GPMC_AD5
GPMC_AD6
GPMC_AD7
GPMC_AD8
GPMC_AD9
GPMC_AD10
GPMC_AD11
GPMC_AD12
GPMC_AD13
GPMC_AD14
GPMC_AD15
DDR_CK
DDR_CK
DDR_CKE
DDR_CS0
DDR_CAS
DDR_RAS
DDR_WE
DDR_DQM0
DDR_DQS0
DDR_DQS0
DDR_DQM1
DDR_DQS1
DDR_DQS1
B15
A10
B5
PHY1_TX1588
RGMII2_RXCLK
RGMII2_RXD3
RGMII2_RXD2
RGMII2_RXD1
RGMII2_RXD0
A17
B17
B16
A16
C15
PMIC_POWER_EN
EXT_WAKEUP
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
MII1_TX_CLK
MII1_TXD0
MII1_TXD1
MII1_TXD2
MII1_TXD3
MII1_TX_EN
MII1_CRS
MII1_COL
MII1_RX_CLK
MII1_RXD0
MII1_RXD1
MII1_RXD2
MII1_RXD3
MII1_RX_ER
MII1_RX_DV
VREFP
VREFN
SPI0_SCLK
SPI0_D0
SPI0_D1
SPI0_CS0
SPI0_CS1
RMII1_REF_CLK
MDC
MDIO
LCD_DATA0
LCD_DATA1
LCD_DATA2
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
LCD_DATA8
LCD_DATA9
LCD_DATA10
LCD_DATA11
LCD_DATA12
LCD_DATA13
LCD_DATA14
LCD_DATA15
E16
E15
E18
E17
UART0_TXD
UART0_RXD
UART0_CTS
UART0_RTS
D15
D16
D18
D17
UART1_TXD
UART1_RXD
UART1_CTS
UART1_RTS
C16
C17
I2C0_SCL
I2C0_SDA
N17
N18
M15
P16
F16
P15
USB0_DP
USB0_DM
USB0_CE
USB0_ID
USB0_DRVVBUS
USB0_VBUS
LCD_PCLK
LCD_VSYNC
LCD_HSYNC
LCD_AC_BIAS_EN
R17
R18
P18
P17
F15
T18
USB1_DP
USB1_DM
USB1_CE
USB1_ID
USB1_DRVVBUS
USB1_VBUS
MCASP0_AHCLKX
MCASP0_ACLKX
MCASP0_FSX
MCASP0_AXR0
MCASP0_AHCLKR
MCASP0_ACLKR
MCASP0_FSR
MCASP0_AXR1
C18
K18
K17
K16
K15
J18
J16
H17
H16
Connected H16 to J16 for
initial test/debug purpose
L18
M16
L15
L16
L17
J15
J17
H18
M18
M17
8
7
6
5
4
3
2
1
RGMII1_TXCLK_R
RGMII1_TXD0_R
RGMII1_TXD1_R
RGMII1_TXD2_R
RGMII1_TXD3_R
RGMII1_TXCTRL_R
9
10
11
12
13
14
15
16
EXB-2HV220JV
22
RGMII1_RXCLK
RGMII1_RXD0
RGMII1_RXD1
RGMII1_RXD2
RGMII1_RXD3
RGMII1_RXCTRL
R72
R73
22
22
R1
R2
R3
R4
T1
T2
T3
T4
U1
U2
U3
U4
V2
V3
V4
T5
MDIO_CLK_2
MDIO_CLK_1
R74
R75
SYS_BOOT0
SYS_BOOT1
SYS_BOOT2
SYS_BOOT3
SYS_BOOT4
SYS_BOOT5
SYS_BOOT6
SYS_BOOT7
SYS_BOOT8
SYS_BOOT9
SYS_BOOT10
SYS_BOOT11
SYS_BOOT12
SYS_BOOT13
SYS_BOOT14
SYS_BOOT15
GND
2.2k
A14
A13
B13
D12
C12
B12
C13
D13
EMU4
ECAP0_IN_PWM0_OUT
AM3359BZCZA80
Vaux2
PHY1_INTPWDN
FTDI_UART3_TXD
FTDI_UART3_RXD
R83
DNP
10k
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k DNP
10k
R94
10k
R95
10k
R96
R97
R98
10k DNP
10k DNP
10k
DDR_VREF
SYS_BOOT0
SYS_BOOT1
SYS_BOOT2
SYS_BOOT3
SYS_BOOT4
SYS_BOOT5
SYS_BOOT6
SYS_BOOT7
SYS_BOOT8
SYS_BOOT9
SYS_BOOT10
SYS_BOOT11
SYS_BOOT12
SYS_BOOT13
SYS_BOOT14
SYS_BOOT15
GND
Vrtc
U16B
SN74AUP2G08DCU
R100
7
4
C201
2.2µF
S1
RTC_PORZ
2
1.00k
GND
U16A
SN74AUP2G08DCU
1
1
R119
100k
4
6
Vaux2
8
8
GND
3
MDIO_DATA_1
MDIO_DATA_2
Vddio
V5
U5
R5
R6
C200
0.01µF
5
22
22
R76
C199
0.1µF AM3359BZCZA80
Vrtc
RGMII1_TXD1
RGMII1_TXCLK
RGMII1_TXD2
RGMII1_TXD0
RGMII1_TXD3
RGMII1_TXCTRL
2
B3U-1000P
GND
R117
2.2k
SYS_WARMRESETn
I2C0_SCL
R101 R102 R103 R104 R105
100kDNP
100k 100k 100k 100k
R118
2.2k
I2C0_SDA
R106 R107
100k 100k
R108 R109 R110
100k 100k 100k
R111 R112 R113 R114
100kDNP
100kDNP
100kDNP
100k
R115
100k
R116
100k
GND
GND
GND
Figure 74. Sitara AM3359 Signal Pins
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
73
Design Files
www.ti.com
Vmmc
R120
10k
Vdds_DDR
R121 R122
10k
10k
R123 R124
10k
10k
R125
10k
C202
10µF
C203
0.1µF
C204
0.1µF
R126
49.9
Vdds_DDR
U17
B2
D9
G7
K2
K8
N1
N9
R1
R9
DDR_CLK_P
DDR_CLK_N
R131
10k
GND
R132 DDR_CSn
240 DDR_RASn
DDR_CASn
DDR_WEn
C208
0.1µF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
BA0
BA1
BA2
M8
H1
DDR_VREF
NC
NC
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
M2
N8
M3
DDR_BA0
DDR_BA1
DDR_BA2
LDM
UDM
RESET
CKE
CK
CK
CS
RAS
CAS
WE
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
LDQS
LDQS
UDQS
UDQS
ODT
ZQ
T2
K9
J7
K7
L2
J3
K3
L3
DDR_RESETn
DDR_CKE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
K1
L8
DDR_ODT
1
2
3
4
5
6
7
8
MMC1_CLK
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A1
A8
C1
C9
D2
E9
F1
H2
H9
Vdds_DDR
R129
1.00k
J6
GND
MMC1_DAT2
MMC1_DAT3
MMC1_CMD
R127
49.9
VREFCA
VREFDQ
DDR_CLK_P
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR_D6
DDR_D7
DDR_D3
DDR_D1
DDR_D4
DDR_D5
DDR_D2
DDR_D0
DDR_D10
DDR_D8
DDR_D11
DDR_D9
DDR_D14
DDR_D13
DDR_D15
DDR_D12
F3
G3
C7
B7
MMC1_DAT0
MMC1_DAT1
10
11
U18
1
2
3
Vtt_DDR
4
Vmmc
R128
DDR_A0
DDR_WEn
DDR_A1
DDR_A12
DDR_BA1
DDR_A4
DDR_DQS0_P
DDR_DQS0_N
DDR_DQS1_P
DDR_DQS1_N
E7
D3
DDR_CLK_N
1
2
3
4
5
6
7
8
10
IO1
IO2
IO3
IO4
IO5
IO6
NC
NC
VCC
16
15
14
13
12
11
10
9
6
7
8
DAT2
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1
S1
S2
S3
S4
CD
SW
9
12
13
14
502774-0891
GND
9
5
GND
MicroSD_case
TPD6E001RSER
C205
C206
0.01µF
GND
0.1µF
GND
EXB-2HV470JV
47
DDR_DQM0
DDR_DQM1
MicroSD_case
R130
J1
J9
L1
L9
M7
T7
DDR_A8
DDR_A6
DDR_A11
DDR_A10
DDR_A9
DDR_A13
DDR_A7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Vddio
C207
EXB-2HV470JV
47
0.1µF
U19
R133
DDR_CSn
DDR_ODT
DDR_BA0
DDR_A3
DDR_CASn
DDR_A5
DDR_A2
DDR_BA2
B1
B9
D1
D8
E2
E8
F9
G1
G9
1
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
2
3
4
A0
VCC
A1
WP
A2
SCL
VSS
SDA
8
7
6
I2C0_SCL
5
I2C0_SDA
CAT24C256WI-GT3
GND
EXB-2HV470JV
47
R134
DDR_RASn
47
MT41J128M16JT-125K TR
GND
GND
Vdds_DDR
Vaux33
Vtt_DDR
U20
TP1
R136
10.0k
R137
10k
R135
10k
10
9
7
DDR_VTT_EN
1
Vdds_DDR
Vtt_DDR
Vdds_DDR
Vdds_DDR
Vaux33
R138
10.0k
C210
1000pF
2
VIN
PGOOD
EN
REFIN
VLDOIN
VO
VOSNS
REFOUT
EP
GND
PGND
3
TP2
5
6
DDR_VREF
C209
0.1µF
11
8
4
TPS51200DRCR
GND
C211
10µF
C212
10µF
C213
0.1µF
C214
0.1µF
C215
0.1µF
C216
0.1µF
C217
0.1µF
C218
0.1µF
C219
0.1µF
C220
0.1µF
C221
0.1µF
C222
0.1µF
C223
0.1µF
C224
0.1µF
C225
10µF
C226
10µF
C227
10µF
C228
0.1µF
C229
0.1µF
C230
0.1µF
C231
10µF
C232
10µF
C233
4.7µF
GND
GND
GND
GND
GND
Figure 75. Sitara DDR3, E2PROM, and SD-Card Memory
74
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
Vdc_USB
L8
1
USBD_FT_P
2
USBD_FT_N
Vddio
12
37
64
Vddio
L9
4
150 ohm L11
9
150 ohm
49
FT_Vdd1v8
L12
50
VCCIO
VCCIO
VCCIO
VCCIO
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
VCORE
VCORE
VCORE
VPHY
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
VPLL
VREGOUT
VREGIN
150 ohm
Vddio
C236
0.1µF
R148
10k
R149
10k
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
C237
0.1µF
7
USBD_FT_N
R150
10k
8
USBD_FT_P
DM
DP
GND
R154
2.2k
U23
6
3
C239
0.1µF
5
4
VCC
DO
63
1
62
DI
EECS
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
EECLK
61
EEDATA
14
RESET
Vddio
CS
CLK
VSS
R156
2
2.2k
93LC56B-I/OT
R157
6
PWREN
SUSPEND
REF
12.1k
AGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ABM3-12.000MHZ-D2Y-T
Y5
GND
2
2
OSCI
3
OSCO
1
12MHz
13
TEST
26
27
28
29
30
32
33
34
R141 0
0
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRSTn
R140
R142 0
0
R144
R143
0
MP1
MP2
MP3
MP4
U21
6
2
1
3
4
C235
0.01µF
VBUS
DD+
ID
GND
GND
GND
10104111-0001LF
5
NC
TPD4S012DRYR
USB_case
GND
Vddio
R145
FT_sRESET
0
C234
4.7µF
MH1
MH2
MH3
MH4
JTAG_EMU0
0
Vddio
R147
L10
R146
4.7k
150 ohm
GND
JTAG_EMU1
0
USB_case
GND
38
39
40
41
43
44
45
46
FTDI_UART3_RXD
FTDI_UART3_TXD
Vddio
C238
DNP
0.01µF
GND
R152JTAG_TDO
RTCK
4.7k
TCK
EMU_RSTn
EMU2R
EMU4R
R155
4.75k
DNP
2
4
6
8
10
12
14
16
18
20
JTAG_TRSTn
TDIS
R151
DNP
4.7k
R153
4.7k
JTAG_EMU1
EMU3R
TFM-110-02-S-D-A-K-TR
GND
60
36
R158
10.0k
10
1
5
11
15
25
35
47
51
R159
DNP
0
RTCK
JTAG_TCK
R160
DNP
0
TCK
EMU2_GPIO0_19
R161
DNP
0
EMU2R
EMU3_GPIO0_20
R162
DNP
0
EMU3R
EMU4
R163
DNP
0
EMU4R
SYS_RESETn
R164
DNP
0
GND
C241
27pF
GND
J8
1
3
5
7
9
11
13
15
17
19
JTAG_TMS
JTAG_TDI
JTAG_EMU0
Vdc_USB
48
52
53
54
55
57
58
59
FT2232HL-REEL
C240
27pF
Vdc_USB
R139
16
17
18
19
21
22
23
24
Vdc_USB
3
ACM2012H-900-2P-T00
Vdc_USB
U22
20
31
42
56
J7
1
2
3
4
5
USBD_N
USBD_P
4
GND
GND
EMU_RSTn
DNPC242
0.1µF
GND
Vddio
FT_Vdd1v8
Vddio
U24
1
2
FT_sRESET
R165
4.7k
3
NC
A
VCC
Y
5
4
C243
0.01µF
GND
SYS_RESETn
C244
0.1µF
C245
0.1µF
C246
0.1µF
C247
0.1µF
C248
0.1µF
C249
0.1µF
C250
0.1µF
C251
4.7µF
GND
SN74LVC1G06DCK
GND
GND
GND
Figure 76. USB Virtual COM Port and JTAG Interface
space
space
space
space
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
75
Design Files
8.2
www.ti.com
Bill of Materials
To download the bill of materials (BOM), see the design files at TIDA-00204.
Table 34. BOM
QTY
76
REFERENCE
PART DESCRIPTION
MANUFACTURER
MANUFACTURER
PARTNUMBER
PCB FOOTPRINT
NOTE
TDK
C1608X5R1E106M080AC
0603
Fitted
MuRata
GRM21BR72A474KA73L
0805_HV
Fitted
TDK
C2012X7S2A105K125AB
0805_145
Fitted
39
C1, C2, C3, C17, C18,
C36, C40, C45, C51,
C63, C67, C72, C78,
C80, C81, C86, C88,
C89, C90, C104, C107,
C110, C113, C116,
C126, C131, C148,
C149, C170, C171,
C185, C202, C211,
C212, C225, C226,
C227, C231, C232
CAP, CERM, 10 µF, 25 V, +/- 20%,
X5R, 0603
1
C4
CAP, CERM, 0.47 µF, 100 V, +/- 10%,
X7R, 0805
1
C5
CAP, CERM, 1 µF, 100 V, +/- 10%,
X7S, 0805
2
C6, C8
CAP, CERM, 0.1 µF, 100 V, +/- 10%,
X7R, 0603
MuRata
GRM188R72A104KA35D
0603
Fitted
2
C7, C9
CAP, CERM, 1000 pF, 100 V, +/10%, X7R, 0603
MuRata
GRM188R72A102KA01D
0603
Fitted
1
C10
CAP, CERM, 1 µF, 25 V, +/- 10%,
X7R, 0603
MuRata
GRM188R71E105KA12D
0603
Fitted
1
C11
CAP, CERM, 10 µF, 100 V, +/- 20%,
X7S, 2220
TDK
C5750X7S2A106M
2220
Fitted
9
C13, C82, C83, C84,
C85, C87, C233, C234,
C251
CAP, CERM, 4.7 µF, 16 V, +/- 10%,
X5R, 0603
MuRata
GRM188R61C475KAAJ
0603
Fitted
1
C14
CAP, CERM, 8.2 pF, 25 V, +/- 5%,
C0G/NP0, 0402
MuRata
GRM1555C1E8R2CA01D
0402
Fitted
11
C15, C22, C27, C28,
C29, C30, C55, C56,
C57, C58, C206
CAP, CERM, 0.1 µF, 16 V, +/- 10%,
X7R, 0402
MuRata
GRM155R71C104KA88D
0402
Fitted
3
C16, C100, C101
CAP, CERM, 1 µF, 10 V, +/- 10%,
X7R, 0603
MuRata
GRM188R71A105KA61D
0603
Fitted
1
C21
CAP, CERM, 470 pF, 50 V, +/- 10%,
X7R, 0402
MuRata
GRM155R71H471KA01D
0402
Fitted
10
C23, C91, C92, C93,
C94, C95, C96, C97,
C98, C201
CAP, CERM, 2.2 µF, 10 V, +/- 10%,
X7R, 0603
MuRata
GRM188R71A225KE15D
0603
Fitted
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
Table 34. BOM (continued)
QTY
REFERENCE
PART DESCRIPTION
MANUFACTURER
MANUFACTURER
PARTNUMBER
PCB FOOTPRINT
NOTE
17
C24, C99, C199, C203,
C204, C207, C209,
C236, C237, C239,
C244, C245, C246,
C247, C248, C249,
C250
CAP, CERM, 0.1 µF, 10 V, +/- 10%,
X7R, 0402
MuRata
GRM155R71A104KA01D
0402
Fitted
24
C25,
C42,
C48,
C54,
C70,
C76,
CAP, CERM, 1000 pF, 16 V, +/- 10%,
X7R, 0201
MuRata
GRM033R71C102KA01D
0201
Fitted
8
C31, C32, C60, C61,
C192, C193, C240,
C241
CAP, CERM, 27 pF, 50 V, +/- 5%,
C0G/NP0, 0402
MuRata
GRM1555C1H270JA01D
0402
Fitted
2
C33, C59
CAP, CERM, 1000 pF, 2000 V, +/10%, X7R, 1206_190
Johanson Technology
202R18W102KV4E
1206_190
Fitted
69
C35, C37, C41, C46,
C52, C64, C68, C73,
C79, C102, C103, C105,
C106, C108, C109,
C111, C112, C114,
C115, C117, C118,
C119, C120, C121,
C122, C123, C124,
C125, C127, C128,
C129, C130, C132,
C133, C134, C135,
CAP, CERM, 0.01 µF, 10 V, +/- 10%,
C136, C137, C138,
X7R, 0201
C142, C143, C144,
C146, C147, C172,
C173, C174, C175,
C176, C177, C178,
C179, C180, C181,
C182, C183, C184,
C186, C187, C188,
C189, C190, C191,
C195, C196, C200,
C205, C235, C243
MuRata
GRM033R71A103KA01D
0201
Fitted
4
C139, C140, C141,
C145
Samsung
CL03A105MP3NSNC
0201
Fitted
C26,
C43,
C49,
C65,
C71,
C77,
C38, C39,
C44, C47,
C50, C53,
C66, C69,
C74, C75,
C197, C210
CAP, CERM, 1 µF, 10 V, +/- 20%,
X5R, 0201
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
77
Design Files
www.ti.com
Table 34. BOM (continued)
QTY
78
REFERENCE
C151,
C154,
C157,
C160,
C163,
C166,
C169,
C214,
C217,
C220,
C223,
C229,
C152,
C155,
C158,
C161,
C164,
C167,
C208,
C215,
C218,
C221,
C224,
C230
PART DESCRIPTION
MANUFACTURER
MANUFACTURER
PARTNUMBER
PCB FOOTPRINT
NOTE
Samsung
CL03A104KP3NNNC
0201
Fitted
MuRata
GRM1555C1H180JA01D
0402
Fitted
36
C150,
C153,
C156,
C159,
C162,
C165,
C168,
C213,
C216,
C219,
C222,
C228,
2
C194, C198
CAP, CERM, 18 pF, 50 V, +/- 5%,
C0G/NP0, 0402
1
D1
Diode, Schottky, 60V, 1A, SMA
ON Semiconductor
MBRA160T3G
SMA
Fitted
5
D2, D3, D6, D11, D14
LED, Green, SMD
OSRAM
LG L29K-G2J1-24-Z
LG L29K_GREEN
Fitted
2
D4, D9
LED, Yellow, SMD
OSRAM
LY L29K-J1K2-26-Z
LY L29K_Yellow
Fitted
2
D5, D10
LED, Red, SMD
OSRAM
LS L29K-G1J2-1-Z
LS L29K_Red
Fitted
2
D7, D12
LED, Orange, SMD
OSRAM
LO L29K-J2L1-24-Z
LO L29K_Orange
Fitted
2
D8, D13
Diode, TVS, Bi, 5 V, 300 W, SOT-23-6
Semtech
SRV05-4.TCT
SOT-23-6
Fitted
4
H1, H2, H3, H4
Machine Screw, Round, #4-40 x 1/4,
Nylon, Philips panhead
B&F Fastener Supply
NY PMS 440 0025 PH
NY PMS 440 0025 PH
Fitted
4
H5, H6, H7, H8
Standoff, Hex, 0.5"L #4-40 Nylon
Keystone
1902C
Keystone_1902C
Fitted
2
J1, J3
Header, 100mil, 2x1, Tin, TH
Sullins Connector Solutions
PEC02SAAN
CONN_PEC02SAAN
Fitted
1
J2
Power Jack, mini, 2.1mm OD, R/A, TH
Switchcraft
RAPC722X
CONN_RAPC722X
Fitted
2
J4, J5
Modular Jack(Shielded), Gold, R/A,
TH
Molex
43202-8916
Molex_43202-8916
Fitted
1
J6
Conncetor, micro SD Card, 1.1 mm,
R/A, SMT
Molex
502774-0891
Molex_502774-0891
Fitted
1
J7
Receptacle, 0.65 mm, 5x1, Gold, R/A,
SMT
FCI
10104111-0001LF
FCI_10104111-0001LF
Fitted
1
L1
Inductor, Shielded Drum Core, Ferrite,
1 µH, 1.5 A, 0.085 ohm, SMD
Coilcraft
LPS3010-102MRB
LPS3010
Fitted
1
L2
Inductor, Shielded Drum Core, Ferrite,
15 µH, 3.5 A, 0.03 ohm, SMD
Coilcraft
MSS1260-153MLB
MSS1260
Fitted
3
L3, L4, L5
Inductor, Shielded, Ferrite, 2.2 µH,
2.62 A, 0.043 ohm, SMD
TDK
VLCF5020T-2R2N2R6-3
VLCF5020
Fitted
6
L6, L7, L9, L10, L11,
L12
Ferrite Bead, 150 ohm @ 100 MHz,
0.8 A, 0805
Laird-Signal Integrity
Products
LI0805H151R-10
0805_HV
Fitted
CAP, CERM, 0.1 µF, 10 V, +/- 10%,
X5R, 0201
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
Table 34. BOM (continued)
QTY
REFERENCE
PART DESCRIPTION
MANUFACTURER
MANUFACTURER
PARTNUMBER
PCB FOOTPRINT
NOTE
1
L8
Common Mode Filter, 90 Ohm, 6
GHz, SMD
TDK
ACM2012H-900-2P-T00
TDK_ACM2012H-900-2P-T00
Fitted
1
R1
RES, 10 ohm, 5%, 0.25W, 0603
Vishay-Dale
CRCW060310R0JNEAHP
0603
Fitted
1
R2
RES, 453 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402453KFKED
0402
Fitted
1
R3
RES, 750, 5%, 0.063 W, 0402
Vishay-Dale
CRCW0402750RJNED
0402
Fitted
2
R4, R119
RES, 100 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402100KFKED
0402
Fitted
1
R5
RES, 80.6 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040280K6FKED
0402
Fitted
3
R6, R36, R65
RES, 1.00 M, 1%, 0.063 W, 0402
Vishay-Dale
CRCW04021M00FKED
0402
Fitted
1
R7
RES, 249 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402249KFKED
0402
Fitted
14
R8, R9, R10, R12, R15,
R71, R139, R140, R141,
RES, 0, 5%, 0.1 W, 0603
R142, R143, R144,
R145, R147
Vishay-Dale
CRCW06030000Z0EA
0603
Fitted
1
R13
RES, 360, 5%, 0.063 W, 0402
Vishay-Dale
CRCW0402360RJNED
0402
Fitted
1
R14
RES, 150 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402150KFKED
0402
Fitted
1
R16
RES, 110 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW0402110KFKED
0402
Fitted
7
R19, R43, R44, R46,
R47, R50, R51
RES, 0, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04020000Z0ED
0402
Fitted
1
R20
RES, 0, 5%, 0.0625 W, Resistor Array
- 8x1
Panasonic
EXB-2HVR000V
RESCAXS_EXB-2HV
Fitted
8
R21, R38, R41, R67,
R68, R136, R138, R158
RES, 10.0 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040210K0FKED
0402
Fitted
8
R22, R24, R32, R37,
R42, R48, R58, R64
RES, 75.0, 1%, 0.1 W, 0603
Vishay-Dale
CRCW060375R0FKEA
0603
Fitted
8
R23, R29, R45, R55,
R146, R152, R153,
R165
RES, 4.7 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04024K70JNED
0402
Fitted
9
R25, R26, R27, R33,
R52, R53, R54, R60,
R66
RES, 560, 5%, 0.063 W, 0402
Vishay-Dale
CRCW0402560RJNED
0402
Fitted
5
R28, R30, R49, R56,
R59
RES, 11.0 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040211K0FKED
0402
Fitted
5
R31, R34, R57, R61,
R62
RES, 2.49 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW04022K49FKED
0402
Fitted
1
R69
RES, 22, 5%, 0.0625 W, Resistor
Array - 8x1
Panasonic
EXB-2HV220JV
RESCAXS_EXB-2HV
Fitted
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
79
Design Files
www.ti.com
Table 34. BOM (continued)
MANUFACTURER
MANUFACTURER
PARTNUMBER
PCB FOOTPRINT
NOTE
17
R70, R84, R94, R95,
R96, R120, R121, R122,
R123, R124, R125,
RES, 10 k, 5%, 0.063 W, 0402
R131, R135, R137,
R148, R149, R150
Vishay-Dale
CRCW040210K0JNED
0402
Fitted
10
R72, R73, R74, R75,
R77, R78, R79, R80,
R81, R82
Vishay-Dale
CRCW040222R0JNED
0402
Fitted
5
R76, R117, R118, R154,
RES, 2.2 k, 5%, 0.063 W, 0402
R156
Vishay-Dale
CRCW04022K20JNED
0402
Fitted
3
R99, R126, R127
RES, 49.9, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040249R9FKED
0402
Fitted
2
R100, R129
RES, 1.00 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW04021K00FKED
0402
Fitted
12
R101,
R105,
R108,
R111,
RES, 100 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW0402100KJNED
0402
Fitted
3
R128, R130, R133
RES, 47, 5%, 0.0625 W, Resistor
Array - 8x1
Panasonic
EXB-2HV470JV
RESCAXS_EXB-2HV
Fitted
1
R132
RES, 240, 5%, 0.063 W, 0402
Vishay-Dale
CRCW0402240RJNED
0402
Fitted
1
R134
RES, 47, 5%, 0.063 W, 0402
Vishay-Dale
CRCW040247R0JNED
0402
Fitted
1
R155
RES, 4.75 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW04024K75FKED
0402
Fitted
1
R157
RES, 12.1 k, 1%, 0.063 W, 0402
Vishay-Dale
CRCW040212K1FKED
0402
Fitted
1
S1
SWITCH TACTILE SPST-NO 0.05A
12V
Omron Electronic
Components
B3U-1000P
SW_B3U-1000P
Fitted
2
T1, T2
Transformer, 325 uH, SMT
Pulse Engineering
HX5008FNL
PULSE_HX5008FNL
Fitted
U1
3.5V to 60V 2A Synchronous StepDown Voltage Regulator, PWP0016A
Texas Instruments
LM46002PWP
PWP0016A_N
Fitted
1
U2
Single Output LDO, 1 A, Fixed 3.3 V
Output, 2.2 to 5.5 V Input, with
Reverse Current Protection, 6-pin
SOT-223 (DCQ), -40 to 125 degC,
Green (RoHS & no Sb/Br)
Texas Instruments
TPS73733DCQ
DCQ0006A_N
Fitted
1
U3
1A SIMPLE SWITCHER® Nano
Module with 5.5V Maximum Input
Voltage, SIL0008A
Texas Instruments
LMZ10501SIL
SIL0008A
Fitted
1
U5
350mA, Ultra-Low VIN, RF LowDropout Linear Regulator with Bias
Pin, DRV0006A
Texas Instruments
TPS72011DRV
DRV0006A
Fitted
QTY
1
80
REFERENCE
R103,
R106,
R109,
R115,
R104,
R107,
R110,
R116
PART DESCRIPTION
RES, 22, 5%, 0.063 W, 0402
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
Table 34. BOM (continued)
QTY
REFERENCE
PART DESCRIPTION
MANUFACTURER
MANUFACTURER
PARTNUMBER
PCB FOOTPRINT
NOTE
U6, U12
Robust, Low Power 10/100/1000
Ethernet Physical Layer Transceiver,
PAP0064M
Texas Instruments
DP83867IRPAPR
PAP0064M_N
Fitted
2
U7, U9
1, 4, 6 CHANNEL PROTECTION
SOLUTION FOR SUPER-SPEED (UP
TO 6 GBPS) INTERFACE,
DQA0010A
Texas Instruments
TPD4E05U06DQA
DQA0010A
Fitted
1
U11
Single 2-Input Positive-AND Gate,
DCK0005A
Texas Instruments
SN74AHC1G08DCK
DCK0005A_N
Fitted
1
U13
Integrated Power-Management Unit
Top Specification, RSL0048A
Texas Instruments
TPS65910A3A1RSL
RSL0048A
Fitted
1
U14
Single Output High PSRR LDO, 150
mA, Fixed 1.8 V Output, 2.5 to 6.5 V
Input, with Low IQ, 6-pin WSON
(DSE), -40 to 125 degC, Green (RoHS
& no Sb/Br)
Texas Instruments
TPS71718DSER
DSE0006A
Fitted
1
U15
Sitara Processors, ZCZ0324A
Texas Instruments
AM3359BZCZA80
ZCZ0324A
Fitted
1
U16
LOW-POWER DUAL 2-INPUT
POSITIVE-AND GATE, DCU0008A
Texas Instruments
SN74AUP2G08DCU
DCU0008A_N
Fitted
1
U17
2GBIT DDR3 SDRAM, 96-FBGA
Micron Technology
MT41J128M16JT-125K TR
96-FBGA
Fitted
1
U18
Low-Capacitance + / - 15 kV ESD
Protection Array for High-Speed Data
Interfaces, 6 Channels, -40 to +85
degC, 10-pin UQFN (RSE), Green
(RoHS & no Sb/Br)
Texas Instruments
TPD6E001RSER
RSE0010A
Fitted
1
U19
256 kb I2C CMOS Serial EEPROM,
SOIC-8
ON Semiconductor
CAT24C256WI-GT3
SOIC-8
Fitted
1
U20
Single Output LDO, 3 A, 2.375 to 3.5
V Input, with DDR Termination, 10-pin
SON (DRC), -40 to 85 degC, Green
(RoHS & no Sb/Br)
Texas Instruments
TPS51200DRCR
DRC0010A
Fitted
1
U21
USB ESD Solution with Power Clamp,
4 Channels, -40 to +85 degC, 6-pin
SON (DRY), Green (RoHS & no
Sb/Br)
Texas Instruments
TPD4S012DRYR
DRY0006A
Fitted
1
U22
Dual High Speed USB To
Multipurpose UART/FIFO IC, LQFP64
FTDI
FT2232HL-REEL
LQFP64_N
Fitted
1
U23
2K Microwire Compatible Serial
EEPROM, SOT-23-6
Microchip
93LC56B-I/OT
SOT-23-6
Fitted
1
U24
Single Inverter Buffer/Driver With
Open-Drain Output, DCK0005A
Texas Instruments
SN74LVC1G06DCK
DCK0005A_N
Fitted
2
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
81
Design Files
www.ti.com
Table 34. BOM (continued)
QTY
PART DESCRIPTION
MANUFACTURER
MANUFACTURER
PARTNUMBER
PCB FOOTPRINT
NOTE
2
Y1, Y2
Crystal, 25 MHz, 18 pF, SMD
Abracon Corportation
ABM3-25.000MHZ-D2Y-T
XTAL_ABM3
Fitted
1
Y3
Crystal, 24 MHz, 18 pF, SMD
Abracon Corportation
ABM3-24.000MHZ-D2Y-T
XTAL_ABM3
Fitted
1
Y4
Crystal, 32.768kHz, 12.5pF, SMD
Epson
MC-306 32.7680K-A0:ROHS
XTAL_MC-306
Fitted
1
Y5
Crystal, 12 MHz, 18 pF, SMD
Abracon Corportation
ABM3-12.000MHZ-D2Y-T
XTAL_ABM3
Fitted
0
C12
CAP, CERM, 0.022 µF, 50 V, +/- 10%,
X7R, 0402
MuRata
GRM155R71H223KA12D
0402
Not Fitted
0
C19, C20
CAP, CERM, 1 µF, 10 V, +/- 10%,
X7R, 0603
MuRata
GRM188R71A105KA61D
0603
Not Fitted
0
C34, C62
CAP, CERM, 1000 pF, 2000 V, +/10%, X7R, 1812
AVX
1812GC102KA1
1812
Not Fitted
0
C238
CAP, CERM, 0.01 µF, 10 V, +/- 10%,
X7R, 0201
MuRata
GRM033R71A103KA01D
0201
Not Fitted
0
C242
CAP, CERM, 0.1 µF, 10 V, +/- 10%,
X7R, 0402
MuRata
GRM155R71A104KA01D
0402
Not Fitted
0
J8
CONN SHRD HDR HDR 20 POS
1.27MM SLDR ST SMD
Samtec
TFM-110-02-S-D-A-K-TR
Samtec_TFM-110-02-S-D-A-K
Not Fitted
0
R11, R159, R160, R161,
RES, 0, 5%, 0.1 W, 0603
R162, R163, R164
Vishay-Dale
CRCW06030000Z0EA
0603
Not Fitted
0
R17, R18, R39, R40,
R63
RES, 0, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04020000Z0ED
0402
Not Fitted
0
R35
RES, 22, 5%, 0.063 W, 0402
Vishay-Dale
CRCW040222R0JNED
0402
Not Fitted
0
R83, R85, R86, R87,
R88, R89, R90, R91,
R92, R93, R97, R98
RES, 10 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW040210K0JNED
0402
Not Fitted
0
R102, R112, R113,
R114
RES, 100 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW0402100KJNED
0402
Not Fitted
0
R151
RES, 4.7 k, 5%, 0.063 W, 0402
Vishay-Dale
CRCW04024K70JNED
0402
Not Fitted
U4
Single Output LDO, 300 mA, Fixed 1.8
V Output, 2 to 5.5 V Input, with Low
IQ, 5-pin SOT-23 (DBV), -40 to 125
degC, Green (RoHS & no Sb/Br)
Texas Instruments
TLV70218DBVR
DBV0005A_N
Not Fitted
U8, U10
1, 4, 6 CHANNEL PROTECTION
SOLUTION FOR SUPER-SPEED (UP
TO 6 GBPS) INTERFACE,
DQA0010A
Texas Instruments
TPD4E05U06DQA
DQA0010A
Not Fitted
0
0
82
REFERENCE
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
8.3
Layer Plots
To download the layer plots, see the design files at TIDA-00204.
Figure 77. Top Overlay
Figure 78. Top Solder Mask
Figure 79. Top Layer
Figure 80. Mid Layer 1
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
83
Design Files
84
www.ti.com
Figure 81. Mid Layer 2
Figure 82. Mid Layer 3
Figure 83. Mid Layer 4
Figure 84. Mid Layer 5
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
Figure 85. Mid Layer 6
Figure 86. Bottom Layer
Figure 87. Bottom Solder Mask
Figure 88. Bottom Overlay
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
85
Design Files
www.ti.com
Figure 89. Drill Drawing
8.4
8.4.1
Figure 90. Board Dimensions
PCB Layout Guidelines
Layer Stack
Ensure that the differential signal layers have a reference ground and that the PCB differential signal
traces are matched to 100-Ω impedance. For the single-ended traces, the board is matched to 50 Ω.
A layer size of 0.018 mm was chosen for the top and mid layers. This size can be defined as the base
thickness. When actually building the board, the mid layers will decrease in size and the outer layers will
increase in size. This means that the expected top layer thickness would be 0.040 mm and a mid layer
would have an expected thickness of 0.012 mm. This decrease and increase in thickness varies on the
manufacturer. This variation is why it is very important when working with high-speed differential signals to
define the layer stack and double check with the PCB manufacturer to ensure that the expected
impedances are achieved.
Figure 91. Layer Stack
For a less complex processor design, the PCB layers for DP83867IR routing can be reduced to four
layers. See the DP83867IR datasheet for examples [1].
86
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
8.4.2
Layout RGMII Signals
Looking at the layout, each RX or TX group of the RGMII signals are routed on the same layer with
matched trace length as outlined in Section 4. To aim for routing, the signals minimized the trace length of
both RGMII1 and RGMII2 interfaces.
A second important point is that when changing layers, a GND via is added next to the signal via to
ensure a good matching as well offer a current return path close to the signal.
The PCB signals are impedance controlled to 50 Ω, and have series line termination. For the series
termination at both the PHYs, 0-Ω resistors were chosen due to the DP83867IR internal 50-Ω impedance.
These resistors were only added for test and debug. For the AM3359, 22-Ω series termination resistors
were chosen.
Termination for RGMII RX
on top layer
Length matching for RGMII
RX on layer 3
U15
U12
Length matching for RGMII
TX on layer 6
GND via to ensure GND
matching when changing
layers on signals
Termination for RGMII TX
on top layer
Figure 92. Layout Guidelines for RGMII Signals
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
87
Design Files
8.4.3
www.ti.com
Layout for the Differential Gigabit Ethernet Signals
From the PHY to the magnetics the differential pairs are routed on the top layer with differential
impedance control matching of 100 Ω. The reference GND is on mid layer 1. This is achieved by ensuring
that isolation between top layer and mid layer 1 is smaller than the surrounding planes.
From the magnetics to the RJ45 the differential pairs A, C, and D are routed on the top layer while pair B
is routed on mid layer 2. This is due to crossing the signals on the RJ45 Ethernet jack. Again, the
differential pairs are impedance matched to 100 Ω with reference to GND on mid layer 1. Due to the GND
being mid layer 1, there is no need for GND vias added around the B signal.
This routing achieves the minimum possible trace lengths from PHY to magnetics, magnetics to RJ45, and
here a maximum delta of the trace lengths of 1 mm between the differential pairs.
TI TVS diode array
TPD4E05U06 with easy
routing pinout
Differential length matching
and routing for signals from
transformer to RJ45
J4
U6
T1
Differential length matching
and routing for signals from
PHY to transformer
Clearance between signal lines
and GND and Earth/Shield
To ensure shortest routing of
the signals a layer change was
done due to pinout of RJ45
Figure 93. Layout Guidelines for PHY Differential Signals
88
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
8.4.4
Layout PHY Power Supply
For the 2.5-V LMZ rail, add a keep-out GND cut in mid layer 1 to decrease noise coupling. To additional
thermal management, add as many vias as possible on the powerPAD of the 1.1-V and 1.8-V LDO and
add an additional thermal release plane on the bottom side of the board.
Ensure wide enough traces when adding the 1.1-V and 2.5-V power rails. The 1.1-V rail is added as a
solid supply plane below each PHY. Figure 94 shows the PCB layout of TIDA-00204.
GND cut ring in mid
layer 1 around the LDOs
to further reduce noise
coupling
GND cut in mid layer 1
around the LMZ10501
device to reduce noise
coupling
Added additional vias to
insure the best possible
thermal release of LDO
GND guard ring in mid
layer 1 around the
crystals to further reduce
noise coupling
Ensure wide traces that
provide the 1v1 and 2v5
power rail
U6
T1
1v1 power rail of the PHY
added as a solid supply plane
below each PHY
Figure 94. Layout Guidelines for the PHY Power Supply
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
89
Design Files
8.4.5
www.ti.com
Layout of the 24-V to 5-V DC/DC Buck (LM46002)
Follow the layout guidelines from the LM46002 datasheet. Cut out layer 1 under LM46002 to avoid
coupling into other layers. Ensure that current loop of the device is maintained as small as possible. The
example layout of the LM46002 on TIDA-00204 is shown in Figure 95.
Noise sensitive signals removed
from noisy ground plane
Current loop as small as possible
GND cut in mid layer
1 around the
LM46002 device to
reduce noise coupling
U1
Vias around the GND
cut to reduce noise
coupling
J1
Figure 95. Layout Guidelines for 24-V to 5-V DC/DC Buck With LM46002
8.4.6
Layout Sitara Power Supply
For the Sitara power supply, the following guidelines were considered.
Routing the power tracks to the Sitara each power track as a GND plane as reference GND, mid layer 4
used as supply layer with supply planes for each high current power track. VMMC, VAUX33, and VAUX1
power track added in mid layer 2 and VDIG2 and VPLL power track added in mid layer 6.
VDAC intentionally does a u-trace as the DAC functionality is not used. If this functionality is needed, add
additional traces for this power rail.
8.4.7
Layout DDR3
Layer 6 is GND reference for DDR3 (90-µm dielectric distance layer to layer). The other layers are 400 µm
away. All DDR3 signals are on one layer.
90
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Design Files
www.ti.com
8.5
Altium Project
To download the Altium project files, see the design files at TIDA-00204.
8.6
Gerber Files
To download the Gerber files, see the design files at TIDA-00204.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
91
Software Files
9
www.ti.com
Software Files
To download the software files, see the design files at TIDA-00204.
10
References
1. Texas Instruments, DP83867IR Robust, Low Power 10/100/1000 Ethernet Physical Layer Transceiver,
DP83867 Datasheet (SNLS484).
2. Texas Instruments, AN-1469 PHYTER Design & Layout Guide, Application Report (SNLA079).
3. Texas Instruments, EN55011-Compliant, Industrial Temperature 10/100-Mbps Ethernet PHY Brick, TI
Design (TIDU515).
4. Texas Instruments, PCB Design Guidelines For Reduced EMI, Application Report (SZZA009).
5. Texas Instruments, AM335x Sitara™ Processors, AM335x Datasheet (SPRS717).
6. Texas Instruments, AM335x Sitara™ Processors, AM335x Technical Reference Manual (SPRUH73).
7. Texas Instruments, TPS65910Ax User's Guide For AM335x Processors, TPS65910Ax User’s Guide
(SWCU093).
8. Texas Instruments, TI Network Developer's Kit (NDK) v2.24, NDK User’s Guide (SPRU523).
9. Texas Instruments, Sitara Wiki Page (http://processors.wiki.ti.com/index.php/Sitara).
10. Texas Instruments, AM3359 Industrial Communications Engine, Evaluation Module, Part #
TMDSICE3359 (http://www.ti.com/tool/tmdsice3359).
11. Texas Instruments, LM46002 SIMPLE SWITCHER® 3.5 V to 60 V 2 A Synchronous Step-Down
Voltage Converter, LM46002 Datasheet (SNVSA13).
12. IEEE, 802.3-2012 – IEEE Standard for Ethernet, Section Three (http://standards.ieee.org).
13. HP, Reduced Gigabit Media Independent Interface (RGMII) 4/1/2002 Version 2.0: Reduced Pin-count
Interface for Gigabit Ethernet Physical Layer Devices
(http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf).
14. Dirk S. Mohl, IEEE 1588 Precision Time Protocol (http://www.ieee1588.com).
15. CISPR11 / EN 55011+A1:2010-01-31, EN 55011: Industrial, scientific and medical equipment - Radiofrequency disturbance characteristics - Limits and methods of measurement.
16. IEC, Adjustable speed electrical power drive systems - Part 3: EMC requirements and specific test
methods, IEC 61800-3 ed2.0: 2004-08-12.
17. IEC, Amendment 1 - Adjustable speed electrical power drive systems - Part 3: EMC requirements and
specific test methods, IEC 61800-3-am1 ed2.0: 2011-11-14.
18. Micron, TN-41-08: Design Guide for Two DDR3-1066 UDIMM Systems.
19. Wireshark, v1.12.3 (http://www.wireshark.org).
20. TeraTerm, v4.76 (http://ttssh2.sourceforge.jp/).
21. GCD-Printlayout GmbH (http://www.gcd-printlayout.de/).
22. MinGW, Minimalist GNU for Windows (http://www.mingw.org/).
23. SourceForge, Win32 Disk Imager (http://sourceforge.net/projects/win32diskimager/).
11
About the Authors
KRISTEN MOGENSEN is a system engineer in the Industrial Systems Motor Drive team at Texas
Instruments. Mogensen is responsible for developing reference designs for industrial drives.
MARTIN STAEBLER is a system engineer in the Industrial Systems Motor Drive team at Texas
Instruments. Staebler is responsible for developing reference designs for industrial drives.
92
EMI/EMC-Compliant Industrial Temp Dual-Port Gigabit Ethernet Reference
Design
Copyright © 2015, Texas Instruments Incorporated
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Revision History
www.ti.com
Revision History
Changes from Original (March 2015) to A Revision ....................................................................................................... Page
•
Changed from preview page ............................................................................................................. 1
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
TIDU832A – March 2015 – Revised April 2015
Submit Documentation Feedback
Revision History
Copyright © 2015, Texas Instruments Incorporated
93
IMPORTANT NOTICE FOR TI REFERENCE DESIGNS
Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“Buyers”) who are developing systems that
incorporate TI semiconductor products (also referred to herein as “components”). Buyer understands and agrees that Buyer remains
responsible for using its independent analysis, evaluation and judgment in designing Buyer’s systems and products.
TI reference designs have been created using standard laboratory conditions and engineering practices. TI has not conducted any
testing other than that specifically described in the published documentation for a particular reference design. TI may make
corrections, enhancements, improvements and other changes to its reference designs.
Buyers are authorized to use TI reference designs with the TI component(s) identified in each particular reference design and to modify the
reference design in the development of their end products. HOWEVER, NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL
OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY THIRD PARTY TECHNOLOGY
OR INTELLECTUAL PROPERTY RIGHT, IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right,
or other intellectual property right relating to any combination, machine, or process in which TI components or services are used.
Information published by TI regarding third-party products or services does not constitute a license to use such products or services, or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
TI REFERENCE DESIGNS ARE PROVIDED "AS IS". TI MAKES NO WARRANTIES OR REPRESENTATIONS WITH REGARD TO THE
REFERENCE DESIGNS OR USE OF THE REFERENCE DESIGNS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING ACCURACY OR
COMPLETENESS. TI DISCLAIMS ANY WARRANTY OF TITLE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT, QUIET POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY
INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO TI REFERENCE DESIGNS OR USE THEREOF. TI SHALL NOT BE LIABLE
FOR AND SHALL NOT DEFEND OR INDEMNIFY BUYERS AGAINST ANY THIRD PARTY INFRINGEMENT CLAIM THAT RELATES TO
OR IS BASED ON A COMBINATION OF COMPONENTS PROVIDED IN A TI REFERENCE DESIGN. IN NO EVENT SHALL TI BE
LIABLE FOR ANY ACTUAL, SPECIAL, INCIDENTAL, CONSEQUENTIAL OR INDIRECT DAMAGES, HOWEVER CAUSED, ON ANY
THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, ARISING IN
ANY WAY OUT OF TI REFERENCE DESIGNS OR BUYER’S USE OF TI REFERENCE DESIGNS.
TI reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per
JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant
information before placing orders and should verify that such information is current and complete. All semiconductor products are sold
subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques for TI components are used to the extent TI
deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not
necessarily performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
Reproduction of significant portions of TI information in TI data books, data sheets or reference designs is permissible only if reproduction is
without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for
such altered documentation. Information of third parties may be subject to additional restrictions.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards that
anticipate dangerous failures, monitor failures and their consequences, lessen the likelihood of dangerous failures and take appropriate
remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in
Buyer’s safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed an agreement specifically governing such use.
Only those TI components that TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components that
have not been so designated is solely at Buyer's risk, and Buyer is solely responsible for compliance with all legal and regulatory
requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated