ProspectusforaMini‐Consortiumon
HighDensityIntegration(HDI)
Fred C. Lee
Dushan Boroyevich
Qiang Li
Guo-Quan Lu
Paolo Mattavelli
Khai Ngo
Center for Power Electronics Systems
Bradley Department of Electrical and Computer Engineering
College of Engineering
Virginia Tech
Blacksburg, VA
January, 2013
Mini‐Consortium:
High‐DensityIntegration
Introduction
Over the past two decades, CPES has secured research funding from major industries, such as GE, Rolls‐Royce, Boeing, Alstom, ABB, Toyota, Nissan, Raytheon, and MKS, as well as from government agencies including the NSF, DOE, DARPA, ONR, U.S. Army, and the U.S. Air Force, in research pursuing high‐density system design. CPES has developed unique high‐density and high‐temperature packaging technologies applicable to such products as point‐of‐load converters, RF amplifiers, and wireless chargers. In the HDI mini‐consortium, the goal of high power density will be pursued following two coupled paths, both leveraging the availability of wide‐band‐gap power semiconductor, as well as high‐temperature passive components and ancillary functions. The switching frequency will be pushed as high as component technologies, thermal management, and reliability permit. At the same time, the maximum component temperatures will be pushed as high as component technologies, thermal management, and reliability permit. The emergence of wide‐bandgap semiconductors such as Silicon Carbide (SiC) and Gallium Nitride (GaN) makes it possible to realize power switches that operate at frequency beyond 5 MHz and temperature beyond 200°C. As the switching frequency increases, switching noise is shifted to higher frequency and can be filtered with small passive components, leading to improved power density. Higher operating temperatures enable increased power density and applications under harsh environments, such as military systems, transportation systems, and outdoor industrial and utility systems. The HDI mini‐consortium recognizes that the high‐frequency, high‐temperature switches need to be accompanied by high‐frequency or high‐temperature components and packages in the remainder of the power‐electronic system. Thus, HDI has developed die‐attach materials that can be processed at low temperature, yet are reliable at the temperature of the wide‐band‐gap junction. Processes have been developed to encapsulate ultra‐thin planar packages with polymer having high glass‐transition temperature and dielectric strength. Techniques to decouple the noise loops have been identified to enable high‐dV/dt commutation. Magnetic powder with low core loss density has been synthesized from magnetic metals for 1 – 5 MHz operation. Inductors have been integrated into the converter package as a substrate to achieve power density approaching 1 kW/in3. Design methodologies for high‐temperature capacitors, power buses, protection, sensing, digital control, etc. have also been documented. Companies interested in joining the HDI mini‐consortium would be Principal Plus Members in the CPES Industry Consortium. These members pool resources and work jointly and synergistically with CPES researchers. Pre‐competitive technologies developed under this effort are shared among mini‐consortium members. 1 The HDI mini‐consortium operates according to the following guidelines: 
Annual Principal Plus Member contribution of $50K; 
Number of students involved would be proportional to the number of mini‐consortium members; 
Scope of work would fall within the topics outlined below, to be discussed and modified during regular progress reviews; 
Progress reviews are conducted three or four times per year, with at least one face‐to‐
face meeting held in conjunction with CPES annual conference or other IEEE conferences, while others would be conducted via WebEx; 
As Principal Plus Members, mini‐consortium members have automatic membership in CPES Intellectual Property Protection Fund (IPPF). IPPF is a unique IP access mechanism designed to provide all Principal‐level members with extraordinary IP advantage automatically, at no additional cost. Principal‐level members are invited to participate in quarterly IPPF telecons with CPES inventors to discuss invention disclosures and jointly decide which technologies to protect, with patenting costs covered by IPPF. Once a technology is protected, all Principal‐level members are granted a royalty‐free, non‐exclusive, non‐transferable license to use the technology disclosed during their membership years. The scope of work currently conducted includes the following topics: Integration technologies ‐ Die‐attachment on copper surface by sintering of nano‐scale silver paste ‐ High‐temperature encapsulants for power electronic modules – thermal stability of nano‐composites ‐ Magnetic materials for high‐frequency conversion and EMI containment Components ‐
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Characterization and modeling of wide‐bandgap semiconductor devices Low‐profile magnetic substrate Magnetic structures with high energy density Module‐level integration ‐ High‐speed and high‐temperature SiC power module for high‐frequency motor drive systems ‐ High‐temperature performance and reliability of planar power modules with double‐
sided cooling capability and sintered joints ‐ Integrated‐passives module for resonant conversion and EMI containment System‐level integration ‐ High‐frequency converter packaging ‐ EMI and emission containment ‐ High‐temperature converter packaging 2 HDIMini‐Consortium‐ScopeofWork
1. High‐TemperatureIntegrationTechnologies
Fundamental issues at the materials, structure, and process levels need to be addressed if high‐
temperature packages are to be reliable. The mini‐consortium will address the following issues at the fundamental level: Substrates: Investigation of the impact of structural shaping, encapsulating, metal alloying, re‐
surfacing, dimensional optimization, etc. on failure modes induced by thermal or power cycling. Die‐Attach Materials: Investigation of the impact of paste formulation, sintering profile, dimensions, shapes, etc. on die‐shear strength, residual stress, or thermal impedance; investigate mechanisms to relieve stress at the interface between substrate and bond line (see Figure 1(a)) induced by thermal or power cycling. Figure 1. (a) Sintered bond line after 500 cycles (‐55 °C → 250 °C) showing vertical cracks to reduce stress owing to aluminum deformation; (b) a high‐temperature encapsulant makes possible a high‐temperature, high‐voltage power module; (c) setup to measure creep displacement with 100 nm resolution Encapsulants: Investigation of flowability, curability, and processability versus package structures and materials; formulation of void‐free material systems and processes for surface passivation and bulk encapsulation versus package structure (see Figure 1(b)); characterization of mechanical, thermal, and electrical properties of encapsulants and encapsulated packages versus temperature excursions; investigation of the impact of encapsulation on thermo‐
mechanical stress and reliability. Structures and Processes: Development of processes for 3D integration of multiple dice with a minimal number of masks and steps; investigation of thermo‐mechanical stress and reliability for high‐speed packages with integrated EMI and thermal management. Infrastructure: Establishment of hardware capability for sintering of silver paste, measuring mechanical properties (see Figure 1(c)), thermal cycling, power cycling, shearing of large joints, virtual cross‐sectioning (e.g., 3D X‐ray); development of software for material characterization and computer models for simulation of packages; training and sustaining a critical mass of multi‐disciplinary students skilled at packaging. 3 1.1 Die‐AttachmentonCopperSurfacebySinteringofNanosilverPaste
Wide‐bandgap power semiconductors are targeting higher operation temperature (e.g. 200 °C) in order to achieve higher power density. Traditional die‐attach technologies cannot meet such high‐temperature requirement. Low‐Temperature‐Joining‐Technique (LTJT), which is based on sintering of silver particles, is a promising die‐attach technique for high‐temperature applications. Nanosilver was utilized for the die‐attachment to avoid high‐range (> 30 MPa) sintering pressure that traditional LTJT required. One limit of applying nanosilver paste for die‐attachment is that the attaching surface of both the die and the substrate needs to be metallized with silver or gold. Directly sintering nanosilver paste onto copper surface and getting good adhesion will be an essential step to lower the cost for the die‐attachment and broaden the application scope of nanosilver paste. The basic challenge for this research is the copper oxidation problem during the sintering process (sintering temperature is about 250 °C). Copper oxide layer will prevent the bonding formation between copper and silver, which leads to a weak bonding. However, there are some organics inside the nanosilver paste preventing the agglomeration of nanoparticles below sintering temperature, which need to be totally burned out during sintering process. The combustion of binder needs the presence of oxygen. The goal of the research is to overcome the contradiction of the presence of oxygen, and achieve robust bonding among copper surface, sintered silver and die. Tasks for the research: (1) Process development  Large‐area chip size (> 3×3 mm2): Apply low range pressure during the sintering of nanosilver paste.  Small‐area chip size (< 3×3 mm2): Change sintering atmospheres. (2) Reliability test  Temperature cycling test: Sintered joints (die ‐ sintered Ag ‐ copper) can be subjected to temperature cycles using a thermal chamber, to check its resistance to thermal fatigue.  Power cycling test: Gate‐emitter voltage of IGBT can be chose as temperature sensitive parameter, which can be used to compare the transient thermal impedance (Zth) of samples made with different die‐attach materials, as well as after power cycling them. Figure 2. Die‐attachment on copper surface by sintering of nanosilver paste 4 1.2 High‐TemperatureEncapsulantsforPowerElectronicModules–Thermal
StabilityofNano‐Composites
There has been a trend of using wide‐bandgap devices to broaden the range of operation temperature of power modules. To achieve high‐temperature and high‐density packaging, encapsulation is an issue that needs to be re‐considered. Polymeric encapsulants are widely used in electronic packaging industries to protect chips and interconnections from mechanical, chemical, and electrical damages. At high temperature, however, encapsulants suffer from fast chemical decomposition, which embrittles and cracks the polymers, as shown in Figure 3(a). Correspondingly, cracking results in a significant reduction in the dielectric strength, as shown in Figure 3(b). Therefore, to achieve high operation temperatures, the thermal stability of the polymeric encapsulants much be improved.
Figure 3(a). Cracks in Nusil EPM2422 after aging at 250 °C for 14 days Figure 4(b). Dielectric strength of three commercial encapsulants with respect to thermal aging (250 °C) time Therefore, the goals of this research are to, (1) Investigate the mechanism of thermal‐
assisted degradation of common polymeric encapsulants, and (2) modify current materials to improve their thermal stability and long‐term reliability. Improved thermal stability is expected to retard the embrittlement process occurred in the polymer matrix during high‐temperature operation. When the materials’ elasticity is maintained, delay in the cracking process is expected. Therefore, the properties (dielectric, chemical, etc.) of the encapsulants can be retained for a longer time, meaning an improved reliability. The technical challenge towards this target mainly involves understanding the degradation mechanism and finding an appropriate method to improve the thermal stability. Many researches have reported that polymers degrade through a thermal‐
assisted chain‐scission process. It has also been reported that fillers may retard the thermal degradation by restraining the chain mobility. However, appropriate fillers and mixing method must be employed. In this research, composites of silicone elastomer and several types of inorganic fillers will be fabricated. Their thermal stability will be investigated by an isothermal soaking (250 °C) test. The dielectric properties of the composites will also be monitored with respect to aging time. 5 2. Components
2.1 CharacterizationandModelingofWide‐BandgapSemiconductorDevices
CPES has been characterizing and modeling SiC power semiconductor devices in support of the development of medium‐to‐high power converters switched at hundreds of kHz to reduce the size of passive filters and to boost system power density. In previous work, SiC devices were shown to have better performance than those of conventional Si semiconductors in high‐power applications. Namely, SiC devices have proven to experience lower on‐resistances and faster switching speeds. Further, SiC devices have high‐temperature reliability, which Si lacks. This improved performance has led to the commercialization of various SiC power semiconductor devices, such as the normally‐on and normally‐off JFET, MOSFET and BJT. With the emergence of these new SiC devices, the question of how the performances of each compare to one another arises. Consequently, research is being performed to characterize and compare numerous SiC power semiconductors. More specifically, the static and dynamic characteristics, as well as driving requirements, of seven 1.2 kV SiC power semiconductor devices will be analyzed at temperatures from 25 °C to 200 °C. The studied devices are: three different 1.2 kV SiC MOSFETs, two different 1.2 kV SiC BJTs, a 1.2 kV normally‐off SiC JFET, and a 1.2 kV SiC SJT. For the static performance comparison, the specific on‐resistance of each device will be analyzed. The on‐resistance of each semiconductor will be measured up to 200 °C by a curve tracer, and then specific on‐resistance, in units of mΩcm2, will be calculated using die area. This is done to allow for a fair and valuable comparison among the various devices since resistance and size are directly related (i.e. a larger die area results in a lower resistance). The means of comparison for the dynamic performance of each device is switching energy loss density in units of μJ/cm2. A double‐pulse test (DPT) will be performed on each device up to 200 °C, from which the switching loss will be computed. Dividing this computed loss by the die area yields the switching energy loss density. Figure 4 shows the high‐temperature DPT setup used for measuring switching loss. Figure 4. High‐temperature DPT setup used to measure the device switching energy. A hotplate is used to heat the device under test to 200 °C 6 2.2 High‐FrequencyMagneticMaterialsandLow‐ProfileMagneticSubstrate
With low power level, today’s industry can perform integration to achieve very high‐
density and compact DC‐DC converter, but with high power, it is very difficult to integrate the magnetic with a silicon IC by using state‐of‐the‐art technology. Basically, the bulky and high‐profile magnetic is the bottleneck for high‐power integration, in which the magnetic needs to have a certain volume to handle large amounts of energy. In order to increase the power density of high power DC‐DC converter, two things have to happen simultaneously: One is a significant increase in the switching frequency to reduce the size and weight of the magnetics and capacitors, which typically occupy more than two‐thirds of the volume of converter. The second is to integrate passive components, especially magnetics, with active components to realize a much more compact structure. It is highly desirable to have magnetic materials operable at a frequency of 3‐5 MHz with power loss below 300 kW/m3, permeability above 100, and saturation field above 40 Oe or operating current at 30 A for a particular coil design. Furthermore, the material should be integrable with standard electronic device fabrication and the thickness can be varied up to 1 mm. Commercial amorphous or nanocrystalline ribbons typically operate below 200 kHz. Fe‐based powder, including Kool Mu, core materials cannot be operated at MHz frequency as shown in Figure 5. At higher frequencies, CoZrO granular films of less than 10 µm thick have the lowest core loss. CoNiFe thin films also have acceptable losses. However, it is not economically viable to grow multilayered materials (ferromagnet / insulator) of mm thickness using vacuum deposition, making these materials unsuitable for proposed power applications. MnZn and NiZn ferrites are currently used for high frequency multi‐MHz applications. However, it is not suitable for integrated application due to its very high sintering temperature. CPES has several years’ effort to explore LTCC for power electronics applications. The Low Temperature Co‐fire Ceramic (LTCC) based integration can have better thermal performance, which is critical for high power application. Secondly, as a thick film technology, it is very easy to use LTCC technology to fabricate a sufficiently thick magnetic core and winding in mm thickness range. In addition, the ferrite based LTCC material has comparable core loss with conventional NiZn ferrite, in multi‐MHz range. Figure 5. Core loss density as a function of frequency 7 CPES proposed the 3‐dimensinal (3D) integration concept, in which the magnetic serves as the substrate carrying the rest of converter circuit. The beauty of this structure is footprint saving and fully utilization of the available space. CPES has successfully demonstrated the 3D integration method using magnetic as a substrate to achieve a very high power density at a high current load (30 A). Figure 6 and Figure 7 show two low profile LTCC inductor designs. It was demonstrated that for an ultra‐low profile inductor design the lateral flux structure was significantly better than that of the vertical flux structure due to its higher inductance density. The inductor size can be dramatically reduced by using inverse coupled inductor structure as shown in Figure 8, because of the DC flux cancellation effect. Based on the novel magnetic structure and high frequency integration, we realized the chip‐scale integrated high current (20 A) POL as well as 2‐
phase coupled inductor with 40 A can have power density as high as 1000 W/in3. Much of that improvement is on the size reduction of the magnetic substrate. We also built a two‐
phase coupled inductor buck VR to demonstrate the scalability for a higher current operation. (a) (b) Figure 6. Low profile inductors. (a) Vertical flux structure, (b) lateral flux structure Figure 7. Footprint comparison between LTCC vertical flux and lateral flux inductors Figure 8. Lateral flux coupled inductor substrate. 40% volume reduction compared with lateral flux non‐coupled inductor 8 Later on, the effort is spent to explore a low temperature and cost‐effective integration technique. By embedding the magnetic core into PCB board, more compact and thinner DC‐DC converter can be achieved compared to the conventional circuit. In addition, the standardized manufacturing process reduces the cost because less manual steps are necessary. The fabrication process needs no high temperature steps. CPES cooperates with NEC/Tokin to develop metallic flake material, which has much higher permeability than that of the conventional flake material. By aligning the small flake pieces, the eddy current loss is also reduced dramatically. More importantly, the core material is very easy to be cut and holed. Figure 9 shows the PCB embedded inductor substrate and the PCB integrated POL module with 20 A output current. The PCB integrated module achieves almost the same power density as the LTCC integrated alternative, while the cost is reduced and the easier to be fabricated. (a) (b) Figure 9. (a) PCB embedded inductor substrate; (b) PCB integrated POL converter 9 3. Module‐LevelIntegration
3.1 High‐SpeedandHigh‐TemperatureSiCPowerModuleforHigh‐Frequency
MotorDriveSystems
There has always been a trend for power electronics converters to go high‐switching‐
frequency, and / or high‐temperature to increase the power density of the whole system. A specific example being dealt with in this project is the development of a high‐frequency motor drive system for the PCB winding permanent magnetic motor, with the output power of 10 kW or so, as shown in Figure 10. The motor itself is designed in a compact fashion, and has very small line inductances of 28 μH for each phase. When using the traditional Si IGBT technology which switches at tens of kHz, additional inductances need to be inserted between the motor and its driver to suppress the current ripple. The converter itself is also very bulky compared to the motor because of all the passive components and the cooling system at low frequency and low temperature. The ultimate goal of this project, therefore, is to totally eliminate the additional inductors by increasing the switching frequency to hundreds of kHz, with the use of commercial SiC MOSFETs. These wide‐bandgap devices have been proved by many researchers to outperform conventional Si IGBTs by providing much smaller conduction and switching losses. The converter itself can also be designed more compact if fully utilizing the high‐
temperature capability of the SiC MOSFET as well. Figure 10. High‐frequency motor drive for PCB winding motor The technical challenges towards this target, however, lie in the packaging and integration of these devices, which is also the main focus of this project. As a penalty of the high‐
speed switching operation, the parasitic inductances from traditional packaging structures (i.e. wire‐bond package) significantly deteriorate the switching waveforms, causing excessive device over‐stress and EMI noise. The physics behind the parasitic ringing thus needs to be explored to find out its basic mechanism, and based on this new packaging structures, such as planar or hybrid structures (See Figure 11), will be explored. In order for the SiC power module to support higher temperature operations, suitable packaging materials and corresponding processing methods will also need to be surveyed and selected. In summary, the development of such a power module will lead to the comprehensive understanding of the device characteristics, packaging structures, materials, and multi‐physics (electrical and thermal) interactions. 10 Figure 11. A hybrid packaging structure developed for reducing parasitic inductances and easing fabrication processes 11 3.2 High‐TemperaturePerformanceandReliabilityofPlanarPowerModules
withDouble‐SideCoolingCapabilityandSinteredNanosilver
Interconnection
Power electronics for use in electrical vehicles need to function reliably at chip junction temperatures over 175 °C. Currently, inverter packages utilize solder and wirebonding for power device attachment. These interconnections have proven unreliable when cycling in this temperature regime. Innovations in both device interconnection and package thermal management are necessary for operation at high temperatures. The use of sintered nanosilver, a low‐temperature joining technology (LTJT), for die interconnection presents a desirable alternative for device interconnection due to its higher electrical and thermal conductivity, proven cycling reliability and low homologous temperature (T/Tmelting). Nanosilver paste attachment profiles are also ideal for implementation of a double‐sided package which will enhance heat dissipation and allow for increased device operation temperatures. The objective of this project is to assess the feasibility of using established nanosilver sintering processes for production of functioning double‐sided packages. The device configuration chosen for packaging is the smallest functional unit of a full inverter circuit or a quarter bridge configuration (Figure 12). The packaging material combinations to be researched will vary to include silicon and silicon carbide power devices on double bond copper (DBC) substrates of alumina and silicon nitride (Si3N4). The primary challenges for fabrication will be mitigation of the large Coefficient of Thermal Expansion (CTE) mismatches for the stacked structure. The largest barrier for characterization in a double sided package is accurate measurement of all appropriate thermal quantities. Characterization of functioning power modules will focus mainly on reliability of the packaging scheme and its operation at temperatures above 175 °C. To evaluate package performance at high temperatures, quarter bridge modules will be operated at device junction temperatures in excess of 200 °C. The packaged device operation and thermal characteristics will be monitored in an effort to determine packaging integrity. Reliability of the package will be evaluated using combinations of power (device self‐heating while loaded) and thermal (changing ambient operating temperature) cycling. We will monitor device and package performance cycling over a temperature range from ‐40 °C to 250 °C with emphasis on mimicking actual application cycling profiles. 12 Figure 12. An increase in power electronics operation temperatures utilizing sintered nanosilver paste and planar packaging will minimize necessary cooling loops in electrical and electrically assisted vehicles, potentially lowering overall weight without sacrificing efficiency or reliability 13 4. System‐LevelIntegration
4.1 High‐DensityPowerSuppliesonaChip
Today’s every processor is powered with a multi‐phase VR developed at CPES. These circuits occupy considerable footprint (about 30%) on the motherboard. The problem is exacerbating with the current trend of reducing the size of all forms of portable computing equipment. Recently, industry leaders such as IBM and Cisco are promoting the idea of replacing these embedded VR solutions with plug‐in “power blocks” to save the motherboard real estate for other critical functions. Thus, power supplies in the form of a chip have been demonstrated at a level of 1 to 5 A. This might address the need of PDA and smart‐phone‐type of applications. It is far from meeting the needs for such applications as netbook, notebook, desktop, and server applications where tens of amperes and hundreds of amperes are needed. In this area of applications, VRs operate from 12 V and deliver high current to the low‐voltage processors. Power supplies on‐a‐
chip should be targeted at 10 to 30 A level. Recently, CPES has successfully demonstrated the 3D integration of power supplies on‐a‐
chip (PSOC) that used ferrite‐based LTCC magnetics as substrate upon which power devices, drivers, and input/output capacitors were mounted. Figure 13 shows the prototype of the 3D PSOC that operates at up to 5 MHz switching frequency with 10 A and 20 A output currents. With this design of using an ultra‐low profile inductor to serve as a substrate with a unique lateral flux design pattern, the power density can reach as high as 800 W/in3 for single phase module. With the flux cancellation of coupled inductor, the power density can reach over 1000 W/in3, a magnitude of improvement over the current VR. (a) (b) Figure 13. (a) 3D integration; (b) single phase & two phase 3D integrated POL converter 14 4.2 BatteryChargerplusEMIFilterforHybridElectricVehicle
This task focuses on increasing the overall power density of the battery charger circuit plus the EMI filter for an automotive application by a factor of 10. A commercial battery charge (plus EMI filter) by Delta‐Q is used as a reference. This circuit is simulated to understand its working and ascertain the conducted EMI emission to establish a benchmark. EMI filter has to reduce 10X in size to meet the final goal and this can be achieved by a number of ways. Conducted EMI mitigation along the propagation path is tried first; this involves modifying the topology itself to act as a filter. By increasing the switching frequency 10 times a 10X decrease in overall converter size is expected. In line with this idea a new Zero Emission and Zero Ripple Boost converter (Figure 14) is investigated at 1 MHz switching frequency. This has an EMI filter integrated into the topology itself and hence if successful the need for an external EMI filter is removed. In lieu with this goal accurate high frequency model of the components in the circuit are prepared to ascertain the actual advantage with this converter over other conventional topologies. Another method for size reduction is by integration of different components; intelligent packaging of things will not only help in reduction of the parasitic components but will also results in overall size reduction. Figure 14. Technical Witt’s zero emission and zero ripple topology 15