SILICON CONTROLLED RECTIFIER MODEL
A Silicon Controlled Rectifier (SCR) Model
The equivalent SCR subcircuit shown in Figure 14 will be used
for the SCR model. SCR’s are difficult to model because the
typical data sheet does not provide adequate information and
the anode gate terminal is not available to generate test data.
The approach presented here will focus on making a model that
gives reasonable results for dv/dt sensitivity, holding current
and storage time. The dv/dt sensitivity is defined as the rate of
anode to cathode voltage which will turn the device on without
any applied gate current. It varies with gate voltage bias;
however, rate sensitive turn on will occur even when the
cathode gate is shorted to the cathode. The extra NPN transistor in the model is used to model the lateral base resistance and
account for this effect. The 2N6397 data sheet will be used for
the sample calculations.
1
1, Anode
Q1
2, Gate
Q3
Q3
RBN
Q4
2
3, Cathode
3
Figure 14, The Intusoft SCR equivalent circuit (Right) and SPICENET
symbol, QN6397, (Left).
When the compound Hfe of the NPN and PNP transistors is
greater than unity, the SCR will turn on. The 2N6397 data sheet
shows the holding current and the DC trigger current to be
nearly equal, suggesting the two transistors have about the
same Hfe versus current behavior. Hfe will increase at higher
currents so that the holding current must be a result of low
current Hfe roll off which is modeled by selecting NE and ISE as
described by the BJT equations resulting in NE=2 and ISE=4E9. The value for IS and RBN are initially selected based on the
generic power transistor.
98
CHAPTER 7 - MODELS FOR POWER ELECTRONICS
The dv/dt specification is 50 v/usec, at 125 Degrees C, where
Hfe is typically twice its room temperature value. The trigger
current should be one fourth its high temperature value since
there is a cascade of two current gains. The SCR should then
turn on when the current through the collector-base capacitance is 1.25ma.
i = C*dv/dt,
Eq. 7.10
Ctotal = Ih/dv/dt = 25PF
Eq. 7.11
This will give a value of about 100PF at zero bias so that the CJE
and CJC of the two transistors can be set to 50PF. This
capacitance will also affect circuit performance, so independent verification was also be made by laboratory test.
The 40 Ohms resistance connecting the two bases is chosen
based on the generic power transistor model. When the gate is
shorted, it will be necessary to have an additional 15ma of
current through the capacitance, which will increase the dv/dt
threshold by a factor of four. Predictions for a typical device at
room temperature are then 200 V/USEC open gate and 800 V/
USEC shorted gate. In order to obtain proper temperature
sensitivity, it is necessary to also set XTB, the forward Beta
temperature exponent, to 2.5.
Selecting BF, BR, TF and TR is more difficult. These parameters will describe the dynamic SCR behavior, which is a
function of the current distribution when all junctions are forward biased. Experimental evaluation of the simulation parameters shows that the NPN must be slower and have higher gain
than the PNP in order for the NPN base emitter to remain
forward biased during turn off. If the NPN base emitter turns off
first, then a large negative voltage transient is predicted for the
gate, a condition that is not observed. Trial simulations were run
to determine a reasonable set of gain and transit time parameters. The starting point used the generic power transistor
parameters. The final set of parameters is in the SCR.LIB file.
Simulations were run to verify DC trigger current, dv/dt, turn on
and turn off characteristics. Figure 15 shows the simulation for
99
SPECIAL SOURCES FOR POWER SUPPLY DESIGNERS
800
400
0
1.50
500M
-500M
-1.50
Wfm#1 VIN in Volts
Wm#1
VIN in Volts
1.20K
200
2.50
Wfm#2VGATE
VGATE in
Wm#2
inVolts
Volts
Wfm#3
VAC in Volts
Wm#3 VAC in Volts
1.60K
-200
1
1
2
-600
-1.00K
-1.40K
3
2.00U
6.00U
10.00U
TIME in Secs
14.0U
18.0U
Figure 15, A 2N6397 SCR turn on and turn off response, 125 Deg. C.
turn on and turn off at 125 Degrees Celsius-. where dv/dt
triggering is shown.
Special Sources For Power Supply Designers
Included in the Signal.Lib file are several signal sources especially developed to assist the power
supply designer. Two sources of
.SUBCKT GEN3 3 7 1 20
special note are the 3 phase gen* FREQ = {FREQ} AMPLITUDE = {VGEN}
C1 2 20 {1/(6.28319K*FREQ)}
erator capable of supplying 3 phase
R1 2 20 1E6
voltages, with or without magniI1 20 2 PULSE {VGEN*1U} 0
tude and phase error, and a vari* MAKES UIC UNNECESSARY
E1 5 20 20 2 1
able phase Sin/Cosine source.
V1 3 20 SIN 0 {VGEN} {FREQ}
[Figures 16a-c].
E2 7 20 POLY(2) 5 20 3 20 0 -866.00M -500.00M
E3 1 20 POLY(2) 5 20 3 20 0
+ {(1+.01*MAGERR)*(.866*(1-.5*(.0174533*PHASE)^2)
+ -.5*.0174533*PHASE*(1+.166667*
+ (.0174533*PHASE)^2))}
+ {(1+.01*MAGERR)*(-.5*(1-.5*(.0174533*PHASE)^2)
+ -.866*.0174533*PHASE*(1+.166667*(.0174533*PHASE)^2))}
G1 20 2 20 3 1M
R2 7 0 100MEG
R3 1 0 100MEG
R4 3 0 100MEG
3 Phase Generator
R5 5 0 100MEG
Subcircuit Listing
.ENDS
100
The 3 phase generator is made up
of an integrator that converts the
basic sine source to a cosine
source. Summers are then used
with varying weighting constants
to give the desired output signals.
The source allows the user to define the peak amplitude and frequency. Magnitude and phase un-