ISD15D00 Thermal Guidelines
AN-15D.0001
1. Introduction
The scope of this document is to provide a brief outline of layout design considerations
for the ISD15D00 series devices.
2. Output Power and Dissipated Heat
The ISD15D00 features two 1-watt direct-drive outputs:
 Class-D PWM and
 Class-AB BTL.
Output power and the corresponding efficiency are shown in the figures below.
1.5
1
0.8
0.7
1
Efficiency
Class-D PWM Power (W)
0.9
0.5
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
2.5
3
3.5
4
4.5
5
5.5
6
0
VCCSPK (V)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2
Class-D PWM Power (W)
Figure 1 Class-D Power vs. VCCSPK
Figure 2 Class-D Power vs. Efficiency
1.5
1
0.8
0.7
1
Efficiency
Class-AB BTL Power (W)
0.9
0.5
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2
2.5
3
3.5
4
4.5
5
5.5
6
0
VCCSPK (V)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2
Class-AB BTL Power (W)
Figure 3 Class-AB Power vs. VCCSPK
Figure 4 Class-AB Power vs. Efficiency
1
Publication Release Date: Apr 19, 2010
Revision 0.1
ISD15D00 Thermal Guidelines
AN-15D.0001
The dissipated heat at a certain output power can be calculated as:
Dissipated Heat = Output Power x (1 - Efficiency)
Example of Dissipated Heat:
 For the Class-AB BTL output
 VCCSPK = 5V.
 Volume level set to -3dB.
 Figure 3 shows that Class-AB BTL delivers 1.0 watt at VCCSPK = 5V, given that
volume sets to its maximum (0dB). Therefore, Class-AB BTL delivers 0.5 watt at
VCCSPK = 5V, given that volume sets to -3dB.
 Figure 3 shows that Efficiency = 0.43 when Class-AB BTL delivers 0.5 watt.
 Dissipated Heat
= Output Power x (1 - Efficiency)
= 0.5 x (1 - 0.43)
= 0.285 watt
3. Thermal Package Information
The ISD15D00 are available in two packages:
 48L-LQFP 7x7mm and
 32L-QFN 5x5mm with exposed pad
o The exposed pad is the bottom of the lead-frame pad and can improve
heat dissipation.
o The exposed pad should be connected to analog ground.
Table 1 below shows thermal resistance of the two available packages.
0 m/s**
1 m/s
2 m/s
Ѳja* (C/W)
Ѳjc (C/W)
48L-LQFP
60
17
32L-QFN
37.68
35.16
33.29
6.56
Table 1 Theta J of ISD15D00 packages
*note: please see appendix at the bottom for an explanation of theta J.
**note: m/s is meters per second – ambient air speed.
The increased temperature can be calculated as:
Increased Temperature = Dissipated Heat x Ѳja
Example of Increased Temperature:
 For the 32L-QFN package
 Ambient air is still.
 Dissipated heat = 0.285 watt (from the dissipated heat example).
 Increased Temperature
= Dissipated Heat x Ѳja
= 0.285W x 37.68 C/W
= 10.739 C
2
Publication Release Date: Apr 19, 2010
Revision 0.1
ISD15D00 Thermal Guidelines
AN-15D.0001
4. Layout Suggestions
4.1
Guideline for basic PCB layout design practice:

Component placement:
Components associated with ISD15D00 should be placed as close as possible to
the respective pins.

Power Supply Decoupling:
Place 0.1µF ceramic capacitor as close as possible to each of the power supply
pins.

Ground Pins:
The analog and digital ground should connect to a common ground plane.

Power Supply Pins:
VCCD, VCCA and VCCSPK should have separate power planes.
3
Publication Release Date: Apr 19, 2010
Revision 0.1
ISD15D00 Thermal Guidelines
AN-15D.0001
4.2
PCB Copper Area Calculation for Heat Dissipation
Note: Terms and experiment data can be referred to
http://focus.ti.com/lit/ml/slup230/slup230.pdf
Figure 5 Electrical equivalent circuit of heat transfer.
-
RJC: junction to case thermal resistance, usually specified
RCS: interface resistance, specified for heat sink insulators, negligible for solder
connections
RSA: sink to ambient resistance, specified for heat sinks
TA = Ambient Temperature
Example: Calculate the copper area needed for ISD15D00 when it works under
the worst scenario:
o Ambient temperature: 85ºC
o Power loss: 0.4 W
4
Publication Release Date: Apr 19, 2010
Revision 0.1
ISD15D00 Thermal Guidelines
AN-15D.0001
o part is working at its maximum temperature tolerance: 125ºC
Input:
Parameter
Pdiss
Tjunction
Value
0.4
125
Units
W
C
Tambient
Theta JC
Theta CS
Theta SA
85
6.56
0
1000
C
C/W
C/W
(cm²)*C/W
Notes
Power Dissipated in Device
maximum or desired junction
temperature
ambient temperature
thermal resistance of junction to case
thermal resistance of case to surface
thermal resistance of a 1 cm² surface to
ambient
Formulas:
Area = Pdiss*Theta_SA/(Tjunction - Tambient - Pdiss*(Theta_JC + Theta_CS))
= (0.4*1000)/(125-85-0.4*(6.56+0)) = 400/37.38 = 10.70 cm².
Results:
Parameter
Parameter
Area
Value Units Notes
Value
10.70
Units
cm²
Notes
Required PCB
copper area
Combine the exposed copper area size and the center pad size; it roughly gives
total size of 11cm².
4.3
Guideline for ISD15D00 Heat Dissipation
Component placement:
 It is ideal to place ISD15D00 near the edge of the PCB board for better air flow.
 ISD15D00 should not be placed close to other high power components. Being
close to other high power components may cause heat dissipation difficulty for
ISD15D00.
Heat Dissipation Pad design consideration:


According to the copper area calculation, it is desired to have copper area which
is equal to or greater than 11 cm². For information regarding copper area
calculation, please refer to section 3.3.
The center pad (see Figure 6) should have 6x6 or greater matrix of thermal vias
to aid good heat conductivity.
5
Publication Release Date: Apr 19, 2010
Revision 0.1
ISD15D00 Thermal Guidelines
AN-15D.0001


The center pad should be the same size as the maximum dimension of the
ISD15D00 exposed pad, which will be connected to VSSA.
Heat dissipating area design can adopt the pattern shown below:
Figure 6 PCB TOP side center pad and exposed copper area
Figure 7 PCB Bottom side exposed copper area
6
Publication Release Date: Apr 19, 2010
Revision 0.1
ISD15D00 Thermal Guidelines
AN-15D.0001

Thermal vias on the auxiliary heat dissipating pads (see Figure 6) aim to ensure
that there are two surfaces dissipating heat instead of one.

The total exposed copper area equals to top side pad size + bottom side pad size,
and it needs to be no less than 11 cm².
To reduce thermal resistance, the exposed copper area thickness may be 2 x
normal copper thickness – (for example, if default copper thickness is 3.5um, the
exposed copper area thickness can be 7um).

4.4
Other Layout considerations for ISD15D00 QFN package
PCB pin pad layout recommendations
Figure 8 Exposed Metal of Peripheral Pad Layout recommended for QFN32 Package




Extension of the PAD from the edge of the package (d) – 0.15mm.
Width of the pad to be larger than lead nominal width on each side (e) by
0.025mm
Minimum distance between two adjacent pads – 0.15mm.
Inside edge of the peripheral pad to be in line with inside edge of the
peripheral lead and between 0.15 and 0.25mm away from the center pad
Solder mask


Allow sufficient distance between the peripheral pads (0.15mm recommended)
to accommodate the solder mask. This will prevent shorting between two
pads or between two leads.
Allow sufficient distance between the center pad and the inside edge of the
peripheral pads (0.15mm recommended) to accommodate the solder mask
and prevent shorting between the center pad and peripheral leads.
Prevent solder wicking

For the auxiliary heat dissipating pads (Figure 6 and Figure 7), there is no
solder wicking issue since there is no solder applied on these pads.
7
Publication Release Date: Apr 19, 2010
Revision 0.1
ISD15D00 Thermal Guidelines
AN-15D.0001

For the center pad (Figure 6 and Figure 7), Top-Side Via Tenting, or other
method, should be applied to prevent solder wicking.
5. Thermal Model
This guideline only provides recommendations for improving heat dissipation of the
ISD15D00. Only a thermal model of the whole system can determine heat generation
and dissipation. Users should do a thermal simulation of their PCB with all system
components to verify sufficient heat flow out of I15D00 to meet their specific
requirements.
6. Appendix – Theta J Numbers***
***note: the following paragraph is excerpted from http://www.siliconfareast.com/theta.htm
Advanced thermal modeling of complex products is usually performed through finite
element analysis. However, there is a simple heat-transfer model for semiconductor
devices that is still widely used today. In this model, heat is transferred from the die to
the surface of the package through thermal conduction, and from the package to its
surroundings by convection and radiation.
The rate of heat transfer between two bodies may quantified in terms of the thermal
resistance between them. In the simple model mentioned above, the over-all thermal
resistance between the die and the surroundings of the device, θja ('ja' stands for
'junction-to-ambient') is the sum of two thermal resistances: 1) the thermal resistance
between the die and the package, θjc ('jc' stands for 'junction-to-case'); and 2) the
thermal resistance between the package and the surroundings, θca ('ca' stands for
'case-to-ambient').
Below are the equations relating these thermal resistances.
θja = θjc + θca (deg C/W)
θjc = (Tj - Tc) / P
θca = (Tc - Ta) / P
θja = (Tj - Ta) / P
θja is the junction-to-ambient (or die-to-ambient) thermal resistance;
θjc is the junction-to-case (or die-to-package) thermal resistance;
θca is the case-to-ambient (or package-to-ambient) thermal resistance;
Tj is the average junction or die temperature;
Tc is the average case or package temperature;
Ta is the ambient temperature; and
P is the power dissipated by the device (in watts).
8
Publication Release Date: Apr 19, 2010
Revision 0.1