6
CHIP PACKAGING:
THERMAL REQUIREMENTS AND CONSTRAINTS
ÒThe best you can do is break even.Ó
Ñ First Law of Thermodynamics
ÒYou canÕt even break even.Ó
Ñ Second Law of Thermodynamics
THE ROLE OF THERMAL MANAGEMENT
The charge extracted by Nature for information processing is waste heat being generated. As
energy builds up, the junction temperature increases. The temperature difference between the
devices and their surroundings drives the heat flow out of the system. The greater the temperature
difference, the higher the energy flow. The maximum temperature of a device junction is reached
when the heat flow out to the ambient is able to keep up with the energy being produced by the
junction. Thermal management engineering determines what this temperature will be.
Beyond the above concerns, there is a reliability and speed penalty associated with increasing
junction temperature. In general, all failure mechanisms have an activation energy associated
with them that are accelerated by increased temperature. For an activation energy for the failure
mechanism of 0.5eV, typical of punch-through failures, for example, every 10¡C increase in junction temperature results in the lifetime of a device cut roughly in half (Figure 6-1). Because channel resistance increases with temperature, switching delay for a gate is also increased about two
percent for a 10¡C rise in temperature. For these reasons, it is necessary to prevent the junction
temperature from rising too high.
In general, the junction temperature should be kept below 115¡C for a reasonable lifetime. IBM
uses 85¡C as its design guideline. Intel uses 90¡C as the maximum junction temperature specification for the Pentium processor. With an ambient that might be 40¡C (113¡F) inside an enclosure,
the maximum temperature drop between the junction and the ambient is typically on the order of
50¡C. The purpose of a thermal management strategy is to provide a method of extracting whatever thermal power is generated and dissipating it into the environment, while keeping the junction temperature below 90¡C, using at most a temperature differential of 50¡C. At the same time,
there is often an acoustic noise specification that must be met.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-1
Chip Packaging: Thermal Requirements and Constraints
Relative Lifetime
100
10
1
0.1
0.01
-25
0
25
50
75
Temperature (°C)
Source: ICE, "Roadmaps of Packaging Technology"
100
125
15809
Figure 6-1. Relative MTBF with Activation Energy of 0.5eV
Among all device families, there are two sources of power dissipation that are important. There
is a component that is independent of the switching frequency, called the DC or quiescent power
dissipation. There is an AC or switching power dissipation that increases with switching frequency. In general, the DC power dissipation is high for ECL but nearly zero for CMOS. The AC
power dissipation can be comparable in the two technologies.
DC Power and Speed Tradeoffs in ECL
Electrical power is dissipated only when current flows through a resistive element. This occurs in
a steady state, as with pull-up, pull-down, or terminating resistors, and when current flows
through a buffer transistor during the transient charging and discharging of a capacitor. A capacitor can be an input gate, on-chip metallization, or output load capacitance, for example.
The steady-state power dissipated, PDC, by a current, I, flowing through a resistor, R, or voltage
drop, ÆV, is:
PDC = I∆V = I 2 R
Modern ECL gates are biased on at a steady current value using a current source. This is diagrammed in Figure 6-2. The bias current value is chosen based on a balance between the DC
power dissipation and switching speed.
The time required to charge or discharge a capacitance, C, such as an on-chip interconnect fanout
or input gate, tdischarge, is:
t discharge =
6-2
C∆V
I
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
V
(0V)
CC
Output
VEE (–3.4V)
1
Current Source
(0.5mA – 10mA)
VEE (–5.2V)
2
Source: ICE, "Roadmaps of Packaging Technology"
15807
Figure 6-2. Current Source Bias for an ECL Gate
In ECL circuits, the bias current is what charges or discharges an interconnect to change its voltage level. To switch faster, a higher DC current level is required. This higher current also means
more DC power dissipated. Combining the switching time and resulting power dissipation yields
the speed-power tradeoff for ECL:
t discharge PDC = C( ∆V )
2
In many ECL gate array families, the designer can select the bias current level to trade off speed
and power as appropriate. For example, in the Motorola MCAIII family, there is a low-power,
low-speed option that offers 0.2nsec switching times and 1mW/gate, or a high-power, high-speed
option at 0.12nsec and 3.5mW/gate. The output drivers can be optimized as well.
In CMOS technology, the output drivers are never both on simultaneously in DC mode. A typical output driver is diagrammed in Figure 6-3. When the device is set to output high, the p gate
is on, and the output is effectively switched to the VDD rail. When the device is set for output
low, the output is effectively switched to the VSS rail, which is typically ground.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-3
Chip Packaging: Thermal Requirements and Constraints
VDD
P CHANNEL
INPUT
OUTPUT
N CHANNEL
VSS
Source: ICE, "Roadmaps of Packaging Technology"
22366
Figure 6-3. Typical CMOS Inverter Buffer Output Gate
In typical high speed CMOS circuits, the output load is capacitive. There may be a series resistor acting as a source termination or damping resistor, but the DC resistance of the load is typically very high. At steady state there is no current flow out of the driver, either through the n or
p transistors. In DC, when the device is not switching, there is very little power dissipation in a
CMOS device.
AC Power Dissipation in CMOS
The energy, U, switched in a capacitor, C, when it changes voltage from 0 to V is:
U=
1
CV 2
2
Because of the nature of RC circuits, all the stored energy will be converted into heat energy each
time the capacitance is either charged or discharged. When this voltage makes two transitions per
clock cycle, the average power dissipated, PAC, is:
PAC = CV 2 Fclock
The power dissipation depends on the switching voltage, the gate capacitance and the switching
or clock frequency. Because of the voltage squared dependence, decreasing the switching voltage
can have a large impact on decreasing the power consumption. For example, at 1 micron channel
length, the typical power consumption of a 5V CMOS gate is on the order of 6µW/MHz/gate for
internal gates. If the voltage were dropped to 3V, the power consumption would drop to
2.2µW/MHz/gate.
6-4
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
In addition, the area of the gate contributes to the gate capacitance. Reducing the feature size also
reduces the gate capacitance. However, the gate oxide thickness is also reduced, which acts to
increase the gate capacitance. The net result of decreased feature size is still a reduction of power
dissipation. For 0.5 micron CMOS, operating on 3V supplies, the gate power dissipation is
roughly 1.5µW/MHz/gate.
At 100MHz, the power dissipation per internal gate for 1 micron CMOS would be 0.6mW/gate.
Because of the larger size of output drivers, power consumption would be roughly 2.4mW/gate.
This is comparable to ECL DC power dissipation. However, in CMOS, it is only those gates actually switching that contribute to the power dissipation.
For example, a 50,000-gate array, with 20 percent of the internal gates switching per cycle and 50
output drivers switching per cycle would dissipate:
PAC = (6µW x 10,000) + (24µW x 50) = 61.2mW/MHz.
If each of the output gates drives a 25pF load, the dissipation would be an additional
30mW/MHz. The total power dissipation at 100MHz, for example, would be nine watts for a
CMOS device!
The trend of more gates per chip and higher clock frequencies both lead to higher power dissipation per die. This trend in processors is shown in Figure 6-4. The typical power consumption for
a variety of CMOS devices are listed in Figure 6-5.
40
35
Watts
30
25
20
15
10
5
0
0
40
80
120
160
200
Speed (MHz)
Source: Advanced Packaging/ICE, "Roadmaps of Packaging Technology"
22080
Figure 6-4. Evolution of Power Dissipation for Desktop MPUs
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-5
Chip Packaging: Thermal Requirements and Constraints
Clock
Frequency
(MHz)
Power
(watts)
Intel 386DX
33
2
Intel 486DX
66
7
Intel Pentium
100
16
Motorola 040
40
9
Motorola 060
66
5
PowerPC 601
80
10
SGS RISC
55
8
MIPS R4400SC
150
15
HP PA7100
100
20
DEC Alpha 21064
210
30
Processor
Source: EP&P/
ICE, "Roadmaps of Packaging Technology"
22081
Figure 6-5. Power Dissipation in Microprocessors
Thermal Engineering
The first step in managing the heat flow out of the system is to do everything possible to not create
the heat in the first place.
Power dissipation is an inevitable part of information processing. The faster the clock frequency,
the higher the power dissipation. However, the more heat that must be dissipated, the higher the
cost will be to the system. This cost will appear as more expensive thermally enhanced packages,
larger fans, heatsinks and baffling, or larger openings in the enclosure which may mean added
expense for EMI protection.
Portable systems have the added problem of limited run time based on battery life. Battery energy
is rated in Amp-hours. 1 amp-hour is 3,600 joules. For example, two AA batteries that supply a
palmtop PDA may have a total energy supply of only 2 amp-hrs. A Sharp Zaurus PDA is rated at
0.5 watts peak, with 0.05 watt typical. Two AA batteries would last for 40 hours, running continuously. Sharp rates the typical time between battery replacements to be 2 months.
There are four things that can be done to cut power consumption to a minimum:
1. Design the IC for lower power consumption
2. Reduce the supply voltage
6-6
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
3. Using smart power management, adjust the clock frequency to slow down when not in use
4. Cut the interconnect capacitance that must be driven by the output drivers to a minimum
by keeping interconnect lengths as short as possible.
Of these, the two that are most widely implemented are smart power management and reducing
the supply voltage. Smart power management utilizes specialized chips that monitor the CPU
activity level. As the activity level drops, the clock frequency is drastically slowed down. After
all, most PDAs, for example, are not performing any real activity between button pushes. In
effect, smart power management puts the system to sleep between key strokes or other activities.
The second most common method of cutting power consumption is lowering the supply voltage.
This has the added benefit of requiring fewer batteries to get the higher voltages, and not requiring DC to DC converters. The disadvantage of low supply voltage is a slower switching speed.
However, in portable applications, the lower power consumption is worth it.
There is a growing trend among all CMOS devices to use lower voltages. This is due to the
decrease in gate oxide thickness, as part of the shrinking device features. Figure 6-6 shows this
trend in gate oxide thickness.
160
140
Published Data
Trend Line
Gate Oxide Thickness (Å)
120
100
80
60
40
20
0
0
0.1
0.2
0.3
Gate Length (µm)
0.4
Source: Intel/ICE, "Memory 1997"
0.5
0.6
20284A
Figure 6-6. Gate Oxide Versus Gate Length
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-7
Chip Packaging: Thermal Requirements and Constraints
In a CMOS gate, the voltage applied across the gate oxide to the channel creates an electric field
in the gate oxide. The field depends on the ratio of the voltage/thickness. There is a limit to the
highest field before the oxide breaks down, causing a failure. As the thickness decreases, the highest voltage that can be applied must be reduced to keep the field below breakdown.
For gates typically of greater feature size than 0.5 micron, the maximum allowable voltage is
above 5V. When 5V supplies are used, this has no impact on device performance. However, for
less than 0.5 micron device, the supply voltage has had to drop. This drop in maximum voltage
is shown in Figure 6-7.
6
5
Operating Voltage (V)
Published Data
Trend Line
4
3
2
1
0
0
0.1
0.2
0.3
Gate Length (µm)
0.4
Source: Intel/ICE, "Memory 1997"
0.5
0.6
20285A
Figure 6-7. Gate Length Versus Operating Voltage
One benefit to the lower voltage is the associated reduction in power consumption. However, the
net effect of higher frequency, more gates per chip and lower supply voltage is still a net higher
power dissipation. This higher power must be extracted from the junctions and dissipated in the
ambient by the thermal management system.
THERMAL MANAGEMENT: REQUIREMENTS
Performance-driven applications require the highest power dissipation while offering the highest
speeds. In the case of the MCAIII ECL family, the user can configure a chip to have a power dissipation from 1mW/gate to 3.5mW/gate. With a maximum of 10,000 gates available, although a
6-8
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
particular chip fabricated in this family can have a power dissipation from 10 watts up to 35 watts,
high-end applications will dissipate the full 35 watts. Next generation ECL gate arrays dissipate
more than 50 watts.
The NEC ECL-4A family of gate arrays offers up to 35,000 available gates, with 0.15nsec propagation delays and 4.8mW/gate. It is possible to have 168 watts dissipated by a device made in
this family! It is clear that the trend will be towards higher and higher power dissipation for ECL
devices.
An advantage of CMOS technology is the absence of DC power dissipation. However, the AC
power dissipation increases with frequency. As the example above showed, the power dissipation
at 100MHz can approach 10 watts, comparable to ECL devices. At 200MHz, and reduced supply
voltage, the power dissipation is still over 16 watts.
The power associated with driving the output load capacitance can be a significant fraction of the
total. In the CMOS example above, it is about 35 percent. For portable devices, where minimizing power dissipation is critical, the output load capacitance must be kept to a minimum.
The SIA roadmap estimates power dissipation of future high-, mid- and low-end devices, as
shown in Figure 6-8.
180
High End
Mid Range
Portable
160
Power Consumption (watts)
140
120
100
80
60
40
20
0
1994
1996
1998
Source: ICE, "Roadmaps of Packaging Technology"
2000
2002
2004
2006
2008
2010
Year of Introduction
22208
Figure 6-8. SIA Roadmap for Single Chip Power Dissipation
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-9
Chip Packaging: Thermal Requirements and Constraints
A high-end device is on the order of 17mm on a side, which gives a surface area of almost 3.0cm2.
With 30 watts for some high end, high speed processors, the power flux densities from their surfaces can be on the order of of 10W/cm2. This is comparable to the power flux on the nose cone
of a vehicle re-entering from earth orbit. Figure 6-9 shows heat fluxes of various activities.
Extracting this heat while maintaining acceptable junction temperatures is a significant engineering challenge.
Rocket Nozzle
Throat (Internal)
4
10
Nuclear Blast
(1Mt, 1mi)
3
Heat Flux (W/cm 2 )
10
Ballistic Entry
2
10
VLSI
Re-entry from Earth Orbit
10
Rocket Motor Case (External)
1
–1
Solar Heating
10
–2
10
0
1,000
2,000
3,000
4,000
5,000
Temperature (°K)
Source: ICE, "Roadmaps of Packaging Technology"
15808A
Figure 6-9. Heat Fluxes of Various Activities
THERMAL MANAGEMENT: CONSTRAINTS
In describing how the heat is extracted from the chip, it is convenient to divide the pathway into
two parts; the junction-to-case path, which is often called the internal path, and the case-to-ambient path, which is called the external path. These are diagrammed in Figure 6-10.
The junction-to-case path typically has a region directly in contact with the die in which heat flow
is predominantly in one dimension, and then a region with a heat spreader, in which lateral flow
may dominate. In general, the junction-to-case region can be characterized by intrinsic material
properties, and scales with the geometry. A heat spreader is any thick, thermally conductive plate.
Typically, there is as much heat flow laterally as through the thickness of the plate. This has the
effect of increasing the surface area through which heat can flow from the case to the ambient.
The case-to-ambient path is dominated by the mechanism for transferring heat out into the ambient environment. This could be a heatsink in contact with an air flow or cold plate in contact with
liquid flow or a reservoir. In general, especially for air cooling, the ability to extract heat out of
6-10
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
the system depends on extrinsic properties of the package and heatsink, such as the shape, surface area exposed to air and ability to allow large volumes of air to flow through it. The case-toambient thermal resistance is usually empirically characterized.
Ambient
Ambient
θ ca
Heatsink
Fins
Junction
Case
θ jc
Package "Case"
Chip
Power
Generator
Chip
Pins
θ cb
Board
Board
Physical Structure
Internal Path:
θ jc = Junction to case thermal resistance
θ cb = Case to board thermal resistance
123
External Path:
Equivalent Thermal Model
θ ca = Case to ambient thermal resistance
Source: ICE, "Roadmaps of Packaging Technology"
22209
Figure 6-10. Thermal Model of a Package
The Thermal Budget
Thermal budget is used to allocate the distribution of temperature drop between the junction- tocase, and case-to-ambient. If the maximum junction temperature allowed is 90¡C, and the maximum ambient temperature is 40¡C, then the total temperature budget is 50¡C. Of this, typically
70% is allocated to the case-to-ambient differential, and 30% allocated to the junction-to-case differential, or 35¡ for the case-to-ambient and 15 ¡C for the junction-to-case.
In the thermal path to get heat out of a chip, there can be many layers, each with a thermal resistance. The total thermal resistance is the sum of the thermal resistance of the layers. In Figure 611, some examples of the thermal resistance associated with the junction-to-case path are listed.
For a chip 1cm on a side, an example of the partitioning of the thermal resistance and the resulting temperature drops for a power of 20 watts is shown in Figure 6-12.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-11
Chip Packaging: Thermal Requirements and Constraints
DESCRIPTION
THICKNESS
(cm)
MATERIAL
κ
(W/cm•°K)
THERMAL
RESISTANCE
(°C/W)
Chip
Silicon
0.075
1.5
0.05
Die Attach
Silver-Filled Epoxy
Solder
Epoxy
0.0025
0.005
0.0025
0.008
0.51
0.002
0.313
0.0098
1.25
Ceramic Package
Alumina
Copper Tungsten
Aluminum Nitride
0.08
0.08
0.08
0.2
2.48
2.3
0.4
0.032
0.035
Interconnect
FR4 Board
Polyimide
0.25
0.005
0.002
0.002
Heat Spreader
Copper
Aluminum
0.63
0.63
4.0
2.3
125.0
2.5
0.158
0.274
Source: ICE, "Roadmaps of Packaging Technology"
15811A
Figure 6-11. Selected Junction-to-Case Thermal Resistances
Element
Thermal Resistance
(°C/W)
Temperature Drop
(°C)
Silicon Die
0.05
1
Silver-filled Epoxy
0.3
6
Ceramic Base
0.4
8
Total Junction-to-Case
0.75
15
Source: ICE, "Roadmaps of Packaging Technology"
16453
Figure 6-12. Layer Contributions to Thermal Resistance and Temperature Drop for 20 Watts
Decreasing the thermal resistance of the junction-to-case path is critical when the power densities
approach the 30W/cm2 range. There are two approaches currently being used to minimize the
junction-to-case thermal resistance: decreasing the number and thickness of the layers between
the chip and the heat spreader, and using more effective heat spreader substrate materials with
high thermal conductivity, such as copper, silicon carbide, and aluminum nitride.
In the DEC VAX 9000, the backs of the 35 watt ECL dice are attached directly to a copper plate heat
spreader with diamond filled thermally conductive epoxy. The total junction-to-case thermal
resistance is about 0.35¡C/W, and the junction-to-case temperature drop is about 12¡C.
Junction-to-Case Thermal Resistance
For conduction based heat flow in one dimension, the temperature drop, ÆT, between two regions
in a structure, will depend on the power flow, P, and the thermal resistance, Rthermal:
∆T = R thermal P
6-12
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
Thermal resistance is the thermal analog to electrical resistance. Both qualities impede the flow of
something. Temperature drop is like a voltage difference and power flow is similar to a current.
A large thermal resistance will cause a large temperature drop for a given power flow. If a chip is
dissipating 10 watts of power, a higher thermal resistance between the junction to the ambient will
result in a larger temperature drop between the junction and ambient. The goal in thermal management is to decrease the thermal resistance as much as possible.
The units of thermal resistance are ¡C/W. The heatsink associated with the Pentium processor, for
example, has a thermal resistance of about 12¡C/watt.
Thermal resistance is an ÒextrinsicÓ property, in that it depends on geometry in addition to intrinsic material properties. The thermal resistance to heat flow in one dimension, diagrammed in
Figure 6-13, depends on a material property, the thermal conductivity, kthermal, and the dimensions of the layer: the thickness, Llayer, and the area, Alayer:
R thermal =
L layer
K thermal A layer
A layer
L layer
θ=
L layer
1
x
A layer
K
intrinsic
[°C / Watt]
extrinsic
Source: ICE, "Roadmaps of Packaging Technology"
22210
Figure 6-13. Definition of Thermal Resistance
Figure 6-14 lists the thermal conductivity of some of the more important packaging materials.
For example, the thermal resistance of a 100mil thick layer of cofired ceramic substrate (96%
Alumina), 18mm on a side is:
R thermal =
0.100inch • 2.54 cm inch
= 0.7° C watt
0.2 w cm − °K • 1.8cm
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-13
Chip Packaging: Thermal Requirements and Constraints
MATERIAL
METALS
Silver
Copper
Gold
Copper Tungsten
Aluminum
Molybdenum
Brass
Nickel
Solder (SnPb)
Steel
Lead
Stainless Steel
Kovar
Silver Filled Epoxy
SEMICONDUCTORS
Silicon
Germanium
Gallium Arsenide
LIQUIDS
Water
Liquid Nitrogen (at 77°K)
Liquid Helium (at 2°K)
Freon 113
GASES
Hydrogen
Helium
Oxygen
Air
Thermal
Conductivity (κ)
W/cm-°K
4.3
4.0
2.97
2.48
2.3
1.4
1.1
0.92
0.57
0.5
0.4
0.29
0.16
0.008
1.5
0.7
0.5
0.006
0.001
0.0001
0.0073
MATERIAL
Thermal
Conductivity (κ)
W/cm-°K
INSULATORS
Diamond
AlN (Low O2 impurity)
Silicon Carbide (SiC)
Beryllia (BeO) (2.8 g/cc)
Beryllia (BeO) (1.8 g/cc)
Alumina (Al2O3) (3.8 g/cc)
Alumina (Al2O3) (3.5 g/cc)
Alumina (96%)
Alumina (92%)
Glass Ceramic
Thermal Greases
Silicon Dioxide (SiO2)
High-κ Molding Plastic
Low-κ Molding Plastic
Polyimide-Glass
RTV
Epoxy Glass (PC Board)
BCB
FR4
Polyimide
Asbestos
Teflon™
Glass Wool
2 0.0
2.30
2.2
2.1
0.6
0.3
0.2
0.20
0.18
0.05
0.011
0.01
0.02
0.005
0.0035
0.0031
0.003
0.002
0.002
0.002
0.001
0.001
0.0001
0.001
0.001
0.0002
0.0002
Source: ICE, "Roadmaps of Packaging Technology"
15810A
Figure 6-14. Thermal Conductivities of Various Materials
(At Room Temperature Unless Noted Otherwise)
Plastic packaging is commonly regarded as a high thermal resistance packaging technology, suitable for only low power devices. This is true for overmolded parts. In such a case, the thickness
of the molding compound from the die to the ambient might be 1mm. With a thermal conductivity of roughly 0.005 watt/cm-¡C, the thermal resistance of the junction to case might be 20¡C/watt.
In addition, the coupling to the air might be 60¡C/watt, making the total thermal resistance
80¡C/watt. In such packages, typically, as much power could flow out the leads of the package
as through the case, lowering the effective thermal resistance to about 40¡C/watt. With a thermal
drop of 50¡C, this means such a package would not be suitable for devices of higher power than
about 1.2 watts.
However, this thermal resistance can be greatly improve for Òthermally enhancedÓ plastic
packages. There are four methods commonly employed to cut the thermal resistance down in
plastic packages.
6-14
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
All of them employ a cavity-down
orientation with the die cavity
facing the circuit board, with the
back of the die facing up, available
for heatsink attach. In a cavity-up
orientation, the die faces upward
and the package is soldered to the
board.
These orientations are
shown in Figure 6-15.
The first thermal enhancement
method uses a filler in the plastic to
increase the thermal conductivity of
Source: Matsushita/ICE, “Roadmaps of Packaging Technology”
22507
the molding compound. Typical
Figure 6-15. Cavity-Up Versus Cavity-Down Packages
fillers are silica and aluminum
nitride powder. Figure 6-16 illustrates the enhanced thermal performance of a 208 package with these different molding compounds. The increase in performance can be 30%-40%.
Epoxy Molding Compound Filled With:
40
Fused Silica
Thermal Resistance (°C/watt)
35
32 Leads, Fused Silica
Silica Coated Aluminum Nitride
30
Exposed Heat Slug With Fused Silica
25
20
15
10
5
0
0
100
200
300
400
500
600
700
800
Air Velocity (ft3/min)
Source: Advanced Packaging/ICE, "Roadmaps of Packaging Technology"
22211
Figure 6-16. Thermal Performance with Silica and Aluminum Nitride Fillers
The second method uses an insert of a high thermal conductivity plate, typically aluminum or
copper. This acts as a heat spreader, while reducing the path through the higher thermal resistance molding material. A cross section and top view of a plastic package with an insert is shown
in Figure 6-17.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-15
Chip Packaging: Thermal Requirements and Constraints
Die Attach
Epoxy
Sidewall
Locking Feature
Copper
Leadframe
Moat
(Optional)
Copper Heatsink
Leadframe
Attach Tape
,,,,,,,,,,
Die
,,,,,,,,,,
Mold Compound
Gold
Wirebonds
Source: Amkor Anam/ICE, "Roadmaps of Packaging Technology"
22083
Figure 6-17. Thermally Enhanced PQFP with Embedded Heat Spreader
The third method involves the use of a metal substrate from which the package is fabricated. Two
examples are the MQUAD and MBGA packages, from Olin Interconnect. An example of the
MQUAD is shown in Figure 6-18. In each case, the base of the substrate is made up of an aluminum platebase. The leads of the MQUAD are stamped leadframes, adhesively attached to the
aluminum plate. After die attach a cover plate is attached. The aluminum base is exposed to facilitate heatsink attach. The junction to case thermal resistance can be kept to less than 1.8¡C/watt.
The fourth method of dramatically reducing the junction-to-case thermal resistance of a plastic
package is primarily used in plastic packages which use a PCB substrate, such as a PPGA or
PBGA. The chip cavity is punched out and the substrate is laminated to a metal base. The chip
is attached directly to the metal base, with a very low junction-to-case thermal resistance. The
cross section of this type of package is shown in Figure 6-19. An example of a PPGA with copper
base is shown in Figure 6-20. High performance PPGA and PBGA packages can have a junctionto-case thermal resistance of less than 1¡C/watt, primarily limited to the die attach conditions.
6-16
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
Anodized
AI Alloy Base
Sealing
Epoxy
Cu Alloy
Pad
,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,
,,,,,,
,,,,,,
Cu Alloy
Leadframe
,yz
Pad Attach
Anodized
AI Alloy
Lid
,,,,,,
,,,,,,
,,,,,,
Die Attach
Die
Vent
Cap
Source: IEEE/Olin/ICE, "Roadmaps of Packaging Technology"
22088
Figure 6-18. Cavity Down MQUAD¨ Package
Heatsink
Substrate
,,,
,,
,
,,,
,,
,,
,,,,,,,
,,,,,,,
,,,,,,,,
,,,,,,,,,,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,,,,,,,,,,
,,,
,,,,,,,,,
,,,,,,,
,,
,,,,,,,
,,,,
Die
,,,
,,,,,,,
,,
Lid
Interconnects
Pin For
Board Attach
Seal
Ring
Thermal And Stress–
Compatible Substrate
Die
Protection
Layer
Courtesy of Motorola/Source: ICE, "Roadmaps of Packaging Technology"
4958A
Figure 6-19. Motorola VLSI Package with Die Cavity Below and Finned Heatsink Above
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-17
Chip Packaging: Thermal Requirements and Constraints
Source: Printed Circuit Builders/
ICE, "Roadmaps of Packaging Technology"
16129
Figure 6-20. FR4-Based PGA with Integrated Heatsink
Case-to-Ambient Thermal Resistance
The thermal resistance from the case to the ambient depends on how efficiently the fluid, (typically air), extracts the heat; the heat carrying capacity of the fluid; and the surface area in contact
with the fluid. A heatsink, using vertical fins, horizontal discs, pins, or convoluted channels, is
used to increase the surface area through which the heat flows. Some examples of common
heatsinks on packages is shown in Figure 6-21.
Ultimately, it is a change in temperature of an air stream or liquid stream or a phase change that
carries the heat out of the system. The efficiency of a heatsink is related to how much it is able to
raise the temperature of the fluid with which it is in contact. The closer the out flowing fluid temperature is to the case temperature, the more efficient the heatsink is. The surface area and the
design of the heatsink will clearly play a role in influencing the efficiency.
How much heat can be extracted per unit area from a surface, in W/cm2, by a heatsink depends
on its efficiency, the surface area of contact, the thermal properties of the fluid, and the volumetric
flow rate. These interact in a very complex manner. However, two approaches can be used to estimate the heat extraction capabilities of various technologies.
When the heatsink efficiency is low and the temperature of the air or liquid is not increased very
much by heat transfer from the heatsink, the power flow to the fluid can be described by:
P = h A heatsink ∆T
6-18
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
where
P = the power flow in watts
h = thermal transfer coefficient in W/cm2 ¥ ¡C
ÆT = the temperature drop between the heatsink and the fluid
Aheatsink = surface area of heatsink in contact with the fluid
Courtesy of AMD/Source: ICE, "Roadmaps of Packaging Technology"
16091
Figure 6-21. Variety of Heatsinks
Heatsinks are usually designed with a surface area much larger than the heat generating surface
area, typically by a factor of two to five. h is a measure of the heat extraction capability of the surface. It depends on the thermal properties of the fluid, the flow rate, and the nature of the flow.
The table in Figure 6-22 lists the values of h for various flows, the typical heat extraction capabilities of surfaces for a ÆT of 50¡C, and the heat extraction capability of a heatsink when its surface
area is 5x the surface area of the heat source. The numbers in the table represent an estimate of
the values that can be reached realistically without engineering heroics. They are shown graphically in Figures 6-23 and 6-24.
The most efficient heat exchanger cannot extract any more heat than can be carried by the heat
capacity of the fluid. The volumetric flow rate and specific heat of the cooling medium set the ultimate power extraction capability for the most efficient heatsinks.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-19
Chip Packaging: Thermal Requirements and Constraints
Fluid
Thermal Transfer
Coefficient
h (W/cm 2- °C)
Flow
Power Flow/Area
Q/A fins
(W/cm2 )
Q/A source
(W/cm2 )
Air
Free
0.001
0.05
Air
Forced
0.01
0.50
2.50
Water
Forced
1.0
50.00
250.00
Water
Microchannel
4.0
200.00
1000.00
Source: ICE, "Roadmaps of Packaging Technology"
0.25
16486
Figure 6-22. Heat Extraction Capabilities for ÆT = 50¡C
Microchannel
Cooling
Forced Water
Flow
Forced Air
Free
Convection Air
0.1
1
10
100
Heat Flux of Source (W/cm 2)
Source: ICE, "Roadmaps of Packaging Technology"
1,000
15812A
Figure 6-23. Heat Flux Density at Source (Thermal Extraction Area = 5x Heat Source Area)
Free-Air Heat-Capacity Limitations
The specific heat of air is 1.3mJ/cm3-¡C (21mJ/in3-¡C). If the heatsink were 100% efficient in heating the air up to the case temperature, the effective thermal resistance would be at best 50¡C/W
for 1in3/sec of air flow. If the air flow were to double, the thermal resistance would halve. This
assumes perfect efficiency of raising the air up to the case temperature. In practice, heatsinks are
not much more than 50% efficient. The effective heat extraction capability of air cooling is illustrated in Figure 6-25. In practice, the thermal resistance for air-cooled systems is never less than
100¡C/W for 1in3/sec of air flow. For example, in the IBM 4381 air-cooled module, about
610in3/sec of air flow provides a case-to-ambient thermal resistance of 0.23¡C/W. This is
140¡C/W for 1in3/sec of air flow.
The Motorola MCAIII package uses a heatsink 1.75 inches on a side, and 0.5 inch high. At
600ft/min flow velocity, which is relatively high, through its cross section of 0.5 inch by 1.75
inch, the volumetric flow rate is slightly over 100in3/sec. The optimum thermal resistance
would be 1¡C/W. In fact, it is rated at about 1.5¡C/W. In general, thermal resistance decreases
with increasing flow rate.
6-20
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
1,832
600
1,112
t io
n
1,000
752
io
n,
a
nd
ra
di
a
400
392
ct
on
ve
35.6
W
at
er
,f
Im
or
m
ce
er
d
si
co
on
nv
,f
ec
or
tio
n
d
ce
al
ur
at
,n
on
si
er
Im
m
2.0
flu
or
oc
ec
nv
co
ec
nv
co
6.0
tio
n
or
oc
a
flu
n
tio
10
4.0
104
,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,
ng
68
oili
,,,,,,,,,,,,,,,,,,,,,
nB
o
i
s
,,,,,,,,,,,,,,,,,,,,,
er
mm
,,,,,,,,,,,,,,,,,,,,,
s–I
n
o
50
b
,,,,,,,,,,,,,,,,,,,,,
car
oro
u
,,,,,,,,,,,,,,,,,,,,,
l
F
42.8
,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,39.2
rb
on
s
r,
f
ai
Di
re
ct
20
ar
bo
ns
r,
c
or
ce
d
ta
re
c
40
140
ai
ir,
60
212
Temperature Difference (°F)
io
n
co
nv
e
na
t
ur
al
100
Di
Temperature Difference (°C)
ct
200
1.0
0.01
0.02
0.04 0.06 0.1
0.2
0.4 0.6 1.0
2.0
Surface Heat Flux (W/cm2)
33.8
4.0 6.0
10
Source: 3M/ICE, "Roadmaps of Packaging Technology"
20 30
19146
Figure 6-24. Efficiencies of Select Heat Transfer Processes
Power Extracted (Watts)
10,000
1,000
100
10
1
10
100
Air Flow Rate (cu ft/min)
Source: ICE, "Roadmaps of Packaging Technology"
1,000
15813A
Figure 6-25. Maximum Heat Flux Extracted by Air Cooling
(50% Efficiency, ÆTca = 50¡C, 1 cu. ft/min = 29 cu in/sec)
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-21
Chip Packaging: Thermal Requirements and Constraints
The product of the thermal resistance and the area through which the power flows is called the
specific thermal resistance, θthermal:
θ thermal = R thermal A layer
The units are often identified as ¡C/(W/cm2). The heatsink used by the MCAIII package provides
a specific thermal resistance of 5.1¡C/(W/in2), or 33¡C/(W/cm2). For an estimated 50¡C case-toambient temperature drop allowed, high flow velocity air cooling can remove about 10 W/in2, or
1.6W/cm2, in the MCAIII heatsink. The VAX 9000 uses a pin array to extract 300 watts per 16in2
or about 19W/in2.
Heatsink Thermal Resistance Evaluation
In general, the air flow across a heatsink is not ducted. This means the volumetric flow rate is not
very well controlled. In order to evaluate the performance of a heatsink, it has become conventional to measure the case-to-ambient thermal resistance when the heatsink is in a uniform velocity air stream, typically generated inside a wind tunnel. This controlled environment allows the
comparison between different heatsinks.
Figure 6-26 compares the thermal resistance of various style heatsinks as measured in a wind
tunnel, each was about 0.5 inches tall with a base of about 1.2 inches on a side. This test compares
plate fins, pin fins, elliptical fins and an integrated fan. Air velocity through a heatsink is always
less than the air velocity in a wind tunnel due to the constrictions of the fins. In order to use this
characterization data for system design, it is necessary to know the air flow velocity inside the
product enclosure. Since this is very difficult to determine, the characterization curves are used
as guidelines or for relative comparisons.
The introduction of the Pentium processor accelerated the use of active heatsinks. An active
heatsink has a fan attached to it which dramatically increases its cooling effectiveness. An example of an active heatsink is shown in Figure 6-27. The thermal resistance of various heatsinks with
and without an attached fan is shown in Figure 6-28.
Thermal Spreading And New Materials
The thermal resistance of an interface is inversely related to the area through which the heat flows.
Increase the area and the thermal resistance decreases. Thermal spreading plays the role of effectively increasing the cross-sectional area through which heat can flow.
6-22
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
10
9
Plate Fin
Thermal Resistance (°C/watt)
8
7
Elliptical Fin
6
Pin Fin
5
4
3
Fan
2
1
0
0
100
200
300
400
500
600
700
800
Air Speed (Linear Feet per Minute)
Source: Intricast/ICE, "Roadmaps of Packaging Technology"
22213
Figure 6-26. Case to Ambient Thermal Resistance for Similar Size, Different Pinned Heatsinks
Source: EP&P/ICE, "Roadmaps of Packaging Technology"
22089
Figure 6-27. Microprocessor with a Pin Fin Heatsink Combined with a Small, Low Power DC Fan
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-23
Chip Packaging: Thermal Requirements and Constraints
10
Natural Convection
,,,
,,, TCM (Fan)
Forced Convection (400 FPM)
9
8
RθSA (°C/Watt)
7
6
5
4
3
2
1
0
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
Heatsink
2330B
2321B
2333B
2325B
2334B
PGA Size
15 x 15
17 x 17
18 x 18
21 x 21
21 x 21
Source: EP&P/ICE, "Roadmaps of Packaging Technology"
22084
Figure 6-28. Thermal Performance Comparison of Standard Heatsink and Integrated Fan
There are two situations where thermal spreading applies: when the area of the chip is effectively
increased by a flat plate into a larger flat area, and when multiple fins are used to increase the surface area in contact with the cooling fluid flow.
In the first case, the effective area of the chip is typically increased to the size of the package. This
increase in exposed area is on the order of the inverse of the packaging efficiency, 1/η. The
increased area contributed by the fins is typically a factor of two to five. The increase in area due
to fins is twice the ratio of fin height to fin pitch.
Taken together, the two elements of thermal spreading can transform the area of the chip, typically 0.2in2, into a surface area for heat flow of 5in2. It is important to use high thermal conductivity materials such as aluminum, copper, or copper tungsten as heat spreaders. To offer the
option of electrical insulation with high thermal resistance, aluminum nitride is beginning to play
a role. Single-chip packages with aluminum-nitride bases and simple leadframes, are shown in
Figure 6-29.
An intriguing material with high thermal conductivity is diamond. Its thermal conductivity is
higher than any other homogenous material. Recent advances in CVD deposition of diamond
films has moved diamond into the realm of possibilities. Currently, the only commercially viable
6-24
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
application for diamond is as heat spreaders for laser diodes. In this application, the power densities are very high, and getting the heat out to a larger area where it can be removed to the ambient by conventional methods is worth the added cost of a diamond substrate.
Source: Narumi/ICE, "Roadmaps of Packaging Technology"
16107
Figure 6-29. Quad Flat Pack with Aluminum-Nitride Substrate
There has been some attention paid to using diamond substrates for MCMs. However, because
thermal spreading is not significant, the slight added performance with diamond has not justified
its added expense. When the cost is comparable to machined copper, there will be a significant
market for diamond as a thermal spreader.
Thermal spreading is absolutely critical for high-power chips. For a heatsink with specific thermal
resistance of 33¡C/(W/cm2) and a chip having a power flux of 50W/cm2, the temperature rise
would be 1,600¡C without thermal spreading! This is a fundamental limitation of air cooling. If the
ÆT is 50¡C, then for chip power fluxes above about 2W/cm2, a larger area must be provided for the
heatsink than the footprint of the die. For all high-power chips, heat spreaders are necessary, and
the area of the substrate associated with the die must be increased to provide adequate cooling.
For a power dissipation of P, the case-to-ambient temperature drop, ÆTca, will be:
∆TCA =
θ thermal
P
A heatsink
In order to provide a temperature drop of at most 50¡C, the heatsink area, Aheatsink, must be
larger than:
A heatsink =
INTEGRATED CIRCUIT ENGINEERING CORPORATION
θ thermal
P
50°C
6-25
Chip Packaging: Thermal Requirements and Constraints
Thermal Spreading with Heat Pipes
One way of transferring the heat from the chip surface to the air is by conduction. A second way
is by a phase change in a transported fluid using a heat pipe. In a heat pipe, a fluid is made to
evaporate or boil at the heat source. The vapor carries heat away with it as heat of vaporization.
The vapor travels to a cooler surface where it condenses. The heat of vaporization is then given
off to the cooling fins.
A cross section of a typical heat pipe is shown in Figure 6-30. It consists of five elements:
¥ a boiler, in contact with the heat source,
¥ a phase changing fluid, typically a water/alcohol mix or fluorinert fluid,
¥ a transfer tube in which the evaporated vapor will travel to the condenser
¥ a condenser where the vapor is cooled and condenses back into a fluid
¥ return path for the fluid, which is either capillary tubes to wick the fluid back, or a vertical
tube, which allows gravity to return the fluid.
Evaporator
Section
Heating
Liquid
Condensate
Vapor
Adiabatic
Section
Wick
Condenser
Section
yyyyy
,,,,,
,,,,,
yyyyy
,,,,,
yyyyy
,,,,,
yyyyy
,,,,,
yyyyy
Vapor
Space
Cooling
Source: CEMCM '96 PROCEEDINGS/ICE, "Roadmaps of Packaging Technology"
22090
Figure 6-30. Heat Pipe Fluid/Vapor Path
The effective power flux transport ability of various fluids heat of vaporization and boiling points
for various fluids is shown in Figure 6-31.
6-26
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
Zn
109
Intrinsic Effective Power Flux Removal (W/cm2)
Li
Mg
Cd
Na
Hg
108
K
H2O
Rb
107
C5
NH3
CH3OH
C2H5OH
CCI4
106
0
100
1,000
T (°K)
1,500
2,000
Source: ICEMCM/ICE, "Roadmaps of Packaging Technology"
22091
Figure 6-31. Working Fluids for Heat Pipes
The only purpose of a heat pipe is to take heat from a source, usually a high density surface and
transport it with low thermal resistance to another surface where it can be removed from the
system, usually using large area fins.
A novel application involves embedding the heat pipes in a heatsink to provide a lower thermal
resistance than a solid aluminum heatsink. Figure 6-32 lists the specifications of an enhanced
heatsink with an embedded heat pipe.
Another novel application of heat pipes is the flexible heat pipe, trade named Oasis, from Aavid
Engineering. An example is shown in Figure 6-33. It consists of a boiler with a uranium boiling
initiator, a mylar bag containing the boiling fluorenert fluid, a tube to the condenser and a plastic
condenser. All the parts are heat sealed Mylar. This type of construction has the potential of very
low NRE and unit costs. It can be designed to retrofit into an existing enclosure. Samples have
been demonstrated to extract over 50 watts from single chips.
An added advantage of a heat pipe is that the thermal resistance drops dramatically at the boiling
point of the fluid. As the power dissipation goes up, the amount of boiling goes up, but the temperature rises only slightly. This naturally regulates the chip temperature at roughly the boiling
temperature of the fluid, plus the junction-to-case temperature rise. The thermal performance of
a typical heat pipe is shown in Figure 6-34.
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-27
Chip Packaging: Thermal Requirements and Constraints
180
Aluminum
160
Copper
Max Temp Rise (C)
140
TC1050
120
100
80
60
40
20
0
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140 150 160 170 180 190 200
Dissipated Power (W)
Source: Advanced Ceramics Corp./ICE, "Roadmaps of Packaging Technology"
22214
Figure 6-32. Typical Thermal Performance of the TC1050, a Heatsink with Embedded Heat Pipe
Condenser
Close up of evaporation stage on
top of processor
Source: EDNICE, "Roadmaps of Packaging Technology"
22092
Figure 6-33. AavidÕs ÒOasisÓ Fluid Cooling System
Conduction Cooling in the Substrate
For circuit boards which have only a few high power components, a significant amount of heat can
flow into the substrate, with the circuit board acting as a giant heat spreader and fin. The better
thermal transfer through the leads, into the board, the more effective the motherboard will be in
cooling. For example, a 119 pin BGA , with the balls under the chip, can sink over 85% of the total
6-28
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
power into the substrate. Also, a thicker board with more power and ground layers can better
function as a heatsink. An example of the effectiveness of the substrate in cooling is shown in
Figure 6-35, comparing a 119 BGA and a 160 PQFP on a single layer substrate and a 4 layer board
with power and ground planes. For the BGA, the decrease in thermal resistance is about in half.
700
Evaporator-Condenser
600
Junction-Condenser
Power (W)
500
400
300
200
100
0
2
4
6
8
10
12
14
16
18
20
Tepmperature Rise (°C)
Source: ICEMCM/ICE, "Roadmaps of Packaging Technology"
22085
Figure 6-34. Ammonia Heat Pipe Condenser/Evaporator and Condenser/Junction Temperature Rise
70
Std. SEMI board/119PBGA
4 lyr board/119PBGA
60
Std. SEMI board/160PQFP
4 lyr board/160PQFP
curves regressed to a quadratic
Rja (C/W)
50
40
30
20
119 PBGA: 14 x 22mm
Die: 4 x 7mm
160PQFP: 28 x 28mm
Die: 10 x 10mm
10
Test Method: SEMI
Standard G38-87
0
0
0.5
1
Air Flow (m/s)
Source: IEEE/ICE, "Roadmaps of Packaging Technology"
1.5
2
22215
Figure 6-35. Rja Versus Air Flow Characteristics, 119 PBGA Versus 160 PQFP,
Standard and Enhanced Boards
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-29
Chip Packaging: Thermal Requirements and Constraints
The substrate is only going to be effective when there is good thermal contact between the package and board, when the board has thick power and ground planes and when there are not many
other high power devices near by. When these conditions are met, the thermal resistance between
the junction and ambient can be reduced by 50%.
WATER COOLING
The volumetric specific heat of water is 4.2J/cm3¥¡C (69J/in3¥¡C), about 3,000x that of air. The
ultimate thermal resistance of a water-cooled heat exchanger would be 0.2¡C/W at 1cm3/sec of
water flow. At a more typical 50 percent efficiency, the thermal resistance expected would be no
lower than 0.4¡C/W for 1cm3/sec flow. In the IBM 3081 TCM, the thermal resistance per
module is 0.015¡C/W with a flow rate of 40cm3/sec. This is 0.6¡C/W for a 1cm3/sec flow rate.
The heat that can be extracted for a 50¡C case-to-ambient temperature drop is diagrammed in
Figure 6-36.
Power (Watts)
10 5
10 4
10 3
10 2
1
10
100
Water Flow Rate (cm3/sec)
Source: ICE, "Roadmaps of Packaging Technology"
1,000
15814
Figure 6-36. Maximum Heat Flux Extracted by Water Cooling
(50% Efficiency, ÆTca = 50¡C)
In water-cooled systems, the thermal resistance from the junction to the case is usually higher than
the case-to-ambient. The limitations from the packaging are really based on the thermal resistance
of the junction-to-case path and the thermal spreading. A one inch thick plate of copper has a specific thermal resistance of 0.5¡C/(W/cm2). The series combination of silver-filled die attach and
the copper heat spreader would have a thermal resistance of about 0.8¡C/(W/cm2). With these
ideal conditions, a 50 watt chip would have a junction-to-case temperature drop of 40¡C. It is thus
critical to reduce the junction-to-case thermal path.
6-30
INTEGRATED CIRCUIT ENGINEERING CORPORATION
Chip Packaging: Thermal Requirements and Constraints
The limitations to the power densities that can be extracted with water cooling are set by the manufacturing costs for particular engineering solutions. Using very efficient heatsink designs based
on microchannel cooling, power fluxes of 1,000W/cm2 have been demonstrated. With these efficiencies, the thermal challenges are with the thermal resistance from the junction to the case.
Summary of the Thermal Resistance of Various Packages
The final thermal performance of a package is measured by the junction to ambient thermal resistance. Keeping the criterion of a maximum junction temperature of 90¡C, and an ambient temperature of 40¡C, the maximum temperature drop from junction to ambient is 50¡C. With this
criterion, the maximum power a package can handle for a given thermal resistance is shown in
Figure 6-37. For example, if the package has a thermal resistance of 25¡C/watt, it can handle at
most 50¡C/25-¡C/watt or 2 watts.
25 Watts
Cavity PBGA With Heat Spreader and Heat Fins
PBGA, Thermal Vias
B
PBGA,
Standard
G
A CBGA With Fins
CBGA No Fins
25 Watts
AI2O3, With Cu-W Cavity Insert and Heat Fins
P
G
A AI2O3, With Heat Fins
AI2O3, No Fins
Same as Above, No Heat Fins
M-QUADTM With Heat Fins
AI2O3, With Heat Fins
AI2O3, No Fins
PQFP
With
Heat
Slug & Heat Fins
Q
PQFP With Heat Slug
F
P
Plastic QFP with Heat Fins
MQUAD, Standard 28mm Package
Multilayer Leadframe PQFP, No Fins
Plastic QFP, No Fins
0
2
4
6
8
Power Dissipation (Watts)
10
12
Source: ROSE AssociatesICE, "Roadmaps of Packaging Technology"
22093
Figure 6-37. Power Dissipation of Various Packages in Still Air
INTEGRATED CIRCUIT ENGINEERING CORPORATION
6-31
Chip Packaging: Thermal Requirements and Constraints
6-32
INTEGRATED CIRCUIT ENGINEERING CORPORATION