System-on-a-Chip
and Interfaces
Richard Newton
University of California at Berkeley
1
System on a Chip
Framework in Which to
Understand
IMPACT OF SUBSTITUTION
Modems shipped to North America
Unit price, $
350
300
250
200
150
9,600 bps or less
100
50
0
1992
1993
1994
1995
1996
1997
1998
1999
Projected
Source: Dataquest; McKinsey analysis
2000
IMPACT OF SUBSTITUTION
Modems shipped to North America
Unit price, $
350
300
19,200 bps
250
200
150
9,600 bps or less
100
50
0
1992
1993
Source: Dataquest; McKinsey analysis
1994
1995
1996
1997
1998
1999
Projected
2000
IMPACT OF SUBSTITUTION
Modems shipped to North America
Unit price, $
350
28,800 and 33,600 bps
300
19,200 bps
250
200
150
9,600 bps or less
100
50
0
1992
1993
Source: Dataquest; McKinsey analysis
1994
1995
1996
1997
1998
1999
Projected
2000
IMPACT OF SUBSTITUTION
Modems shipped to North America
Unit price, $
350
28,800 and 33,600 bps
300
19,200 bps
250
200
150
56 Kbps
9,600 bps or less
100
50
0
1992
1993
Source: Dataquest; McKinsey analysis
1994
1995
1996
1997
1998
1999
Projected
2000
IMPACT OF SUBSTITUTION
Modems shipped to North America
Unit price, $
350
28,800 and 33,600 bps
300
19,200 bps
250
200
150
100
Avg
ASP
56 Kbps
9,600 bps or less
50
0
1992
1993
Source: Dataquest; McKinsey analysis
1994
1995
1996
1997
1998
1999
Projected
2000
WORLDWIDE SEMICONDUCTOR REVENUES
GROWING RAPIDLY
Merchant semiconductor sales, $ Billions
350
300
250
200
14%
1996-2000 CAGR
150
100
21%
1990-96 CAGR
50
19%
1985-90 CAGR
0
1985
Source:
1990
ICE, Dataquest
1995
2000
PC INDUSTRY LARGE DRIVER OF
GROWTH FROM 1985-1995
$ Billions
150.2
0.4
Military/
civil
Industrial/ aerospace
transportation
14.1
21.1
Consumer
22.3
19.1
Communications
Non-PC
computing
27.1
46.1
PCs
1985
CAGR
Source: Dataquest; ICE status
1995
34%
14%
21%
14%
14%
1%
PCs AND COMMUNICATIONS EXPECTED TO
DRIVE GROWTH THROUGH 2001
$ Billions
Military/
0.8
Industrial/
civil
17.7
transpor- aerospace
Consumer
20.1
tation
Communications
31.3
Non-PC
14.6
Computing
PCs
65.4
150.2
300.1
1995
CAGR
Source: Dataquest (October 1997)
2001
14%
10%
14%
10%
11%
8%
WINNERS HAVE PROFITED
HANDSOMELY
Financial performance of leading players
Segment
Company
Memory
(mostly
DRAM)
Micron
Microprocessors
Intel
Programmable logic
ICs
Xilinx
Average operating
margins, 1992-96
23
34
32
TSMC
Source: 10Ks; McKinsey Corporate Finance Practice; Annual reports
42
42
27
32
Foundry
Average ROIC, 1992-96
Percent
25
UNATTRACTIVE INDUSTRY RESULTS
Economic profit margin of U.S. semiconductor
companies
Percent
40
30
20
10
Created
value
0
-10
Destroyed
value
-20
-30
1970
1975
1980
1985
1990
1997
Note: Economic profit margin is weighted (ROIC-WACC) for AMD, Analog, Cypress, IDT, Intel, LSI Logic, Micron, National, VLSI (and TI from 1995)
Source: Annual reports; Compustat
INTEL’S PROFITABILITY HAS
CARRIED THE INDUSTRY
Average ROIC, 1990-97
37.6
12.9
Average WACC = 13.2
Intel
The rest
* Includes AMD, Analog Devices, Cypress, Cirrus Logic, LSI, Micron, National, VLSI, and TI
Source: Annual reports; Compustat
Background
The Seven Views of
Computer Systems
Bell, Mudge & McNamara
Source: Bill Lattin, Synopsys
The Seven Views of Computer Systems
View One:
Structural Levels of a Computer System
View Two:
Levy’s Levels of Interpreters
View Three:
Packaging Levels of Integration
View Four:
A Marketplace View of Computer Classes
View Five:
An Applications/Functional View of Computer
Classes
View Six:
The Practice of Design
View Seven:
The BLAAUW Characterization of Computer
Design
Source: Bill Lattin, Synopsys
View One: Hierarchy of Computer
Levels
Adapted from
Bell and Newell [1971]
Source: Bill Lattin, Synopsys
View Two: A Hierarchy of Interpreters
[Levy, 1974]
Source: Bill Lattin, Synopsys
View Three: Packaging Levels of
Integration
■ This
is a Structural View That Packages the Various
Components (Hardware and Software) into Levels. The
Levels for DEC Computers in 1978 Were as Follows:
➝ 9
➝
➝
➝
➝
➝
8
7
6
5
4
➝ 3
➝ 2
➝ 1
Applications
Applications Components
Special Languages
Standard Languages
Operating Systems
Cabinets (to Hold Complete Hardware
Systems)
Boxes
Modules (Printed Circuit Boards)
Integrated Circuits
Source: Bill Lattin, Synopsys
View Four: A Marketplace View of
Computer Classes
Price vs. Time for
Each Machine Class
Source: Bill Lattin, Synopsys
View Five: An Applications/ Functional View
of Computer Classes
■ PMS Level Configuration: A Configuration is Chosen to Match the
Function to Be Performed. The User (Designer) Chooses the Amount of
Primary Memory, the Number and Types of Secondary Memory, the Types of
Switches, and the Number andTypes of Transducers to Suit His Particular
Application.
■ Physical Packaging: Special Environmental Packaging is Used to
Specialize a Computer System for Certain Environments, Such as Factory
Floor, Submarine, or Aerospace Applications.
■ Data-type Emphasis: Computers are Designed with Data-types (and
Operations to Match) that are Appropriate to Their Tasks. Some Emphasize
Floating-point Arithmetic, Others String Handling. Special-Purpose Processors,
Such as Fast Fourier Transform Processors,Belong in This Category Also.
■ Operating System: The Generality of the Computer is Used to Program
Operating Systems That Emphasize Batch, Time Sharing,Real-Time, or
Transacting Processing Needs.
Source: Bill Lattin, Synopsys
View Six: The Practice of Design
Hardware Development
Costs for Developing a
$50K Processor in ‘74
[Phister,1976]
Source: Bill Lattin, Synopsys
View Seven: The Blaauw Characterization of
Computer Design
Characteristics of Design Areas
Architecture
Implementation
Realization
Purpose
Function
Cost and
Performance
Buildable and
Maintainable
Product
Principles of
operation
Logic design
Release to
manufacturing
Language
Written
algorithms
Block diagram,
expressions
Lists and
diagrams
Quality
measure
Consistency
Broad scope
Reliability
Meanings
(used herein)
ISP
Machine ISP
RT level machine;
microprogrammed
sequential machine
(at logic level)
Physical
realization;
physical
implementation
Source: Bill Lattin, Synopsys
The Five Views of System on a Chip
View One:
Semiconductor Process & Packaging View
View Two:
IP Functional View
View Three: IP Design Methodology View
View Four: System Design Methodology View
View Five:
System Software View
Source: Bill Lattin, Synopsys
View One: Semiconductor Process &
Packaging View
■ SIA
Roadmap
➝
T HE CHALLENGES OF CHANGING CHIPS
Ca te gory
Proble m
Ke y parame te rs
tendency
Complexity
increase
W ill challenge
fault isolation
Tre nds
1995
1998
2001
2004
2007
2010
12
14
26
50
210
430
900
4-5
1350
5
2000
5-6
2600
6
3600
6-7
4800
7-8
Chip size
250 mm 2
300 mm 2
360 mm 2
430 mm 2
520 mm 2
620 mm 2
Number of logic
transistors, in millions
I/O
Wiring levels
Dimension
W ill require
Minimum feature size
0.35 µm
0.25 µm
0.18 µm
0.13 µm
0.1 µm
0.07 µm
decrease
higher-powered,
slower inspection
Minimum defect size
Interlevel contact
diameter
Gate dielectric
thickness
0.12 µm
0.4 µm
0.08 µm
0.28 µm
0.06 µm
0.2 µm
0.04 µm
0.14 µm
0.03 µm
0.11 µm
0.02 µm
0.08 µm
7-12 nm
4-5 nm
4-5 nm
4-5 nm
<4 nm
<4 nm
Logic clock speed
Threshold voltage
variation
350 MHz
70 mV
450 MHz
50 mV
Supply voltage
Metal wiring
2.5-3.3 V 1.2-2.5 V 1.2-1.8 V 1.2-1.5 V
AI
Performance
acceleration
New materials
New styles of
packaging
W ill raise sensitivity
to subtle, hard-to
find facts
W ill need new
delayering
techniques
W ill force physical
fault isolation
to be done from
back of chip
Insulator
Flip-chip,
chip-on-board
(COB), chip-on-chip
Oxide
−
600 MHz 800 MHz 1000 MHz 1100 MHz
40 mV
30 mV
25 mV
20 mV
<1.2 V a
AI, Cu
<1.2 V a
Oxide, air, polyimide, low dielectric
−
−
−
−
−
Data from National Technology Roadmap f or Semiconductors, 1994, Semiconductor Industry A ssociation
Source: Bill Lattin, Synopsys
Conclusions From View One
■20M Gates will be Here in 2000
■Multiple Power Supplies will Require DCL
Descriptions (Equations vs Tables)
■Copper is Here Now (6 Layers)
■Trench DRAM Hybrid Process in 1999
■I/O Continue to Grow (Power Management
EMI Analysis & Synthesis)
Source: Bill Lattin, Synopsys
View Two: IP Functional View
■ Microprocessor
■ Memory Sub System
■ ASIC (Customer’s Logic)
■ DSP
■ RF (Analog)
■ Mixed Signal
■ I/O Systems
■ On Chip Bus
Source: Bill Lattin, Synopsys
In
te
gr
at
io
n
An
al
ys
is
Cr
ea
tio
n
View Three: IP Design Methodology
System
RTL
Physical
Source: Bill Lattin, Synopsys
System-on-a-Chip IP Creation and
Analysis Flow
Architectural Design
Digital Control
Memory
Datapath
RTL
Functional
Description
Memory Behavior
Model
Logic
Synthesis
Logic Design
& Simulation
Decoder/
Periphery Design
Logic
Verification
Performance
Optimization
Core Cell
Sense Amp
Datapath
Compiler
Analog
Analog Functional
Model
Analog Circuit
Design & Sim.
Custom
Layout
Std Cell
P&R
Chip Assembly
Block P&R
DRC/LVS/Extraction
Parasitic Reduction
Final Power &
Reliability Check
Full Chip
Timing Verification
Full Chip
Func Simulation
Source: Bill Lattin, Synopsys
System-on-a-Chip Design Flow
Architectural Design
Digital Control
Memory
Datapath
RTL
Functional
Description
Logic
Synthesis
Logic Design
& Simulation
Logic
Verification
Performance
Optimization
Datapath
Compiler
Global
Timing/Power
Memory Behavior
Model
Analog
Analog Functional
Model
Decoder/
Periphery Design
Block
Timing/Power
Core Cell
Sense Amp
Analog Circuit
Design & Sim.
Custom
Layout
Physical
Floorplan
Std Cell
P&R
Chip Assembly
Block P&R
DRC/LVS/Extraction
Parasitic Reduction
Final Power &
Reliability Check
Full Chip
Timing Verification
Static Timing
Models
Functional
Models
Full Chip
Func Simulation
Source: Bill Lattin, Synopsys
System-on-a-Chip Integration Flow
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Physical
Manufacturing
Reliability
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Power
Noise
System
Hardware/Software
Partitioning
Timing
Test
System
Physical
Floorplan
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Functional
Power Models
Timing Models
Bus Functional Models
Models
Software
Source: Bill Lattin, Synopsys
View Four - System Design Methodology
■ Problems Migrate to the IP Block Boundaries
■ IP Blocks Effect Each Other
■ Tools Must Enforce IP Block Boundaries
■ IP Blocks Need Different Analysis Tools
✔Digital IP Blocks
✔Mixed Signal IP Blocks
✔RF IP Blocks
✔Memory IP Blocks
Source: Bill Lattin, Synopsys
SoC Model Views
Bus Functional
Full Function Cycle
Timing Model
Full-Function with Timing
Software Design
Set
Physical Design
n
e
tur
tec
i
h
Arc
Power Design
uctio
Manufacturing Design
Testbench/Tests
Instr
Automatic
Model
Creation
Integration
Timing Design
Core Design
Core Views
Functional Design
Core Creation
Test Model
Post-Design
Remodeling
Floorplan/Phy Model
Electrical Rule Model
Place & Route
and
Chip Finishing
Source: Bill Lattin, Synopsys
Tradeoffs Among Types of System
Designs
High
Flexibility
Low
Low
High
Predictability, performance, and complexity
Source: Bill Lattin, Synopsys