Isolated gate driver rejects hybrid powertrain
drive common mode noise
Choo Mei Zhen, Avago Technologies - September 15, 2011
One of the challenges engineers often encounter while designing a practical and reliable powertrain
drive is the existence of high common mode noise. Common mode noise (also known as dV/dt noise)
is generated naturally within a system when there is high frequency switching between high voltage
supplies. This article will discuss the possible sources of dV/dt noise in a hybrid powertrain drive and
suggest solutions to the problem.
Sources and effects of powertrain drive common mode noise
A typical block diagram of a hybrid powertrain drive is shown below. When the gate drivers switch
the high side and low side IGBTs (insulated gate bipolar transistors) in sequence, high dV/dt noise is
generated. For example, a typical powertrain connected to a high voltage 400 VDC with the
switching rise and fall time of 50 ns, will generate dV/dt noise of 400V/50 ns ~ 8 kV/μs whenever the
gate driver switches.
When faced with short circuit conditions due to faults, additional overshoot voltage (V=L*di/dt) will
add on to the DC rail voltage. This additional overshoot voltage is caused by large short circuit
current transient (di/dt) flowing through the circuit stray inductance, L. The gate driver circuit must
be capable of handling this additional dV/dt noise so as to maintain control and execute the correct
protection protocol.
Additionally, the need for higher DC rail supply voltage for larger hybrid vehicles, such as trucks and
buses, and the need for faster switching frequency to reduce conduction loss, have increased system
requirements for higher dV/dt noise rejection. Normally, having a hybrid powertrain drive with dV/dt
noise rejection of 15kV/μs is essential to maintain overall system performance, reliability, and
robustness.
When dV/dt noise couples through parasitic capacitances within the system and causes undesired
voltage transition, it becomes a serious threat. It may eventually cause the system to lose control,
i.e. arm short, false feedback, etc. Although dV/dt noise is very much undesired, it exists naturally
within the powertrain drive as explained earlier. Designers have no choice but to identify and tackle
all possible coupling paths of dV/dt noise. The figure below illustrates the possible parasitic
capacitance paths existing within a system.
Solutions to parasitic capacitance
To provide adequate rejection for common mode noise, designers have to tackle the aforementioned
parasitic capacitances within the system.
First of all, designers should aim to minimize the gate driver external/layout parasitic capacitance
through efficient layout design. It is essential to maintain sufficient isolation spacing between the
two adjacent low voltage and high voltage regions of the circuit board. Insufficient spacing will
reduce the effective isolation and increase parasitic coupling, which will degrade common mode
rejection performance.
Additionally, high impedance signal lines that are more sensitive to dV/dt noise (i.e. VIN+, VIN- and
DESAT pins of the ACPL-38JT optocoupler in the figure below) should be kept as far away as
possible from the adjacent isolated region to avoid parasitic coupling. It is always recommended to
place bypass capacitors close to the driver supply pins to keep the supply current loop as small as
possible and minimize the stray inductance coupling by common mode transient current. The figure
below shows the comparison between a dV/dt sensitive layout (top) and a recommended layout
(bottom) using the ACPL-38JT optocoupler.
Secondly, designers should address the Miller capacitance coupling. When dV/dt noise couples
through the Miller capacitance during switching, it will induce transient noise current. This
transient noise current will flow through the stray inductance existing along the layout paths from
the IGBT gate to the gate driver, and it will affect the gate control voltage. To minimize the effect of
dV/dt noise through the Miller coupling and to provide cleaner switching waveforms, designer
should keep the IGBT gate charging and discharging loop as small as possible. An example of a gate
driver current buffer circuit to the IGBT is shown below (top), and a recommended layout is shown
at the bottom.
Internal parasitic capacitances
Finally, designers should choose the right isolator to limit or reject the common mode noise coupled
through the internal parasitic capacitances. There are various isolation techniques available on the
market, such as optical isolation (also known as optocoupler), magnetic (transformer) isolation,
capacitive isolation, etc. See below for basic internal block diagrams of an optocoupler, transformer
isolator, and capacitive isolator.
Among them, the optocoupler is known as one of the most popular and effective isolation techniques
to provide high common mode rejection. As an example, Avago Technologies optocouplers offer
the following advantages to enhance common mode rejection:
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Low impedance LED drive: The LED shows low impedance when it turns on, therefore it is less
susceptible to common mode transient current induced by dV/dt noise. Also, the LED junction
capacitance of ~80 pF helps to reject high frequency common mode noise.
Internal shield at the photodiode and IC side of the optocoupler: A transparent shield allows an
optical signal to transmit, and at the same time, helps to redirect the common mode transient
current to the ground instead of affecting the detector and IC circuit.
The internal shield is usually not implemented in transformer and capacitive isolators. This is mainly
because the internal shield will block the intended magnetic signal coupling in the transformer
isolator and the capacitive signal coupling in the capacitive isolator. Without the shield, unintended
dV/dt noise could couple through the same channel as the signals and affect the control signal.
Benchmark CMR tests of different isolators
In order to benchmark the common mode rejection (CMR) capability of the various isolator types,
some individual gate drivers have been chosen to undergo in-house benchmark CMR testing. Typical
benchmark CMR test setup for the isolated gate driver is shown below.
The benchmark CMR test results showed that the optocoupler has better CMR than transformer and
capacitive isolators. The Avago Technologies gate drive optocoupler (ACPL-38JT) tested is capable of
withstanding high common mode transient without failure and achieves minimum 30 kV/μs CMR for
both output high (CMH) and output low (CML) levels. This performance is favorable compared to an
available transformer isolator and capacitive isolator. A summary of the test results is shown in this
table.
Taking a closer look and comparing the CMH waveforms of the three different isolators, no failure is
seen from the CMH waveform of the gate drive optocoupler. The first figure below shows the Avago
gate driver optocoupler is capable of maintaining a high output state of dV/dt of 67 kV/μs and
VCM=1.5 kV, resulting from the low impedance LED drive and internal shielding that enhances the
gate driver CMR.
The next figure shows the transformer isolator failed the benchmark CMH test, with the gate driver
not capable of maintaining its output at high even if the VCM is set to 500V with the slow rise time
of 160 ns (dV/dt~2.5 kV/μs).
Likewise, last figure shows the capacitive isolator CMH level drops to less than 15 kV/μs when the
VCM rises to 900V, and failure is observed when VCM rises to 1 kV and above for the output high
test (dV/dt~4.5kV/μs).
Conclusion
Hybrid powertrain drives deal with large amounts of dV/dt noise while operating in harsh
automotive environments. In order to maintain system reliability and ensure passengers safety,
designers should minimize the threat of unpredicted common mode noise by employing good layout
and system design and by choosing the right isolation device. A gate driver optocoupler that features
low impedance LED drive and internal shielding is effective in rejecting high common mode
transient noise.
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