IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
1
Analytical Phase Noise Modeling and Charge Pump
Optimization for Fractional-N PLLs
Frank Herzel, Sabbir A. Osmany, and J. Christoph Scheytt, Member, IEEE
Abstract—We present an analytical frequency-domain phase
noise model for fractional-N phase-locked loops (PLL). The
model includes the noise of the crystal reference, the reference
input buffer, the voltage-controlled oscillator (VCO), the loop
filter, charge pump device noise, sigma-delta modulator (SDM)
noise including its effect on the in-band phase noise. Thermal
device noise of the charge pump and the turn-on time of the
charge pump output current are found to be limiting the inband phase noise of state-of-the-art synthesizers. Device noise
considerations for bipolar transistors and MOSFETs suggest
the use of CMOS-only charge pumps (CP), even in BiCMOS
technologies. We present a noise-optimized CMOS CP, specifically
designed for a dual-loop PLL architecture using two CPs. This
PLL architecture keeps the DC output voltage of the noiserelevant CP and the phase noise spectrum constant, regardless
of temperature variations.
Index Terms—charge pump, fractional-N PLL, phase noise.
I. I NTRODUCTION
P
HASE noise limits the performance of wireless and highspeed digital systems. Frequency synthesizers are commonly characterized in the frequency domain by phase noise
spectra. Jitter is the corresponding time-domain equivalent and
is used for characterizing clock generation circuits as well as
clock and data recovery (CDR) circuits. Several theoretical
publications on phase noise and jitter modeling of PLLs have
appeared during the last decade, e.g. [1]-[4]. An accurate
prediction of phase noise requires simulation on transistor
level. However, a complete transistor-level simulation of a
PLL is difficult or impossible, even in the absence of noise
sources. This is due to very different time scales of the VCO
dynamics and the PLL settling. In order to simulate the PLL
including nonlinear effects, behavioral system-level simulations are helpful [5]-[11]. An even more simplified approach is
linear analytical phase noise modeling, where the main noise
contributions are described by adjustable parameters. These
models correctly reflect the dependence of the phase noise
spectrum on design parameters like loop filter values, charge
pump current, divider ratios, etc., but they inevitably need
some fit parameters. These can be determined from theory,
simulation or measurements.
In this paper, we consider only charge-pump PLLs due to
their popularity in state-of-the-art synthesizer design. For the
Manuscript received October 20, 2009; revised December 8, 2009, accepted
December 22, 2009.
The authors are with IHP, Im Technologiepark 25, D-15236 Frankfurt
(Oder), Germany (e-mail: herzel@ihp-microelectronics.com).
Copyright (c) 2009 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending an email to pubs-permissions@ieee.org.
same reason, we assume that the fractional-N divider ratio
is obtained by using a sigma-delta modulator (SDM). The
SDM in a fractional-N synthesizer inevitably results in large
momentary phase errors, even in the absence of noise. This
makes the description difficult within an analytical model. Our
approach is based on the linear model presented in [12], where
the quantization noise spectrum for a multi-stage noise shaping
(MASH) SDM was included based on the expression given in
[13]. Another critical problem related to SDM noise, which
has been disregarded in [12], is the turn-on time of the charge
pump (CP), resulting in nonlinearities in the phase detector
(PD) as described in [14]-[20]. The combination of an SDM
with a nonlinear PD may fold the SDM noise from large
frequency offsets down to the in-band region of the spectrum.
This effect has been modeled analytically in [18]-[20]. It can
be interpreted as self-mixing of the SDM noise in the nonlinear
PD, which is composed of phase-frequency detector (PFD) and
CP. To avoid confusion with CP device noise and linear SDM
noise, this noise contribution will be referred to as PD noise.
This paper presents an analytical phase noise model for a
PLL including PD noise. The modeled phase noise spectrum
and its components are visualized by MATLAB. Finally, a
simple CP architecture is suggested, which allows CP device
noise and PD noise to be reduced drastically.
II. PLL P HASE N OISE S OURCES
In a charge-pump PLL as used in modern communication
systems, the output phase of the VCO is divided by N and
compared with a reference phase in a PFD. A charge pump
current proportional to the phase error is produced, low-pass
filtered, and applied to the control input of the VCO as shown
in Fig. 1. In fractional-N PLLs the divider ratio is controlled
by an SDM.
REF
PFD
CP
LPF
VCO
Multi-Modulus
Frequency Divider
Ctrl
Fig. 1.
Sigma-Delta
Modulator
Schematic view of a fractional-N synthesizer architecture.
The output voltage of a PLL can be described as
Vout (t) = V0 cos[ω0 t + φout (t)] ,
(1)
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
where V0 is the amplitude, f0 = ω0 /(2π) is the oscillation
frequency, and φout (t) is the excess phase. In this paper, the
term phase noise spectrum refers to the two-sided power spectral density (PSD) of φout in units of rad2 /Hz or dBrad2 /Hz,
when expressed in decibel. In the latter case, the phase noise
is almost identical to the single-sideband phase noise £ in
units of dBc/Hz, if and only if white noise sources dominate
the PLL noise [4]. The presence of flicker noise results in
the well-known 1/f 3 shape of the close-in VCO phase noise
spectrum, whereas the single-sideband phase noise spectrum
is a Voigt function, which resembles a Gauss function at very
small offsets [21]. In this paper, we will include the following
seven noise sources:
•
•
•
•
•
•
•
reference noise,
reference input buffer noise,
VCO noise,
loop filter noise,
charge pump device noise,
Σ − ∆ quantization noise,
phase detector noise.
Fig. 2 shows the linearized model of a PLL as presented
in [12]. Of special interest in this paper is the PD composed
of PFD and CP, which converts a phase error φ at the input
into an output current I averaged over one comparison period.
For an ideal PD, the gain KPD = dI/dφ is given by ICP /2π,
where ICP is the CP current in the ON state. The loop filter
transimpedance is denoted as F (s), and the VCO gain is
KVCO /s. N is the divider ratio of the PLL. Note that the VCO
ICP / 2π
π
F(s)
ICP F (s)KVCO
.
(2)
2πs
For the third-order filter according to Fig. 3, we obtain the
H0 =
R5
R3
R1
R4
Z1
Z2
C1
Third-order loop filter.
KVCO / s
F (s) =
where
Z1 =
and
1/Z2
1
,
sC3 1/Z1 + 1/Z2
1
R1 +
sC1
1/N
Linearized PLL model.
gain KVCO = dω/dVctrl refers to the angular frequency and
||
1
|| R4 || R5
sC2
(3)
(4)
1
.
(5)
sC3
Unlike in [12], we have incorporated a voltage divider at the
filter input here, which is useful in the context of a dual-loop
PLL as discussed in [23]. For a traditional single-loop PLL,
R4 and R5 should be omitted or huge values should be used
in the noise model.
In the following section, the noise sources mentioned in
Section II will be analytically described.
Z2 = R3 +
IV. P HASE NOISE POWER SPECTRAL DENSITY
The noise sources discussed in this section are uncorrelated.
Therefore, the phase noise PSD at the PLL output is the
superposition of the seven mentioned noise contributions, each
multiplied by its specific noise transfer function. Emphasis is
placed on those components, which are not or only insufficiently included in [12], namely, input buffer noise, charge
pump noise and phase detector noise.
A. Reference Noise
The phase noise contribution of the reference oscillator as
a function of the frequency offset f is modeled by
SREF (f ) = SREF (∆f )
Fig. 2.
C3
C2
transimpedance
III. L INEARIZED PLL M ODEL
+
is given in units of rad/s/V. The forward path transfer function
H0 is given by
Fig. 3.
The latter contribution represents the noise folding of the SDM
quantization noise in the nonlinear phase detector. Noise in
the frequency dividers is disregarded in this paper, which is
focused on phase detector design. It could be added to the
phase noise model, if measured phase noise spectra at the
feedback divider output and the reference divider output are
available. As an alternative, the white spectrum of the inputreferred divider noise can be modeled as a function of delay
mismatch in the feedback divider [15], [19]. Another type of
noise is caused by digital circuits such as frequency dividers,
SDM and PFD, affecting the performance of noise-sensitive
analog circuits through supply and substrate coupling. Supplyand substrate-induced jitter may easily exceed device-noiseinduced jitter in high-speed digital systems [22].
φin
2
(∆f )2
+ SREF,floor ,
f2
(6)
where SREF (∆f ) is the phase noise at a specific offset ∆f
in the -20dB/decade region of the spectrum and SREF,floor is
the noise floor of the reference. The reference noise spectrum
at the output reads
out
SREF
= SREF N 2 |H|2
(7)
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
with the transfer function given by
H=
H0 /N
.
1 + H0 /N
(8)
B. Reference Input Buffer Noise
As discussed in [23], the noise of the reference buffer
may become a major contributor to the output phase noise.
We use an ESD protected CMOS inverter chain as input
buffer shown in Fig. 4. The first CMOS inverter converts the
3
where kB is Boltzmann’s constant, T is the absolute temperature, and YFIL = 1/Z1 + 1/Z2 is the complex admittance of
the filter from the charge pump output to ground. The resulting
noise spectrum at the output is given by
2
2 KV CO 2
out
SFIL (s) = SFIL (s) |F (s)| |1 − H| .
(13)
s E. Charge Pump Device Noise
For a PLL to work at a given bandwidth, a large charge
pump current is generally favorable in order to reduce the
loop filter resistance R1 . The large current, however, produces
significant current noise. The time between two phase comparison instants is referred to as Ts = 1/fs , where fs is the
frequency at the PFD input at which the PLL phase error is
sampled.
In order to describe the thermal CP noise qualitatively, we
write the two-sided thermal drain current noise PSD of a
MOSFET according to [24] as
SiMOS = γ 2kB T gDS0 ,
Fig. 4.
Proposed input buffer (a) and noise model (b).
crystal oscillator signal into a rectangular signal on the chip.
Assuming a sinusoidal reference signal with peak amplitude
V0 , we obtain for the phase noise at the PLL output
out
=
SBUF
SVBUF 2
N |H|2 ,
V02
(9)
where SVBUF is the input-referred noise voltage PSD. The
transconductance of the MOSFETs (∝ W/L) must be large
enough to make this noise negligible.
C. VCO Noise
The phase noise of a free running oscillator is modeled by
(∆f )2
fcVCO
SVCO (f ) = SVCO (∆f )
+ Sfloor , (10)
1
+
f2
f
where SVCO (∆f ) is the phase noise at a specific offset ∆f in
the -20dB/decade region of the spectrum, fcVCO is the 1/f 3
noise corner of the VCO, and Sfloor is the noise floor of the
VCO. The PLL output noise due to VCO phase noise is given
by
out
SVCO
= SVCO |1 − H|2 ,
(11)
where H is given by (8).
where gDS0 is the channel conductance with zero drain-source
voltage, and γ is between 2/3 and 1 for long-channel devices
and somewhat larger for short devices, typically 1-3. This type
white
of the charge
of noise results in a white noise spectrum SCP
pump described by one parameter. This parameter can be fitted
to measurements or simulated by periodic steady-state analysis
(PSSA) [8]. Thermal noise must be multiplied by the CP duty
cycle αCP = TON /Ts , where TON is the CP activation time.
In addition to thermal noise, CPs also exhibit flicker noise
2
(1/f noise). The flicker noise PSD is proportional to αCP
[25].
This is due to the large auto-correlation time of this type of
noise, which is assumed to be much larger than Ts . Adding
the two noise contributions, we obtain
αCP fc
white
,
(15)
SCP = SCP
αCP 1 +
f
where fc is the 1/f noise corner frequency of the transistor.
Note that the flicker noise corner of the CP scales with αCP ,
which usually makes flicker noise small compared to thermal
noise, unless a large CP duty cycle is used. For the white noise
white
current PSD normalized to the CP current SCP
/ICP we
−19
found a value of 6×10
A/Hz for the cascode CP from [23].
This value was obtained by a PSSA followed by a periodic
noise analysis using Virtuoso Analog Design Environment.
More details will be given in Section VI. The noise spectrum
at the PLL output reads
2
2
2 KVCO out
|1 − H| .
(16)
SCP = SCP |F (s)| s F. Sigma-Delta Quantization Noise
D. Loop Filter Noise
We model the noisy loop filter by a noise current in parallel
with a noise-less admittance. The two-sided power spectral
density of noise current in can be expressed as
SFIL (s) = 2kB T Re(YFIL (s)) ,
(14)
(12)
The quantization noise spectrum for an m-th order MASH
type SDM is given by [13]
2(m−1)
(2π)2
πf
SSDM =
2 sin
,
(17)
12fs
fs
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
where m is the order of the modulator. The SDM noise
spectrum at the PLL output is given by
out
SSDM
= SSDM |H|2 .
(18)
G. Phase Detector Noise
If both UP and DOWN current are changing in the steady
state of the PLL, then the phase detector gain will be discontinuous, if UP and DOWN currents do not match. This
case has been discussed in [20]. For a low-noise PLL in
fractional-N mode, an offset current at the CP output is highly
recommended as shown in [16]. If the offset current is a
sufficiently large down current, then only the UP current
will respond to phase error changes in the steady state. This
improves the linearity of the phase detector and reduces phase
noise significantly. In this case, the output current I of the CP
is a continuous function of the phase error φ at the PFD input,
ideally a linear function. In reality, the limited turn-on time
of the current will result in deviations from this behaviour.
Taking the nonlinearities into account in the lowest order, we
can write the current as
β
(19)
I = φ KPD (1 + φ) ,
2
where KPD is the linear PD gain, and β represents the firstorder nonlinearity. It can be determined from
dI/dφ = KPD (1 + β φ) ,
(20)
resulting in β = (d2 I/d φ2 ) /KPD . The linear term in (19)
produces the quantization noise spectrum described in Section IV-F, and the quadratic term will cause the PD noise
discussed in this sub-section. Third-order nonlinearities in the
PD transfer function have been disregarded in this paper. Such
nonlinearities have been modeled in [10] in the zero phase
offset region. Fig. 5 shows the simulated PD gain dI/dφ
as a function of the phase error at the PFD input for the
cascode CP used in [23]. Here, the sampling frequency fs was
Gain [mA/rad]
−∞
with ω = 2πf and the brackets < ... > denoting the stochastic
(ensemble) average. Substituting (19) into (21) we obtain
2
2
SI (f ) = KPD
< I1 > +KPD
β < I2 > +
2
β2
KPD
< I3 >
4
(22)
with the integrals
I1 (f ) =
Z
∞
φ(t + τ ) φ(t) exp(−jωτ ) dτ,
(23)
φ(t + τ ) φ2 (t) exp(−jωτ ) dτ,
(24)
−∞
I2 (f ) =
Z
∞
−∞
and
I3 (f ) =
Z
∞
φ2 (t + τ ) φ2 (t) exp(−jωτ ) d τ.
(25)
−∞
The first term in (22) corresponds to the term SSDM discussed
in Section IV-F. The other terms describe noise folding contributions. If the process φ(t) is symmetric with respect to the
sign, positive and negative contributions in I2 will cancel out.
In order to calculate I3 , we decompose φ(t) into a Fourier
integral
Z
∞
φ(f ) exp(jωt) df.
φ(t) =
(26)
−∞
Equation (25) then reads
Z Z Z Z Z
I3 (f ) =
φ(f1 ) φ(f2 ) φ(f3 ) φ(f4 )
exp[jω4 t] exp(−jωτ ) dτ df1 df2 df3 df4 ,
Slope: 0.035 mA / rad
−1.20
2
−1.25
linear fit
δ(f1 + f2 − f ) exp[jω1 t] exp[jω2 t]
simulated
−1.30
exp[jω3 t] exp[jω4 t] df1 df2 df3 df4 .
−2
−1
0
1
(27)
where all integrals are to be taken from −∞ to +∞. Integration with respect to τ yields
Z Z Z Z
I3 (f ) =
φ(f1 ) φ(f2 ) φ(f3 ) φ(f4 )
β=0.028 / rad
2
Phase Error [rad]
Fig. 5.
offsets in the nonlinear PD. Note that the PD gain is a fairly
linear function of the input phase error over a wide range. In
other words, the parabolic approximation of the PD transfer
function given by (19) seems reasonable for this particular CP.
In order to calculate the two-sided spectrum of the CP current,
we write it as the Fourier transform of the auto-correlation
function (ACF) according to the Wiener-Khintchine theorem
Z ∞
hI(t + τ ) I(t)i exp(−jωτ ) d τ
(21)
SI (f ) =
exp[jω1 (t + τ )] exp[jω2 (t + τ )] exp[jω3 t]
−1.15
−1.35
4
Phase detector gain versus input phase error for cascode CP.
100 MHz, and the CP current was as large as 8 mA for a low
in-band phase noise. As evident from Fig. 5, the PD gain is not
constant but depends on the phase error, which causes noise
folding in the PLL. More specifically, the quantization noise
described in Section IV-F is folded down to low frequency
Integration with respect to f2 , f3 and f4 results in
Z ∞
φ(f1 ) φ(f − f1 ) φ2 (t) df1 .
I3 (f ) =
(28)
(29)
−∞
Taking the average on both sides yields
Z ∞
2
< φ(f1 ) φ(f − f1 ) > df1 .
< I3 (f ) >= σφ
(30)
−∞
The PD noise is basically a convolution of the SDM phase
noise with itself, multiplied by the variance of the phase. In
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
the context of close-in phase noise, the low-frequency limit is
relevant. We obtain for f = 0
Z ∞
< |φ(f1 )|2 > df1 ,
(31)
< I3 (0) >= σφ2
−∞
where we have exploited the property φ(−f ) = φ∗ (f ) for the
real-valued process φ(t). For the PD noise we obtain
2
2
KPD
β2
2 KVCO 2
out
< I3 (f ) > |F (s)| SPD (f ) =
|1 − H|
4
s (32)
where the same transfer function as for the CP noise current
was used.
For Gaussian noise of φ, we can further simplify the result
for the in-band phase noise due to the nonlinear PD. The
net charge delivered by the charge pump and the resulting
squared phase error φ2 are sampled at the rate fs = 1/Ts .
From the Nyquist-Shannon sampling theorem we know that
this sampled process can be expressed by a continuous-time
signal the spectrum of which has no Fourier components
above the Nyquist frequency fs /2. We assume similarly to
[18] and [20] that the spectrum Sφ2 (f ) of φ2 is white for
−fs /2 < f < fs /2. The variance of φ2 then follows by
integration of Sφ2 (f ) and reads
(33)
The quadratic term in (19) results in the PD noise current
spectrum
2
2 β
Sφ2 .
(34)
SPD = KPD
4
Substituting (33) into (34) and multiplying the result by the
noise transfer function, we obtain
out
(f )
SPD
=
2
KPD
β2 < φ4 > − < φ2 >2 ×
4 fs
2
2 KVCO 2
|F (s)| |1 − H| .
s phase noise is proportional to σφ4 , that is, a reduction of σφ by
a factor of two will lower the phase noise by 12 dB. Therefore,
for a relatively poor PD linearity as in [23] a single-loop
SDM might be the better choice, since the momentary phase
error and σφ are lower than for a MASH type SDM [14]. A
reduction of the nonlinearity parameter β by a factor of 10
will reduce the in-band PD noise by 20 dB as evident from
(38). Therefore, a MASH type SDM might be the better choice
for a highly linear PD as proposed in Section VI. It has the
advantage of easy integration in CMOS or BiCMOS and is
unconditionally stable.
V. PLL P HASE N OISE S PECTRUM
Since the noise sources are uncorrelated, the corresponding
noise spectra must be added to obtain the total phase noise
spectrum at the PLL output given by
out
out
out
S out (f ) = SREF
(f ) + SBUF
(f ) + SVCO
(f ) +
out
out
out
out
SFIL (f ) + SCP (f ) + SSDM (f ) + SPD
(f ) , (39)
out
out
out
out
out
where SREF
(f ), SBUF
(f ), SVCO
(f ), SLPF
(f ), SCP
(f ),
out
out
SSDM (f ), and SPD (f ) are the phase noise contributions of the
previously discussed noise sources referred to the PLL output.
The rms phase error [degree] at the PLL output, sometimes
called absolute phase jitter, is given by
sZ
∞
◦
180
2 S out (f ) df .
(40)
σφout =
π
0
Fig. 6 shows the simulated phase noise spectrum and
the components for a 10 GHz frequency synthesizer, which
employs a cascode charge pump. Here, the model parameters
-60
σφ=1.43o
-70
(35)
For a high order of the SDM, the probability density of φ
is approximately Gaussian. By using partial integration, we
obtain the averages in (35) given by
Z ∞
2
φ2 exp (−φ2 /2σφ2 ) dφ = σφ2 (36)
< φ2 >= √
2πσφ 0
CP
Phase Noise [dBc/Hz]
σφ2 2 =< φ4 > − < φ2 >2 = Sφ2 fs .
5
-80
Total
REF
PD
-90
VCO
BUF
-100
-110
SDM
LPF
-120
and
< φ4 >= √
2
2πσφ
Z
0
-130
∞
φ4 exp (−φ2 /2σφ2 ) dφ = 3σφ4 . (37)
By substituting (36) and (37) into (35) we finally obtain
2
2
KPD
β 2 σφ4
2
2 KVCO out
|1 − H| . (38)
SPD (f ) =
|F (s)| 2 fs
s Note that we have a close similarity to the analytical result of
Mao [20], where β 2 /2 corresponds to the mismatch parameter
γ in [20] and σφ2 corresponds to σ(|∆φ|). The same result
could not be expected, since [20] considers the case of a
discontinuous PD gain due to mismatch between UP and
DOWN current, whereas we consider the case of a continuous
PD gain realized by an offset current at the CP output. The
-140
102
103
104
105
106
107
108
Frequency Offset [Hz]
Fig. 6. Modeled phase noise spectrum for a 10 GHz synthesizer using a
cascode charge pump.
have been adapted to measurements on the experimental dualloop PLL presented in [23]. For space limitations, we only
sketch this process here. First, the noise of the 100 MHz
crystal oscillator mounted on the PCB was measured by
a spectrum analyzer. Subsequently, the noise of the input
buffer was measured using small sinusoidal input signals to
maximize the reference buffer noise. The VCO noise spectrum
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
was determined from phase noise measurements on the freerunning oscillator. For the noise contributions of the loop filter
and the SDM no parameters but the filter values and the SDM
order are required. In order to model the PD noise, the rms
phase error σφ was estimated from MATLAB simulations
and the curvature parameter β was obtained from transient
circuit simulations using the simulator Virtuoso Analog Design
Environment. Charge pump device noise was also modeled by
circuit simulation. Details of these simulations will be given
in Section VI-C.
Unlike in traditional PLLs, the VCO phase noise is bandstop filtered due to the presence of the voltage divider R4/R5
at the charge pump output as shown in Fig. 3. For the same
reason, all other noise transfer functions are modified at low
frequencies. These modifications are not critical, provided
that the biasing resistors are not too small. The relatively
high level of PD noise can be explained by the high PLL
output frequency of 10 GHz in conjunction with strong PD
nonlinearity and the employment of a MASH type SDM,
which results in a large rms phase error in fractional-N mode.
In our example, the PD noise due to CP nonlinearity and the
CP device noise dominate the in-band phase noise. This was
the main motivation for improving the CP with respect to
linearity and device noise as discussed in the following section.
VI. S UGGESTED N OVEL C HARGE P UMP
In this section, we will consider the output noise PSD of a
bipolar transistor and a MOSFET. The potential of MOSFETs
with large gate-source voltages in the context of low-noise
CPs is outlined. This is followed by a brief description
of a low-noise dual-loop PLL architecture with CP output
biasing. Subsequently, we describe a simple CP architecture
specifically designed for VCO fine tuning using this PLL
architecture. An improvement by 10 dB over the existing
design from [23] with respect to CP thermal device noise and
PD noise is predicted.
A. Transistor Noise Considerations
This paper was motivated by the desire to improve the synthesizer for space applications in SiGe-BiCMOS technology.
BiCMOS technologies offer the opportunity to choose between
bipolar transistors and MOSFETs for the best design of each
building block. Generally, bipolar transistors have the reputation to provide better high-frequency noise performance than
MOSFETs, which is only partly true. This reputation mainly
results from the large transconductance of (hetero-) bipolar
transistors compared to MOSFETs. While this advantage is
crucial for amplifiers, this is not necessarily the case for other
circuits like charge pumps. Here, the white device noise in the
output circuit (drain or collector) must be compared for the
two devices. A transformation to the gate or base terminal as
typically performed in low-noise amplifiers is not meaningful
here. In the following, we compare the white output noise
power spectral densities (PSD) for the two types of devices.
The two-sided thermal drain current noise PSD of a MOSFET was according to (14)
SiMOS = γ 2kB T gDS0 .
(41)
6
In saturation, the transconductance gm is given by
sat
gm
= 2ID /Vov = gDS0 ,
(42)
where the gate-source overdrive voltage Vov = VGS − Vth was
introduced. By substituting (42) in (41) we obtain
SiMOS = 4γkB T
ID
.
Vov
(43)
The two-sided shot noise PSD of a bipolar transistor is given
by
SiBip = qIC ,
(44)
where IC is the DC collector current and q is the elementary
charge. Assuming the same DC current for the two transistors,
we obtain from (43) and (44) for the ratio between the output
current noise PSDs
208 mV
4γVT
≈
.
(45)
SiMOS /SiBip =
Vov
Vov
Here we assumed γ ≈ 2 and T = 300 K, resulting in a
thermal voltage VT = kB T /q of 26 mV. We conclude that
MOSFETs may show much less white output noise compared
to their bipolar counterparts, provided that the overdrive voltage is much larger than 200 mV. Obviously, the advantage of
MOSFETs over bipolar transistors is especially pronounced for
processes with a higher CMOS supply voltage. This advantage
reduces with technology scaling, which makes MOSFETs less
attractive for low-voltage applications. We have disregarded
flicker noise in this comparison. We believe that flicker noise
is less important than thermal noise for the following reason.
The CP flicker noise corner is given by αCP fc according to
(15). Assuming a transistor noise corner of 1 MHz and a duty
cycle of 10 percent, we obtain a CP flicker noise corner of
100 kHz. The optimum loop bandwidth is typically larger
in a fractional-N PLL, suppressing flicker noise in the CP
efficiently. We will show that the condition Vov >> 200 mV
can be fulfilled by employing the modern dual-loop PLL
architecture from Section VI-B in conjunction with the CP
architecture from Section VI-C. This architecture will allow
the gate-sources voltages to be fully switched between ground
(VSS) and CMOS supply (VDD=2.5 V in our case). For
the CP MOSFETs might be the better choice compared to
SiGe-HBTs, whereas HBTs are better suited for low-noise
VCOs and frequency dividers at high frequencies due to the
large transconductance compared to MOSFETs. Moreover, the
flicker noise performance of SiGe-HBTs based VCOs is much
better [26].
B. PLL Architecture for Low Phase Noise
A dual-loop architecture using two parallel CPs was described in [23] and [27]. A slightly modified version is
suggested in Fig. 7. Here, the two charge pumps CP1 and CP2
for fine and coarse tuning, respectively, are composed of five
binary weighted CPs each, selectable by a common five-bit
control line. Two current sources (CS) are added to generate
offset currents IOS1 and IOS2 in the fine tuning loop and the
coarse tuning loop, respectively. They are composed of five
binary weighted CSs each, which are controlled by another
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
CS_ctrl<4:0>
CS1
0-2 mA
OUT
CP_ctrl<4:0>
FINE
COARSE
VCO
DIV
CP1
0-8 mA
LPF
PFD
CP2
0-600 µA
BAND
SELECT
REF
Digital Control
CS2
0-150 µA
7
with moderate gate-source voltages VGS or moderately sized
MOSFETs with large VGS can be used. From (43) we conclude
that the latter option results in a lower device noise.
The next step in the design of a low-noise CP is to find an
architecture, where the gate-source voltages are maximized.
The simplest CP with this property consists of a pMOSFET
M1 delivering the UP current and an nMOSFET M2 delivering
the down-current. Such a circuit is shown in Fig. 8. Unlike
conventional CPs, it does not use cascode transistors or current
mirrors, which avoids additional potential noise sources. A
Vdd
Fig. 7.
Schematic view of dual-loop frequency synthesizer.
five-bit control line. The advantage of an offset current at the
CP output is the opportunity to shift the steady-state operation
point of the phase detector in order to improve its linearity
[28], [16]. Since the two CPs are driven by the same PFD, the
condition IOS1 /ICP1 ≈ IOS2 /ICP2 should be fulfilled in order
to keep the DC value of the fine tuning voltage constant. The
noise in the low-current charge pump CP2 for coarse tuning is
minimized by a large capacitor to ground (100 nF in [23]). As
a result, the phase noise is dominated by the fast fine tuning
loop. Due to the low fine-tuning gain of the VCO the overall
phase noise is significantly reduced compared to a single-loop
PLL with the same tuning range as experimentally verified in
[23]. This improvement is especially important for fractionalN PLLs, where the large CP duty cycle increases phase noise
and spurs, particularly, if a DC offset current is added to the
CP output current.
C. Charge Pump Architecture for Low Phase Noise
In most cases, charge pumps have been designed and
optimized for single-loop PLLs. A vast number of publications
is devoted to this topic, see [29], [30] and references therein.
In order to obtain a good matching between UP and DOWN
currents over the whole PLL tuning range, a large output
resistance of the CP is generally mandatory for single-loop
PLLs. The situation is completely different, if a CP is used
for fine tuning of the VCO only, where its output DC voltage
is almost fixed as in [23]. In this case, emphasis can be placed
on fast current switching of the CP and on a low device noise
by simplifying the CP architecture. In this paper, we confine
ourselves to this dual-loop PLL architecture and consider
only the charge pump for fine tuning. For coarse tuning, a
traditional low-current CP with a higher output impedance
could be used.
As was shown in Section VI-A, MOSFET-based CPs can
provide a low white noise, if their gate-source voltages are
large. In addition, they also exhibit flicker noise. However,
the flicker noise corner frequency of the CP given by αCP fc
according to (15) is lower than the transistor noise corner
by the factor αCP . Since αCP is typically lower than 10
percent, flicker noise is usually less important than thermal
noise in the context of CP design. The CP current ICP is
usually determined from system simulations and results in
a given drain current ID of the CP output transistors. In
order to generate the drain current ID , either large MOSFETs
UP
R5
M1
OUT
DOWN
M2
CS
M3
R4
Vss
Fig. 8.
Charge pump architecture used in CP1.
switchable CS realized by the transistor M3 between the output
and ground was also introduced to improve the PD linearity.
At first sight, this CP seems unacceptable for low-noise PLL
design, since the output resistance is rather low, and the
matching between UP and DOWN current extremely depends
on the output voltage. In traditional single-loop PLLs this
would inevitably result in large spurs and a strong dependence
of the PLL phase noise spectrum on the output frequency.
However, these problems are solved, if this CP is used for fine
tuning of the VCO (CP1 in Fig. 7), whereas a traditional lowcurrent CP is used for coarse tuning (CP2 in Fig. 7). The noise
of the latter can be reduced to a negligible level by loading
it with a large capacitor [23]. A voltage divider composed
of two resistors R4 and R5 on the order of 1 kΩ is added
at the output of CP1 to stabilize the DC output voltage at
a desired value given by VDD×R4/(R4+R5). This eliminates
the need for a high output impedance of CP1 and improves
its performance. At the same time, the VCO fine tuning gain
is kept almost constant, which makes the PLL phase noise
spectrum robust with respect to device parameter variations
with process, supply voltage and temperature (PVT variations).
Note that the PVT dependence of the CP itself is larger than
for a typical cascode CP. However, the loop bandwidth in a CP
PLL is proportional to the product KVCO ICP . In an integrated
VCO, the gain can easily vary by a factor of three or more
over the tuning range. By contrast, variations in the threshold
voltage of magnitude ∆V cause relative changes of the charge
pump current on the order of 2∆V /Vov ≈ 2∆V /V DD only,
as evident from (42). This is much smaller than relative KVCO
changes in a single-loop PLL. The relatively constant loop
bandwidth over a wide tuning range in a dual-loop PLL using
a cascode CP with output biasing has been experimentally
demonstrated in [27] and [23]. The low output impedance
of our new CP will reduce supply rejection. However, will
believe this drawback to be less significant than the advantage
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
Charge Pump Currents [mA]
8
IUP
6
IDOWN
4
IOFFSET
2
0
79
80
−1.25
2
Slope: −0.0019 mA / rad
Gain [mA/rad]
of having a highly linear CP with a low thermal device noise.
To minimize the effect of CP supply noise on the VCO, an
on-chip voltage regulator and a separate CP supply would be
helpful.
The CP draws an additional DC current VDD/(R4+R5) due
to output biasing. This results in a trade-off between power
consumption and phase noise. The fractional-N PLL in [23]
uses R4=R5=1 kΩ to stabilize the output DC voltage of the CP
generating a current up to 8 mA. This choice was motivated
by the desire to minimize the phase noise, whereas power
consumption was considered less critical in satellite applications. By contrast, the integer-N PLL for 60 GHz wireless
communications in [27] used R4=R5=100 kΩ. Generally, R4
and R5 should be larger for integer-N PLLs compared to
fractional-N PLLs due to the lower CP duty cycle of the
former. Moreover, CMOS VCOs require larger resistors R4
and R5 than bipolar oscillators to guarantee sufficient flicker
noise suppression in the loop.
Fig. 9 shows the simulated charge pump currents in the
fine tuning loop for two different offset currents. Obviously,
8
β=−0.0015/rad
−1.26
linear fit
simulated
−1.27
−1.28
−2
−1
0
1
2
Phase Error [rad]
Fig. 10. Phase detector gain versus input phase error for new charge pump.
the PFD input for the new CP. It was calculated by simulating
the average CP output current as a function of the input phase
error and numerically differentiating the result with respect to
the phase error. The PD gain dI/dφ = ICP /2π=8 mA/2π ≈
1.27 mA/rad is almost the same as in Fig. 5 to make the two
CPs comparable. The slope of this gain curve is essentially the
curvature of the phase detector characteristic I(φ) according to
(20) and below. The average slope is lower by a factor of 18
compared to the cascode CP gain in Fig. 5. This improvement
of the linearity is expected to have a significant effect on the
in-band phase noise and spurs of the fractional-N PLL.
In addition to improving the PD linearity, the new CP
reduces thermal device noise. Fig. 11 shows the simulated
device noise of the new CP and of the cascode CP used in
[23]. Note that the large duty cycle of 30 percent represents
81
Time [ns]
Fig. 9. Simulated UP and DOWN currents of CP1 and offset current IOS1
for two offset current levels.
the short DOWN current pulse is not affected by the offset
current, whereas the UP current pulse becomes broader with
increasing offset current. This allows the phase detector to
be linearized by shifting the operation point into a region,
where only the UP current responds to the inevitable phase
error changes in fractional-N mode [16]. In order to obtain
a high linearity of the PD, the current pulses should be as
steep as possible. This is achieved in our CP architecture by
the large swings and the steep waveforms of the gate-source
voltages toggling between VSS and VDD. As a result, the turnon time and turn-off time are as low as 250 ps and 200 ps,
respectively, which is approximately one inverter delay. The
turn-on time is about four times shorter than the value of 1 ns
reported for a charge pump in 0.35 µm CMOS technology
using a cascode architecture [31]. Cascode architectures can
provide a high output resistance and good current matching,
but the swing of the gate-source voltages of the switching
MOSFETs is significantly smaller than VDD, limiting their
turn-on times and, thereby, the PD linearity. Fig. 10 shows the
simulated PD gain dI/dφ as a function of the phase error at
ICP = 4mA
αCP = 30%
Cascode CP
New CP
Fig. 11. Simulated output noise current PSD for new CP (lower curve) and
cascode CP.
a worst case with respect to CP device noise. For a 100 MHz
reference as in [23], this duty cycle corresponds to a CP
activation time TON of 3 ns, which is sufficiently large to
linearize the PD, even if a MASH SDM with its large rms
phase error is employed. The noise plateau is reduced by 10 dB
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
as a result of the larger gate-source voltages and the small
number of transistors. Remember that the noise corner of the
CP is proportional to αCP according to (15). This long-term
correlation effect is not correctly reflected by the simulation,
which overestimates the 1/f noise by a factor of 1/αCP . For
typical values of αCP =1-10 percent, this corresponds to 1020 dB. However, the white noise plateau is correctly modeled.
Therefore, we can expect a reduction of the in-band noise
contribution in the phase noise plateau by 10 dB for the new
CP.
As assumed in (15), the noise current PSD SCP due to
thermal device noise is expected to be proportional to the
CP duty cycle. In order to confirm this assumption and to
white
determine the ratio SCP
= SCP /αCP , we have simulated
the high-frequency noise PSD over a wide range of αCP .
Fig. 12 shows the simulated device noise for different phase
errors corresponding to different CP duty cycles. For the white
2
Current PSD [(pA) /Hz]
200
linear fit
150
100
50
0
2
Slope: 250 (pA) /Hz
0
20
40
60
9
PLL output by using
σφout
1800
=
π
sZ
fmax
df 2 Sout (f) ,
(46)
fmin
where we employ fmin = 100 Hz and fmax = 100 MHz as
integration limits.
In high-speed digital design, the absolute PLL jitter (or
tracking jitter) is often used for noise characterization. It
describes the deviation of the zero crossings of the output
clock from the ideal positions, where a clean input clock is
assumed. Absolute PLL jitter is given by
σφout
T0 ,
(47)
3600
where T0 = 1/f0 is the ideal period of the PLL output signal.
In CDR circuits, the output signal is often referred to itself
shifted by a delay τ . For a very long delay τ , the autocorrelation of the output signal converges to zero, and the
self-referenced jitter σSR (τ ) approaches a steady-state value
σSR (∞). If white noise sources dominate the√phase noise, then
we find for the long-term jitter σSR (∞) = 2 σabs as shown
in [32].
In conclusion, the improvement of the charge pump will
not only reduce the phase noise, but also rms phase error,
absolute jitter and long-term jitter. In order to predict the
expected improvement, we assume a reduction of white charge
pump device noise by 10 dB and a reduction of β by a factor
of 10. These numbers are consistent with the simulations
presented in Section VI. Fig. 13 shows the simulated phase
noise spectrum and its components for this case. The PD noise
σabs =
αCP [percent]
-60
Fig. 12. Simulated output current PSD at 10 MHz as a function of CP duty
cycle αCP for ICP =4 mA.
VII. I NTEGRATED P HASE E RROR AND T IMING J ITTER
Timing jitter and phase noise describe the same physical
effect. Timing jitter describes the fluctuations of the zero
crossings of the output signal around the ideal values, whereas
phase noise is the corresponding frequency-domain equivalent.
In RF synthesizer design, the rms phase error is often used as
a metric to quantify the overall phase noise performance. We
calculate the integrated rms phase error σφout [degree] at the
Phase Noise [dBc/Hz]
white
noise current PSD normalized to the CP current SCP
/ICP
−20
we found a value of 6.3 × 10
A/Hz for this CP, which is
an order of magnitude lower than for the cascode CP.
As an illustration, we consider a 10 GHz PLL driven by
a 100 MHz reference using a 4 mA CP in the fine tuning
loop. Assuming a duty cycle αCP of 20 percent, we obtain
in
an input-referred white phase noise SCP
= SCP /(ICP /2π)2
−16
2
of 1.25 × 10
rad /Hz. This corresponds to a phase noise
of -159 dBrad2 /Hz or -159 dBc/Hz, as follows from the
remark after (1). At the 10 GHz PLL output this noise appears
amplified by 20 log(10 GHz/100 MHz) = 40 dB, resulting in
an in-band phase noise due to thermal charge pump noise of
-119 dBc/Hz. This noise level is negligible compared to other
noise sources as evident from Fig. 6.
-70
σφ=0.75o
CP
-80
REF
Total
-90
VCO
BUF
-100
-110
PD
SDM
-120
LPF
-130
-140
102
103
104
105
106
107
108
Frequency Offset [Hz]
Fig. 13. Modeled phase noise spectrum for a 10 GHz synthesizer using the
novel charge pump for fine tuning.
due to CP nonlinearity is now almost negligible, which can
be understood from equation (38). Since the PD phase noise
is proportional to β 2 , the linearity improvement by a factor
of 10 will lower this phase noise contribution by 20 dB. As
a result, the integrated phase error is reduced from 1.43 to
0.75 degree. The latter value corresponds to an absolute jitter
of σabs = (0.750 /3600 )/10GHz = 0.21 ps for our 10 GHz
PLL. This value is much lower than the best reported values
for CMOS clock generators [33].
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010
VIII. C ONCLUSION
We have presented analytical expressions for the phase noise
spectrum of phase-locked loops. The results were visualized
by MATLAB. For an existing design, thermal noise and
nonlinearity of the charge pump were found to be critical
with respect to phase noise. A method was proposed to reduce
these noise contributions drastically. By using a dual-loop PLL
topology in conjunction with the novel charge pump, a very
low PLL jitter is predicted, which is robust with respect to
PVT variations.
10
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PLACE
PHOTO
HERE
PLACE
PHOTO
HERE
Frank Herzel was born in Güstrow, Germany in
1963. He received his M.S. degree in Berlin (1989)
and his Ph.D. in Rostock (1993), both in theoretical
physics. Since 1993 he has been with the IHP in
Frankfurt (Oder), where he was mainly involved in
semiconductor device modeling until 1996. Since
then he has been working in the design of silicon
IC’s for RF communications. Currently, he is focusing on SiGe BiCMOS frequency synthesizers for
space applications.
Sabbir A. Osmany was born in Bangladesh in
1975. He received his M.S. degree from University
of Ulm, Germany in Communications Technology.
Since 2005 he is with the IHP, where he is working
towards the Ph.D. degree. His research interest involve mixed-signal and RF IC design for wireless or
optical communication with emphasis on integer-N
and fractional-N frequency synthesizers.
J. Christoph Scheytt (M’01) received his diploma
degree (M.S., 1996) and Ph.D. degree (2000, with
highest honors) both from Ruhr-University Bochum,
Germany. In 2000 he co-founded advICo microPLACE
electronics GmbH, a German IC design house. For
PHOTO
6 years he served as CEO at advICo where he
HERE
was responsible for various projects in the area of
wireless and fiber-optic IC design. Since 2006 he
is with IHP where he is head of circuit design
department, a group of about 30 researchers working
on high-frequency and broadband IC design. Dr.
Scheytt has authored and co-authored more than 40 papers and holds 6 patents.
His research interests include RFIC and broadband IC design, PLL techniques,
and design with SiGe BiCMOS technologies.
11