PMOS Testing at Rochester Institute of Technology Dr. Lynn
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PMOS Testing at RIT ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING PMOS Testing at Rochester Institute of Technology Dr. Lynn Fuller webpage: http://www.rit.edu/~lffeee Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 email: LFFEEE@rit.edu MicroE webpage: http://www.microe.rit.edu Rochester Institute of Technology Microelectronic Engineering Revised 11-11-2010 pmostest.ppt © November 11, 2010. Dr. Lynn Fuller Page 1 PMOS Testing at RIT OUTLINE Test Chip Test Equipment Resistive Structures Transistors Integrated Circuits Ring Oscillator Digital Circuits Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 2 PMOS Testing at RIT THE TEST CHIP Alignment Marks CD Linewidth, Overlay Van Der Pauw, p+ DS, Metal MOSFET’s, Inverters Ring Oscillator CBKR Digital Circuits Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 3 PMOS Testing at RIT PMOS TEST CHIP Fall 2010 Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 4 PMOS Testing at RIT TEST FACILITY HP4145 Semiconductor Paramater Analyzer Keithley 7001 Switch Matrix Ultracision Semi-Automatic Wafer Prober Computer ICS Software Camera Rochester Institute of Technology Microelectronic Engineering Test Fixture and Manual Probe Station © November 11, 2010. Dr. Lynn Fuller Page 5 PMOS Testing at RIT TEST EQUIPMENT Semi-automatic Prober Automatic Prober Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 6 PMOS Testing at RIT TEST EQUIPMENT Manual Prober Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 7 PMOS Testing at RIT RESISTOR TEST RESULTS R = Rhos L/W L/W = 400/60 R = V/I = 1/slope = 647 Ω Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 8 PMOS Testing at RIT VAN DER PAUW TEST STRUCTURES FOR SHEET RESISTANCE I V1 Rs I V1-V2 V2 I I I (V1-V2) Π Rs = I ln 2 V1 Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller V2 Page 9 PMOS Testing at RIT VAN DER PAUW TEST RESULTS 26.4 Ohms Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 10 PMOS Testing at RIT CBKR AND INVERTERS Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 11 PMOS Testing at RIT CROSS BRIDGE KELVIN RESISTANCE TEST STRUCTURES FOR CONTACT RESISTANCES Gc V1-V2 I V1 V2 W2 W1 I I (V1-V2) Rc = I I 1 Gc = (V1-V2) W1 x W2 Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 12 ohms mhos/µm2 PMOS Testing at RIT METAL AND DIFFUSION SERPENTINE Line width = 15 µm Line Space = 30 µm L/W = 269 Area Covered by metal = 62050 µm2 500 µm 100 µm R = Rhos L/W Defect density ( in #/cm2 ) = (# defective x 1612) / (# tested) Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 13 PMOS Testing at RIT PMOS TRANSISTORS Layout Photograph Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 14 PMOS Testing at RIT PMOS TRANSISTOR TEST RESULTS Vds D +G Vgs Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 15 - S Id PMOS Testing at RIT TRANSISTOR LINEAR REGION VT, GM Vd = -0.1 Volt D + S -5 -4 -3 -2 Id Non Saturation Region Vgs G - -Ids Vgs -Vds Vsub G S Vsub = 0 -Id gm -1 -2 -3 volts Body Effect Vsub D p p n Vsub pMOSFET with Vt=-1, since the Drain is at -0.1 volts and the source is at zero. Both drain and source will be on at gate voltages greater than -1.1 volt. the transistor will be in the non saturation region. -Vg Vto gm = ∆Id/∆ ∆Vg Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 16 PMOS Testing at RIT LINEAR REGION TEST RESULTS Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 17 PMOS Testing at RIT TRANSISTOR SATURATION REGION VT, GM Id -Ids Saturation Region -5 -4 Vgs -3 -2 + D PMOS Vgs=Vds G S Vsub -Vds G S p Vsub = 0 -Id D p n Body Effect gm Vsub -1 -2 -3 volts pMOSFET with Vt=-1, Drain end is never on because Voltage Gate to Drain is Zero. Therefore this transistor is always in Saturation Region if the gate voltage is above the threshold voltage. -Vg Vto gm = ∆Id/∆ ∆Vg Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 18 PMOS Testing at RIT TRANSISTOR SUB THRESHOLD ID-VGS Id (Amps) Id D G S + Vgs=Vds - 10-2 10-3 -4 10-5 10 -6 Lights On 10-7 10 -8 10-9 10-10 10 10-11 10-12 Sub Vt Slope (mV/dec) Vgs Vt The subthreshold characteristics are important in VLSI circuits because when the transistors are off they should not carry much current since there are so many transistors. (typical value about 100 mV/decade) Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 19 PMOS Testing at RIT INVERTERS L = 40µm W = 20µm L = 20µm W = 50µm Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 20 PMOS Testing at RIT INVERTERS VOUT VIN VOUT -V Slope = Gain Inverter Gain = Wd/Ld Wu/Lu Voh -V VoL VOUT VIN VIN 0 0 ViL PMOS Inverter with Enhancement Load Rochester Institute of Technology Microelectronic Engineering Vih -V ∆ 0 noise margin = ViL - Voh ∆ 1 noise margin = Voh - Vih © November 11, 2010. Dr. Lynn Fuller Page 21 PMOS Testing at RIT INVERTER TEST RESULTS Gain = -2.64 Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 22 PMOS Testing at RIT RING OSCILLATOR, td Seven stage ring oscillator with two output buffers td = T / 2 N td = gate delay N = number of stages T = period of oscillation Vout Vout T = period of oscillation Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 23 PMOS Testing at RIT 9 STAGE RING OSCILLATOR Gnd Vcc Out Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 24 PMOS Testing at RIT RING OSCILLATOR OUTPUT td = T / 2n = 500 ns / 2 / 9 = 28 ns 500ns Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 25 PMOS Testing at RIT DIGITAL CIRCUIT TESTING Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 26 PMOS Testing at RIT LAB VIEW SOFTWARE Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 27 PMOS Testing at RIT HARDWARE FOR OUTPUT 6 Analog Outputs Ribbon Cable Terminal Board Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 28 PMOS Testing at RIT HARDWARE FOR INPUT 16 Analog Inputs Ribbon Cable Terminal Board Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 29 PMOS Testing at RIT FINAL SYSTEM Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 30 PMOS Testing at RIT CUSTOM SOFTWARE INTERFACE Click on digital testing icon to invoke the lab view software and this main menu. Click to select the type of test you wish to run. MAIN MENU Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 31 PMOS Testing at RIT NOR GATE AND NOR FLIP FLOP PMOS 2 INPUT NOR PMOS NOR RS Flip Flop Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 32 PMOS Testing at RIT TESTING TWO INPUT ONE OUTPUT LOGIC GATES Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 33 PMOS Testing at RIT FOUR CHOICES FOR SUPPLY VOLTAGES CLICK TO SELECT ONE CMOS/TTL Vcc = +5 Volts Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 34 PMOS Testing at RIT PROBE CARD/WIRE CONNECTIONS 18 20 16 22 Rochester Institute of Technology Microelectronic Engineering 14 12 10 24 2 4 © November 11, 2010. Dr. Lynn Fuller 8 6 Page 35 PMOS Testing at RIT SWITCH MATRIX (MANUAL) Wire #17 Supply Vcc -V Gnd Outputs abcdef Inputs abcdef Wire #8 Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 36 PMOS Testing at RIT RUN TEST Click to Start Test Stop Test Click to Select When Output is High or Low Test Results For Xor Gate Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 37 PMOS Testing at RIT PMOS INVERTER GAIN=4 Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 38 PMOS Testing at RIT PMOS 2-INPUT NOR Test for PMOS Two Input NOR, Gain = 4 or 8 Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 39 PMOS Testing at RIT PMOS 2-INPUT XOR Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 40 PMOS Testing at RIT WAFER MAPS FOR MESA nmos Vt target +1 000000000000000 000050505050000 000000000000000 005060507050700 000000000000000 004040304030300 000000000000000 004040404040400 000000000000000 004050405090600 000000000000000 005050606060700 000000000000000 000050505050000 000000000000000 Col 1 Col 15 Row 1 Row 15 T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T row 1 is the first row in which a full die is located column 1 is the first column in which a full die is locatedd Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 41 PMOS Testing at RIT WAFER MAPS FOR MESA Code 0 1 2 3 4 5 6 7 8 9 no die value<(Target-40%) (Target-40%)<value<(Target-30%) (Target-30%)<value<(Target-20%) (Target-20%)<value<(Target-10%) (Target-10%)<value<(Target+10%) (Target+10%)<value<(Target+20%) (Target+20%)<value<(Target+30%) (Target+30%)<value<(Target+40%) (Target+40%)<value Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 42 PMOS Testing at RIT WAFER MAP Example: Given a wafer with test chips located as shown and nmos threshold voltage data encoded and stored in MESA as shown. Reconstruct a wafer map using EXCELL spreadsheet. Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 43 PMOS Testing at RIT FUTURE WORK More Automation Improved Wafer Mapping More Complete Testing Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 44 PMOS Testing at RIT CONCLUSION A test specification has been developed A history data base has been developed Testing is very time consuming. It takes us 9 hours to do all the specified tests and even then we only test a few devices on a wafer. Currently we test about 1% of the devices Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 45 PMOS Testing at RIT REFERENCES 1. LabView Software, National Instruments, http://www.natinst.com Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 46 PMOS Testing at RIT REVIEW QUESTIONS - PMOS TEST SPECIFICATION 1. How is Vt and gm found from the transistor family of curves. 2. Is the Vt and gm the same in the non-saturation region as in the saturation region? 3. What is the significance of the sub-threshold slope. What is the difference between sub-threshold slope and subthreshold swing? 4. What is the significance of the noise margin. 5. What is the purpose of the ring oscillator test structure. Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 47 PMOS Testing at RIT MUX LAYOUT AND GATE LEVEL SCHEMATIC 25 Transistors I0 A A’ A’BI1 I1 I2 AB’I2 B Rochester Institute of Technology Microelectronic Engineering A’B’I0 B’ I3 © November 11, 2010. Dr. Lynn Fuller ABI3 Page 48 Q PMOS Testing at RIT PMOS 4-INPUT MULTIPLEXER Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 49 PMOS Testing at RIT MUX TEST RESULTS A B I3 I2 I1 I0 A B I3 I2 I1 I0 In PMOS logic low is 0 volts, logic high is -Vcc A A B B I3 I3 I2 I2 I1 I1 I0 I0 Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 50 PMOS Testing at RIT MUX TEST RESULTS A B I3 I2 I1 I0 A B I3 I2 I1 I0 In PMOS logic low is 0 volts, logic high is -Vcc A A B B I3 I3 I2 I2 I1 I1 I0 I0 Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 51 PMOS Testing at RIT PMOS FULL ADDER Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 52 PMOS Testing at RIT PMOS CLOCKED DATA LATCH Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 53 PMOS Testing at RIT PMOS ANALOG MUX Rochester Institute of Technology Microelectronic Engineering © November 11, 2010. Dr. Lynn Fuller Page 54
