Contamination Aspects in Integrating High
Dielectric Constant and Ferroelectric
Materials into CMOS Processes
Der Technischen Fakultät der
Universität Erlangen-Nürnberg
zur Erlangung des Grades
DOKTOR-INGENIEUR
vorgelegt von
Hocine Boubekeur
Erlangen 2002
Als Dissertation genehmigt von
der Technischen Fakultät der
Universität Erlangen-Nürnberg
Tag der Einreichung:
Tag der Promotion:
Dekan:
1. Berichterstatter:
2. Berichterstatter:
Weiteres prüfungsberechtigtes Mitglied
20.09.2001
05.03.2002
Prof. Dr.-Ing. W. Glauert
Prof. Dr.-Ing. H. Ryssel
Prof. Dr. I. Eisele
Prof. Dr. A. Winnacker
Acknowledgments
First and foremost, I am enduringly grateful to my advisor Prof. Dr.-Ing. H. Ryssel, for
the opportunity to undertake this research work under his supervision. His guidance
and support made this work possible.
I am also indebted to Dr. Thomas Mikolajick and Dr. Lothar Frey, who clarified many
points in this research. The contribution of Thomas and Lothar to this thesis has been
not only through many hours of detailed discussions, but also through continuous
encouragement and endless support. My interaction with them has been a precious
learning experience.
I owe many thanks to Dr. Werner Pamler for the invaluable support and stimulating
suggestions to this research. The numerous discussions with him have enriched my
academic experience.
I thank Prof. Dr. I. Eisele for kindly agreeing to serve on my thesis committee and for
the expertise to the evaluation of this work.
I am sincerely grateful to Dr. Christine Dehm and Joachim Höpfner for administration
assistance and advice. I am also very grateful to Dr. Helmut Klose for his interest in
the progress of this work.
The work presented in this dissertation would not have been possible without the
contribution of many individuals. I wish to thank Barbara Hasler for introducing me to
the production line and pointing me in the right direction as I started the fabrication of
the test structure. Specifically, I thank Dr. Joseph Steiner, Dr. Rolf Treichler, Dr.
Franz Jahnel, Dr. Andreas Rucki, and Dr. Wolfgang Hösler for efficiently performing
countless measurements. A large amount of thanks goes to the clean room staff of
Fraunhofer Institute of Integrated Circuit. I would like to thank Dr. Anton Bauer, Katrin
Fischer, Stephanie Natzer, Dagmar Kraus, Mathias Rommel, Fabian Quast, Holger
Kotouc, and Gudrun Rattmann for their help.
No amount of gratitude would be sufficient for my parents, brothers, and sisters. I
dedicate this thesis to them in appreciation of their constant encouragement and
support in all aspects of my life. My mother for setting a remarkable example to
follow.
Contents
Abstract...................................................................................................................iii
Zusammenfassung (Abstract in German).............................................................. iv
1 Introduction ............................................................................................................ 1
2 Advanced Memory Concepts and New Materials for Giga-Bit Scale Memories..... 6
2.1 The Evolution of Dynamic Random Access Memories...................................... 6
2.2 High Dielectric Constant Materials .................................................................... 7
2.3 Non Volatile Ferro-Electric Memories................................................................ 9
2.4 Integration Aspects of High Dielectric Constant and Ferroelectric Films in
CMOS Processes.................................................................................................. 11
2.4.1 Barium Strontium Titanate and Strontium Bismuth Tantalate ................... 13
2.4.2 Iridium and Platinum Electrodes ............................................................... 14
3 Experimental Methods ......................................................................................... 17
3.1 Method and Principle of Intentional Contamination ......................................... 17
3.2 Analytical and Electrical Measurements.......................................................... 20
3.2.1 Total Reflection X-Ray Fluorescence and Vapor Phase DecompositionTotal Reflection X-Ray Fluorescence ................................................................ 20
3.2.2 Time of Flight-Secondary Ion Mass Spectroscopy.................................... 23
3.2.3 Electrolytic Metal Tracer .......................................................................... 26
3.2.4 Deep Level Transient Spectroscopy ........................................................ 29
3.2.5 Gate Oxide Integrity.................................................................................. 32
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in
Silicon ....................................................................................................................... 41
4.1 General Properties of Metals in Silicon ........................................................... 41
4.2 Desorption Properties of Contaminants on Silicon Surface............................. 43
4.2.1 Desorption Properties of Barium............................................................... 43
4.2.2 Desorption Properties of Strontium........................................................... 46
4.2.3 Desorption Properties of Bismuth ............................................................. 48
4.2.4 Desorption Properties of Iridium ............................................................... 50
4.2.5 Desorption Properties of Platinum ............................................................ 53
4.3 Diffusion Properties of Contaminants in Silicon............................................... 57
4.3.1 Time of Flight-Secondary Ion Mass Spectroscopy Analysis of Barium,
Strontium, and Bismuth ..................................................................................... 57
4.3.2 Temperature Dependence of the Barium and Strontium Diffusion
Coefficient.......................................................................................................... 60
4.3.3 Secondary Ion Mass Spectroscopy Analysis of Iridium and Platinum....... 61
4.3.4 Study by Deep Level Transient Spectroscopy .......................................... 67
4.4 Diffusion of Contaminants in Poly-Silicon........................................................ 71
5 Electrical Characterization of Intentionally Contaminated Samples ..................... 77
5.1 Influence on the Minority Carrier Lifetime........................................................ 77
Contents
ii
5.1.1 Barium, Strontium, and Bismuth Contaminated Wafers............................ 78
5.1.2 Iridium Contaminated Wafers ................................................................... 83
5.1.3 Platinum Contaminated Wafers ................................................................ 87
5.2 Design and Technology of Test Chip .............................................................. 90
5.2.1 LOCOS Isolation....................................................................................... 91
5.2.2 N+ and P+ Implantation ............................................................................. 91
5.2.3 Gate Oxide Growth, Poly-Silicon Deposition, and Patterning ................... 92
5.2.4 Interlayer Dielectric and Planarization ...................................................... 93
5.2.5 Metallization.............................................................................................. 93
5.3 Leakage Current Measurement on Contaminated Diodes .............................. 95
5.3.1 Barium, Strontium, and Bismuth Contaminated Diodes............................ 97
5.3.2 Iridium Contaminated Diodes.................................................................. 100
5.3.3 Platinum Contaminated Diodes .............................................................. 103
5.3.4 Discussion of the Leakage Current Results ............................................ 105
5.4 Gate-Oxide Integrity Evaluation..................................................................... 106
5.4.1 Results from E-Ramp ............................................................................. 106
5.4.2 Results from Constant Current Stress Charge to Breakdown................. 113
5.4.3 Discussion of the Results ....................................................................... 125
6 Summary and Outlook ....................................................................................... 132
6.1 Résumé of the Properties of the Contaminants............................................. 132
6.2 Résumé of the Impact of the Contaminants .................................................. 133
6.3 Future Work and General Conclusion ........................................................... 135
References......................................................................................................... 136
List of Symbols and Abbreviations......................................................................143
Abstract
In memory technology, new materials are being intensively investigated to overcome
the integration limits of conventional dielectrics for Giga-bit scale integration, or to be
able to produce new types of non-volatile low power memories such as FeRAM.
Perovskite type high dielectric constant films for use in Giga-bit scale memories or
layered perovskite films for use in non-volatile memories involve materials to
semiconductor process flows, which entail a high risk of contamination. The
introduction of large amounts of metal contamination during processing, however, is
a major concern of reliability and yield of complementary metal oxide semiconductor
devices.
The integration of these materials into back-end process flow is not only a process
engineering challenge, but also an evaluation of contamination issues, parallel to the
effort of integration into CMOS process.
In this dissertation, the risk of fabrication with barium strontium titanate or strontium
bismuth tantalate films with iridium/platinum electrodes, and their impact on yield and
reliability is estimated by first gaining knowledge about the properties of these new
materials, and then assessing the impact on device performance after intentional
contamination.
The results demonstrate that the risk is manageable and that the contamination
aspects are not “showstoppers” to the development of ferroelectric memories and
DRAMs using high-k capacitor dielectrics. The impact of contamination in the BackEnd Of Line on device performance is not significant as it could be in the Front-End
Of Line because of the device configuration, which offers gettering possibilities. This
has been demonstrated in the course of this work.
iii
Zusammenfassung
In der Speichertechnologie werden neue Materialien intensiv untersucht, um die
Integrationsgrenzen konventioneller Dielektrika zu überwinden und in der Lage zu
sein, neuartige nichtflüchtige Speichertypen mit niedrigem Energieverbrauch wie z.B.
FeRAM herzustellen.
Perowskitartige Schichten mit hoher Dielektrizitätszahl für Gigabit-Speicher oder
Materialien mit Perowskit-Schichtstruktur für die Verwendung in nichtflüchtigen
Speichern führen Materialien in den Halbleiterherstellungsprozeß ein, die ein hohes
Kontaminationsrisiko nach sich ziehen.Die Einführung von großen Mengen von
Metallkontaminationen während der Prozessierung ist ein Hauptproblem hinsichtlich
Zuverlässigkeit und Ausbeute von CMOS-Bauelementen.
Die Integration dieser Materialien in den Backend-Prozeßfluß ist nicht nur eine
Herausforderung aus Sicht der Prozeßentwicklung, sondern erfordert auch eine
Evaluierung der Kontaminationsaspekte begleitend zur Integration in CMOSProzeße.
In dieser Dissertation wird das Risiko der Herstellung von Barium Strontium Titanat
oder Strontium Wismut Tantalat mit Iridium/Platin-Elektroden und deren Auswirkung
auf Ausbeute und Zuverlässigkeit abgeschätzt. Es werden zuerst die Eigenschaften
dieser Materialien untersucht und danach die Auswirkung auf die Eigenschaften der
Bauteile nach gezielter Kontamination ausgewertet.
Die Ergebnisse demonstrieren, daß das Risiko zu handhaben ist und daß die
Kontaminationsaspekte kein fundamentales Hindernis für die Entwicklung von
ferroelektrischen Speichern bedeuten. Die Auswirkung der Kontamination innerhalb
des „Back-End of Line“ auf die Bauelementeseigenschaften ist nicht so
bedeutungsvoll wie im „Front-End of Line“, da aufgrund der Bauteilkonfiguration,
Möglichkeiten des „gettering“ vorhanden sind. Dies konnte im Rahmen dieser Arbeit
gezeigt werden.
iv
1 Introduction
The development of a new dynamic memory generation implies downscaling of the
device dimensions, while maintaining the storage charge at an adequate level to
retain data against leakage current. The data, representing one of the two binary
logical states is stored as an electrical charge. Depending on the circuit associated
with the memory cell, such as the sensitivity of the sense amplifier and the parasitic
capacitance, the minimum charge required is about 50-75 fC. With the ever
continuing downscaling, this minimum charge was ensured through the
compensation of the capacitance by increasing the area (A) or using thinner dielectric
(thickness d) having relatively high dielectric constant (εr):
C=
ε0 εr A
d
(1.1)
The use of thin oxynitride (ON) or oxide/nitride/oxide (ONO) (εr ≈ 7), as storage
dielectric in planar capacitor alone was not sufficient for the achievement of the
required capacitance for good device operation. To increase the capacitor area, the
architecture of the cell was modified from a simple planar capacitor to complicated
3D trench capacitor structures. Further development using this concept is
approaching its limits, in terms of physical thickness and since the capacitor area
cannot be increased without drastically increasing the product cost.
Consequently, new materials have to be introduced in microelectronics to overcome
integration limits and to be able to manufacture new products. For example, the need
of low resistance interconnect for high speed devices obliges to replace the standard
aluminum interconnect by copper metallization. The new high clock frequency
microprocessor from Intel and AMD have copper interconnects1. Another requirement
of low parasitic capacitance, as well as lower RC time constant (resistancecapacitance charging time to reduce cross-talk between interconnect as the
separating dielectric layer decreases), forced to replace the conventional inter-layer
dielectric with low dielectric constant (low-k) material.
The most prominent examples in memory technology are the high dielectric constant
barium strontium titanate (BaSrTiO3 or BST) and ferroelectric strontium bismuth
tantalate (SrBi2Ta2O9 or SBT) or lead zirconate titanate (PbZrxTi1-xO3 or PZT)
materials. BST exhibits one of the highest dielectric constants ever measured [Jeo
97] and, therefore, is seen as a promising material for storage capacitors in future
gigabit range DRAM. BST is also widely investigated for thin film gate dielectric as
alternative to the silicon oxide based gate dielectrics [Jeo 98]. Ferroelectric memories
1
See Semiconductor Business News of November 07, 2000
2
1 Introduction
(FeRAMs), based on layered perovskite materials as capacitor dielectric, have
recently found increasing interest due to the non-volatility of data storage, the
potential of high integration scale because of small DRAM-like cell size, fast read and
write as well as low voltage/low power properties. The properties of FeRAM, in
comparison to dynamic memories (DRAM), static memories (SRAM), or Flash
memories are presented in Table 1.1
Table 1.1: Comparison between FeRAM properties and others memories type.
Value after the arrow represents the prognostic for a further development
[Deh 99].
FeRAM
Read cycles
Write cycles
Write voltage
Access time
Write time
Relative cell size
Data Retention
12
DRAM
SRAM
1015
1015
1 – 5V
40 – 70 ns
ns
1x
volatile
15
→ 10
10
1012 → 1015
5V → 0.8V
< 100ns→ 20ns
< 100ns→ 20ns
1x
> 10 years
1015
1015
1 – 5V
6 – 70 ns
ns
> 4x
volatile
Flash
1015
106
12 – 16V
40 – 70 ns
µs - ms
1x
> 10 years
The low voltage/low power characteristic is particularly suitable for mobile
application. For low integration scale (in kbit range) the offset concept is sufficient
and low density FeRAM are already in production for smartcard application [Shi 99].
For high Integration scale (in Gigabit range), and to minimize the cell size as
requirement to achieve this goal, the capacitor is integrated directly above the
transistor. A schematic view of the memory device configuration is presented in
figure 1.1 for high integration stacked cell (a) and low integration scale offset cell
concept (b).
Capacitor module
bitline
WL
plug
WL
drain
WL
WL
source
a) stacked cell
drain
b) offset cell
Fig. 1.1: 1T-1C (one transistor-one capacitor) bit cell concepts for use in
ferroelectric memories (a) stacked cell and (b) offset cell. WL stands for Word
Line
1 Introduction
3
A special specification for the use of SBT or BST material is the need for an
electrode, which has to be resistant against oxidation. Because of the highly oxidizing
ambient required for the crystallization of the perovskite layer, conventional
electrodes such as poly-Si cannot be used. The electrode should remain highly
conductive after exposure to oxygen atmosphere at high temperatures. The only
electrodes that qualify are noble metals or conductive oxides. Platinum is the
commonly used electrode in this technology as it is very stable against oxidation.
However, diffusion of oxygen through the platinum layer can occur easily during
anneal and thus lead to the oxidation of the underlying material (generally of doped
poly-silicon), which has the function of connecting the transistor to the capacitor.
Therefore, an oxygen diffusion barrier to protect the poly-plug is additionally
introduced between the platinum electrode and the plug-material. Iridium/iridium
oxide stacked layer has the desired property to prevent diffusion of oxygen [Nak 94].
In the ferroelectric memories concept, new materials, exotic to standard memory
technology (like barium, strontium, or bismuth) or previously avoided elements (like
transition metals platinum or iridium), are introduced in high amounts in production
lines.
While it is likely that FeRAM has the potential to replace the conventional Flash
memory as the next nonvolatile memory generation and that it is of great advantage
to replace capacitor dielectric by BST material in DRAM, one of the important
remaining questions is the compatibility of these materials with the standard CMOS
processes. The acceptance of new elements in a semiconductor fabrication is difficult
because many elements cause serious degradation of device properties. In
semiconductor terminology, the word “contamination” was associated with any matter
other than intentionally applied, which can adhere to the wafer and causes
performance degradation or device functionality troubles.
When metal contamination is present on the surface of the wafer, several kinds of
lattice defects in the active region or at the surface can be generated after a thermal
treatment at high temperature. Metals can form precipitates, generate stacking faults
or dislocations, or enhance the roughness of the Si/SiO2 interface. Such defects are
extremely detrimental for the reliability of the devices and are one of the biggest
factors in determining the yield. Metals that remain dissolved in the silicon matrix
create efficient recombination centers and lead to increase of the junction leakage
current, which in turn causes refresh failure or loss of the information in the memory
cell.
Paradoxically to the need of metals’ introduction in the ferroelectric memory, as the
shrinkage of the device dimension continues to progress in sub 0.1 µm dimensions,
the demand of clean process increases, forcing the National Technology Roadmap to
further lower the tolerated concentration to levels of 109 at/cm2, which are very
difficult to detect with the available techniques.
Cleaning processes cannot be the unique remedy against (intentional or even
unintentional) contamination. Preventing the contamination to spread through any
potentially contaminating sources (equipment, tweezers, ...) is also necessary. Both
are desirable, but unfortunately not sufficient.
4
1 Introduction
Understanding the properties of these new elements, of course, cannot eliminate
completely the contamination but can help to decrease their level, predict and
evaluate their detrimental effects and, if possible, engineer their integration in a
CMOS process. A knowledge has to be established to understand:
•
•
•
•
•
•
•
What are the properties of the contaminants,
How do the contaminants react to create defects,
Which degradation mechanisms are generated,
How critical is the cross contamination risk and how could it be prevented,
Which processes are critical, which are less critical. Which processes need
to be run on dedicated equipment,
Are diffusion barriers or protecting cap layers needed to prevent their
existence in the device active regions,
Is the risk manageable?
It is not that all contamination will necessarily cause harmful defects, but rather that
there exists a risk which can be enhanced or minimized depending on the
contamination nature, the process conditions, and the gettering possibilities. The
experience with copper shows that the associated risk is manageable, despite the
fact that copper is one of the most harmful elements in Si technology. With the
implementation of copper in advanced microelectronics interconnect, the feasibility to
meet complex contamination control has been demonstrated.
Fortunately, and since the capacitor module of FeRAMs is integrated in the Back-End
Of Line (BEOL) after a standard Front-End Of Line (FEOL) processing of the
transistor, many companies have chosen the prudent solution to process the
capacitor module in dedicated and separated clean room facilities, so that the risk of
FEOL contamination of production line can be avoided. Meanwhile, and in order to
be able to estimate the fabrication risks of products with these new elements, an
evaluation of contamination issues is indispensable parallel to process development
and integration.
This thesis is aimed at the study of contamination aspects of the high dielectric
constant BST and layered perovskite SBT materials, as well as the electrodes and
the oxygen barrier involved in the fabrication of these kind of memories.
The motivation behind this work is to realistically assess the impact of contamination
on yield and reliably of ferroelectric memories by examining the contamination after
device processing, i.e. in BEOL, as it may occur in ferroelectric memories.
We have approached the contamination aspects study from two directions: (a)
determination of the contaminants properties in silicon as well as in poly-silicon, and
(b) experimentally evaluate the effect of the contaminants on device performances.
The determination of properties deals with the desorption and diffusion properties of
the contaminants after an anneal at high temperatures. The diffusion properties were
extended to poly-silicon, in order to investigate the possibility of diffusion to the active
regions of the transistor through the plug-material. In this approach, some physical
effects such metal precipitation in the oxide or at the silicon/oxide interface were also
studied.
The yield and reliability approach was treated by examining the effect of the
contamination on leakage current and gate oxide integrity of diodes and MOS
1 Introduction
5
structures, respectively. Wafers with test structures were intentionally contaminated
after the main processes involved in the FEOL, such as junction formation, gate
oxide growth, poly-silicon plug material deposition and subsequent doping, and finally
inter-layer dielectric deposition.
The thesis is organized as follows: In chapter 2, arguments to justify the need for
BST or SBT materials are given after an brief description of the memories evolution.
Process integration of these materials in the stacked cell memory scheme is then
presented. A short survey of the contamination aspects of barium, strontium,
bismuth, platinum, and iridium, as already elaborated from the literature is given.
In chapter 3, the method of intentional contamination and its principle is presented,
as well as the analytical methods used in this work. Total-reflection x-ray
fluorescence technique and vapor-phase decomposition in combination with totalreflection x-ray fluorescence, to measure the contamination level on the wafer
surface or in the oxide film respectively, are described. The principle of depth profile
measurement using time of flight secondary ion mass spectroscopy is explained. The
technique for minority carrier lifetime measurement using the electrolytic metal tracer
is then introduced and the deep level transient spectroscopy for trap level
investigation is outlined. Finally, an appropriate model to fit the statistical results of
the gate oxide integrity measurement, adapted from the work of Degraeve et al. [Deg
98 b], is presented.
Chapter 4 focuses on the properties of the contaminants. Desorption and diffusion
properties of the contaminants after a thermal treatment are investigated and the
measured diffusion profiles in crystalline and poly-crystalline silicon are presented.
Results from Rutherford Back-Scattering and Secondary Ion Mass Spectroscopy
measurements to explore the properties of the contaminants in the poly-silicon plugmaterial, are shown. Cross-sectional transmission electron microscopy and energy
dispersive X-ray analysis are also used to investigate defect formation, such as
precipitation, on unpatterned or patterned wafers with gate oxide and poly-silicon.
The rest of the work is dedicated to the electrical characterization. In chapter 5, the
test structure to measure the electrical parameters is introduced. The influence of the
contaminants on minority carrier recombination lifetime is investigated and results of
the leakage current measurements on contaminated diodes are presented. The third
part of the electrical characterization concerns gate oxide integrity. Results from
voltage ramp and constant current charge to breakdown are shown. Furthermore, the
reason for some observed breakdown cases are identified and explained.
2
Advanced Memory Concepts and New Materials for
Giga-Bit Scale Memories
2.1 The Evolution of Dynamic Random Access Memories
For more than three decades, DRAMs have been a major application of Large Scale
Integration (LSI) and have been serving as the technology driver of semiconductor
technology. Every three years, a new DRAM generation has been introduced, each
offers 4x increase in density, 3x reduction in cell area and 1.4x reduction in the
minimum feature size F (minimal gate physical dimension). The success of DRAMs
over the other memories was the use of a simplified memory cell, consisting only of
one transistor for addressing the bit line and one capacitor for storing the charge
(1T1C), and a successful progress in the scaling of device feature size. Table 2.1
shows the trends of the capacitor for the 64 and 256 Mb (actually in production) and
above 256 Mb (1Gb and 4Gb currently under development).
Table 2.1: The 1999 National Technology Roadmap for Semiconductors
published by the Semiconductor Industry Association. deq is the equivalent
oxide thickness (see equation 2.1)
DRAM
Generation
64 M
Chip
(Year)
1995
Feature Size
F (µm)
0.35
Chip Size
(mm2)
190
Supply
Voltage (V)
3.3
deq
(nm)
4.5
256 M
1998
0.25
280
2.5
2.2
1G
2001
0.18
420
1.8
1.1
4G
2004
0.13
640
1.5
0.5
In scaling down, there are certain limiting factors. According to the generalized
scaling rule, if the transistor channel length L is to be reduced by a factor S, the gate
oxide thickness d should be reduced by the factor S, the voltage applied V should be
reduced by a factor k (generally, k<S), and the substrate doping N should be
increased by a factor S2/k in order to avoid undesirable short channel effects and
especially appearance of the punch-through effect [Bac 84]. The difficulty in DRAM
scaling is the fact that the capacitor cannot be scaled proportionately with cell size.
An adequate minimum charge, generally considered to be about 50-75 fC, is required
for the operation of a memory cell, to improve the signal to noise and for data
retention. The requirement of minimum charge imposed an increase in the capacitor
area and of the dielectric constant while shrinking the gate oxide thickness, leading
the evolution from planar cells architecture to deep trench or stacked cells.
7
2.2 High Dielectric Constant Materials
Conceptually, the merit of high integration density in present memories is due to : 1)
using effectively thinner dielectric layers (oxide nitride ON or oxide-nitride-oxide
ONO) in order to ensure the amount of accumulated electric charge required for
device operation, and 2) improvement in the capacitor-to-cell area ratio by taking
advantage of the third dimension. Technologically, the lithography has been also
evolving to satisfy the needs of scale-down and to make sub-micron structures
possible. Different light sources have appeared, such as KrF deep UV using excimer
lasers at a wavelength of 248 nm.
To enter the G-bit era and to overcome the challenge of 0.18µm technology, the
performances of lithography have to be enhanced and the oxide thinning has to be
pushed beyond the physical limit, established by Buchanan et al., to be between 1.6
and 2 nm. [Buc 96, Buc 97]
It appears unlikely that lithography will be a limiting factor for upcoming scaling of
silicon devices since the 193 nm-deep UV optical lithography meets the requirement
to produce 0.1 µm devices [Roadmap 99]. Moreover, extremely advanced tools of
lithography, like x-ray and e-beam lithography, could be used if the limits of optical
lithography have to be surpassed. Under these considerations, the oxide thinning will
be the fundamental limit for further CMOS-devices scaling. It has been demonstrated
that the gate oxide can be scaled to 2 nm. Below 2 nm, the leakage current becomes
problematic and exceeds the value of 1 A/cm2 [Lo 97]. The leakage current is a key
parameter and an important issue in DRAM, and has detrimental impact on device
yield and reliability.
From the standpoint of process complexity and to meet the market requirement for
G-bit scale memories, planar structure in combination with a high dielectric constant
film as capacitor dielectric is the attractive and the more realistic alternative.
2.2 High Dielectric Constant Materials
The excellent properties of the thermally grown silicon dioxide and its versatile use in
silicon technology (gate dielectric, surface passivation, isolation layer, mask,
sacrificial layer,...) have made it the primary gate dielectric employed in memory
technology. The SiO2 gate oxide or SiO2 based dielectric such as oxynitride (nitrogen
incorporated oxide) or stacked oxide/nitride/oxide layers (ONO) are still used up to 64
Mbit memories.
In 64M DRAMs, the ON effective thickness has reached its ultimate value (less than
5 nm) and the 3D structures have become extremely complicated which results in a
significant absolute difference in height between the cell array and the peripheral
circuit, making it difficult to form fine pattern and increasing production cost.
Moreover, scaling the SiO2 towards a few atomic layers will eventually lead to
reliability problems because of an important leakage current of tunneling nature.
Groesenken and coworkers showed that the intrinsic reliability of the ultrathin gate
oxide (below 3 nm) will be a potential showstopper for further downscaling of the
oxide [Gro 99]. For oxide layers thinner than 3 nm, the leakage current of MOS
structures is not explained by the Fowler-Nordheim mechanism but through the direct
2 Advanced Memory Concepts and New Materials for Giga-Bit Scale Memories
8
tunnel current, which increases exponentially with decreasing oxide thickness [Mas
74]. For example, at a gate bias of 1.5 V, the current density increases by ten orders
of magnitude as the oxide thickness decreases from 3.6 nm to 1.5 nm. The current
density calculated by Lo et al. for 1.5 nm is about 102 A/cm2 [Lo 97]. This theoretical
value agrees well with the experimental data measured by Momose et al. [Mom 94].
Stathis et al., after intensive study of reliability of very thin gate oxide by time
dependent dielectric breakdown measurements, showed that gate oxide or oxynitride
could satisfy 10 years of operation at operating voltage of 1 V only when they have a
thickness above 2.6 nm. The authors also showed that the reliability becomes a
limiting factor in the 2.6 nm gate oxide [Sta 98].
The study of tunneling current and reliability of ultrathin gate oxide has anticipated
the need for high dielectric constant materials (also called high-k materials). It is now
commonly admitted that the need for high-k materials is crucial as an alternative to
gate oxide for future memory generations [Buc 99]. Moreover, the 1999
Semiconductor Industry Association (SIA) roadmap predicted that the transition to
high-k gate dielectric will happen within 5 years.
Several materials were proposed as an alternative to oxide and have been
investigated for use as a gate dielectric for future device generations. Table 2.2
compares the typical dielectric constant of various investigated materials.
Table 2.2: Typical dielectric constant of the candidate materials as gate
dielectric.
Material
ONO
ON
Ta2O5
TiO2
BST
εr
5-7
25
40-86
> 200
Studies of thin film Ta2O5 and TiO2 report that these materials are not stable. The
deposition and subsequent anneal of these films gives rise to an interfacial layer of
SiO2 [ Son 98], [Cam 99]. This interfacial layer reduces the effective capacitance and
thus the effectiveness of any high–k material.
Among the candidate materials, BaxSr1-xTiO3 (BST) appears to be the most
promising material. With a dielectric constant εx of typically 200 for a film thickness dx
of 20 nm, this is equivalent to oxide thickness deq of 0.39 nm, as calculated from the
following equation:
d eq = d x
ε oxide
εx
(2.1)
In DRAMs, BST can be used as a capacitor dielectric. With a dielectric constant of
200 and for a thickness of 20 nm, a specific capacitance of 88.5 fF/µm2 could be
obtained which is much higher than the required DRAM capacitance of 25-30 fF/cell.
Indeed, Kotecki and co-workers from IBM/Siemens DRAM Development alliance
have successfully fabricated planar capacitors of BST with Pt electrodes and were
able to demonstrate a specific capacitance of 90 fF/µm2 [Kot 99].
9
2.3 Non Volatile Ferro-Electric Memories
BST belongs to the perovskite family ABO3 (A = Ba,Sr), presented in figure 2.1. The
electrical dipole in BST results form the shifting of the titanium cation from the center
of the “O6” octahedron leading to a non-coincidence of the gravity centers of positive
and negative charges. It should be emphasized that only the high dielectric constant
property of BST is required for DRAM applications and not the ferroelectric property.
This is why, the BST used in DRAMs is paraelectric.
Fig. 2.1: ABO3 perovskite crystal structure. A= Ba or Sr, B = Ti or Ta
2.3 Non Volatile Ferro-Electric Memories
Ferroelectric memories (FeRAMs) are new types of memories taking advantage of
the electrical polarization to store the information instead of the electrical charge
used in conventional memories. FeRAMs are suitable for memory and mobile
applications due to their properties of non-volatility, high integration scale because of
small DRAM-like cell size, fast read and write as well as low voltage/low power
behavior.
FeRAMs make use of the hysteresis behavior of the electrical polarization versus the
electric field. As it can be seen from figure 2.2, at zero field there are two remanent
polarization states (+Pr and -Pr ) which can be used to store logical “0” and “1”. With
a sufficiently high electric field (E > EC, where EC is the coercive electrical field),
these polarization states can be switched from one state to the other.
Two materials for FeRAM applications have been intensively studied; Lead Zirconate
Titanate (Pb(Zr,Ti)O3 or PZT) and Strontium Bismuth Tantalate (SrBi2Ta2O9 or SBT).
Lead based ferroelectrics have a problem of fatigue, scalability to low voltage, and
environmental, safety, and health concerns. While SBT offers significant advantages
over PZT, such as resistance to fatigue (the decrease in switchable polarization with
electric field cycling), excellent performance in sub-100nm thickness, and operation
2 Advanced Memory Concepts and New Materials for Giga-Bit Scale Memories
10
on a wide variety of electrodes including Pt, PZT has a high potential for FeRAM
application because of large remanent polarization (Pr) and low processing
temperature.
P
+Pr
-E c
+Ec
E
-P r
P sa t
Fig. 2.2: Typical hysteresis curve of a ferroelectric film. Ec is the coercive field
and Psat is the saturated polarization.
The crystal structure of SBT is presented in figure 2.3. It is a layered structure
consisting of two perovskite layers (SrTaO3) along the ab plane and a Bi2O3 layer
between two perovskites along the c-axis with a unit cell a = 5.5306Å, b = 5.5344Å,
c = 24.9839Å.
Fig. 2.3: Crystal structure of SrBi2Ta2O9 (SBT) film [Cho 99].
11
2.4 Integration Aspects of High Dielectric Constant and Ferroelectric Films in CMOS Processes
SBT films with good ferroelectric properties were obtained by Metal-Organic
Chemical Vapor Deposition (MOCVD) [Hin 98]. MOCVD is suitable for high
integration density because of its good step coverage. SBT with good properties was
also demonstrated using the metalorganic solution deposition (MOD) technique
[Nar 99]. In this technique, a thin film is spin-coated using a stable alkoxidecarboxylane precursor solution prepared at room temperature.
2.4 Integration Aspects of High Dielectric Constant and Ferroelectric
Films in CMOS Processes
Two schemes were proposed for applying a high dielectric constant or ferroelectric
layer to DRAMs or FeRAMs, respectively. The capacitor can be arranged directly
above the bit line (stack cell) or can exist on the peripheral circuits (offset cell). For
low integration densities (e.g. for chip cards) the easier offset-cell approach is
sufficient and some companies have shown its feasibility [Shi 99]. However, for
highly integrated devices, a stack-cell must be employed.
In the stack cell as well in the off set cell scheme, the ferroelectric capacitor (bottom
electrode, dielectric layer, and top electrode) is deposited after MOSFET processing
and dielectric passivation. A SEM cross section of a stacked cell configuration with
SBT and a cross-section TEM of a stacked cell with BST are shown in figure 2.4. The
transistor is connected to the storage node electrode by the contact plug made of
doped poly-silicon, which is embedded in an interlayer dielectric (typically a
borophosphosilicate glass BPSG or a tetraethoxysilane oxide layer TEOS)
Pt top
electrode
BST
W
Pt bottom
Pt1
Pt2
electrode
SBT
poly Si
plug
ILD
Poly-Si
Barrier
plug
500 nm
(a)
(b)
Fig. 2.4: SEM and cross-sectional TEM pictures of stacked cells with SBT
films (a) or BST films (b) respectively [Bei 99].
In order to obtain the desired crystallographic structures, the perovskite or layered
perovskite films require to be annealed in an oxidizing atmosphere. Due to this
requirement, the commonly used electrode in SiO2/Si3N4 dielectric cannot be
employed. None of the traditional semiconductors or metals, such as Poly-Si, W, TiN,
Al, or silicides such as TiSi2, are acceptable because these electrodes are not stable
2 Advanced Memory Concepts and New Materials for Giga-Bit Scale Memories
12
against oxidation. An underlying oxide layer between the electrode and the dielectric
film reduces the effectiveness of any high-k material, since a low dielectric constant
oxide in series with the high-k material will decrease the effective capacitance of the
film. The materials of choice for the electrodes must be stable in oxygen ambient, or
form a conductive oxide after oxygen exposure. The only materials that qualify are
noble metals such as Pt, Pd, Ir, or Ru or conductive oxides such as IrO2 or RuO2. Pt
is commonly used as an electrode for the ferroelectric memories, because it does not
readily form an oxide in an oxidizing atmosphere and exhibits low resistivity and low
heat resistance [Cha 95]. However, despite these excellent properties, O2 easily
diffuses through Pt. This fact rendered the integration more complicated since a
barrier, to prevent oxygen diffusion to the poly-plug, is needed. This barrier must also
remain conductive after the thermal processing in oxygen atmosphere. IrO2 acts as a
good diffusion barrier against oxygen at annealing temperatures higher than 600°C.
Moreover, IrO2 has a very low resistivity of 30 µΩ-cm and is stable up to 1100°C in
O2 atmosphere [Rao 74]. To prevent reaction between the poly-Si plug and the
oxygen diffusion barrier, Ir is deposited prior to the oxygen barrier. Ir has the function
to avoid the reduction of IrO2 by the poly-Si during the anneal.
The process flow of integration of the ferroelectric capacitor is schematized in figure
2.5. The process integration can be mainly resumed in the following steps. The
process starts with a front-end processing of the MOSFET, including LOCOS
isolation, p and n-well implantation, gate oxide growth, source/drain implantation,
interlayer dielectric deposition of BPSG (Borophosphosilicate glass), and plug
module processing. A thin layer of Ir/IrO2 and Pt (nearly 100 nm) is subsequently
sputtered. This constitutes the oxygen diffusion barrier and the bottom electrode
respectively. After a short anneal around 600°C, the SBT or BST films are deposited
using MOCVD or MOD. An anneal at 800°C for 60 min. in oxygen atmosphere
follows. This is the standard thermal budget. Actual tendency is towards lower
temperature anneals (below 700°C) [Mör 00]. The top electrode, as well as the SBT
or BST film are structured at the same time using plasma etching. Of course, some
critical technological steps are also involved like plasma etching or Chemical
Mechanical Planarization (CMP) of noble metals.
LOCOS
Wells
Gate
Process
Flow
Front-end processing
of the transistor
Source/Drain
Interlayer Dielectric
Poly-Plug
Oxygen Diffu. Barrier
Bottom Electrode
SBT or BST Deposit.
Back-end processing of
the capacitor module
Top Electrode
Fig. 2.5: Process flow of the integration of ferroelectric capacitor.
13
2.4 Integration Aspects of High Dielectric Constant and Ferroelectric Films in CMOS Processes
In integration of these films, one is faced with a material compatibility issue of
electrodes and is constrained to introduce in CMOS production lines previously
avoided elements like Pt and Ir, known as effective “lifetime killer“. Besides the risk of
contamination with transition metals (Pt and Ir), an additional contamination source is
the dielectric film itself. The deposition, annealing, and processing of the BST or SBT
films present a potential of high contamination with alkaline earth metals (Ba and Sr),
and Bi, a metal from group V.
Ta and Ti are not new elements for the semiconductor fabrication and are acceptable
without problem since they are already integrated in CMOS technology as silicide for
improving contact resistance between silicon and other metals, diffusion barrier such
TiN or TaN, or adhesion layer such as TiO2.
In the following sections, we present in detail the properties of every element as
reported in the literature and the elaborated knowledge about its contamination
aspects.
2.4.1 Barium Strontium Titanate and Strontium Bismuth Tantalate
(Ba,Sr)TiO3
film presents a contamination risk with alkaline earth metals since it
combines both Ba and Sr. In addition to Sr, Bi constitutes another contamination
source for the integration of SrBiTa2O9.
Ba and Sr are completely unknown elements in CMOS technology. Ba is utilized to
produce photocathodes since alkali earth metals deposited on Si are known to
dramatically reduce the substrate work function [Kom 99], a fact that is of great
importance to obtain negative electron affinity photocathodes [Oel 86, Ent 89]
Direct application of Sr in Si technology was not reported and only the case of high
temperature superconductor compound (BiSrCaCuO) for the fabrication of high
speed superconductor-semiconductor devices is known. It was found that Sr
promotes the oxidation of the Si(100) surface and Bi reduces Si oxidation
significantly [Mes 90, Fan 90].
In contrast to the extensively investigated case of Ba and Sr adsorption on silicon
surfaces, the diffusion of Ba and Sr into silicon has received much less attention. For
example, the interaction of Ba overlayers with Si (100) 2 x 1 surfaces has been
intensively studied in recent years [Fan 91, Ura 96, Hu 99]. Fan et al. [Fan 91]
reported different adsorption structures, depending on Ba coverage for temperatures
above 700 °C and presumed that at low coverage (< 1 monolayer ML ), Ba does not
diffuse into the Si(100) surface even at high temperatures of 1000 °C [The coverage
of 1 ML is referred to the number of Si atoms on an ideal unreconstructed Si(100)
surface with the atomic density of 6.8 x 1014 atoms/cm2]. Hongo et al. [Hon 94]
reported that no silicide formation takes place by heating up to 800°C in the case of
sub-monolayer Ba on Si(100) and that silicide is formed very easily by heating up to
250°C for 2 ML Ba on Si(100). Weijs et al. [Wei 92a, Wei 92b] in their work confirmed
that in the case of 5 ML, no Ba silicide is formed at room temperature and that two
phases (BaSi and BaSi2) are detected upon annealing at 277 °C. They also
measured a lowering of Schottky barrier of 0.35 eV in n-substrate.
2 Advanced Memory Concepts and New Materials for Giga-Bit Scale Memories
14
Bi was implanted into Si in the early 1970´s to obtain an n-type dopant [Mar 68,
Pic72]. In comparison to phosphorus, antimony, or arsenic doping, bismuth doped
silicon was not given much attention and Bi as an n-type dopant in Si has been
disregarded of application because of the large ionization energy (71 meV) and the
low solubility limit (8 x 1017 cm-3 at 1320°C) [Tru 60]. The diffusion of Bi in Si was
observed only for relatively high temperature and a diffusion coefficient in the
temperature range between 1050°C and 1200°C was given by Ishikawa et al. [Ish 89]
D = 2.0 x 10-4 exp(-2.5 eV/ kT) cm2/s
(2.2)
At the time of beginning this work, little had been reported on Ba, Sr, or Bi
contamination effects in semiconductor fabrication, and a complete understanding of
degradation behavior was not yet established. Some months lather, it was
demonstrated that Ba and Sr contamination on the wafer surface prior to gate
oxidation increases the defect density in gate oxides [Bea 99, Mer 99]. These results
are not surprising and even expected, since Ba and Sr belong to the same group as
Ca, and thus should behave in the same way as Ca. To that time, however, no useful
knowledge concerning the effect of Ba, Sr or Bi in back-end of line has been obtained
and their behavior, including the diffusion properties at temperatures of 800°C or
below, has not been reported.
2.4.2 Iridium and Platinum Electrodes
2.4.2.1 Platinum
Platinum plays an important role in silicon technology and has attracted a great
interest for lifetime control of minority carriers in the past. Pt introduces deep trap
levels into the bandgap of Si and acts as a very effective recombination center.
Therefore, Pt is widely used to reduce storage times in fast-switching silicon power
devices.
The platinum atom is known as a hybrid solute in silicon and is present in two
configurations. The majority of the solute atoms are stationary substitutionals
whereas a small fraction are highly mobile as interstitial and govern the long-range
transport. During diffusion of Pt, there is a continuous exchange of platinum atoms
between interstitial and substitutional lattice sites. The transformation to the preferred
substitutional configuration can proceed via the Frank-Turnbull mechanism
(dissociative mechanism) [Fra 56], where the interstitial platinum recombines with a
vacancy (V), or via the kick-out mechanism [Gös 80], where the interstitial platinum
kicks out a silicon lattice atom thereby creating a silicon self-interstitial (I). These two
mechanisms are schematically illustrated in figure 2.6.
The reaction of the Frank-Turnbull mechanism is given by:
Pti + V ⇔ PtS
(2.3)
The reaction of the kick-out mechanism can be written as :
Pti ⇔ PtS + I
(2.4)
15
2.4 Integration Aspects of High Dielectric Constant and Ferroelectric Films in CMOS Processes
Pti
Pts
V
(a)
Pts
Pti
I
(b)
Fig. 2.6: Schematic presentation of Frank-Turnbull (a) and Kick-out (b)
diffusion mechanisms.
The Frank-Turnbull mechanism dominates in the diffusion of Au and Pt for sufficiently
low temperatures at which the kick-out diffusion is kinetically hampered [Fra 84]. In
Czochralski silicon the kick-out mechanism is observed to dominate at temperatures
above 730 °C [Man 86, Jac 97]. In float zone material where the thermal equilibrium
concentration of vacancies is believed to be higher, the kick-out mechanism is not
observed below 850 °C [Zim 92, Jac 97].
Substitutional Pt is an electrically active impurity in silicon with two deep energy
levels in the bandgap, an acceptor state in the upper half of the silicon bandgap at
Ec-0.23 eV and a donor state in the lower half at Ev+0.32 eV [Woo 62, Low 80].
Despite the very well understood Pt diffusion mechanism, the diffusion coefficient of
Pt in Si is however not easy to determine. The complexity is due to the dependence
of the interstitial diffusion coefficient on the equilibrium concentration of substitutional
Ceq(Pts) and interstitial Ceq(Pti).
D(Pt i ) = D eff (Pt i )
C eq (Pt s )
C eq (Pt i )
(2.5)
2 Advanced Memory Concepts and New Materials for Giga-Bit Scale Memories
16
where Deff is the effective diffusion coefficient.
The solubility of Pt in silicon in the temperature range between 800°C and 1000°C is
[Lis 75]:
S = 5 x 1022 exp(9.44 – 2.676 eV/ kT) cm-3
(2.6)
At 800°C, the solubility limit of Pt is 1.7 x 1014 cm-3.
Pt was found to be gettered effectively by phosphorus diffusion. Gettering is the
localization of the metallic impurities in region, away from the device active regions,
where they cannot be harmful. Falster explained the mechanism of Pt gettering by
phosphorus as follows [Fal 85)]: The phosphorus diffusion injects silicon selfinterstitials into the bulk, which kick-out the low mobility, high solubility substitutional
Pt into high mobility and low solubility interstitial Pt. This causes a supersaturation of
Pt and leads to its diffusion out of the bulk to the infinite sink at the sample surface,
where it segregates. Pt can also be gettered by structural damage due to high energy
ion implantation, which forms a region in the wafer, where Pt can segregate [Hol 95,
Sch 99].
2.5.2.2 Iridium
Ir was also used in high power fast switching application to reduce the minority
carrier lifetime in order to obtain a short recovery time. Ir found another application in
Schottky infrared detectors to extend the detection range up to 12 µm [Tsa 90].
A diffusion coefficient and a solubility limit in the temperature range of 700°C to
900°C and in Czochralski-Si were given by Azimov et al. [Azi 76,Azi 77] :
D = 7.2 x 10-3 exp(-1.2 ± 0.05 eV/ kT) cm2/s
(2.7)
S = 4 x 1023 exp(-2.2 ± 0.1 eV/ kT) cm-3
(2.8)
At 800°C, the solubility limit of Ir in Si is about 2x1013 cm-3 and in comparison to Pt or
Au, Ir diffuses relatively slowly.
The diffusion properties of Ir in Si were less intensively studied in comparison to Pt or
Au. Recently, Obeidi et al. [Obe 00] investigated the diffusion of Ir in floating-zone Si
wafer at temperatures between 1000 and 1200°C and found that Ir diffuses in Si
mainly via the kick-out mechanisms. Ir diffusion coefficient and solubility were given
by Obeidi et al. :
D = 2.4 x 10-3 exp(-0.91 eV/ kT) cm2/s
S = 6.0 x 1020 exp(-1.6 eV/ kT) cm-3
(2.9)
(2.10)
Bellow 1000°C, and in CZ-Si, which mechanism governs Ir diffusion is still not
reported. The gettering of Ir is also completely unknown.
3 Experimental Methods
3.1 Method and Principle of Intentional Contamination
A method of controlled contamination on the wafer surface, based on the use of an
aqueous solution containing metallic impurities and a spin coater, was utilized for the
intentional contamination of the wafers. This method was proposed by Hourai et al.
[Hou 88], and is also known as spin-coat or spin-on spiking contamination. It is
schematically presented in figure 3.1.
The contaminating solution
Wafer
Teflon chuck
Fig. 3.1: Schematic view of the spin-coating contamination method.
A vacuum chuck, specially designed to avoid unintentional contamination on the
back-side of the wafer was used. This chuck (completely made of Teflon) can be
cleaned from run to run in a solution of 3% HCl (37%) at room temperature. Special
attention has been paid to the contamination from the chuck of the spin tool. This is
very important to obtain reliable results, since an unintentional contamination with
Fe, Ni, Cu much higher than 1010 at/cm2 level could have more impact than the
intentional contamination. On the other hand, the contaminated wafers have to be
further processed in a clean room of class 1, for which stringent and strict
acceptance rules of tolerable contamination level (below 1011 at/cm2 for all elements)
have to be fulfilled. Systematic examination of the initial contamination level from the
chuck was done before and after every run by carrying out either Vapor Phase
18
3 Experimental Methods
Decomposition-Total Reflection X-Ray Fluorescence (VPD-TXRF) or Vapor Phase
Decomposition-Atomic Absorption Spectroscopy (VPD-AAS) analysis (see
chapter 3). Wafers in position “face-down” (front side on the chuck) or “face-up”
(back-side on the chuck) with simulated actions, were routinely analyzed. An
example of this acceptance test, done with VPD-AAS, is shown in Table 3.1.
Table 3.1: Typical residual contamination level (in units of 1010 at/cm2) from
the chuck as obtained from the acceptance test; dl stands for detection limit.
Na
K
Ca
Zn
Fe
Al
Cu
Cr
Ni
Ir
Pt
0.209
0.340
0.083
0.439
0.404
0.279
0.105
2.590
2.639
1.258
< dl
1.225
0.271
< dl
4.267
< dl
< dl
< dl
< dl
< dl
0.889
< dl
0.340
0.104
< dl
9.999
< dl
< dl
< dl
< dl
< dl
3.646
< dl
0.714
0.219
0.915
5.530
< dl
< dl
< dl
< dl
< dl
dl of
0.059
VPD-AAS
Before conta- 1.689
mination
During the
operation
After contamination
This method has the advantage of being more quantitative than the other reported
methods, such as dipping in an aqueous solution containing metallic impurities [Sug
86], scrapping with a metal wire [Spa 86], evaporation of a metal film [Lo 81], or ion
implantation [Ohs 84]. With the exception of ion implantation, these methods are
qualitative and not controllable in low-level contamination. For example, a sputtered
Pt layer, even for very short sputter time, corresponds to a concentration of more
than 1015 at/cm2 on the surface.
Sr(NO3)2, Ba(NO3)2, BiO(NO3), IrCl3, or H2PtCl6 atomic absorption standard from
Aldrich Chemical, containing 1000 mg/l of each element of interest, were used to
prepare the contamination sources. These master solutions were diluted in SC1
solution [NH3(25%):H2O2(31%):H2O in ratio of 1:4:20] down to concentrations
between 1 ppm and 100 ppm. Chemicals with VLSI grade from Merck combined with
DI-water (18 MΩ) were used to maintain any unintentional contamination at levels of
1010 at/cm2.
Prior to the intentional contamination with Sr, Ba, Bi, Ir, or Pt, the wafers received an
RCA clean to remove any initial contamination. At the end of the cleaning process,
the wafer surface was kept hydrophilic. The wafer was then mounted on top of the
chuck, and 10-12 ml of aqueous solution, consisting of controlled quantities of the
metallic impurity (Sr, Ba, Bi, Ir, or Pt) in SC1 solution, was pipetted onto the wafer
surface. The surface was hydrophilic, so that the dropped solution covered the entire
surface of the wafer smoothly and immediately. The wafer was kept in this state for 5
minutes to allow the metal to be adsorbed in the native oxide layer on the surface,
and subsequently spun dry. A high rotation speed of 3500 rpm for 15 seconds was
used to prevent unintentional back-side contamination.
3.2 Method and Principle of Intentional Contamination
19
The adsorption of metallic ions onto hydrophilic surfaces from aqueous solution has
been explained by Loewenstein et al. [ Loe 98, Loe 99 ]. According to their model,
the Si-OH groups act as ion exchangers. The SiOH groups, called silanol groups,
dissociate in water as follows :
KH
SiOH (s) ⇔ SiO − (s) + H + (aq)
(3.1)
where KH is a constant describing the attraction of H+ ions to the surface.
The silica (SiO) has a negative surface charge across most of the pH range
[Sma 98], and positively charged metal ions, therefore, tend to adsorb to negatively
charged silica surfaces over a wide pH range as is shown in equation 3.2
KM
SiO − (s) + Mn+ (aq) ⇔ SiOM(n−1)+ (s)
(3.2)
where KM is a constant which expresses the attraction between surface sites and
metal ion Mn+.
The relationship between the metal surface concentration σSiOM, the metal
concentration in the aqueous solution [M+], and the volume concentration of the
hydrogen ions is given by :
σ SiOM
K M [M+ ] σ
=
1 + K H [H + ] + K M [M + ]
(3.3)
where σ is the surface density of all adsorption sites :
σ = σ SiOM + σ SiOH + σ SiO −
(3.4)
The surface concentration of a metal ion depends on the constant KM, σ the surface
+
density of all adsorption sites, the concentration of the metal ion [M ], and the
volume concentration of the hydrogen ion [H+]. Equation 3.3 can also be written as
follow:
1
σSiOM
=
1 + K H [H+ ] 1 1
⋅ +
K M [M+ ] σ σ
(3.5)
Equation 3.5 shows a linear dependence between (σSiOM)-1 and [M+]-1, which implies
a linear dependence in log-log plot of the metal surface concentration versus the
metal concentration in the solution.
Loewenstein et al. [Loe 98] examined the effect of pH and the time allowed for the
metal to be adsorbed on the surface. They observed a significant effect of pH but not
of time. The time dependence was seen only for a few metals.
20
3 Experimental Methods
The homogeneity of the concentration over the surface was checked before
annealing. Except for Bi, a good homogeneity, with a deviation of nearly 1%, is
obtained from this method as shown in Table 3.2. The relative large deviation in Bi
concentration may be due to a weak attraction coefficient KM between surface
adsorption sites and Bi ions.
Table 3.2: Example of homogeneity of the concentration on the surface using
the spin-coat contamination method. Example is shown for a 10 ppm of each
element in a SC1 solution. All the values are in unit of 1010 at/cm2.
Coordinate in mm
from the center
Point 1 (0,0)
Point 2 (0,40)
Point 3 (40,0)
Point 4 (0,-40)
Point 5 (-40,0)
Mean value
Standard deviation
Standard deviation
(in %)
Ba
Sr
Bi
Ir
Pt
1667.55
1625.97
1632.53
1619.76
1628.93
1635.00
18.81
1698.00
1630.00
1761.00
1672.00
1603.00
1672.80
61.48
1729.00
2283.00
1875.00
1792.00
4721.00
2480.00
1271.24
516.47
529.24
532.85
525.10
537.20
528.17
7.92
716.14
709.18
695.59
685.10
693.26
699.85
12.56
1.1%
3.6%
51.2%
1.4%
1.7%
3.2 Analytical and Electrical Measurements
3.2.1 Total Reflection X-Ray Fluorescence and Vapor Phase DecompositionTotal Reflection X-Ray Fluorescence
Total Reflection X-Ray Fluorescence (TXRF) has become a very important analytical
method which is used routinely to monitor contamination in production line because
11
2
of its sensitivity below 10 at/cm (depending on element). In this non-destructive
method, the sample surface is irradiated with x-ray at a grazing angle less than that
required for total reflection. As a result, the primary x-ray beam is totally reflected.
Only the atoms at the surface of the wafer are excited, which causes them to emit
fluorescence x-rays with energies characteristic of the elements at or near the
surface. The analysis depth corresponds to the penetration depth of X-ray under
total reflection conditions, which can be given by z n = λ 4π β . λ is the wavelength
and β is the imaginary part of the refractive index of the medium (at X-ray
wavelength). For silicon and Mo-Kα radiation, the minimum penetration depth is
3.2 nm. This reduces considerably the undesirable background X-ray radiation from
the substrate because the penetration of the incident radiation into the material is
practically negligible. Emitted fluorescence X-rays are then analyzed by a Si(Li)
detector. The setup of the instrument used in this work is shown in figure 3.2.
Because of the use of an X-ray monochromator, the emitted fluorescence radiation
exhibits an extremely low background. The primary monochromatic X-ray beam is
obtained from a rotating cathode-type X-ray source. A solid state detector (SSD)
detects the emitted fluorescence radiation and converts it into an electrical signal,
which is treated by a pulse processor. A spectrum showing peaks is obtained. All the
3.2 Analytical and Electrical Measurements
21
elements with atomic number Z higher than 11 (sodium), can be detected. For the
elements with Z<11, their detection is problematic, since the wavelength of the
emitted fluorescence signals is above 10Å, which is beyond the sensitivity of the
most X-ray detectors.
The detection limit of TXRF in comparison to the other techniques (some of them
explained in the following sections) is shown in figure 3.3. Also included in this figure
is the TXRF detection limit for commonly used excitation anodes (Mo or Cr).
Linear
Amplifier
Data Processing
Multi-channel
Analyzer
Pre-amplifier
Monochromator
SSD
Scintillation
Counter
Controller
Sample stage (x,y,z,tilt)
Rotating
Anode
Fig. 3.2: Schematic view of the TXRF system
The fluorescence intensity emitted from a layer between depth z and z+d from the
surface, is given, as function of the glancing angle φ, by [Klo97] :
æ z ö é
æ d
φ
I f (φ, z ) = In ⋅ c ⋅ C s ⋅ [1 − R(φ)] ⋅ ⋅ expçç − ÷÷ ⋅ ê1 − expçç −
d
è zn ø ë
è zn
öù
÷÷ ú
øû
(3.6)
where In is a reference intensity, c a constant, Cs the surface concentration, R the
reflectivity of the substrate, and zn the penetration depth of the incident X-ray beam.
The quantity [1-R(φ)].φ, called the transfer energy, represents the quantity of
impinging energy that penetrates into the substrate.
22
3 Experimental Methods
For a thin contamination layer only on the surface, equation 3.6 leads to :
I f (φ) = In ⋅ c ⋅ C s ⋅ [1 − R(φ)] ⋅
φ
zn
(3.7)
The TXRF tool used in this work was the model 8030W from Atomika. This model
operates with a Mo anode at hν=17.44 keV. The measurements were done at an
incident angle of 1.3 mrad (lower than the critical angle of total reflection of 1.74
mrad for 17.44 keV radiation) and an acquisition time of 1000 s. The instrument was
calibrated with a 1 ng Ni droplet standard, which corresponds to a concentration on
the surface of 2.041x1013 at/cm2.
The detection limit of direct-TXRF can be improved by more than 2 orders of
magnitude, if the metal is preconcentrated on a residue. VPD-DSE (Vapor Phase
Decomposition-Droplet Scan Etch) combined with TXRF is one of the standard
analytical techniques used to investigate and monitor metal contamination on silicon
wafer surfaces, and to improve detection limits of TXRF from 1011 at/cm2 to the
range of 109 at/cm2 or below [Fab 95].
Minimum detectable coverage (at/cm2)
1E+14
1E+13
Direct TXRF (Mo)
Direct TXRF (Cr)
VPD-TXRF (Mo)
VPD-TXRF (Cr)
VPD-AAS
VPD-ICPMS
TOF-SIMS
1E+12
1E+11
1E+10
1E+09
1E+08
1E+07
Li Na Al
P
S
Cl
K Ca Ti Cr Fe Co Ni Cu Zn As Br Rb Sr Sn Ba Hf Ta Ir
Pt Pb Bi
Fig. 3.3: Comparison between the detection limit of TXRF and VPD-TXRF for
Mo or Cr anode, ToF-SIMS, VPD-AAS, and VPD-ICPMS. VPD data are given
for wafers of 150 mm diameter.
In the VPD preparation technique, the silicon wafer is exposed to an HF vapor
ambient for some minutes to decompose the oxide film (native or thermal) on the
wafer surface according to the chemical reaction :
6 HF + SiO2 → H2SiF6 ↑+ 2H2O (residue)
(3.8)
3.2 Analytical and Electrical Measurements
23
The residual water contains the impurities from the oxide and the silicon/oxide
interface. Since the treatment in HF results in a hydrophobic wafer surface, large
amount of droplets form on the wafer surface. They are collected by ”rolling off“ an
HF/H2O2 droplet (typical volume of 100 µl) concentrating all the surface contaminants
into a single droplet. The DSE droplet is dried in vacuum on a clean Si wafer, and the
residues, several mm2 size, are analyzed by TXRF. Since the size of the dried
droplet is fully enclosed within the TXRF analysis area (typically 0.5 cm2), the
sensitivity is increased by the ratio wafer area/TXRF analysis area.
The VPD-DSE may lead to erroneous results, if the contamination in oxide can not
be completely collected with the DSE solution. A serious problem with VPD is that
the quantification suffers from the problem of non perfect collection efficiency which
depends on the metal, its chemistry and its concentration on the surface [Met 97].
There is no standard DSE solution, with good collection efficiency for all the
elements. For example, a collection solution consisting of 2 wt% HF/ 7 wt% H2O2 has
an efficiency greater than 80% for Cu, but below 10% for Pt for the same
concentration of Cu and Pt.
3.2.2 Time of Flight-Secondary Ion Mass Spectroscopy
In contrast to dynamic Secondary Ion Mass Spectroscopy (SIMS), in which the
surface of the sample is continuously bombarded with primary ions, the Time of
Flight-Secondary Ion Mass Spectroscopy (ToF-SIMS) uses very short pulses of
primary ions (as short as possible, typically 1ns) having a low enough fluence to
ensure that the probability that a surface region receives more than one primary ion
simultaneously is negligible. Thus the secondary ions are generated almost
simultaneously from one pulse. The secondary ions are accelerated into a massanalyzer with a common accelerating voltage Vac. Due to their different masses, the
various secondary ions reach different velocities. The lighter ions move through the
analyzer more rapidly than the heavier ions. The principle of measurement is
illustrated in figure 3.4
∆tp
∆tD
stop
start
L
Sample
Vac
t
Detector
Fig. 3.4: Principle of measurement with ToF-SIMS instrument.
24
3 Experimental Methods
The times of flight T (time to travel through the analyzer of length L) are measured
and the ions become separated according to the time to traverse the analyzer as
described by equation 3.9 :
m 2 Vac T 2
=
Z
L2
(3.9)
where Z is the atomic number. The detection of elements and large organic
molecules is possible. A mass separation of the ions is then possible with a
resolution of :
∆m ∆E 2( ∆t p + ∆t D )
=
+
m
E
t
(3.10)
where ∆tp is the pulse duration, ∆tD is the time resolution of the detection system, ∆E
is the energy of the emitted secondary ions, and E is the sputter energy. A mass
resolution of 10000 could be obtained.
As shown in figure 3.3 ToF-SIMS has detection limits comparable to direct TXRF and
VPD-TXRF for some elements. The sensitivity of TOF-SIMS combined with the
possibility of imaging on patterned wafers, makes it a powerful analysis technique for
contamination control.
A depth profile measurement with ToF-SIMS can also be performed using a dual
beam mode. As shown in figure 3.5, pulsed primary ions are used to sputter
(remove) many monolayers in a short time. A crater is etched by this low energy
sputter gun equipped with oxygen ion or cesium ion source. After etching, the
sputtering beam is switched off and a second ion gun (generally a liquid metal Ar or
Ga) is then operated in the pulsed mode for the analysis and data acquisition of the
exposed surface in the crater center. A profile is obtained by rapidly switching
between sputtering and analysis.
The relative sensitivity factor (RSF) required to convert ion intensity into
concentration, is determined experimentally or calculated theoretically. For the
determination of the RSFs, ToF-SIMS surface mode measurements are correlated
with the surface concentration of the element Cs, as obtained by direct TXRF, using
the following relationship :
C s = RSF ⋅
I
(3.11)
ISi30
where I is the measured intensity of the element and ISi30 is the intensity of the Si
reference signal of mass to charge ratio m/Z 30.
The RSF of a surface constituent M can be calculated according the theoretical
model given by Benninghoven [Ben 75, Ben 94] :
RSF(M) =
H( X iq ) ⋅ Y( X iq )
⋅ 6.8 x 1014
H(M) ⋅ Y(M)
at / cm 2
(3.12)
3.2 Analytical and Electrical Measurements
25
( )
where H X iq is the average number of secondary particles of a given type X iq
generated from a closed monolayer of particles M by the impact of one primary ion
and Y is the sputter yield (number of sputtered off particles per incident ion).
When comparing the TXRF results of Fe contaminated samples with the results of
ToF-SIMS as obtained from a quantification following the theoretical model of (3.12),
De Witte et al. [DeW 00] observed an agreement on samples with oxidized surfaces.
For non-oxidized surfaces, a difference of a factor of ten was noticed. According to
Benninghoven [Ben 94], this is due to the fact that the sputter yield Y( X iq ) is
influenced by the chemical nature of the surface component M and its chemical
environment. This matrix effect gives rise to quantification problems.
Fig. 3.5: ToF-SIMS depth-profiling measurement principle.
During analysis of insulators like a thermal oxide layer on the surface, charging of
this layer occurs due to the bombardment with charged primary ions. The built-up of
charge in the oxide surface layer complicates the analysis. Charging changes the
trajectories for both primary and secondary ions, makes the detection of the
secondary ions unstable, and reduces, or even completely suppresses the signal
[Hom 84]. An already established method to analyze insulating samples consists in
compensating the charge with the aid of electron beam flooding. This method was
found to be useful and successful for analysis of various dielectric materials
[Hom 84].
26
3 Experimental Methods
3.2.3 Electrolytic Metal Tracer (ELYMAT)
The minority carrier recombination lifetime is an important device parameter, which
can be used to monitor effective recombination centers in the wafer like metallic
impurities or crystalline defects (oxygen precipitation for example). Whereas the
lifetime τ is primary used in integrated circuit engineering, the diffusion length L
( L = Dτ ) is more commonly specified for solar cells.
Mainly three mechanisms of recombination explain the kinetic of carriers
recombination. These mechanisms are Shockley-Read-Hall recombination (SRH),
radiative recombination, and Auger recombination.
The Auger recombination is the dominant mechanism in highly doped Si [Fos 83] or
for high-level injection conditions [Bec 73], the radiative recombination is negligible in
an indirect band material like Si.
According to the SRH model [Sho 52, Hal 52], electrons from the conduction band
and holes from the valence band recombine through discrete levels (generally deep
level) in the semiconductor band gap as illustrated in figure 3.6. These levels are
introduced either by impurities like dissolved metals in Si or by crystal defects.
EC
ET
EV
Fig. 3.6: Shockley-Read-Hall recombination mechanism
The lifetime is then given by :
τ SRH =
(σ p v th NT ) −1 (n 0 + n1 + ∆n) + (σ n v th NT ) −1 (p 0 + p1 + ∆p )
p 0 + n 0 + ∆n
(3.13a)
where σp, σn are capture cross section for holes and electrons respectively, vth the
thermal diffusion velocity of electrons in p-Si (1.93 x 107 cm/s at 300K) and holes in
n-Si (1.6 x 107 cm/s at 300K), NT the impurity density, n0, p0 the equilibrium densities
of electrons and holes respectively, n1, p1 the electrons and holes densities
occupying the energy level ET, and ∆n, ∆p excess carrier densities.
For low level injection (the excess minority carrier density is small compared to the
majority carrier ∆n, ∆p << p0 or n0), the well known approximation of the lifetime is
then obtained :
3.2 Analytical and Electrical Measurements
τ=
1
σ v th NT
27
(3.13b)
If the wafer does not contain a single but rather several different traps, each trap
contributes to the lifetime, and the resulting lifetime is given by :
1 τ = å1 τi
(3.13c)
i
Several measurement techniques are available to measure the minority carrier
lifetime, which are Microwave Photo-Conductivity Decay (µ-PCD), the Surface
Photo-Voltage (SPV) and the Elymat technique. We will discuss here only the used
tools (Elymat and µ-PCD). Details concerning the principle of SPV can be found in
the papers of Lagowski et al. and the references therein [Lag 92, Lag 98].
In µ-PCD, a laser pulse is used to generate excess carriers on the surface of the
wafer, and thus increases the conductivity, which leads to an increase in the
reflected microwave intensity. The measured change in microwave power ∆P is
related to the density of excess carriers ∆n by the relationship :
∆P(t )
∆n(t )
= A ⋅ q ⋅ (µ n + µ p )
P
n
(3.14)
where A is a sensitivity factor, n the carrier density, µn the mobility of electrons (1500
cm2/Vs), and µp the mobility of holes (450 cm2/Vs). Assuming a simple exponential
decay of ∆n(t), the effective lifetime (superposition of bulk and surface
recombination) is measured from the time dependence of P(t).
In µ-PCD, the measured lifetime is influenced by surface and bulk effects, whereby
the bulk recombination is a characteristic parameter of the material. The surface and
bulk recombination cannot be separated, unless the surface is passivated with a high
quality thermal oxide for example [Yos 96]. A limitation with µ-PCD is the use of a
high power laser for the excitation on the surface without controlling the carrier
injection levels. This affects the measured lifetime since it has been reported that the
recombination lifetime increases significantly if the injection level is low [Fij 93].
In the Elymat technique, the wafer is inserted between two electrolytical cells, both
filled with dilute HF (typically 1%). Platinum electrodes are employed for the electrical
contact to the electrolyte cell, and tungsten carbide tips are used for the ohmic
contact with the wafer edge (figure 3.7). The excess of minority carrier is generated
at one side of the wafer by a HeNe laser operating at two wavelengths (670 and
905 nm).
A key feature in Elymat is the use of the electrolyte for surface passivation in order to
minimize the surface recombination velocity. Using a 1% HF, a very low surface
recombination velocity approaching a completely negligible value can be obtained
[Föl 91]. A value of 0.25 to 1 cm/s was given in the literature [Yab 86, M´sa 94].
Elymat operates in two modes. In the BPC (Backside PhotoCurrent) mode, the
minority carriers diffusing through the whole wafer are collected with a reverse-
28
3 Experimental Methods
biased semiconductor electrolyte junction at the back-side. In the FPC (Frontside
PhotoCurrent) mode, the collecting junction is placed at the front side.
In the BPC mode, the generated minority carriers at the front side have to diffuse to
the back surface, where they are collected. On their way through the bulk, the
generated minority carriers recombine with effective recombination centers.
In the FPC mode, the collecting junction is at the front side of the wafer, so the
minority carriers are not allowed to diffuse through the whole wafer. In this mode, the
minority carriers are generated within some few µms from the surface (depending on
the penetration depth of the laser used). If the region near the surface is free from
metal precipitation, the minority carriers will not recombine but will be collected as a
current, which has the same value as the photocurrent used for generation so that
the collection efficiency is equal to 100%. In this mode, the minority carriers are
collected to a good approximation independent of the diffusion length. The effect of
metal contamination is mainly through near surface precipitates which reduce the
collection efficiency of the semiconductor electrolyte junction. In the FPC mode, the
surface layer is mainly probed for defects like metal silicide precipitates.
Depletion layer
Laser
Laser
Beam
Beam
HF
HF
HF
HF
Pt-contact
p-Si
(a)
p-Si
(b)
Fig. 3.7: Elymat in BPC (a) and FPC (b) functional mode
For these reasons and considering the inconvenience of µ-PCD (necessity of
passivation oxide), we choose Elymat, as the principal technique, to assess the
influence of the new elements emerging from the ferroelectric materials on minority
carrier lifetime.
3.2 Analytical and Electrical Measurements
29
The lifetime is calculated from the measured diffusion current using the following
equation :
L = Dτ =
d
, in BPC mode
ar cosh(Ipho / Idiff )
(3.15a)
and
æ
ö
ç
÷
1 ç exp( − W α ) ÷
L = Dτ = ç
− 1÷ , in FPC mode
Idiff
α
ç 1−
÷
ç
÷
I
pho
è
ø
(3.15b)
where Ipho is the photocurrent used for the generation, Idiff the measured diffusion
current, L and D are the minority carrier diffusion length and diffusion coefficient,
respectively (D = 33.5 cm2/s for electrons and 12.4 cm2/s for holes at room
temperature), α the absorption coefficient, W the space-charge region width, and d
the wafer thickness. The equations 3.15 were derived from the expression of the
diffusion current :
Idiff =
q ⋅ A ⋅ P0 ⋅ α 2 ⋅ L2
, in BPC mode
æd− W ö
2
2
α − L − 1 ⋅ coshç
÷
è L ø
(
)
(3.16a)
and
æ
æ α ⋅ W öö
Idiff = q ⋅ A ⋅ P0 çç1 − expç −
÷ ÷÷ , in FPC mode
è 1+ α ⋅ L ø ø
è
(3.16b)
where P0 is the photon flux, and A the laser spot area.
These equations were obtained from the resolution of the one dimensional continuity
equations in steady state, assuming no electric field effect and considering only the
diffusion component [Leh 88]. Although this is a rather crude simplification of the
complicated continuity equations, good agreements between Elymat and other
techniques like SPV are still obtained [Sea 98].
3.2.4 Deep Level Transient Spectroscopy (DLTS)
DLTS is a well-established technique to study and identify deep level impurities in
semiconductors. In bulk silicon, the position of several traps in the bandgap, their
capture cross-sections and their concentrations can be determined. In MOS
structures, the SiO2/Si interface properties can be investigated.
The DLTS is a transient capacitance technique, which in essence measures, in n-Si
for example, the electron emission rate from the trap level to the conduction band.
The principle of the measurements is based on the presence of a space charge
region, and thus a depletion region of a Schottky barrier or reverse biased diode is
needed.
30
3 Experimental Methods
The bias is pulsed between a bias near zero and a reverse bias V0 with a repetition
time. The near zero bias condition is held for a time during which the traps are filled
with majority carriers. During the reverse bias pulse the trapped carriers are emitted
at a rate producing an exponential transient in the capacitance. The example of a
donor trap (positively charged if empty and neutral if filled) is shown in figure 3.8
Initially the junction is reverse biased at V0, and has a space charge width W 0. The
trap level ET intercepts the Fermi level EF at the abscissa :
x = W 0–λ0,
(3.17)
where λ 0 = 2ε 0 ε s (E F − E T ) / q ND and ND is the doping concentration.
For x < W 0–λ0, the traps are empty, and thus positively charged, and for x > W 0–λ0,
they are filled, and thus neutral. At t=0, a reverse bias pulse is applied for very short
time tp having an amplitude V1 < V0. As in the situation of the bias V0, the traps are
filled for x > W 1–λ1, and empty for x < W 1–λ1, with W 1–λ1< W 0–λ0 since V1 < V0.
When the bias is switched back to V0, the filled traps in region between W 1–λ1 and
W 0–λ0 emit electrons back to the conduction band. The emitted electrons are rapidly
swept out of the depletion region by the applied field which results in an increase in
the positive space charge density and thus an increase in capacitance.
C( t ) =A⋅
nt ( t )
q εs
æ
ND çç 1 2 ( V bi + V - 2 k T / q ) è
ND
ö
÷÷
ø
= C0 1−
n t (t )
ND
(3.18)
where nt(t) is the electrons concentration that occupy the deep level trap, Vbi is the
built-in voltage and A the surface.
Assuming nt(t)<< ND, the change in capacitance ∆C(t ) = C(t ) − C(∞ ) can be written :
n (t )
∆C(t )
=− t
C(∞ )
2ND
(3.19)
where C(∞),the final capacitance (nt(∞) = 0), is given by :
C( ∞ ) =A⋅
q εs
ND
2 ( Vbi + V - 2 k T / q )
= C0
(3.20)
3.2 Analytical and Electrical Measurements
31
Semiconductor
Metal
EFM
V0
++
+
+
EC
++
EF
ET
x
0
W 0 −λ 0
W0
V1
+
+
EC
+
ET
x
0
W 1 −λ 1
W1
Fig. 3.8: Schematic presentation of the band structure for the bias V0 (a), and
V1 (b). + denotes empty, • filled traps, and • electrons in the conduction band.
Assuming the thermal emission of electrons as the unique operative process (no
optically induced emission of electrons), the variation with time of electron
concentration nt(t), that occupy the deep trap is:
æ dn t ö
ç−
÷ = e n ⋅ n t (t )
è dt ø
(3.21)
where en is the probability per unit time, commonly termed “emission rate”, that an
electron is emitted to the conduction band. The expression (3.19) can be written :
N
∆C(t )
= − t exp( − e n t )
C(∞ )
2ND
(3.22)
32
3 Experimental Methods
Equation 3.22 shows that the amplitude of the capacitance transient can be related
to the trap concentration and that the time constant of the capacitance transient
gives the thermal emission rate. This constitutes the basis of DLTS, which makes
use of the strong dependence of emission rate on temperature :
æ E ö
en (T ) = γ T 2σn expç − a ÷
è kT ø
(3.23)
where γ is a constant, σn and Ea are the electron capture cross section and activation
energy (Ec-ET).
3.2.5 Gate Oxide Integrity
One of the harmful effects correlated with the presence of metal contamination on
the surface of silicon is a detrimental degradation of the gate oxide strength.
Often, the metal contamination present on the surface, precipitates as a silicide
during any cooling phase of a thermal annealing process prior to the gate oxidation.
These precipitates enhance the surface micro-roughness, and, therefore, cause
inhomogeneities and thickness variation of the gate oxide over the wafer. It was
demonstrated, that the surface micro-roughness reduces the dielectric breakdown
field and the charge to breakdown significantly, if the average micro-roughness Ra
increased from 0.2 to 0.8 nm [Miy 92]. The problem is more exacerbated as in Gbit
scale integration, the necessity to maintain smooth surfaces will be an important
issue and that the micro-roughness will be more pronounced in effect [Fut 98].
If the metal contamination is present just before the gate oxide growth, the metal
precipitate grows up to the oxide, causing a local thinning of the oxide (figure 3.9).
This case was well established for Fe contamination by Honda et al. [Hon 85] and for
Cu contamination by Wendt et al. [Wen 89]. In the vicinity of the local oxide thinning,
the electric field enhances, thus increasing current injection at a lower applied
voltage (VG) and consequently causing breakdown at lower voltage. If the
precipitation of the metal is severe, it can break the gate oxide and cause a pinhole.
These are the most well known cases of the metal contamination effect on gate
oxide integrity (GOI). Other contamination opportunities, i.e. after gate oxidation or
after gate oxidation and further processing, are still unknown. Depending on the
process when contamination occurs (before gate oxide growth, after gate oxide
growth, after gate oxide growth and subsequent processing), the effects are not the
same as in the case when contamination is present prior to gate oxidation. These
effects depend on the solubility, diffusivity and chemical reaction of the contaminant
in the oxide as well as at the interface oxide/silicon. Takiyama et al. [Tak 94] showed
that for the case of Fe contamination, a large difference in the breakdown strength
existed between three types of samples, where (1) Fe is incorporated into the oxide
film and precipitates at the Si/SiO2 interface, (2) Fe is concentrated at the oxide
surface and does not exist at the Si/SiO2 interface, and (3) Fe precipitated at the
Si/SiO2 interface and is not incorporated in the oxide film, although the Fe
contamination level was the same for all samples.
3.2 Analytical and Electrical Measurements
33
VG
VG
deff
0V
∆d
d
Si
Fig. 3.9: Example of local thinning of the oxide due to metal precipitation.
Ramappa et al. [Ram 99] compared their results of Cu contamination effect on oxide
breakdown with the results of Henly et al. [Hen 95] concerning Fe and observed that
Cu is not as detrimental as Fe in causing oxide breakdown. They explain this on the
basis of the difference in segregation properties between Cu and Fe. While Cu
precipitates into the silicon side, Fe segregates into the oxide side of the interface
between SiO2 and Si, and penetrates into the oxide causing a local oxide thinning.
Metals were also observed to degrade the breakdown strength of the gate oxide by
strongly enhancing the decomposition of the oxide. Liehr et al. [Lie 88] showed that If
an oxide film containing metal contamination is given an anneal in inert ambient or
low oxygen partial pressure, the oxide was found to decompose by the formation of
volatile SiO. The decomposition reaction of the oxide, SiO2 + Si → 2SiO,
accelerates at the interface SiO2/Si. Liehr at al. observed two kinds of metal reaction
with oxide. Metals like Al, Mg, and Ti showed chemical reaction with the oxide
leading to the formation of metal silicate and production of the volatile SiO. Others
metals, generally noble metals, like Au, Pt, Ag, Cu, Ni, and W do not react with the
oxide, but diffuse to the SiO2/Si interface to influence oxide decomposition.
According to Liehr et al. interfacial metals enhanced the void nucleation with leads to
the decomposition of the oxide film. This difference can be well understood from
thermodynamical considerations. Table 3.3 shows the enthalpy of formation of some
oxides in comparison to Si. These values indicate that only Ca, Mg, and Al can form
metal oxide during the thermal anneal by reducing the SiO2 to Si. In turn, the other
metals cannot reduce the SiO2, but are reduced by Si to form SiO2. According to
Liehr et al., the noble metal at the interface transfers an electron from its d-band to
the Si-O bond at the interface, since this transfer is thermodynamically favorable
over the formation of SiO2. The formation of volatile SiO is then kinetically enhanced.
34
3 Experimental Methods
Table 3.3: Enthalpy of oxide formation. Negative value of ∆Hf means a heat
releasing process.
Element
Ca
Mg
Al
Si
Na
Cr
Zn
Fe
Ni
Cu
Chemical form of
Metal oxide
CaO
MgO
Al2O3
Na2O3
Cr2O3
ZnO
FexOy
NiO
CuO
∆Hf
(kcal/g)
-76
-72
-66
-53
-50
-45
-42
-33
-28
-20
.
Two failure modes can be observed when oxides fail. The extrinsic mode, occurring
in the early stage of the device operation, and in decreasing failure rate, is attributed
to organic or metallic contamination, to surface micro-roughness, to particles on the
surface [Miy 97] and to substrate related defects like oxygen precipitation. The
intrinsic mode, occurring late, during the wear-out period of the oxide, and in
increasing failure rate, is inherent to the lifetime of the oxide. Therefore, the extrinsic
failure could be more important to the device reliability than the intrinsic failure, if the
early failure rate (known also as infantile mortality) is excessive.
While the intrinsic mode was extensively studied and several models were proposed
to explain the mechanism of oxide breakdown, the extrinsic mode is not well
understood because it depends strongly on process [Shi 99b]. Models to explain the
degradation mechanism were correlated with traps creation as the oxide is stressed.
These traps increase as more current is injected, until a critical defect density is
reached, where the oxide breaks suddenly. The main mechanisms of traps
generation in oxide are:
•
•
•
Anode hole injection [Che 86, Sch 94]
Electron trap generation [Avn 88, Sun 90, Dum 94]
Stress induced leakage current (SILC) [Mas 82, Oli 88]
In the anode hole injection model, the injected electrons from the gate cathode with
high energy undergo impact ionization and generate holes at the anode that can
tunnel back into the oxide (figure 3.10). Intrinsic breakdown occurs when a critical
hole fluence Qcrit is reached. Chen et al. [Che 86] evaluated the Qcrit for 11 nm oxides
to be about 0.1 C/cm2.
3.2 Analytical and Electrical Measurements
35
Cathode
(-)
φB = 3.2 eV
FNtunneling
+
+
+
+
holes
EC
EV
SiO2
Fig. 3.10: Schematic band diagram of MOS structure showing the mechanism
of holes generation at the anode
In the electron trap generation model, a critical density of electron traps generated
during stress is required to trigger oxide breakdown. Degraeve et al. [Deg 98a] used
this concept to develop a percolation model, in which electron traps are randomly
generated across the oxide. They assumed a conductive sphere of radius r
surrounding each trap. As the electron traps increase, conducting clusters are
formed, when these spheres overlap. Therefore, a conducting path is formed and the
breakdown occurs once a conducting path connecting the anode to the cathode is
formed (figure 3.11)
Electron traps
Anode
Cluster
Cathode
Breakdown path
Fig. 3.11: The electron trap sphere model.
36
3 Experimental Methods
By using this model, Degraeve et al. [Deg 98a] established a direct link between the
anode hole injection model and electron trap generation model, and a relationship
between the hole fluence Qp,crit and the critical electron trap density Dot was given :
D ot =
C 7 0.56 C 7
(α ⋅ QBD )0.56
Q p,crit =
p7
p7
(3.24)
where C7 = 5.3 x 1019 cm-1.88 C-0.56 , p7 = 0.03 are fitting parameters, α is the
probability that an injected electron generates a hole that can tunnel back into the
oxide, and QBD is the injected charge. Moreover, they established that the charge to
breakdown is a statistical variable even if extrinsic defects are excluded.
A value of r = 0.45 nm was also given, which means that conduction between traps
separated by a distance of 0.9 nm from each other can occur.
Stress Induced Leakage Current (SILC) has recently gained much attention as a
breakdown mechanism in ultrathin oxides (< 5 nm). A low field leakage current
preceding the tunnel current, has been observed in thin oxide that has been stressed
at high voltages [Mas 82, Oli 88]. After stressing, electron traps are generated in the
oxide, and SILC is caused by a tunneling process of electrons trough these traps [Oli
88] as depicted in figure 3.12.
This higher pre-tunneling leakage current caused by write/erase cycling is at present
one of the major factor preventing the downscaling of nonvolatile EEPROM
(Electrically Erasable Programmable Read Only Memory) [Nar 88].
Poly-Si
SiO2
Si
Fig. 3.12: Energy band diagram of MOS structure showing the trap assisted
tunneling process.
3.2 Analytical and Electrical Measurements
37
For the modeling of the breakdown, two statistical models were developed by Lee et
al. [Lee 88] and Degraeve et al. [Deg 98b].
Lee et al. [Lee 88] modified the intrinsic-breakdown model of Chen et al. [Che 86] to
take in account the oxide thinning by introducing an effective oxide thickness :
deff = d - ∆d , where ∆d is the amount of oxide thinning (figure 3.9).
The time to breakdown is then given by:
t BD = τ 0 exp(G ⋅ d eff / Vox )
(3.25)
where G is a constant and equals 320 MV/cm at 25°C, Vox the voltage across the
oxide, and τ0 = 10-11s (for a wide range of oxide thickness).
By assuming that defects with various degree of severity (various deff) are distributed
over the wafer, the time to breakdown is determined by the ∆d of the weakest spot
contained in the oxide, so that the percentage failure at a certain time t ′BD below tBD,
is equal to the probability of finding ∆d′ > ∆d
P( ∆d′ > ∆d ) = 1- P(no defect with effective thinning > ∆d)
(3.26)
If the defects are not randomly distributed over the wafer, a gamma distribution can
be used to determine the probability, and the analytical expression of the cumulative
failure as a function of the oxide area A, the oxide voltage Vox, the time tBD is :
F(A, Vox , t BD ) = 1 −
(1 + A (a1 e
b1 deff
1
+ a 2 eb2 deff ).S)1/ S
(3.27)
where a1 = 13.1, a2 = 6.3, b1 = -0.26, b2 = -0.11, and deff is related to Vox and tBD
through the equation 3.25. S is a segregation coefficient inherent to the gamma
distribution. A similar expression can be developed for randomly distributed defects
(i.e. using Poisson probability).
It was observed that this model leads in some cases to discrepancies and is unable
to fit the extrinsic part of Weibull distribution [Ogi 95]. This may be due to the fact
that this model is conceptually based on the principle that all the defects in the oxide
are modeled as localized spots with an effective oxide thinning, and, therefore,
ignores all other causes of breakdown.
Typically and traditionally, the breakdown statistics follows the bimodal Weibull
distribution by mixing the extrinsic part and the intrinsic part. The probability density
f(t) and the cumulative distribution F(t) are given by :
f (t ) = p e f e (t ) + (1 − p e ) fi (t )
(3.28)
F(t ) = p e Fe (t ) + (1 − p e ) Fi (t )
(3.29)
38
3 Experimental Methods
where pe is the fraction of the population that fails extrinsically with a Weibull
probability function fe(t) and (1-pe) the fraction that fails intrinsically with a Weibull
probability function fi(t).
β
fe (t ) = e
ηe
β
fi (t ) = i
ηi
æ t ö
⋅ çç ÷÷
è ηe ø
æ t ö
⋅ çç ÷÷
è ηi ø
β e −1
βi −1
é æ t öβe ù
⋅ exp ê− çç ÷÷ ú
êë è ηe ø úû
(3.30a)
é æ t ö βi ù
⋅ exp ê− çç ÷÷ ú
êë è ηi ø úû
(3.30b)
with ηe and ηi the 63% time to breakdown, βe and βi the Weibull slopes.
When plotting the probability density f(t) as function of time, a discrepancy is
observed. As shown in figure 3.13, the failure mode starts extrinsically with a
decreasing rate over the time, followed by the intrinsically mode with an increasing
rate. After that most of all population has already failed intrinsically, a fraction of the
population still fails extrinsically at long time.
Probality density f(t)
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
fi(t)
fe(t)
Failure
f(t)=pe fe(t) + (1-pe) fi(t)
1
10
100
1000
Time to breakdown (s)
Fig. 3.13: Graphic presentation of the discrepancy in the classic model of the
probability function.
3.2 Analytical and Electrical Measurements
39
Degraeve et al. [Deg 98b] have proposed a new expression for computing the
breakdown mechanism.
f ( t ) = p ⋅ fe (t ) ⋅ Ri (t ) + p ⋅ fi (t ) ⋅ R e (t ) + (1 − p ) ⋅ fi (t )
(1)
(2)
(3.31)
(3)
In this expression, a fraction of population fails extrinsically if it has not intrinsically
failed (term 1, where Ri is the intrinsic reliability), a fraction fails intrinsically if it has
survived the extrinsic breakdown (term 2, where Re is the extrinsic reliability) and
population fails full intrinsically (term 3). The factor p is related to defective part of the
population that fails extrinsically or intrinsically, and (1-p) is the defect free part of the
population that fails fully intrinsically. As shown in figure 3.14 (a and b), no extrinsic
breakdown occurs after a full intrinsic one.
0
10
-1
(a)
Probability function f(t)
10
(1-p).fi
-2
10
p.fi.Re
-3
10
p.fe.Ri
-4
10
-5
10
-6
10
0.1
1
10
100
Time to breakdown (s)
Fig. 3.14a: Graphic presentation of the three terms of the probability functions
according to the model of Degraeve et al. [Deg 98b].
40
3 Experimental Methods
10
1
10
0
(b)
Probabilty function f(t)
f(t)=p fe(t) Ri(t) + p fi(t) Re(t) + (1-p) fi(t)
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
1
10
100
1000
Time to breakdown (s)
Fig. 3.14b: Graphic presentation of the total probability function according to
the model of Degraeve et al. [Deg 98b].
4 Properties of Barium, Strontium, Bismuth, Iridium, and
Platinum Impurities in Silicon
4.1 General Properties of Metals in Silicon
The effect of a metal contamination on the device performances depends strongly on
its diffusion properties, so that not all the metals are equally harmful. While some
metals are fast diffusers (Cu, Ni) and thus need only low annealing temperatures or
short times to diffuse deeply into the wafer, others belong to moderately diffusers,
such as interstitial Fe [Gra 95] or Cr, or to slow diffusers such as Ti, Ta, and Mo. The
last require very high annealing temperatures to reach the active regions. This
difference in diffusion properties of metals is related to their incorporation in the
silicon lattice. While slow diffusers are substitutionally dissolved and require intrinsic
point defects, like vacancies or self-interstitials for their diffusion process, fast
diffusers are mainly dissolved in interstitial sites and diffuse from interstitial site to
another one without requiring the presence of intrinsic point defects. Pt and Au,
which predominately are substitutionally dissolved but diffuse interstitially, are
considered as fast diffusers [Gös 88].
On the other hand, the nature of the metal precipitation in silicon can differ greatly
from element to element. Graff made an important contribution to the explanation of
metal precipitation. According to Graff [Gra 95], there are four main conditions of
precipitation of any metal, which have to be fulfilled simultaneously: 1)
supersaturation of the metal in the silicon matrix, 2) presence of nucleation sites in
the form of lattice defects, 3) high mobility of the metal, and 4) low cooling rates.
Graff explained also the precipitation of transition metals at the surface. These
metals exhibit solid solubilities which strongly decrease with decreasing temperature
in combination with high interstitial diffusivities. As a consequence, these impurities
are in supersaturation during the cooling. To avoid the unstable phase in
supersaturation, the impurities outdiffuse to the surface, where they can precipitates
to form a new phase.
Due to the large difference in solubility, diffusivity, and nucleation to form precipitates,
metal precipitation differs from metal to metal. While Cu and Ni precipitate by
homogenous nucleation, Fe precipitates by heterogeneous mechanisms, in which
lattice defects or other impurity precipitates are required as nucleation sites, where
Fe can segregate [Gra 95]. Hourai et al. [Hou 89] explained that Ni and Cu could
easily precipitate during cooling from high temperature, whereas Fe could not easily
precipitate during cooling from high temperature because of its low diffusivity, which
is an order of magnitude lower than the diffusivity of Ni or Cu below 950°C.
42
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
The annealing atmosphere was also observed to influence the diffusion. When
annealed in O2 atmosphere, metals like Fe, Al, and Cr have the tendency to stay in
oxide rather than to deeply diffuse into bulk silicon. Hourai et al. [Hou 88] and Sano
et al. [San 91] explained this tendency from the point of view of the large free
energies of oxidation. The example of Al is explained below:
4
2
Al + O 2 → Al 2 O 3 − 202 kcal
3
3
Si + O2 → SiO2 – 154 kcal
(4.1)
(4.2)
So that
4
2
Al + SiO 2 → Al 2 O 3 + Si − 48 kcal
3
3
(4.3)
The equation (4.3) indicates that Al is oxidized more easily than Si.
In general, metal initially present on the wafer surface before thermal oxidation can
either diffuse into the bulk, stay in the oxide and/or at the interface, or desorb from
the surface leading to cross contamination by gas phase transport.
In terms of cleaning, Ohmi et al. [Ohm 92] showed that metals like Au, Ag, Cu,... with
electronegativity higher than that of Si, are adsorbed directly on the Si surface by
taking an electron from the Si, which make them very difficult to remove from the
surface using the conventional wet clean. Whereas, metals like Fe, Ni, Al,... with
lower electronegativity than Si, have no ability to attract an electron from the Si
surface, and thus do not form a chemical bond with Si. This type of metals can be
removed easily by the conventional wet cleaning.
In this work, the desorption as well the diffusion properties of Ba, Sr, Bi, Ir, and Pt
were studied using TXRF, VPD-TXRF, ToF-SIMS, SIMS, and the DLTS-profiling
method.
If not otherwise specified, the standard anneal, used in this work, was performed at a
temperature of 800°C for 60 min. This corresponds to the maximum thermal budget,
that a wafer is subjected to have after ferroelectric film deposition. The wafers were
annealed in a horizontal furnace, heated with quartz halogen lamps allowing a fast
heating rate of 50°C/min. A relatively slow cooling rate of 20°C/min was adopted from
a typical ferro-anneal to realistically simulate the effect of the contamination. This
cooling rate is sufficiently slow to allow metal precipitation, if any. To check the
temperature variation across the wafer, a specially designed test wafer with a
thermocouple attached to the surface was annealed. The standard deviation was
less than 2 °C from the set point, as shown in Table 4.1
Table 4.1: In-Situ temperature distribution across the wafer during the anneal.
(0,65)
(65,0)
(0,-65)
(-65,0)
(0,0)
Mean
σ
At the beginning of the 804.80
stabilization at 800°C
800.50
At the end of the
stabilization at 800°C
800.20
800.80
801.80
801.60
801.84
1.77
797.50
798.80
799.20
799.20
799.04
1.07
Coordinate in mm
4.2 Desorption Properties of Contaminants on Silicon Surface
43
To avoid cross contamination, intentionally contaminated wafers were separately
annealed. If the cross contamination of a contaminant was critical, then a purge step
at 800°C for 60 min in O2 was done before annealing the next wafers, contaminated
with another element. These precautions were necessary in order to isolate the effect
of every element, so that the results will be reliable.
4.2 Desorption Properties of Contaminants on Silicon Surface
Wafers were intentionally contaminated following the method described in section 3.1
and subsequently annealed in O2 or N2. Since the anneal leads to a loss of volatile
metal species that leave the surface, the concentrations on the surface, before and
after anneal were measured with direct TXRF. This allows also to determine the
amount of the impurities, relatively to the initial concentration, that may desorb.
Furthermore, the remaining concentration after anneal can stay in the oxide or diffuse
into the bulk, so that the distribution of the metal between the oxide and the bulk has
to be determined. The concentration of the species in the oxide is measured using
VPD-TXRF. After the VPD oxide etch, direct TXRF is conducted on the bare silicon
wafer without oxide to determine the amount of the species that may have diffused
into the substrate during the anneal. This measurement procedure was done to
determine the near surface balance between the initial concentration, the desorbed
concentration, the concentration in the oxide, and the concentration that diffuses into
the bulk.
In order to asses cross contamination, a clean wafer was placed in the boat such that
its front surface faced the contaminated surface of the test wafer. If after annealing,
the contaminant was detected on that “pickup” wafer, it must have got there via gas
phase transport. The TXRF measurement of the pickup wafer was done on 5 points
to exclude cross-contamination effects by handling.
4.2.1 Desorption Properties of Barium
Figure 4.1 shows the concentration of Ba on the surface before and after annealing
in O2 as function of the concentration of Ba in the contaminating solution. For a
concentration of Ba in the solution between 1 and 100 ppm, the corresponding
contamination levels are in the range of 1012 to 1014 at/cm2. The concentration of Ba
on the surface increases linearly with a slope of 0.7. Under the specified conditions of
SC1 and spin-dry of 3500 rpm, the Ba concentration on the surface as function of the
Ba concentration in the spiking solution can be described:
0.7
12
CBa,surf = CBa
at / cm2
in solution ( ppm ) x 2.57 x 10
(4.4)
A negligible loss of Ba is observed after annealing at 800°C for 60 min. The
maximum loss was about 10%, in spite of the fact that elemental Ba, in solid or liquid
state, has a high vapor pressure :
log p = 9.013 − 8163 ⋅ T −1 (Pa) , for a temperature range 1000K-1473K
(4.5)
This is due to the fact that Ba is incorporated in the growing oxide or in the native
oxide as an ion and not as an element [Kol 00]. This loss was also negligible for high
temperatures of 900°C and 1000°C as it can be seen from figure 4.2. The fact that
44
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
2
Ba concentration on the surface (at/cm )
Ba does not desorb from the surface, no cross contamination was found, and the Ba
on a facing clean wafer was below the detection limit of TXRF.
14
10
13
Before anneal
After anneal
10
12
10
1
10
100
Ba concentration in the solution (ppm)
2
Ba concentration on the surface (at/cm )
Fig. 4.1: Relationship between Ba concentration before and after annealing at
800°C during 60 min in O2 atmosphere and Ba concentration in the
contaminating solution.
10
15
10
14
10
13
10
12
10
11
Before
anneal
800°C
900°C
1000°C
Fig. 4.2: Comparison between Ba concentration (measured by TXRF) before
anneal and Ba concentration after anneal at different temperatures in O2
atmosphere. Example shown is for 100 ppm Ba solution.
4.2 Desorption Properties of Contaminants on Silicon Surface
45
To get more information on the Ba concentration in the oxide, VPD-TXRF
measurements were performed on wafers initially contaminated with 10ppm Ba and
annealed in O2 or N2. Figure 4.3 gives the concentration of Ba before anneal, after
anneal, the concentration in oxide as measured with VPD-TXRF, and the remaining
concentration after oxide etch.
The Ba concentration does not change significantly upon annealing in nitrogen or
oxygen atmosphere. This is due to the fact that Ba is freely soluble in the native or
thermal oxide. Most of the Ba dissolves in the oxide (native or thermally grown) and
only a very small fraction (less than 5%) was found in the bulk of the silicon after
removal of the surface oxide. The concentration of Ba in the oxide (labeled with VPDTXRF) represents 47% of the total concentration, which means that not all the Ba in
the oxide was effectively collected. The missing concentration points out that a
collection efficiency not exceeding 50% was obtained with 2 wt% HF/ 7 wt% H2O2 ,
for a concentration on the surface of nearly 1013 at/cm2. More accurate in
quantification is the direct-TXRF values (before and after oxide etch) which indicate
that Ba has the tendency to stay mainly in the oxide layer rather than to deeply
diffuse into silicon, and thus Ba has a similar behavior to Al and Fe. This is due to the
fact that Ba has a large free energy of oxidation:
2 Ba + SiO 2 → 2 BaO + Si − 135 kcal mol −1
(4.6)
2
Concentration (at/cm )
1E13
1E12
1E11
1E10
O2
N2
To
( B e ft a l
o re a
nnea
A fte r
l)
anne
al
B a in
( V P D o x id e
-T X R
Ba a
F)
fte r O
x. E t
ch
Fig. 4.3: Total Ba concentration (before anneal), Ba concentration after anneal
at 800°C, Ba concentration in oxide and at the interface (VPD-TXRF) and Ba
remaining concentration after VPD oxide etch upon annealing atmosphere.
46
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
4.2.2 Desorption Properties of Strontium
Several similarities were seen between Ba and Sr. The Sr concentration on the
surface increases linearly with increasing the Sr concentration in the SC1 solution
(figure 4.4). The slope in the log-log plot is 0.97, very close to 1. For the conditions
used in this work, the surface concentration can be given by the following equation :
0.97
12
CSr,surf = CSr
at / cm2
in solution ( ppm ) x 1.22 x 10
(4.7)
2
Sr Concentration on the surface (at/cm )
After annealing up to 1000°C in O2 atmosphere, the loss in Sr is not significant as
shown in figure 4.5, although, Sr like Ba has a high vapor pressure. Here again, Sr is
incorporated in the oxide as an ion and not as an element.
10
14
10
13
10
12
Before anneal
After anneal
1
10
100
Sr Concentration in the solution (ppm)
2
Concentration on the surface (at/cm )
Fig. 4.4: Relationship between Sr concentration before and after annealing at
800°C during 60 min. in O2 and Sr concentration in the contaminating solution.
15
10
14
10
13
10
12
10
11
10
Before
anneal
800°C
900°C
1000°C
Fig. 4.5: Comparison between Sr concentration (measured by TXRF) before
anneal and Sr concentration after anneal at different temperatures in O2
atmosphere. Example shown is for 100 ppm Sr solution.
4.2 Desorption Properties of Contaminants on Silicon Surface
47
Figure 4.6 shows a very close similarity to the case of Ba just discussed above. Most
of the Sr is detected in the native oxide or the thermally grown oxide, and very small
quantities of Sr are found near the silicon surface after the oxide etch. The remaining
concentration after oxide etch is a factor 2 higher under N2 than under O2. This
remaining concentration under O2 was just at the limit of detection with direct TXRF
For Sr like Ba, accurate quantification of Sr in the oxide suffers from the problem of
the collection efficiency, which does not exceed 30% for a surface concentration in
the range of 1013 at/cm2.
2
Concen tration ( at/cm )
1E13
1E12
1E11
1E10
To
( B e f ta l
o re a
O2
N2
nn e a
A f te
l)
r ann
e al
S r in
O
(V P D x id e
-T X R
F)
Sr a
ft e r o
x. e t
ch
Fig. 4.6 : Total Sr concentration (before anneal), Sr concentration after anneal
at 800°C, Sr concentration in oxide and at the interface (VPD-TXRF) and Sr
remaining concentration after VPD oxide etch for O2 and N2 annealing
atmosphere.
The tendency of Sr to stay mainly in the oxide layer rather than to deeply diffuse into
silicon, can be explained on the basis of the large free energy of oxidation:
2 Sr + SiO 2 → 2 SrO + Si − 142 kcal mol −1
(4.8)
The aspect of Sr cross contamination is presented in figure 4.7. Some Sr impurities
can be found on the facing surface of a neighboring, initially clean wafer, however,
less critically under N2 than under O2, not over the whole wafer, and not
homogeneously. Probably due to a cross contamination through wafer handling, like
touching wafers with contaminated tweezers or contaminated wafer box, and not
through gas phase transport.
48
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
1E14
Cross-contamination in O2
Intentionally Sr contaminated wafer
2
1E13
Sr concentration ( at / cm )
2
Sr concentration ( at / cm )
1E14
1E12
1E11
Sr detection lim it
1E10
Point 1
Point 2
Point 3
Point 4
1E12
1E11
Sr detection lim it
1E10
Point 5
cross-contamination in N2
intentionally Sr contaminated wafer
1E13
Point 1
Point 2
Point 3
Point 4
Point 5
Fig. 4.7: Cross contamination aspects of Sr under O2 or N2 atmosphere at
800°C. Dashed columns present the Sr concentration on a clean wafer, facing
an intentionally contaminated wafer (close columns).
4.2.3 Desorption Properties of Bismuth
As shown in figure 4.8, if the Bi concentration in the SC1 solution increases by two
order of magnitude, the Bi concentration on the surface increases only by one order
of magnitude. The relationship between the two concentrations is given by:
2
Bi concentration on the surface (at/cm )
CBi,surf = CBi0.58in solution ( ppm ) x 9.48 x 1012 at / cm2
(4.9)
15
10
14
10
13
10
Before anneal
After anneal
12
10
11
10
1
10
100
Bi concentration in the solution (ppm)
Fig. 4.8: Relationship between Bi concentration (measured by TXRF) before
and after annealing at 800°C during 60 min in O2 and Bi concentration in the
contaminating solution
4.2 Desorption Properties of Contaminants on Silicon Surface
49
A fundamental aspect of Bi is its volatility at relatively low temperatures (the melting
point of Bi is 271.4°C). Figure 4.9 summarizes the effect of annealing atmosphere on
an initial Bi concentration on the surface of nearly 2 x 1013 at/cm2. Also given in this
figure are the Bi concentration after the anneal, the Bi concentration in the oxide, as
well as the remaining Bi concentration after oxide etch. After an anneal at 800°C in
O2, no significant loss in Bi was seen. Bi contamination does not desorb from the
wafer when the heat treatment is performed in O2 atmosphere. This is due to the fact
that Bi makes a strong bond with oxygen to form Bi2O3. If annealing was done in a N2
ambient, however, about 90% of the Bi concentration evaporate from the surface.
After oxide etch (native or thermal), no bismuth was detected on the wafer surface.
This can be an indication that Bi does not diffuse at this temperature.
2
Concentration ( at/cm )
The high volatility of Bi during N2 annealing can lead to severe cross-contamination
of other wafers through the gas phase as shown in figure 4.10. After annealing,
practically the same Bi concentration as on the intentionally contaminated wafer was
found on the facing surface of a neighboring, initially clean wafer. In O2 ambient, on
the other hand, the Bi concentration on the facing clean wafer represents only 4% of
the total concentration on the intentionally contaminated wafer.
1E13
1E12
1E11
O2
N2
To
(B e f t a l
o re
anne
A ft e
a l)
r ann
eal
B i in
( V P D o x id e
-T X R
Bi af
F)
te r O
x. et
ch
Fig. 4.9: Total Bi concentration (before anneal), Bi concentration after anneal
at 800°C, Bi concentration in oxide and at the interface (VPD-TXRF) and Bi
remaining concentration after VPD oxide etch upon annealing atmosphere.
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
Cross-contamination in O2
Intentionally contaminated wafer
1E13
Bi concentration (at/cm2)
Bi concentration (at/cm2)
50
1E12
1E11
D. L.
Point 1
Point 2
Point 3
Point 4
Point 5
Cross-contamination in N2
Intentionally contaminated wafer
1E13
1E12
1E11
D. L.
Point 1
Point 2
Point 3
Point 4
Point 5
Fig. 4.10: Cross contamination aspects of Bi under O2 or N2 atmosphere at
800°C. Dashed columns present the Bi concentration on a clean wafer, facing
an intentionally contaminated wafer (close columns). D.L. is the detection limit.
4.2.4 Desorption Properties of Iridium
The main problem with Ir, as well as Pt, is that no quantification of the metal in the
oxide was possible because the collection efficiency is often well below 10%.
Attempts done with the assistance of GeMeTec company and in cooperation with
FhG-IIS-B to find other suitable solutions for Ir and Pt showed no satisfying results.
Therefore VPD-TXRF cannot be exploited for Ir and Pt. Optimization of DSE solution
for sensitivity improvement is beyond the scope of this work. Therefore, we will
exclude the VPD-TXRF data in the following presentations.
Figure 4.11 shows the concentration of Ir on the surface before anneal, the
concentration after anneal, and the remaining concentration after the oxide etch upon
annealing in O2 or N2 atmosphere. While no loss in the initial concentration is seen
under N2 atmosphere, a very significant loss is observed if anneal is performed in O2
atmosphere. For wafers annealed in N2, the remaining concentration after native
oxide etch is approximately the same as the initial concentration, which means that
all Ir impurities diffuse into the substrate.
After etch of the thermal oxide, Ir is still found on the surface in concentrations two
times higher than the concentration that was measured after anneal. This is because
of the Ir distribution in the oxide, which increases toward the SiO2/Si interface, as
shown in figure 4.12. This figure shows that the maximum Ir concentration is found at
the interface and very little of Ir was found deeper than the interface. It can be
concluded that in O2 atmosphere, Ir desorbs from the surface and can be found on
the facing clean wafer, as demonstrated in figure 4.13. However, and if correlated to
the initial concentration, not very much Ir is found on the faced clean wafer. This
means that most of desorbed concentration was transported inside of the furnace via
the gas phase, and, therefore, contaminates the whole furnace.
4.2 Desorption Properties of Contaminants on Silicon Surface
51
2
Concentration ( at/cm )
1E13
1E12
1E11
1E10
Befo
1E9
A f te r
N2
A fte r
O2
O x.
anne
re an
neal
al
e tc h
Fig. 4.11: Total Ir concentration (before anneal), Ir concentration after anneal
at 800°C, and Ir concentration after oxide etch upon annealing atmosphere.
10
3
SiO2 Si
2
10
1
10
0
10 ppm Ir annealed in O2
Counts
10
0
10
20
30
40
50
Depth (nm)
Fig. 4.12: ToF-SIMS profile of 10 ppm Ir annealed at 800°C in O2.
60
52
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
A severe cross contamination is also observed in N2 atmosphere. The concentration
on a facing clean wafer represents 25% of the initial concentration on the
intentionally contaminated wafer. Since no loss was observed after anneal in N2, this
high concentration is due to the high contamination level of the furnace, caused by a
previous annealing in O2.
1E13
Cross-contamination in N2
Intentionally contaminated wafer
2
Ir concentration (at/cm )
Cross-contamination in O2
Intentionally contaminated wafer
2
Ir concentration (at/cm )
1E13
1E12
1E11
1E10
D. L.
Point 1
Point 2
Point 3
Point 4
1E12
1E11
D. L.
1E10
Point 5
Point 1
Point 2
Point 3
Point 4
Point 5
Fig. 4.13: Cross contamination aspect of Ir in O2 or N2 atmosphere.
The concentration on the surface after an anneal in N2 or in O2 is presented in Figure
4.14. The relationship between the Ir concentration on the surface and the Ir
concentration in the solution upon annealing atmosphere are :
CIr ,surf = CIr0.3in solution (ppm ) x 3.23 x 1011 at / cm2 , in O2
(4.11)
CIr ,surf = C1Ir.1in solution (ppm ) x 3.17 x 1011 at / cm2 , in N2
(4.12)
so that the loss in the initial concentration after anneal in O2 can be given by:
(
)
C loss = C1Ir.1in solution (ppm ) − CIr0.in3 solution (ppm ) x 3 x 1011 at / cm 2
(4.13)
53
2
Ir Concentration on the Surface (at/cm )
4.2 Desorption Properties of Contaminants on Silicon Surface
14
Before annealing
After annealing in N2
After annealing in O2
10
13
10
12
10
11
10
10
10
1
10
100
Ir concentration in the contaminating solution (ppm)
Fig. 4.14: Relationship between Ir concentration before and after annealing at
800°C during 60 min in O2 and N2 atmospheres and Ir concentration in the
contaminating solution.
4.2.5 Desorption Properties of Platinum
The properties of Pt on the surface were found to be influenced by the annealing
atmosphere. Figure 4.15 shows the Pt concentration on the surface, upon anneal in
O2 or N2, versus the initial concentration in the contaminating solution.
If the anneal is performed in N2, no loss in Pt is observed and the concentration on
the surface before or after anneal can be given by :
CPt,surf = CPt in solution ( ppm ) x 7.25 x 1011 at / cm2 , in N2 and before oxide etch (4.14)
After etching of the native oxide, the concentration of Pt is relatively lower than the
concentration before oxide etch. This is because with etching of the native oxide, the
included Pt ions are removed from the oxide. The remaining Pt concentration on the
surface has the following expression :
0.58
11
CPt,surf = CPt
at / cm2 , in N2 and after oxide etch
in solution ( ppm ) x 7.16 x 10
(4.15)
The difference between the two concentrations, which theoretically is the Pt
concentration included in the native oxide, can be expressed as :
(
)
0.58
Cdiff = Cbefore Ox etch – Cafter ox etch = Cppm − Cppm
x 7.2 x 1011 at/cm2
(4.16)
54
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
14
Before oxide etch
After oxide etch
Annealed in N2
2
Pt concentration (at/cm )
10
10
13
10
12
10
11
Annealed in O2
Detection limit
10
10
1
10
100
Pt concentration in the solution (ppm)
Fig. 4.15: Pt concentration on the surface before and after oxide etch for O2
and N2 annealing atmospheres.
After anneal in O2, no Pt could be detected on the surface for low concentrations
(below 10 ppm), whereas there is no real difference between the concentration after
anneal in N2 or O2 for higher concentration. After oxide etch, the Pt reappears on the
surface, with a saturated concentration of 1.7 x 1011 at/cm2. No difference between
the concentration before after oxide etch, for the high concentration of 100 ppm, is
observed.
In O2 anneal, the oxidation of the silicon surface leads to the consumption of the
silicon self-interstitial, and therefore to the suppression of the site change of Pt
[Col86]. This could be the reason why Pt concentration on the surface is very low if
annealed in O2. For higher concentration, however, Pt does not react if exposed to
the oxidizing atmosphere.
Attempts to measure the Pt profile in the oxide using TOF-SIMS (no SIMS is possible
in the oxide for the reason, we explain in the following section ) were not successful
because of the low Pt concentration compared to the detection limit (1017 cm-3). The
tendency of the Pt to reappear after the oxide etch can be explained as follows
(figure 4.16): a 7 nm oxide thickness results from the thermal oxidation of the surface
at 800°C for 60 min. Initially, Pt is included in the native oxide, and with the oxide
growth, Pt is included in the first oxide layer. This is very likely, since Pt, as noble
metal, does not react easily. Consequently, and because the penetration depth
(3.2 nm for quartz glass [Klo 97]) is much shorter than thickness of the oxide layer,
the embedded Pt impurities are not detected. After the oxide-etch, the Pt is exposed
to the X-ray and can be detected.
4.2 Desorption Properties of Contaminants on Silicon Surface
55
X-ray
Z=3.2 nm
Pt
≈
dox=7nm
SiO2
Si
≈
Fig. 4.16: Schematic explanation of the undetected Pt with TXRF before
oxide etch. After oxide etch, Pt is exposed to x-rays and can be easily
detected.
If Pt concentration in the contamination solution is high, agglomeration of Pt on the
surface of the native oxide in form of dendrites or small particles was observed after
the contamination step using an optical microscope (figure 4.17a). No agglomeration
of Pt was observed on the surface for 10 ppm Pt concentration in the solution, even
when observing the surface with Atomic Force Microscopy (AFM) (see figure 4.17b).
After the anneal (either in O2 or in N2), the dendrites disappear completely from the
surface because most of the Pt impurities diffuse into the bulk out from the dendrites,
which act as diffusion source, and no effect of anneal atmosphere could be seen. It
can be concluded from TXRF investigation that if the Pt surface coverage is high,
approaching 1 ML, the anneal atmosphere has no pronounced effect.
(a)
(b)
Fig. 4.17: Optical microscope micrograph of wafer surface contaminated with
100 ppm Pt before anneal showing agglomeration of Pt in the form of
dendrites or small particles (a) and AFM image of wafer surface contaminated
with 10 ppm Pt (b).
56
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
The cross contamination of Pt in O2, or N2 atmosphere is presented in figure 4.18. No
presence of Pt on clean faced wafer was detected, neither in O2 nor in N2
atmosphere. While it is clear that no cross contamination occurs under the N2 anneal
condition, the results under O2 condition have to be carefully seen since the Pt
detection in very low concentration is not straightforward.
1E14
1E12
D. L.
1E11
1E10
Point 1
Point 2
Point 3
Point 4
Measurement point
Point 5
2
Pt cross-contamination in O2 atmosphere
Intentionally contaminated wafer
1E13
Pt Concentration (at/cm )
2
Pt concentration (at/cm )
1E14
Pt cross-contamination in N2
Intentionally contaminated wafer
1E13
1E12
D. L.
1E11
1E10
Point 1
Point 2
Point 3
Point 4
Point 5
Measurement position
Fig. 4. 18: Pt cross-contamination in O2 or N2 atmosphere.
It is difficult to state on the Pt properties only from these surface studies without
knowing the diffusion properties. Results from SIMS and DLTS profiling, that will be
presented in sections 4.2.4 and 4.3.2, respectively, show that the annealing
atmosphere influences only the concentration on the surface, and that in depths of
few microns from the surface, there is absolutely no difference between anneals in
O2 or in N2. It is worth mentioning here that the Pt not detected with direct TXRF or
barely detected after oxide etch diffuses deeply into the bulk and even has the same
volume concentration as if annealed in N2. The problem of Pt detection in case of
very low coverage gives an idea of how sensitive the detection method should be.
DLTS appears to be the most suitable method for Pt detection.
4.3 Diffusion Properties of Contaminants in Silicon
57
4.3 Diffusion Properties of Contaminants in Silicon
4.3.1 Time of Flight-Secondary Ion Mass Spectroscopy Analysis of Barium,
Strontium, and Bismuth
The previous surface analysis by TXRF and VPD-TXRF showed the properties of
these elements only on the surface or close to the interface. No detailed information
was obtained about the diffusion into the silicon substrate. This preliminary study with
the lack of data in the literature about the diffusion of Ba and Sr and Bi into Si cannot
illustrate their diffusion properties and the question whether Ba, Sr, and Bi diffuse at
800°C has not been clarified. It is even questionable, whether there is possible
diffusion in oxidizing atmosphere.
In contrast to the extensively investigated case of Ba and Sr adsorbed on silicon
surfaces, the diffusion of Ba and Sr into silicon has received much less attention. Fan
et al. [Fan 91] reported different adsorption structures, depending on Ba coverage for
temperatures above 700 °C and presuming that at low coverage (< 1 monolayer ML),
Ba does not diffuse into the Si(100) surface even at high temperatures of 1000 °C .
No much is known about diffusion of Sr in Si, except the work of Yamamichi et al.
[Yam 95], who reported a diffusion coefficient of 2 x 10-17 cm2/s for an anneal at
950°C in N2 atmosphere. However, no Sr diffusion coefficient for a certain
temperature range has been reported by Yamamichi et al. Moreover, data on Sr
diffusion in O2 atmosphere has not been reported.
For Bi, a diffusion coefficient in the temperature range between 1050°C and 1200°C
was given by Ishikawa et al. [Ish 89]. Below the temperature of 1000°C, the diffusion
properties of Bi were unknown.
In order to get more insight into the depth distribution of Ba, Sr, and Bi atoms in oxide
as well as in silicon, ToF-SIMS depth profiles were measured. ToF-SIMS is known to
have low detection limits, that are appropriate for such studies, and has also good
depth resolution. Dual beam (Ar+ at 10 keV as analysis primary ions and O2+ at 1 keV
as sputter primary ions) ToF-SIMS mass spectra were recorded on an area of
200x200 µm2. The detected secondary ions were Ba+, Sr+, or Bi+. For better charge
compensation, ToF-SIMS was operated in the “interlaced” mode. In this mode, the
charge are compensated after sputtering and the flight time analysis respectively in a
cycle of 100 µs. A charge compensation system comprising a 30 eV pulsed electron
flood gun is used to prevent charge build-up in insulating samples. Figure 4.19
compares, the performances of dynamic SIMS and ToF-SIMS to measure the profile
of Sr or Ba. Besides a much better depth resolution, measurement in the oxide layers
were possible with ToF-SIMS and not with SIMS due to problem of charge
compensation. ToF-SIMS performs charge compensation better as SIMS;
measurements are even possible in nitride layers, whereas in SIMS, these layers
have to be etched for measurement beyond them [Tre 01].
Theoretically, the diffusion of Ba and Sr can be modeled with a Gaussian distribution.
In this distribution, an infinitesimally thin layer of diffusing substance is deposited on
one surface of the wafer with a constant total concentration S per unit area. The
diffusion source layer is allowed to be consumed during the diffusion process. With
the specific initial condition :
58
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
C(x,t=0) = 0, where C(x,t) is the concentration of the diffusing element at position x
from the surface, after a diffusion time t.
and the boundary conditions :
∞
C( x, t ) dx = S and C(x,∞) = 0
(4.17)
0
the solution of the diffusion equation (also called Fick´s diffusion equation), that
satisfies these conditions, is :
æ x2 ö
(4.18)
expçç −
πDt
è 4Dt
This is a gaussian function with decay width x D = 2 Dt , where D denotes the
diffusion coefficient.
C(x, t ) =
S
SIMS
ToF-SIMS
SIMS
ToF-SIMS
Ba
Counts (a.u.)
Counts (a.u.)
Sr
SiO2 Si
0
SiO2 Si
20
40
Depth (nm)
60
0
20
40
60
Depth (nm)
Fig. 4.19: Comparison between SIMS and ToF-SIMS performances to
measure Sr and Ba diffusion profile after an anneal at 800°C in O2.
Figures 4.20a-c show the ToF-SIMS profiles of Ba, Sr, and Bi after an anneal at
800°C for 60 min in O2 atmosphere. The maximum concentration of Ba and Sr is
found in the oxide and at the SiO2/Si interface. Ba and Sr diffuse into Si over
distances of some tens of nanometers. A good agreement between the measured
profiles and the profiles fitted to equation 4.18 can be obtained. A diffusion of Ba and
Sr into silicon is observed even for low coverage of 0.01 ML.
4.3 Diffusion Properties of Contaminants in Silicon
10
22
SiO2
10
21
10
20
Si
SiO (a.u.)
-3
Concentration (cm )
59
100 ppm
10 ppm
Ba
(a)
2 ppm
10
19
10
18
10
17
0
20
40
60
80
Depth (nm)
SiO (a.u.)
20
Sr
100 ppm
-3
Concentration (cm )
10
10
10 ppm
19
(b)
2 ppm
10
18
10
17
SiO2
0
Si
20
40
60
Depth (nm)
20
SiO (a.u.)
-3
Concentration (cm )
10
19
10
Bi
(c)
18
10
SiO2
Si
17
10
0
20
40
Depth (nm)
Fig. 4.20: ToF-SIMS depth profiles of Ba (a), Sr (b) and Bi (c) after an anneal
at 800°C for 60 min in O2 for different concentrations. The solid lines are fitts
to equation 4.18
60
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
From the depth profiles, diffusion coefficients of 5x10-16 cm2/s and 2x10-16 cm2/s
could be extracted for Ba and Sr respectively. Bi, on the other hand, is found only in
the oxide and at the interface, and no Bi atoms could be detected in Si deeper than
the interface region. At 800°C, Bi does not diffuse into silicon.
4.3.2 Temperature Dependence of the Barium and Strontium Diffusion
Coefficient
For a complete characterization of Ba and Sr diffusion into silicon, the diffusion
coefficient in temperature range between 800 and 1000°C was determined using the
ToF-SIMS profiles. The temperature dependence of diffusivity often follows an
Arrhenius law:
D = D0 exp(- Ea/kT)
from which the activation energy Ea and the pre-exponential term D0 can be
extracted. Figure 4.21 shows an Arrhenius Plot of the Ba, and Sr diffusion
coefficients determined from the diffusion profiles at 800, 900, and 1000°C. While
the measured Sr diffusion coefficients at different temperatures are well fitted by a
straight line, the measured diffusivities of Ba deviate from the fitting line (fitted
according to the least square method). In an attempt to improve the result, the
profiles at 900 and 1000°C were re-measured and the results of the second
measurements were not better. A reason of this difficulty could be a matrix effect of
the ToF-SIMS analysis as pointed out by Benninghoven [Ben 94].
1000
800
-14
Sr
Ba
2
Diffusion coefficient (cm /s)
10
Temperature (°C)
900
10
-15
10
-16
10
-17
8.8
9.2
9.6
10.0
10.4
10.8
11.2
-1
1/kT (eV)
Fig. 4.21: Arrhenius Plot of the Ba, and Sr diffusion coefficients
The expression of Sr and Ba diffusion coefficient determined from figure 4.21 are :
4.3 Diffusion Properties of Contaminants in Silicon
61
DSr = 8.23 X 10-14 exp(-0.588 eV/ kT)
(4.19a)
DBa = 8.81 X 10-13 exp(-0.72 eV/ kT)
(4.19b)
10
-2
10
-5
10
-8
2
Diffusion coefficient (cm /s)
These diffusion coefficients, demonstrate that Sr and Ba belong to the very slowly
diffusing elements in Si. Figure 4.22 compares the diffusion of Sr and Ba with the
very fast diffusing transition metals like Cu, Pd and Au, the moderate slow diffusing
like Ti and the slow diffusing like W.
10
-11
10
-14
10
-17
Cu
Pd
Au
Fe
Ti
W
Ba
Sr
600
800
1000
1200
Temperature (°C)
Fig. 4.22: Comparison between Sr and Ba diffusion coefficient and some
elements. The diffusion coefficient of the others elements are taken from
[Gra 95].
4.3.3 Secondary Ion Mass Spectroscopy Analysis of Iridium and Platinum
First attempts to measure low Pt concentration with ToF-SIMS were hampered by a
low detection limit of 6x1017 cm-3. No profile could be measured for a Pt initial
contamination of 10 ppm annealed in O2. For Pt profiling, only dynamic SIMS was
utilized, using a CAMECA 6f tool.
As discussed in the previous section, a large amount of Ir desorbs from the surface if
annealed in O2 atmosphere, so that no sufficient Ir impurities are available to diffuse.
Up to a concentration of 100 ppm in the contaminating solution, no Ir was detected in
Si. SIMS profiles, performed on these samples with etched oxide (to avoid any matrix
effect), reveal Ir atoms just at the interface as shown in figure 4.23-a and previously
in figure 4.12. For a concentration of 1000 ppm, only very few Ir impurities were
observed to diffuse as depicted in figure 4.23-b.
62
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
The dynamic SIMS diffusion profile of Ir at 800°C in N2 atmosphere, and for different
concentrations is presented in figure 4.24. These profiles were measured using Cs+
primary ions at a net impact energy of 15 keV and were quantified according to a
standard implanted sample from Charles Evans & Associates. Regardless of the
exponential decrease in the concentration (120nm/decade), the measured
concentration exceeded by a factor of 105 the solubility limit of Ir in Si at 800°C, so
that the question arises, if this is not a measurement artifact, and what presents this
high concentration? We ruled out any speculation about the quantification, since the
profiles were quantified according to a standard implanted sample. The RSF factors
(required to convert ion intensity into concentration) were collected from several
measurements of Ir implanted profiles. The RSF of each profile was determined by
normalizing the area under the implant concentration profile to the dose measured by
RBS. The resulting individual RSF values were then averaged. No significant
statistical trends of the individual RSF factors were observed.
10
19
18
10
(b)
Concentration (cm-3)
17
-3
Concentration (cm )
(a)
10
10
18
10
16
10
17
0
50
Depth (nm)
100
15
10
0
100
200
300
400
Depth (nm)
Fig 4.23: Ir Profile of 100 ppm (a) and 1000 ppm (b) concentration in the
contaminating solution, after an anneal at 800°C in O2.
To explain why the measured Ir concentration is higher than the solubility limit of Ir,
cross sectional Transmission Electron Microscopy (TEM) analysis were performed on
the samples, before and after anneal in N2 at 800°C.
Before annealing, dark (flat) areas are observed on the Si surface (figure 4.25a).
These areas extend over a distance of 50 nm. EDX (Energy Dispersive X-ray
analysis) measurements performed with an electron beam focused on this region
confirmed the existence of Ir impurities in a relatively low concentration (figure
4.25b). After anneal, the analysis showed clearly the presence of very fine particles
of 10 nm size as depicted in figure 4.26a. EDX measurements conducted on the
particles (point1 in figure 4.26a) showed that these particles are constituted
essentially of Ir and do not contain significant amount of Si, which means they are no
silicide. In return, EDX measurement done far from the particles (point 2 in figure
4.26a) did not detect the presence of Ir. This is actually the dissolved Ir that could not
be detected with EDX, owing to its low concentration. After anneal, the detected Ir
signal with EDX has a relatively higher intensity as before anneal. During anneal, Ir
growth into particle takes place in regions where it has agglomerated before anneal.
10
20
10
19
10
18
63
100 ppm
10 ppm
-3
Concentration (cm )
4.3 Diffusion Properties of Contaminants in Silicon
1 ppm
10
17
10
16
10
15
10
14
0 .0
0 .2
0 .4
0 .6
0 .8
D ep th (µ m )
Fig. 4.24: Iridium diffusion profiles of 1, 10, and 100 ppm concentration in the
solution after an anneal at 800°C in N2.
Epoxy for
TEM
preparation
(a)
Surface
Si
(b)
Intensity (a.u.)
Si
Energy (keV)
Fig. 4.25: Cross sectional TEM (a) and EDX (b) analysis of 100 ppm Ir
contaminated wafer before anneal. The Circle indicates the region, where EDX
measurements were conducted. The electron beam used for analysis has a
diameter between 30 nm and 50 nm.
64
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
(a)
Epoxy for TEM
preparation
Surface
Si
(b)
Point 2
Intensity (a.u.)
Point 1
Energy (keV)
Energy (keV)
Fig. 4.26: Cross sectional TEM (a) and EDX analysis at point 1 and 2, of 100
ppm Ir contaminated wafer after anneal at 800°C in N2.
The concentrations exceeding the limit of solubility of Ir at 800°C, are due to the
presence of Ir-rich particles on the surface. In area analyzed by SIMS (typically of 60
µm diameter), crystalline Ir is being sputtered.
For platinum, the previous surface study with TXRF showed a pronounced effect of
the annealing atmosphere on the surface concentration. For further investigation of
this effect, more deeper from the surface, SIMS profiles were measured. Pt profiles
were recorded using Cs+ primary ions. For the quantification, a Pt standard from
Charles Evans & Associates was used.
Figures 4. 27 presents the diffusion profile of Pt for different initial concentrations on
the surface, upon anneal in O2 or N2. The results showed the influence of the
annealing atmosphere on the concentration at or near the surface region, in the
same way as TXRF. The Pt concentration decreases exponentially (140 nm/decade)
and after some hundred nanometers, reaches its detection limit of nearly 5x1014 cm-3.
10
19
10
18
10
17
10
16
10
15
10
14
65
10 ppm in O 2
100 ppm in O 2
10 ppm in N 2
100 ppm in N 2
3
Concentration (atoms/cm )
4.3 Diffusion Properties of Contaminants in Silicon
195
0.0
0.2
0.4
0.6
Pt
0.8
1.0
D e p th (µ m )
Fig. 4.27: SIMS profile of 10 and 100 ppm Pt concentration in the solution
after an anneal at 800°C in O2 or N2.
As in the case of Ir, the measured concentrations exceed the Pt solubility limit at
800°C of 2 X 1014 cm-3. The examination of this effect was done in the same way as
previously shown for the Ir case.
Extremely small Pt rich nano-particles were observed on the surface after the anneal.
These Pt-rich nano-particles can easily separate from the surface and be found on
the faced glue sample during TEM preparation.
66
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
(a)
Epoxy for TEM
preparation
Surface
Si
Intensity (a.u.)
(b)
Energy (keV)
Fig. 4.28: Cross sectional TEM (a) and EDX (b) analysis of 100 ppm Pt
contaminated wafer before anneal.
Epoxy for TEM
preparation
Surface
Si
Fig. 4.29: Cross sectional TEM analysis of 100 ppm Pt contaminated wafer
after anneal
4.3 Diffusion Properties of Contaminants in Silicon
67
4.3.4 Study by Deep Level Transient Spectroscopy
4.3.4.1 Trap Level Investigation
The recombination lifetime depends exponentially on the location of the trap level in
the bandgap, so that one trap affects more severely the minority carrier lifetime than
other traps, depending on its position in the bandgap. However, for a level to be an
efficient recombination center its electron and/or hole capture cross sections also
have to be large.
The investigation of the energy level introduced by Pt, Ir, Ba, Sr, and Bi were
performed using DLTS. The measurements were carried out using a Semilab DLS83 tool based on lock-in principle and operating at 1 MHz. The tool is totally computer
controlled. For the temperature cooling, a He-cryostat system allowing measurement
down to 20K, was used. Measurement down to 77K, were performed using liquid
nitrogen, if there is no need to cool samples to deeper cryogenic temperatures.
Standard DLTS spectra were recorded using a reverse bias of 4V with a pulse
frequency of 460 Hz, and a filling pulse of 1.5 V with a duration of 55 µs. For the
determination of the energy level and capture cross section, an Arrhenius plot of the
emission rate was created by varying the frequency.
For the Pt diffused at 800°C, we found a level of donor type, located at Ev+0.313 eV,
with a majority carrier cross capture section σ=3.83x10-15 cm2 and an acceptor
located at Ec-0.227 eV, with σ=2.46x10-15 cm2, in p-type and n-type Si respectively.
Kwon et al. [Kwo 87] found a third energy level, an acceptor level of Ec-0.52 eV, σ=
4.5 x 10-15 cm2, by using the DLTS technique and claimed that the trap concentration
of this level near the surface wafer is low enough to be out of the detectable range.
Therefore, they considered this level to be associated with some interstitial platinumoxygen or other defect complex. The nature of this defect complex was not
characterized or clarified. Recently, Sachse et al. assigned the midgap level to a
platinum-hydrogen complex [Sac 97a] and identified other platinum-hydrogen
complexes: at EC - 0.18 eV, at EV + 0.30 eV, and at EV + 0.4 eV [Sac 97b]. They
demonstrated that hydrogen was introduced during wet chemical etching at room
temperature and showed that all the platinum-hydrogen related complexes
dissociated after an anneal above 600 K which results in a full restoration of
substitutional platinum concentration.
For Ir diffused at 800°C in N2, three energy levels were detected. They are all located
in the upper half of the bandgap, and thus can only be measured in n-type Si:
E1=Ec-0.160 eV, with σ= 1.51x0-15 cm2, E2=Ec-0.271 eV, with σ = 1.28x10-14 cm2, and
E3=Ec-0.534 eV, with σ=1.62x10-15 cm2. A typical DLTS-signal of Ir in n-type Si after
an anneal in N2, is shown in figure 4.30a. Benda et al. [Ben 98] obtained the same
values and showed that levels E1 and E2 correspond to substitutional Ir. They did not
observed the trap E1 in samples annealed at 940°C for 15 min., but could observe it
in samples annealed at 940°C for 155 min. This was their argument why E1 is a
substitutional Ir, since a substitutional Ir diffuses more slowly than interstitial Ir.
For the samples annealed in O2 (figure 4.30b), no peaks were observed for low
concentrations (below 1000 ppm in the solution), whereas the three peaks were
found for high concentration of 1000 ppm, however in very low concentrations, or just
68
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
at the detection limit of 1011 cm-3, as it is the case for the level E1. This is in good
agreement with the results from the SIMS of section 4.3.3.
10 ppm Ir annealed in N2
20
0
(a)
DLS (mV)
-20
-40
EC- 0.160 eV
-60
-80
EC- 0.534 eV
-100
EC- 0.271 eV
-120
50
100
150
200
250
300
350
300
350
Temperature (K)
0
DLS (mV)
(b)
-10
100 ppm
1000 ppm
-20
50
100
150
200
250
Temperature (K)
Fig. 4.30: Typical DLTS of Ir in n-type Si after an anneal at 800°C in N2 (a) or
in O2 (b).
No DLTS investigation of Ba and Sr induced energy levels in the Si bandgap, was
reported in literature. The question if Ba, Sr, and Bi introduce deep level traps was
never clarified. For this purpose and in order to discover the trap levels of Ba, Sr,
and Bi, if they really exist, intensive DLTS measurements were performed on p and
n-type Si substrates in a temperature range from 20 to 300K. In the first set of
measurements, done on 10 ppm Ba, Sr, and Bi contamination, annealed at 800°C in
O2, no specific peak was obtained. The same results were obtained for a second set
of measurements done on 100 ppm contamination. As results, it can be concluded,
that under the tested conditions, Ba, Sr and Bi do not introduce deep energy levels in
silicon and, therefore, should also not be effective recombination centers.
4.3 Diffusion Properties of Contaminants in Silicon
69
4.3.4.2 DLTS Profiling
Dynamic SIMS has a detection limit for Pt and Ir around 5 x 1014 cm-3 and 1 x 1015
cm-3 respectively, so that the profiling of these impurities was not possible at a depth
greater than of a few hundreds of nanometres. This of course, is not sufficient
considering the fact that these elements can deeply diffuse into the substrate, and
reach the active regions located at approximately one micron. This is actually the
typical distance between the bottom electrode and the transistor gate. On the other
hand, these concentrations are still considerably high, that the performance and
product yield can be critically affected, if we rely upon the detection limit of SIMS.
With a detection limit in the range of 10-4 x ND<C<10-1 x ND, where ND is the
substrate doping and C is the impurity concentration, DLTS offers a detection limit of
1011 cm-3, for the commonly used substrates in DRAM technology (typically of 1015
cm-3). The detection range depends on the bridge sensitivity and available
commercial DLTS have a detection limit of even below 1010 cm-3, making DLTS a
powerful sensitive detection method.
The profile measurement with DLTS was performed on samples of 1.4 x 0.4 cm2
size. These samples were beveled with angles of 1.17° or 2.9°, using 3µm Al2O3
powder followed by fine abrasive of 1 µm grain size. The obtained bevel extends over
a distance of 300 to 400 µm deep in the substrate. The samples were then polished
using successively a diamond suspension of 6 µm, 3 µm, 1 µm, and 0.25 µm
diameter size. A cleaning with isopropanol followed. The damaged surface layer was
then removed by etching the samples in an etch mixture of HF(50%)/HNO3(100%)/
CH3COOH(100%) in a ratio of 2:1:2. After this etching step at room temperature, 15
µm of the silicon material was removed. At the end, a 500 nm thick layer of Hf for pSi or Au for n-Si was evaporated through a shadow mask in order to provide a
Schottky contact. The ohmic contact on the back-side was obtained by rubbing Ga.
The device configuration used for the profile measurement is illustrated in figure 4.31.
0.4 cm
Schottky contact
Depth
Ohmic contact (rubbed Ga)
n-Si
1.4 cm
Fig. 4.31: Device configuration used in DLTS-Profiling measurements.
70
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
The Pt depth profile measured in CZ silicon is presented in figure 4.32. The Ushaped profile points out the dominance of the kick-out mechanism in both N2
annealed and O2 annealed samples. The measured concentrations are in good
agreement with the result of the simulation program developed by the Fraunhofer
Institute for Integrated Circuits [Zim 85]. The concentration of Pt in the middle of the
wafer was independent of the annealing atmosphere and has a value of 1.7x1012
cm-3. The U-shaped symmetrical profile indicates a negligible cross contamination
level during anneal. The effect of the annealing atmosphere near the surface could
be seen. However, after a distance of nearly 20 µm, no more difference is observed.
From the point of view of contamination risk, this means that a Pt contamination on
one surface will diffuse during the anneal, through the whole wafer and reach the
opposite surface. This is very alarming, since a Pt contamination on the back side,
which can easily occur through chucks (during Pt deposition or Pt plasma etching for
example), will diffuse to the active regions at the front side of the wafer and lead to
detrimental effects. This implies that the back-surface has to be protected with layers
that can getter Pt or with dense structures that can prevent Pt to diffuse into the Si.
For the first solution, deposition of poly-Si on the backside [Ogu 97], or creation of an
ion-beam damaged layer due to MeV implantation with O [Hol 95] or with He+ [Sch
99] were proposed. For the second solution, a Si3N4 or PSG (phosphoro-silicate
glass) layer were proposed by Deng et al. [Den 95b]
14
annealed in N2
annealed in O2
Simulation
-3
Pt concentration (cm )
10
10
13
10
12
10
11
0
150
300
450
600
Depth (µm)
Fig. 4.32: Pt profiles in a CZ wafer after diffusion at 800°C in N2 or O2
atmosphere compared with simulation results. Example shown corresponds to
a 10 ppm Pt concentration annealed for 60 min.
The example of Pt showed that for low detection of tolerable metal contamination in
bulk, DLTS performs best. Whereas direct TXRF does not detect 10 ppm Pt
annealed in O2, or barely detects it after oxide etch (with VPD-TXRF it is practically
not possible to collect Pt), DLTS shows that Pt diffuses deeply into the wafer and
has the same concentration in the middle of the wafer as if annealed in N2.
4.4 Diffusion of Contaminants in Poly-Silicon
71
The diffusion profile of Ir at 800°C is shown in figure 4.33. After 15 µm silicon etching
during DLTS preparation, the Ir concentration (of the two traps E2 and E3 defined
above) reaches the detection limit after some few tens of microns from both surfaces,
pointing out a relatively slow diffusion of Ir at 800°C. To check this result, we
calculate the diffusion length at 800°C after 3600s diffusion time from the work of
Azimov et al. [Azi 77] and Obeidi et al. [Obe 00] (extrapolated to temperature below
1000°C) and found the value of 77 µm and 214 µm respectively. The measured
profile agrees well with the diffusion coefficient in the temperature range 700-900°C,
measured by Azimov et al. [Azi 77]. The measured profile from the back-surface is
then due to a cross-contamination during the anneal as shown in the previous study
with TXRF and confirmed by the asymmetry of the profile. The danger of cross
contamination with Ir has already been mentioned in section 4.2.4
13
10
-3
Concentration (cm )
Trap E2
Trap E3
12
10
11
10
0
50
600
650
700
Depth (µm)
Fig. 4.33: Ir diffusion profile after anneal at 800°C in N2 atmosphere as
measured with DLTS profiling method.
4.4 Diffusion of Contaminants in Poly-Silicon
The transistor active regions are connected to the bottom electrode through a poly-Si
plug. Investigation of the Ba, Sr, Ir, and Pt diffusion properties in this layer is then of
the same importance as in crystalline Si. The poly-Si layer considered in this study
has 300 nm thickness, and is doped with phosphorus at 900°C using POCl3. The
sheet resistance obtained after doping has a value of 35 ± 0.7 Ω/ . This layer
simulates the poly-electrode, that will be used in the test structure to evaluate the
electrical properties (Chapter 5). The structure investigated consists of a 300 nm
poly-Si on 7.5 nm gate oxide. The substrate has the same specifications as before.
72
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
Figures 4.34a and b show the diffusion profiles of Ba and Sr, respectively, in 300 nm
poly-Si after an anneal at 800°C for 60 min. in O2 atmosphere. The general
observation is that the Ba and Sr diffuse into poly-Si over distances of some tens of
nanometers. From the depth profiles, diffusion coefficients of 4.7 x 10-16 cm2/s and
2.9 x 10-16 cm2/s could be extracted for Ba and Sr, respectively. These coefficients
are very close to the diffusion coefficients of Ba and Sr in crystalline-Si (5 x 10-16
cm2/s and 2 x 10-16 cm2/s for Ba and Sr respectively). This means that Ba and Sr
diffuse in phosphorus doped poly-silicon mainly through bulk diffusion mechanism
and that the diffusion through grain boundaries is not significant.
Counts
SiO
10
4
10
3
10
2
Ba
SiO2
10
(a)
Poly-Si
1
0
10
20
30
40
50
60
70
80
90
100
Depth (nm)
SiO
4
10
3
Counts
10
2
10
Sr
1
10
SiO2
(b)
Poly-Si
0
10
0
50
100
150
Depth (nm)
200
250
300
Fig. 4.34: (a) Ba and (b) Sr diffusion profile in poly-silicon at 800°C for 60 min.
in O2 atmosphere. The initial Ba and Sr concentration (100 ppm of each in the
solution) are 7 x 1013 and 1.5 x 1014 at/cm2 respectively.
4.4 Diffusion of Contaminants in Poly-Silicon
73
It seems relatively certain from these results that the diffusion of Ba and Sr to the
gate oxide through the poly-Si is unlikely, since most of these impurities are found in
the first 100 nm from the poly-Si surface. At this distance, the concentration of Ba
and Sr is 3 orders of magnitude lower than at the surface. As in the case of
crystalline-Si, the maximum of Ba and Sr concentration are found in the oxide and at
the Si/SiO2 interface. Therefore, the presence of Ba and Sr in the gate oxide, where
they can cause gate oxide degradation, is most unlikely due to the property of Ba and
Sr to be mainly included in the oxide and to the beneficial effect of the poly-Si layer to
contain, the rest.
Whereas Ba contamination was not observed to promote poly-Si oxidation, Sr
contamination enhances considerably the oxidation rate of poly-Si. The oxide film
thickness of Sr contaminated poly-Si (30 nm) is two times higher than the normal
thickness at 800°C. The Sr promoted oxidation can affect the device performance
since the poly-plug oxidation leads to an increase of the contact resistance.
For Ir, the case of anneal under N2 atmosphere is more interesting regarding the
diffusion to the active regions, since in O2, most all of Ir impurities evaporate. The
diffusion profile of Ir at 800°C is presented in figure 4.35a. This profile was measured
using SIMS, under the same conditions as in the section 4.3.3. It appears clearly
from the SIMS profile that Ir diffuses through the poly-Si layer and reaches the gate
oxide region and beyond in a considerably high concentration. This profile
corresponds to an initial Ir concentration of 6x1014 at/cm2 .
To confirm the profile measured with SIMS, Rutherford Back-Scattering (RBS)
measurements were performed using He ions accelerated at energy of 2.2 MeV.
Figure 4.35b presents the results of the RBS measurement together with a simulation
representing a spectrum when the distribution of Ir in the poly-Si is homogeneous.
The diffusion of Ir through the poly-Si, thus, is also confirmed by RBS.
21
10
GOX
20
Concentration (at/cm3)
10
Si
300 nm Poly-Si
19
10
18
10
(a)
17
10
16
10
15
10
0
100
200
300
Depth (nm)
400
500
74
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
Energy (MeV)
0.5
2
1.0
1.5
2.0
2.5
3.0
Ir
Yield log(#/uC/keV/msr)
1
300 nm
0
(b)
-1
Simulation
-2
-3
-4
0
100
200
300
400
Channel
Fig. 4.35: SIMS diffusion profile (a) and RBS spectrum (b) of 6x1014 Ir/cm2
diffused into poly-Si at 800°C in N2 atmosphere.
3
Concentration (at/cm )
It is very attractive to see that a good agreement, between the SIMS profile and the
reconstructed profile form the RBS measurement is obtain if the two profiles are
reported on the same plot (figure 4.36). These results point out that the P-doped
poly-Si layer cannot getter the Ir impurities.
10
22
10
21
10
20
10
19
10
18
10
17
10
16
10
15
10
14
GOX
Poly-Si
Si
SIMS
RBS
0
50
100
150
200
250
300
350
400
Depth (nm)
Fig. 4.36: Comparison between measured SIMS and RBS profiles of Ir
diffused into poly-Si at 800°C in N2 atmosphere.
4.4 Diffusion of Contaminants in Poly-Silicon
75
300 nm
Simulation
(a)
-2
10
GOX
-3
Pt/Si (at)
10
(b)
Si
300 nm Poly-Si
-4
10
-5
10
-6
10
0
50
100
150
200
250
300
350
400
Depth ( nm)
Fig. 4.37: RBS spectrum of 4 x 1014 Pt/cm2 diffused into poly-Si at 800°C in N2
(a), and the reconstructed profile from RBS measurement (b).
76
4 Properties of Barium, Strontium, Bismuth, Iridium, and Platinum Impurities in Silicon
To quantify the Ir concentration that reaches the gate oxide (relatively to the initial
concentration), the poly-Si layer was etched selectively to the gate oxide using a
Cholin (4%) solution at 60°C with an etch rate of 70 nm/min. Prior to the Cholin
etching, the native oxide on the surface was etched in BHF for 7 sec. Immediately
after the etching of poly-Si, the wafers were abundantly rinsed with DI-water for
15 min. Direct TXRF measurements were then conducted on the surface on different
positions. The concentration on the surface of Ir that reaches the oxide is (3.17 ±
1.14 ) x 1012 at/cm2. This concentration represents a value of 0.7% of the initial
concentration. This is in good agreement with the estimation done from SIMS and
RBS profiles. After the oxide etch, nearly the same concentration is found at the
surface of the substrate (4.05 ± 2.27)x1012at/cm2, which indicates further diffusion of
Ir into the substrate.
Pt impurities can be easily gettered in the very large number of sink site between
grain boundaries of the poly-Si [Hay 92]. The presence of P as dopant enhances the
effectiveness of gettering [Fal 85]. A RBS spectrum of a 4 x 1014 at/cm2 Pt
contamination level after an anneal at 800°C for 60 min in N2 atmosphere is
presented in figure 4.37a as well as the simulated spectrum of an homogeneously
distributed Pt in the poly-Si. A clear gettering effect of Pt in this layer is observed.
The reconstructed profile of Pt from RBS measurement is presented in figure 4.37b.
5 Electrical Characterization of Intentionally Contaminated
Samples
To undertake the second part of this work and to assess the influence of typical
FeRAM contamination on CMOS device properties, a test chip was designed. This
test chip reproduces the most important technological steps in the front end of line
processing and is used to simulate a typical FeRAM contamination in stacked cell
configuration. The test-chip allows the measurement of leakage current on diodes of
various geometries and areas or the evaluation of the gate oxide integrity on MOS
capacitors also with various areas. The test chip is in fact a simplification of the very
long process flow of the stacked cell FeRAM. It can be run relatively short for a quick
characterization of any possible contamination like electrodes or dielectric films.
5.1 Influence on the Minority Carrier Lifetime
The minority carrier recombination lifetime is a part of the electrical characterization.
In order to investigate the influence of Sr, Ba, Bi, Ir, and Pt contamination on minority
carrier recombination lifetime, intentionally contaminated wafers were analyzed using
the Elymat technique.
For the convenience of data presentation, the contamination level is presented in
units of ppm (i.e. the concentration in the contaminating solution), if the aim is only to
show the effect of increasing concentration. If the effect has to be quantified, the
corresponding concentration on the surface is then mentioned. This allows to present
not very complicated figures and show the results in a simple form. Moreover, the
corresponding concentration on the surface can be easily found in the section 2 of
chapter 4.
One side polished Czochralski silicon wafers of n and p-type, 4-6 Ωžcm, 150 mm in
diameter, were used in this experiment for the evaluation of minority carrier
recombination lifetime. These wafers have an initial oxygen concentration between
7.10 x 1017 cm-3 and 7.85 x 1017 cm-3 and a chemically etched back surface so that
gettering of impurities by defects is expected to be very low. According to the
manufacturer, these wafers have a minority carrier lifetime not lower than 50 µs.
A moderate injection level of 1 mA photocurrent was used in this study, so that the
Auger recombination can be neglected, and the recombination can be described
according to Shockley-Read-Hall (SRH) kinetics. Wafers were measured using
1%HF solution, inserted into the electrolyte in normal position (i.e. front surface was
illuminated) or flipped position (i.e. back surface was illuminated). The comparison
between the results of these two kinds of measurement gives information about the
symmetry of contamination and probes the back-side surface for defects or for cross
contamination.
78
5 Electrical Characterization of Intentionally Contaminated Samples
The lifetime was calculated from the measured diffusion current using the FPC
photocurrent of a 5 Ωžcm high lifetime clean wafer (and not annealed) for the
calibration. Wafers not contaminated, but annealed in O2 or N2, served as reference.
These reference wafers when measured with µ-PCD showed a low lifetime value of
16 µs. This is of course due to the bad surface passivation quality of the thermal or
native oxide that resulted from these anneals. Whereas, when measured with
Elymat, a lifetime exceeding 100 µs was found. The example of reference
measurements showed clearly that µ-PCD is not appropriate for this study.
Since the penetration depth of the laser light into the wafer depends on the energy
respectively the wavelength of the laser light, the lifetime was measured using an
infra-red (IR) light laser (wavelength 905 nm, penetration depth of 38 µm) or red light
laser (670 nm, penetration depth of 4 µm). By measuring with two different
penetration depths, information on depth distribution of the defects or recombination
centers could be extracted.
It should be emphasized here that in FPC mode, and generally speaking, the effect
of metal contamination is mainly through surface near precipitates which reduce the
collection efficiency of the semiconductor electrolyte junction, defined as the ratio of
the measured photocurrent to the generation current. To extend the information
obtained from the FPC mode beyond the depletion layer, the IR laser is used in this
mode.
5.1.1 Barium, Strontium, and Bismuth Contaminated Wafers
A lifetime mapping of 10 ppm Ba, Sr, and Bi contaminated wafers, in comparison to a
not contaminated wafer, after an anneal in O2 is presented in figure 5.1a-d
respectively. Across the whole wafer, a lifetime not lower than 50 µs is obtained. For
this concentration (around 1013 at/cm2 for all contaminants), the lifetime of Ba, Sr, or
Bi contaminated wafer is the same as that for a reference wafer and no degradation
of lifetime is seen.
The examination of diffusion and dark current (that is the leakage current) of the
wafers contaminated up to 100 ppm concentration in the solution, shows no
decrease in the diffusion current or increase in the dark current (figure 5-2). This is a
clear indication about the insignificant change in the recombination rate after the
introduction of Ba, Sr, or Bi contamination. The dependence of the lifetime upon the
contamination level of Ba, Sr, and Bi is presented in figure 5.3a for p-Si and in figure
5-3b for n-Si.
5.1 Influence on the Minority Carrier Lifetime
(a)
150 µs
79
(b)
150 µs
50 µs
(c)
350 µs
50 µs
(d)
150 µs
100 µs
50 µs
Fig. 5.1: Lifetime mapping of Ba (a), Sr (b), Bi (c) contaminated wafers, and
reference wafer (d). The lifetime was measured in BPC-mode using IR laser.
Ba
Sr
Bi
Ba
Sr
Bi
1000
Dark current (µA)
Diffusion current (µA)
1000
100
10
1
Ref.
2 ppm
10 ppm
100 ppm
Concentration in the solution
100
10
1
Ref.
2 ppm
10 ppm
100 ppm
Concentration in the solution
Fig. 5.2: Diffusion current and dark current at the supply voltage of 8 V as
function of Ba, Sr, and Bi concentrations in the contaminating solution.
80
5 Electrical Characterization of Intentionally Contaminated Samples
(a)
B P C , p -S i
IR
R ed
1 00 0
Lifetime (µs)
10 0
10
1
Bi-100 ppm
Bi-10 ppm
Bi-2 ppm
Sr-100 ppm
Sr-10 ppm
Sr-2 ppm
Ba-100 ppm
Ba-10 ppm
Ba-2 ppm
Reference
0 .1
(b)
IR
Red
1000
B P C , n -S i
Lifetime (µs)
100
10
1
Bi-100 ppm
Bi-10 ppm
Bi-2 ppm
Sr-100 ppm
Sr-10 ppm
Sr-2 ppm
Ba-100 ppm
Ba-10 ppm
Ba-2 ppm
Reference
0.1
Fig. 5.3: Minority carrier recombination lifetime dependence on Ba, Sr, or Bi
concentration in the contaminating solution. (a) corresponds to p-Si and (b) to
n-Si wafers. The lifetimes were measured with red and IR laser in BPC mode.
5.1 Influence on the Minority Carrier Lifetime
81
The results of BPC-mode show lifetimes as long as those in the reference wafer and
indicate no degradation or drastic decrease in lifetime with increasing contamination
levels up to 1014 at/cm2. This points out that under the tested conditions, Ba, Sr, or Bi
do not act as efficient recombination centers in n or p-type silicon, which is in good
agreement with DLTS results, where down to 20K, no specific deep trap was found.
Moreover, the comparison between the results of red and IR laser illustrates a good
agreement between the two wavelengths. The comparison between the normal and
the flipped measurement method shows no significant discrepancy between the two
methods, if we consider the fact that the front side (mirror polished) and the backside
(not polished) do not have exactly the same surface properties. It can be concluded
from these comparisons that after Ba, Sr, or Bi contamination up to a level of 1014
at/cm2, the bulk as well as the front and back surface of the wafer are still free from
effective recombination center or defects like precipitates.
N orm al
F lipped
Lifetime (µs)
1 00 0
10 0
10
Bi-100 ppm
Bi-10 ppm
Bi-2 ppm
Sr-100 ppm
Sr-10 ppm
Sr-2 ppm
Ba-100 ppm
Ba-10 ppm
Ba-2 ppm
Reference
1
Fig. 5.4: Comparison between the result of normal and flipped BPC
measurements.
The results of FPC-mode, where the surface was checked for metal precipitates,
assert the plausibility of the statement that no surface defects are generated by Ba,
Sr, or Bi. Up to contamination levels of 1014 at/cm2, the lifetime has a unique value
around 1000 µs across the whole wafer for all measured wafers, including the
reference. Because the presence or absence of Ba silicide (not too much is known
about Sr silicide) is related to the amount of Ba introduced in silicon, it can be
concluded that up to the mentioned concentrations range, no Ba or Sr silicidation is
likely to occur. This is in good agreement with the results of Hongo et al., who
demonstrated that no Ba silicide could be formed in submonolayer range at
temperature of 800°C [Hon 94]. This can also be seen clearly in figure 5.5, where
the collection efficiency of electrolyte junction in FPC mode is approaching the value
of 100% or is equal to the reference wafer value, annealed in the same conditions
(here O2 atmosphere). If compared to N2 atmosphere, we note here that the thermal
treatment at 800°C in O2, may lead to a slight degradation of the surface properties
82
5 Electrical Characterization of Intentionally Contaminated Samples
since the collection efficiency is relatively low. Point-defect generation due to dry
silicon oxidation, like injection of interstitial from the oxidizing interface into the
silicon, has been well established by Hu [Hu 74] and Dunham and Plummer [Dun 86].
This could be a reason of the relatively low collection efficiency of the reference
wafers annealed in O2 in comparison to those annealed in N2.
Collection efficiency (%)
104
100
96
92
88
84
Bi-100ppm
Bi-10 ppm
Bi-2 ppm
Sr-100ppm
Sr-10 ppm
Sr-2 ppm
Ba-100ppm
Ba-10 ppm
Ba-2 ppm
Ref-N2
Ref-O2
80
Fig. 5.5: Collection efficiency of the electrolyte junction in FPC mode, as
function of Ba, Sr, or Bi concentration, and in comparison to reference wafer
annealed in O2 (Ref-O2) or in N2 (Ref-N2).
After this analysis of minority carrier lifetime, some preliminary conclusions about the
nature of Ba, Sr, and Bi can be drawn:
•
Up to concentration of nearly 1014 at/cm2, neither Ba, nor Sr, nor Bi affect
the minority carrier lifetime.
•
No Ba or Sr silicide are possible to form in the sub-monolayer range after
an anneal at 800°C.
•
It can be concluded on the basis of the good correlation with DLTS
measurement, that Ba, Sr, or Bi do not introduce effective recombination
centers, and, therefore, are not considered as lifetime killers.
5.1 Influence on the Minority Carrier Lifetime
83
5.1.2 Iridium Contaminated Wafers
Figure 5.6 presents the lifetime mapping, in BPC and FPC mode, of 1 ppm Ir
contaminated wafer after an anneal in O2. Although Ir evaporates under O2 anneal,
and its presence was not found deeper in the bulk, the lifetime obtained has a very
low value, both in BPC and FPC mode. An explanation could be found in the
examination of the diffusion and dark current of figure 5.7.
(a)
(b)
8 µs
7 µs
6 µs
3 µs
Fig. 5.6: Lifetime mapping of 1 ppm Ir contamination annealed in O2. The
lifetime was measured in BPC-mode (a) and FPC mode (b) using IR laser.
The clear degradation of lifetime across the whole wafer is attributed to a drastic
decrease of the diffusion current with increasing Ir concentration, due to
recombination of the minority carriers with effective recombination centers introduced
by Ir. If annealed in N2, the diffusion current decreases linearly with increasing Ir
concentration. Whereas, if annealed in O2, the diffusion current saturates at a value
of one order of magnitude lower than the reference. The dark current exhibits the
same behavior, independently of the annealing atmosphere, if the Ir concentration is
higher than 10 ppm. The saturation of the dark current, which is a direct measure of
the recombination rate, has two meanings : 1) the dark current it is not determined
only by the bulk recombination, but rather by an additional recombination rate, which
of course is a surface recombination, since the other recombination mechanisms
(Auger or radiative) are excluded. 2) This additional recombination rate at the surface
even dominates the total recombination.
The influence of the surface recombination seems very plausible, especially in O2
annealing conditions, since Ir diffusion in the bulk was not observed as explained in
the section 4.3.3. Up to 100 ppm, all Ir impurities remaining after anneal, are located
very close to the surface. By exploiting the results of FPC mode measurement, the
influence of the surface can be seen. The plot of collection efficiency as function of Ir
concentration in the solution (Fig. 5.8) demonstrates clearly the degradation of
lifetime near the surface region.
84
5 Electrical Characterization of Intentionally Contaminated Samples
1000
Diffusion current (µA)
N2
O2
(a)
100
10
1
0.1
Reference
1 ppm
10 ppm
100 ppm
Ir concentration in the solution
6000
N2
O2
Dark current (µA)
5000
(b)
4000
3000
2000
1000
0
Reference
1 ppm
10 ppm
100 ppm
Ir concentration in the solution
Fig. 5.7: Diffusion current (a) and dark current (b) at the supply voltage of 6 V
as function of Ir concentration in the contaminating solution, upon annealing
atmosphere.
105
N
Collection efficiency (%)
100
O
2
2
95
90
85
80
75
70
65
100ppm
10ppm
1ppm
Ref-O2
100ppm
10ppm
1ppm
Ref-N2
60
Ir c o n c e n tr a tio n in th e s o lu tio n
Fig. 5.8: Collection efficiency of the electrolyte junction in FPC mode, as
function of Ir concentration in the contaminating solution.
5.1 Influence on the Minority Carrier Lifetime
85
The dependence of lifetime on the Ir concentration is illustrated in figure 5-9a for ntype and in figure 5-9b for a p-type silicon. The general observation is that the lifetime
of Ir contaminated wafers showed no dependence on the Ir concentration. A
discrepancy between the normal and flipped measurement method of FPC mode is
seen, more pronounced in p-type as in n-type Si. Absolutely, no difference between
the IR and red light (not presented here to avoid a huge graphical presentation) is
observed.
A similar result of lifetime independence on the concentration was obtained by Kittler
et al. [Kit 91] for the case of Ni contamination, who showed that the minority carrier
diffusion length is related to the precipitates density N of Ni in Si by the relationship :
L D = 0.7 x N −1 3
(5.1)
Kittler et al. demonstrated that the diffusion length depends only on the density of the
precipitates and not on the concentration of the impurity and that the NiSi2
precipitates provide the dominant recombination path. For our case, this explanation
can be ruled out since no Ir precipitation was observed with TEM (section 4.3.3). Or
at least, Ir does not strongly precipitate, so that a quantification of lifetime
measurement is possible, according to the criteria of Falster [Fas 98]. Falster
reported that quantification of lifetime measurement is possible only with the metalsilicon system, in which the metal is homogeneously dissolved as isolated atoms
through the wafer thickness. Metals, which precipitate strongly like Cu or Ni render
the quantitative analysis of the lifetime quite difficult, or even impossible.
For the explanation of these results, we propose the model of high surface
recombination velocity due to the presence of Ir impurities on the surface as the main
recombination path and argue this as follow: For the case of anneal in O2, SIMS and
DLTS measurements showed the presence of Ir only at the interface Si/SiO2. For the
case of anneal in N2, SIMS as well as DLTS show higher Ir concentration at the
surface than in the bulk. The concentration, in fact, decreases exponentially from the
surface. Good agreement between Elymat and µ-PCD is observed which supports
the hypothesis of the dominance of surface recombination because the surface of
these wafers were not really passivated, so that the dominance of the surface
recombination in µ-PCD measurement, is evident. No difference between FPC and
BPC values are observed, which points out a very short diffusion length.
86
5 Electrical Characterization of Intentionally Contaminated Samples
no rm a l B P C
flip p e d B P C
no rm a l F P C
flip p e d F P C
µ-P C D
(a)
Lifetime (µs)
10 00
O2
N2
1 00
10
1
R eference
1 ppm
1 0 p p m 1 0 0 p p m 1 pp m
1 0 p p m 1 00 p p m
Iridium concentration
10 0 0
N2
n o rm a l B P C
flip p e d B P C
n o rm a l F P C
flip p e d F P C
µ-P C D
O2
(b)
Lifetime (µs)
100
10
1
0 .1
0.0 1
R eference 1 ppm
10 ppm
100 ppm
1 ppm
10 ppm
100 ppm
Iridium concentration
Fig. 5.9: Minority carrier recombination lifetime dependence on Ir
concentration in the contaminating solution upon annealing atmosphere for ntype Si (a) and p-type Si (b).
5.1 Influence on the Minority Carrier Lifetime
87
5.1.3 Platinum Contaminated Wafers
The case of Pt is found to be not as complicated as the Ir case. Increase of
recombination rate with increasing of Pt concentration is obtained as illustrated in
figure 5.10. The diffusion current of BPC mode (figure 5.10a) decreases linearly and
the dark current increases linearly (figure 5.10b) with increasing Pt concentration on
the surface. The linear decrease is also observed in the FPC mode, presented in the
results of collection efficiency (figure 5.11). The anneal atmosphere has no prominent
effect. Nevertheless, the decrease of the collection efficiency is an indication of
surface degradation which has to be correlated with the presence of Pt.
(a)
Diffusion current (µA)
1000
N2
O2
100
10
1
0.1
Reference
1 ppm
10 ppm
100 ppm
Pt concentration in the solution
2000
(b)
Dark current (µA)
1600
N2
O2
1200
800
400
Reference
1 ppm
10 ppm
100 ppm
Pt concentration in the solution
Fig. 5.10: Diffusion current (a) and dark current (b) as function of Pt
concentration in the contaminating solution for N2 and O2 annealing
atmospheres.
88
5 Electrical Characterization of Intentionally Contaminated Samples
105
N2
O
2
100
Collection efficiency (%)
95
90
85
80
75
70
65
60
55
100ppm
10ppm
1ppm
Ref-O2
100ppm
10ppm
1ppm
Ref-N2
50
P t c o n c e n t r a t io n
Fig. 5.11: Collection efficiency of the junction electrolyte as function of Pt
concentration in the contaminating solution for N2 and O2 annealing
atmospheres.
Although no Pt precipitation occurs easily under the conditions used, and proved also
by TEM observations, the recombination at the surface has to be accounted. The
dependence of the minority carrier lifetime on Pt concentration and annealing
atmosphere is presented in figure 5.12a-b for n-Si and p-Si respectively as measured
in BPC and FPC mode for the normal and flipped methods. At 800°C Pt diffuses
through the kick-out mechanism, which leads to U-shaped profiles as measured with
the DLTS-profiling method. The concentration at the middle of this profile has a value
of 1.7 x 1012 cm-3, independently of the annealing atmosphere and the initial
concentration. Only, the concentration at the surface was observed to be dependent
on the annealing atmosphere and/or initial concentration. This concentration ranges
between 1013 cm-3 and 1014 cm-3. The effect of the concentration at the surface can
be seen in the measured lifetime. The lifetime in FPC mode decreases more rapidly
than in the BPC mode with increasing the concentration. The lifetime in FPC mode is
higher than in BPC mode for low concentration. However, the difference between the
two modes decreases with increasing the concentration. For high concentration, no
difference is observed.
Considering the capture cross-section of Pt (σn = 2.5 x 10-15 cm2 and σp = 4 x 10-15
cm2 ), the concentration at the middle of the profile leads to a calculated minority
lifetime of 8 µs for n-type and 12 µs for p-Si. This should be the lifetime due to
volume recombination, and most likely to be measured in BPC mode, if no other
recombination is involved. Indeed, the measured lifetime of 1 and 10 ppm
concentration is very close to the theoretical value, regardless of the annealing
atmosphere. With increasing concentration, the contribution of the surface
component dominates because the concentration of Pt increases in this region. This
5.1 Influence on the Minority Carrier Lifetime
89
explains, why for a high concentration of 100 ppm, no difference between BPC and
FPC results is observed.
1000
N2
Lifetime (µs)
100
normal BPC
flipped BPC
normal FPC
flipped FPC
µ-PCD
O2
10
1
0.1
0.01
-Reference
1 ppm
10 ppm 100 ppm 1 ppm
--
10 -ppm
100-- ppm
Pt concentration
normal BPC
flipped BPC
normal FPC
flipped FPC
µ-PCD
1000
N2
Lifetime (µs)
100
O2
10
1
0.1
0.01
-Reference
1 ppm
10 ppm 100 ppm 1 ppm
--
10 -ppm
100-- ppm
Pt concentration
Fig. 5.12: Minority carrier recombination lifetime dependence on Pt
concentration in the contaminating solution for n-type Si (a) and p-type Si (b)
and N2 and O2 annealing atmospheres.
90
5 Electrical Characterization of Intentionally Contaminated Samples
5.2 Design and Technology of Test Chip
Diodes or MOS structures having square geometry of 0.0625 mm2, 0.25 mm2, 1
mm2, 4 mm2 or 16 mm2 have been designed with a guard ring surrounding the active
region for a precision measurement of the leakage current. All the contacts, including
the substrate contact were integrated on the top surface as shown in figure 5.13.
Active
region
Guard-ring
Substrate
contact
Fig. 5.13 : View of the test structure 0.5 x 0.5 mm2, showing contact pad K,
guard ring pad G, and substrate contact pad S.
The guard ring is situated at a distance of 4.5 µm from the periphery of the active
region, has a width of 5 µm, and is constituted of a doped poly-Si on 7.5 nm gate
oxide. By forming an accumulation region (for a p-substrate, the guard ring is
negatively polarized with respect to the substrate) the coupling of adjacent devices is
prevented. The substrate contact surrounds the guard ring and is situated at a
distance of 4.5 µm from it.
For the evaluation of the periphery effect, structures with different peripheries have
been also designed using finger shaped electrodes. The geometries used have the
same area of 1 mm2 but different perimeters.
The test structure was fabricated on p-Si material, the same as used in the previous
studies. The technological parameters utilized originate from a 0.5 µm CMOS
5.2 Design and Technology of Test Chip
91
technology. The following section describes the most important steps of the process
flow.
5.2.1 LOCOS Isolation
The process starts with the LOCOS (LOCal Oxidation of Silicon) technique for device
isolation. The so-called poly buffered LOCOS was used to minimize the extent of the
bird’s beak and to reduce the stress between silicon substrate and nitride layer. A
pad oxide of 20 nm was grown at a temperature of 900°C in a dry O2 ambient. Low
pressure chemical vapor deposition (LPCVD) deposition of 100 nm poly-silicon at
620°C and 250 nm nitride at 680°C followed. For stress reduction, a ratio of
diclorosilane (DCS) to ammonia NH3 of 4:1 was used in the deposition of nitride.
After patterning with photolithography, the nitride was etched using a plasma
process. The gas used for etching was a mixture of CHF3 and O2. While CHF3 is
used mainly to etch the nitride, O2 etches the resist. Flow used in this work was found
to etch nitride at a rate of 30 nm/min. The nitride on the back-side was etched using a
spin etcher without the need to protect the front side with photoresist. The field oxide
was grown in a steam oxidation at 1000°C intervening two dry oxidation steps. The
resulting field oxide has a thickness of 625 nm. The nitride as well as the poly-Si
were then stripped.
5.2.2 N+ and P+ Implantation
Ion implantation was used for the formation of n+p junctions, and to dope the region
of the substrate contact (require to assure a good ohmic contact). A splitting of the lot
precedes the n+ ion implantation, since only wafers for diode structures received this
implant. A 20 nm TEOS deposited at 670°C was used as a screening oxide. The n+
active regions were formed by As+ implantation at energy of 80 keV with a dose of
5x1015 cm-2, followed by an anneal at 900 °C for 10 minutes in order to activate the
dopant. The depth distribution of the dopant as obtained from SIMS measurements is
presented in figure 5.14. The n+p junction depth is approximately 0.3 µm.
21
10
20
10
-3
Concentration (cm )
19
10
18
10
17
10
16
10
15
10
14
10
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Depth (µm)
Fig. 5.14: SIMS depth profile of implanted As at energy of 80 keV with a dose
of 5 x 1015 cm-2, followed by an anneal at 900 °C for 10 minutes.
92
5 Electrical Characterization of Intentionally Contaminated Samples
The p+ implantation under the substrate contact was performed with a BF2
implantation at energy of 50 keV and dose of 5 x 1015 cm-2.
5.2.3 Gate Oxide Growth, Poly-Silicon Deposition, and Patterning
Immediately after striping of the screening oxide and the cleaning of the wafers with a
cholin based solution, the wafers were loaded into the oxidation furnace. To avoid the
growth of a native oxide, the time coupling between the oxidation and the cleaning
step prior to oxidation does not exceed some few minutes. The thermal growth of the
gate oxide was done in a horizontal furnace. Wafers were loaded into the furnace at
temperature of 800 °C in a O2/N2 mixture ambient. The gate oxide was grown at
atmospheric pressure in dry O2 during a time tox resulting in 7.5 nm thick oxide. The
uniformity of the oxide is of a large concern in the process. Ellipsometry
measurements showed a good uniformity from run to run, with a standard deviation
never exceeding the value of 10% for all performed oxidations. The very good oxide
uniformity was also demonstrated from the tunnel current measurement on MOS
structures as shown in figure 5.15.
300 nm poly-Si deposition followed the gate oxidation with a time coupling shorter
than 2 hours. The poly-Si was deposited in a LPCVD furnace at 620°C using SiH4 at
a deposition rate of 11.0 ± 1.1 nm/min. A subsequent doping of the poly-Si was
performed at 900°C using POCl3. The phosphosilicate glass that results was stripped
in buffered HF. After doping, the poly-Si has a sheet resistance of 35 ± 0.7 Ω/ . The
poly-Si was then patterned using HBr/Cl2 in a plasma process. To avoid gate oxide
over-etch at the LOCOS edge, the electrode was extended over the field oxide as
shown in the inset of figure 5.16.
-3
10
-5
Current (A)
10
-7
10
-9
10
10
-11
0
2
4
6
8
10
12
Electric Field (MV/cm)
Fig. 5.15: Example of gate oxide uniformity measured on 118 capacitors.
5.2 Design and Technology of Test Chip
93
I-line lithography (wave length of 365 nm) was used in this work with an advanced
optical stepper tool from CANON, operating in projection mode. A 150 mm Reticle
mask was projected with a magnification of 1:5 on the wafer surface. After exposure
of one chip site, the wafer is stepped to the next chip site. The chip size is 18680 µm
x 19880 µm. 1.5 µm thick photoresist was utilized. A dose of 2400 J/cm2 was used to
expose the resist. For a fine and precise alignment, a TV image processing system
using predefined marks on the wafer, performed automatically the alignment task.
5.2.4 Interlayer Dielectric and Planarization
Interlayer dielectric (ILD) serves to isolate electrically the transistor from the bottom
electrode. This dense structure may also have the beneficial effect of preventing the
metals to diffuse into it and have in the same time a potential of gettering, since it
contains both P and B [Fal 85, Pol 88]. The ILD is constituted of 150 nm TEOS and
1600 nm BPSG, deposited in situ at temperature of 410°C in an APCVD furnace
using PH3, B2H6 and SiH4. The BPSG was doped with 4% by volume with
phosphorus and boron each.
The planarization of a pre-deposited ILD is desired to continue with a planar surface
and achieve an overall lower topography for low depth of focus requirement.
Chemical mechanical planarization was performed using a Westech 472 polisher for
150 mm wafers. A ready for use Klebosol suspension from Höchst corporation was
used as slurry.
After planarization, an opening hole, direct above the active region, was etched into
the ILD in a plasma etch process. This terminates the front-end of line processing of
the test structure. This opening until the poly-electrode allows to bring the
contamination to the active region. The device configuration, before contamination, is
shown in figure 5-16.
The wafers were then contaminated in a separated clean-room. The annealing as
well as further processing of the wafers were done in the Materials Innovation
Laboratory (MIL), a clean room of class 1, devoted to the development of new
materials by Infineon company.
5.2.5 Metallization
After that the wafers were contaminated and annealed, 300 nm TEOS was deposited
to protect the active region from other undesirable contamination that occurs during
the subsequent metallization. Contact holes for n+ side of the junctions, guard-ring
and substrate were then patterned into the ILD. Stacked metallization of 40/100/800
nm layer of Ti/TiN/AlSiCu was sputtered in situ in AMAT Endura HP PVD system.
The Ti is used to reduce the contact resistance and TiN as diffusion barrier for Al and
Cu penetration from Al-Si-Cu interconnect. Aluminum silicon copper metal alloy (Cu
percentage between 0.5wt-% and 3wt-%) has been used to improve electromigration
resistance and metal reliability. Due to low percentage of copper 0.5wt-%, with the
fact that Cu atoms alloyed with aluminum are immobilized by the aluminum matrix,
which acts as a very efficient getterer, Cu contamination is of no concern in this work
[Dor 00]. At the end, contact pad, guard-ring pad and substrate pad were patterned
on the top surface as already shown in figure 5.13. Sintering in forming gas
(95%N2:5%H2) at 430 °C for 30 min completes the process run. The final device
configuration is schematized in figure 5.17
94
5 Electrical Characterization of Intentionally Contaminated Samples
Active region
Guard-ring
200 nm nitride for
SEM preparation
ILD
Field
Oxide
Fig. 5.16: Device configuration just before the contamination.
Substrate contact
Guard-ring
Poly-electrode
Contamination
ILD
p+
n+
p
Fig. 5.17: Final device configuration used for the electrical measurements.
5.3 Leakage Current Measurement on Contaminated Diodes
95
5.3 Leakage Current Measurement on Contaminated Diodes
The reverse bias current of junction diodes is known to have two components: the
diffusion current and the thermal generation current. The generation current is
described according to SRH generation-recombination current and is given under
reverse bias condition by:
Ir = qA ò
W
0
U(x ) dx ,
(5.1)
where U(x) is the generation rate of electron-hole pairs per unit volume and unit time,
q the electron charge, A the junction area, and W the width of the space charge
region.
U(x ) =
(
)
σpσn v thNT np − ni2
é
é
æ E − Ei ö ù
æ E − ET ö ù
σn ên + ni expç T
÷ ú + σp êp + ni expç i
÷ú
è kT ø û
è kT ø û
ë
ë
(5.2)
where n and p are the electrons and holes concentration, respectively, and ni is the
intrinsic carrier concentration.
Assuming that all the trap centers (NT) have the same energy level ET, the capture
cross section for electron and holes (σn and σp respectively) have the same value σ,
the distribution of the recombination centers in the bulk crystal is constant, and the
product np over the space charge region is constant for a given bias, the reverse bulk
generation current is given by [Aha 97]:
Igen,r =
where τ =
q A W ni
,
æ E T − Ei ö
2 τ coshç
÷
è kT ø
1
σ v th NT
is the minority carrier recombination lifetime.
Considering the
æ E − Ei
τ g = τ coshç T
è kT
Igen,r =
(5.3)
definition
of
the
minority
carrier
generation
lifetime
ö
÷ , the generation current can be expressed as follow :
ø
q A W ni
2 τg
(5.4)
By analogy to the bulk generation current, the surface generation current, well
explained by Grove and Fitzgerald [Gro 66] and caused by the generation centers in
the depletion region at the Si/SiO2 interface along the junction periphery, has the
following expression:
96
5 Electrical Characterization of Intentionally Contaminated Samples
Igen,s =
1
q n i s Ws L
2
(5.5)
where s is the surface recombination velocity, W s is the depletion width at the Si/SiO2
interface, and L is the perimeter length of the junction.
The total reverse generation current is given by the sum of the bulk and surface
generation currents :
Ig,r = Igen,r + Igen,s =
æ W s Ws ö
1
q A ni ç
+
L÷
çτ
÷
2
A
g
è
ø
(5.6)
The dependence on the temperature of the total generation current is mainly through
the temperature dependence of the intrinsic carrier concentration ni and the
hyperbolic expression in equation (5.3). Sproul and Green [Spr 93] proposed the
following analytical expression of ni :
n i = 1.640 x 1015 T 1.706 exp( −E g / 2kT )
(5.7)
The temperature dependence of T1.706 is not important compared with the
exponential term, which explains the approximated result that the slope of the
generation current, if presented in Arrhenius plot, is proportional to − E g / 2 , for ET =
Ei [Aha 97].
The diffusion component in reverse bias condition is given by :
Id,r = q A ni2
Dn 1
,
τn N A
(5.8)
Dn is the electron diffusion coefficient and NA is the acceptor density.
This involves that the slope of ln(Id,r/T3) versus 1/T gives an activation energy equal
to Eg.
The leakage current (reverse bias current) is then obtained by adding the two
components of reverse generation current to the reverse diffusion component :
é
ù
Dn 1
1 W
1
Ir = Id,r + Igen,r + Igen,s = q êni2
A + ni
A + ni s Ws L ú
2 τg
τn NA
2
ëê
ûú
(5.9)
The two first components of the reverse current are related to the volume and the last
component is related to the Si/SiO2 interface at the junction perimeter and, therefore,
called the peripheral current. According to equation (5.9), the reverse bias diode
current can be expressed as the sum of the area current and the peripheral current :
Ir = JA A + JP L
(5.10)
5.3 Leakage Current Measurement on Contaminated Diodes
97
The most general criterion for the separation between the diffusion and generation
current is the temperature dependence of the two currents. If the diffusion current
dominates, an activation energy close to Eg is obtained, and in the case of generation
current dominance an activation energy close to Eg/2 is obtained.
The I-V diodes characteristic was measured using a parameter analyzer HP4156B.
The voltage bias of the n+ contact was varied, while the substrate contact was
grounded. The current was measured in step of 0.1 V using the medium integration
mode. The bias of the guard ring was -5 V with respect to the substrate. The system
leakage is in the range of 1 fA, allowing very precise measurements. For statistical
purpose, 30 diodes per each wafer were measured. For temperature dependence of
the leakage current, I-V curves were measured on a thermal vacuum chuck after a
waiting time of 3 minutes, sufficient to temperature stabilization over the whole wafer.
At each temperature, an entire I-V curve was measured in the conditions specified
above.
5.3.1 Barium, Strontium, and Bismuth Contaminated Diodes
The general I-V characteristic of 100 ppm Ba, Sr, or Bi (nearly 1014 at/cm2 for all)
contaminated diodes, after an anneal at 800°C in O2 atmosphere is presented in
figure 5.18. No clear difference between the leakage current distribution of the
contaminated wafers and a reference wafer is seen. Statistically, the leakage current
of Ba, Sr, and Bi contaminated wafers has nearly the same value as a non
contaminated wafer, even if it is processed in ultra-clean conditions, as it is illustrated
in figure 5-19a for a reverse bias of 7 V. Up to contamination levels of nearly 1014
at/cm2, no increase in leakage current is observed. The rather invariant value of the
leakage currents with increasing the concentration of the contaminants indicates that
Ba, Sr, or Bi does not cause the junctions to leak.
Figure 5-19b plots the temperature dependence of the leakage current of the 100
ppm Ba, Sr, and Bi contaminated diodes. The activation energy extracted from the
Arrhenius plot in the range between 28 and 120 °C, is 0.68 eV, which indicates that
the generation current dominates the reverse bias current and points out that no
additional traps are introduced by Ba, Sr, or Bi into the depletion region.
These results agree well with the previous results of minority carrier lifetime
measurements and support the evidence that under the tested conditions, BST or
SBT dielectrics can be integrated in CMOS technologies without major minority
carrier lifetime and leakage degradation concerns.
98
5 Electrical Characterization of Intentionally Contaminated Samples
1
10
-1
10
-3
10
-5
10
-7
10
-9
10
10
10
(a)
2
-11
0
2
4
-1
10
-3
10
-5
10
-7
10
-9
10
-2
1
(b)
Current density (A/cm )
2
Current density (A/cm )
10
6
8
-11
-2
10
0
2
4
6
8
10
Voltage (V)
Voltage (V)
1
10
0
10
(d)
Current density (A/cm )
2
Current density (A/cm )
2
(c)
-2
10
-5
10
-8
-3
10
-6
10
10
-9
10
-11
10
-12
-2
0
2
4
Voltage (V)
6
8
10
10
-2
0
2
4
6
8
10
Voltage (V)
Fig. 5.18: I-V diodes characteristic of (a) reference wafer, 100 ppm
contaminated wafer with (b) Ba (7x1013 at/cm2), (c) Sr (1.5x1014 at/cm2), and
(d) Bi (1014 at/cm2).
5.3 Leakage Current Measurement on Contaminated Diodes
99
(a)
-9
1x10
Ba
Sr
Bi
-10
Ref.
ultra clean
I (A)
1x10
10
-11
10
-12
10
10
Ref.
11
12
10
10
10
13
10
14
2
Contamination level (at/cm )
100 ppm Ba
100 ppm Sr
100 ppm Bi
-8
1x10
Ea= 0.68 eV
I (A)
-9
1x10
1x10
-10
10
-11
(b)
2.4
2.6
2.8
3.0
3.2
3.4
-1
1000/T ( K )
Fig. 5-19: Leakage current at 7V, as a function of the contamination level of
Ba, Sr, and Bi (a), and Arrhenius plot of the leakage current for 100 ppm Ba,
Sr and Bi contamination (b). The diodes area is 1 mm2.
100
5 Electrical Characterization of Intentionally Contaminated Samples
5.3.2 Iridium Contaminated Diodes
An interesting aspect with Ir contamination is that Ir can diffuse through the n+ doped
poly-silicon. Therefore, the possibility of Ir-impurities diffusion to the active region,
where they can easily generate deep level centers, is a cause of concern.
I-V curves of 100ppm and 50 ppm Ir contaminated diodes after anneal at 800°C in N2
atmosphere are presented in figure 5.20. An increase in leakage current is clearly
observed and is due to the contribution of the Ir impurities present in the active
region. The increase, however, is small because a large amount of Ir is contained in
the poly-Si electrode. If correlated to the initial concentration, nearly 1% of this initial
concentration reaches the active region as demonstrated in section 4.4, so that a
significant increase in leakage current occurs only if the initial contamination is
relatively high. Figure 5.21 summarizes the dependence of leakage current at 7V
reverse bias on the Ir contamination level.
10
-7
100 ppm
2
Current density (A/cm )
50 ppm
10
-8
10
-9
10
Reference
-10
-2
0
2
4
6
8
10
Voltage (V)
Fig.5.20: I-V diodes characteristic of reference wafer, 50 ppm and 100 ppm Ir
contaminated diodes and annealed in N2 (3x1013 at/cm2 and 6x1013 at/cm2
respectively)
If annealed in O2 atmosphere, the leakage current does not increase because of the
important loss in Ir concentration after anneal. The increase in the leakage current
occurs under the N2 anneal condition if the initial concentration is higher than
6x1012 at/cm2. The correlated concentration that reaches the active region is then
6x1010 at/cm2. This is actually the contamination level (1010 at/cm2) established by
several authors that may influence the DRAM performance [Tsu 90, Shi 90]. A good
5.3 Leakage Current Measurement on Contaminated Diodes
101
quantitative agreement is obtained between the tolerated concentration in FEOL and
the onset of the impact of Ir contamination on leakage current in BEOL.
Arrhenius plot of the leakage current in temperature range from 30°C to 120°C
(figure 5.22) shows the contribution of an additional trap at low temperatures below
60°C. This trap has an activation energy of 0.3 eV and is therefore located at 0.26 eV
from the conduction band. This trap corresponds to the level EC-0.28 eV measured
previously with DLTS in section 4.3.4. As a result, it is concluded that this level is the
dominant generation center.
2
Ir concentration on the surface (at/cm )
2
Current density (nA/cm )
1000
<5E10
3.7E11
5.66E13
annealed in N2
annealed in O2
100
10
6.41E12
Ref.
1
0.1
0.1
Ref.
1
10
100
Ir concentration in the solution (ppm)
Fig. 5.21: Leakage current density at 7V, as a function of the Ir contamination
level and annealing atmospheres.
An Arrhenius plot of the leakage current at different applied reverse voltages is
presented in figure 5-23. The activation energy is nearly independent of the reverse
bias, which implies that the leakage current is explained only by the SRH-generation
of homogeneously distributed centers and that the thermal generation according to
Poole-Frenkel effect 1 is not significant [The 85].
1
Poole-Freankel effect describes the lowering of the ionization energy by a field for a center that has a
Coulombic attractive interaction with the emitted carrier
5 Electrical Characterization of Intentionally Contaminated Samples
10
4
10
3
10
2
10
1
2
Current density (nA/cm )
102
Ea=0.7 eV
Ea=0.3 eV
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
-1
1000/T (K )
Fig. 5.22: Arrhenius plot of the leakage current at 7V reverse bias of 6x1013
Ir/cm2 contaminated diodes.
@ 3V
5V
7V
9V
2
Current density (nA/cm )
1000
100
Ea=0.3 eV
10
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
-1
1000/T (K )
Fig. 5.23: Arrhenius plot of the leakage current at different reverse biases of
6x1013 Ir/cm2 contaminated diodes.
5.3 Leakage Current Measurement on Contaminated Diodes
103
5.3.3 Platinum Contaminated Diodes
2
Current density (A/cm )
The poly-silicon layer provides the benefit of Pt gettering out of the active regions. If
the Pt impurities do not really reach the active region, its detrimental electrical activity
could not happen. This could be clearly seen if one examines the reverse I-V
characteristics of Pt contaminated diodes. Figure 5.24 shows the leakage current of
diodes contaminated with 4 x 1014 at/cm2 and annealed in N2. Even if the
contamination level is very high, the leakage currents are in the same range as of a
reference wafer (not presented here because the IV curves overlap and make the
results not clear to see ).
10
-7
10
-8
10
-9
10
-10
0
2
4
6
8
10
Voltage (V)
Fig. 5.24: I-V diodes reverse characteristic of 4 x 1014 at/cm2 Pt contaminated
diodes annealed in N2.
Figure 5.25 summarizes the dependence of the leakage current at 7V reverse bias
on the Pt contamination level. Pt contaminated diodes up to the range of 1ML have
the same value of the leakage current as non contaminated diodes. The effect of Pt
as an effective recombination is completely invisible. This is confirmed also by
Arrhenius plot of the leakage current of the 4 x 1014 at/cm2 contaminated diodes
(figure 5.26) which points out that no traps are introduced by Pt into the depletion
region. The activation energy extracted from the Arrhenius plot in the range between
30 and 100°C, is 0.69 eV, which indicates that the generation current dominates the
reverse bias current .
All these results are consistent with the RBS result demonstrating the absence of Pt
impurities in the active regions. As results, it can be concluded that Pt in the Back-
104
5 Electrical Characterization of Intentionally Contaminated Samples
End Of Line (BEOL) is not culprit of performance degradation in the same manner as
in the Front-End Of Line (FEOL) [Den 95] if the contamination occurs after device
processing. These results with those concerning Ir point out clearly that the influence
of metal contamination depends strongly on the efficiency of gettering technique. It is
worth to mention that no diffusion barrier was used in this work. A diffusion barrier
may be beneficial to lower or even prevent, the diffusion of Pt into the poly-Si, hence
reducing the risk of Pt diffusion to the active region.
2
Pt Concentration on the surface (at/cm )
<5E10
1E13
7E13
Ref.
10 ppm
100 ppm
4E14
2
Current density (nA/cm )
100
10
1
0.1
1000ppm
Pt Concentration in the contaminating solution
2
Current density (A/cm )
Fig. 5.25: Leakage current density at 7V, as function of the Pt contamination
level.
10
-5
10
-6
10
-7
10
-8
10
-9
Ea=0.69 eV
-10
10
2.6
2.8
3.0
3.2
3.4
-1
1000/T (K )
Fig. 5.26: Arrhenius plot of the leakage current at 7V reverse bias of 4x1014
Pt/cm2 contaminated diodes.
5.3 Leakage Current Measurement on Contaminated Diodes
105
5.3.4 Discussion of the Leakage Current Results
While the results concerning Ba, Sr, and Bi influence on the leakage current were
obvious since these elements are not observed to decrease the minority carrier
lifetime, two interesting cases of Ir and Pt were shown.
With our better understanding of Ba, Sr, and Bi properties, evidences of the
relaxation of the Ba, Sr, and Bi contamination was established from the minority
carrier lifetime measurements. From the results of leakage current, the evidence that
Ba, Sr, and Bi do not introduce efficient deep levels recombination center into Si and,
therefore, do not cause the junctions to leak, has been reinforced. It is concluded that
in the tested conditions, BST or SBT dielectrics can be integrated in CMOS
processes without major minority carrier lifetime and diode leakage current
degradation concerns.
The leakage current results were also an opportunity to confirm the results of the
previous study concerning Ir and Pt diffusion properties in the poly-Si. Increase or
invariance in the leakage current is simply a measure of presence or absence of
metallic impurities in the active regions. Diffusion of Ir to these regions has been
proven by the increase of the leakage current with increasing the Ir concentration. A
quantification of the tolerated Ir contamination in the Back-End Of Line is now
established to be 5 x 1012 at/cm2. This level is in very good quantitative agreement
with the tolerated level in the Front-End Of Line of 1010 at/cm2.
Effective gettering by the phosphorus doped poly-Si of Pt up to levels of 4 x 1014
at/cm2 has been also demonstrated from the electrical measurement of Pt
contaminated diodes.
It becomes clear that the concern of increase in leakage current in FeRAM should be
based on two considerations: 1) any effective recombination center, and 2)
simultaneously can diffuse through the poly-Si plug to transistor active regions. Of
course, the diffusion from the back-side is also a concern.
106
5 Electrical Characterization of Intentionally Contaminated Samples
5.4 Gate-Oxide Integrity Evaluation
The first work of GOI assessment was done on the MOS capacitors fabricated as
described above. Owing to the very huge numbers of wafers to be contaminated and
the diversity of the experiments (ambient effects and/or concentration effects for
each contaminant) in addition to the long time necessary for the production of the test
wafers (maximal 25 wafers in 10 weeks approximately) the test structure was
simplified to MOS planar capacitors without lateral isolation (i.e. LOCOS).
Wafers with p+/p epitaxial substrate were used for their high quality, defect free and
to avoid any effect of the CZ substrate. The substrate is constituted of a boron doped
epitaxial layer of 8 ± 0.5 µm thick on highly doped boron 150 mm CZ wafer of 0.01 to
0.02 Ω·cm resistivity. After the 7.5 nm gate oxide growth and poly-Si deposition, the
poly-Si was doped with phosphorus using POCl3 at 900 °C for 30 min. The
phosphorus glass that results from the doping and drive-in step was etched using
BHF solution. The wafers were then cleaned and their surface was kept hydrophilic
at the end of the cleaning process. The front poly-Si surface of the wafers was
intentionally contaminated and subsequently annealed at 800°C for 60 min. The polySi on the back-side (used to prevent any contamination on the back side to diffuse to
the front side) was then etched in a mixture of HF/HNO3 after protecting the front
side by photoresist. MOS capacitor structures with areas of 0.1 mm2, 1 mm2, 4 mm2,
and 16 mm2 were chemically defined. The back-side contact was obtained by the
evaporation of 500 nm Al followed by a forming gas anneal at 430°C for 30 min.
There are mainly three methods of stressing the oxide leading to its breakdown,
which are E-Ramp, Constant Current Stress Charge to break-down (CCS-QBD), and
Time-Dependent Dielectric Breakdown (TDDB). E-Ramp method consists in
stressing the oxide film to breakdown by application of a voltage that is ramped with
time, whereas in TDDB , the breakdown is examined under a constant voltage, thus
requires a long testing time. The advantage of E-Ramp over TDDB method is the
rapidity of assessing wafer-level reliability, while the TDDB has the merit to be more
straightforward with respect to lifetime extrapolation, since it reproduces the real
conditions in which the device operates [Hor 97]. CCS-QBD is commonly used to
assess the influence of the processing condition on device reliability [Nig 98, Mar 98].
5.4.1 Results from E-Ramp
Breakdown events were evaluated on 118 MOS capacitors on each wafer.
Breakdown was determined in accumulation condition by applying a voltage stress
that linearly increases with time in rate of 0.1 V/s . The applied electrical field ranges
from 0 to 12 MV/cm and the breakdown was defined by a threshold current density of
0.1 mA/cm2. After this first stage test, the field is switched back to 2 MV/cm to
determine if the failure was irreversible or tunneling in nature. Population of
capacitors, that survived, are determined as predominately intrinsic breakdown in a
follow-up test at 12 MV/cm. Statistical variation from wafer to wafer is taken into
account by considering the results on each of three separate wafers.
Typically, histograms that plot the number of failed capacitors versus the breakdown
field Ebd, can be divided in three modes, namely, mode A, B, and C. Population that
5.4 Gate-Oxide Integrity Evaluation
107
fail in low field range (E<0.5 MV/cm) represents the mode A failure, and is attributed
to pinhole or to metal contamination. The failure mode B (0.5<Ebd<7.5 MV/cm) is due
to a weak spot which had originally not been conductive until breakdown occured
[Hor 97]. The mode C (7.5<Ebd<12 MV/cm), is due to a defect free population that fail
intrinsically, hence, called the intrinsic failure mode.
5.4.1.1 Barium, Strontium, and Bismuth Contaminated MOS Structures
Current-electric field curves of 1000 ppm Ba, Sr, or Bi contaminated MOS structures,
as well as of clean wafers, are presented in figure 5.27 for capacitors areas of 1 mm2.
These curves reflect the worst case, that could happen for Ba, Sr, or Bi
contamination up to levels of 4 x 1014 at/cm2, 9.6 x 1014 at/cm2, or 5.2 x 1014 at/cm2
respectively. Only a small number of low field breakdowns were apparent. The I-E
curves of contaminated wafers, similar to the reference wafers, are tightly grouped
and the main breakdown events occur in the intrinsic range.
-2
(a)
-2
10
-4
-4
10
10
14
2
Ba(4x 10 at/cm)
-6
10
Current (A)
Current (A)
(b)
10
-8
10
-6
10
4
6
-8
10
10
-12
-12
10
10
0
2
4
6
8
10
0
12
2
8
10
12
Electricfield(MV/cm)
Electricfield(MV/cm)
(d)
-2
-2
10
-4
10
10
-4
10
14
2
Bi (5.2x10 at/cm)
-6
10
Current (A)
Current (A)
2
-10
-10
10
(c)
14
Sr (9.6x10 at/cm)
-8
10
Reference
-6
10
-8
10
-10
-10
10
10
-12
-12
10
10
0
2
4
6
8
Electricfield(MV/cm)
10
12
0
2
4
6
8
10
12
Electricfield(MV/cm)
Fig. 5. 27: Voltage ramp I-E curves of contaminated MOS capacitors with Ba
level of 4 x 1014 at/cm2 (a), Sr level of 9.6x1014 at/cm2 (b), Bi level of 5x1014
at/cm2 (c), in comparison to reference wafers (d). The capacitors area is
1 mm2.
108
5 Electrical Characterization of Intentionally Contaminated Samples
Histograms of oxide breakdown fields for 1 mm2 electrode area are shown in figure 5.
A breakdown frequency exceeding 90% is observed at a breakdown field of
12 MV/cm for the contaminated wafers as well as the reference wafers. Some
breakdown events (lower than 10%) occur below 12 MV/cm, however, still in the
intrinsic range between 7.5 and 12 MV/cm.
80
60
B a (4 x 1 0
14
2
a t/c m )
40
20
0
0
1
2
100
Breakdown failure (%)
Breakdown failure (%)
100
3
4
5
6
7
8
Electric field (M V/cm )
80
60
B i (5 .2 x 1 0
14
2
a t/c m )
40
20
0
0
1
2
3
4
5
6
7
8
80
60
S r (9 .6 x 1 0
14
2
a t/c m )
40
20
0
9 10 11 12 13
0
1
2
100
Breakdown Failure (%)
Breakdown failure (%)
100
3
4
5
6
7
8
9 10 11 12 13
Electric field (M V/cm )
80
60
R e fe re n c e
40
20
0
9 10 11 12 13
Electric field (M V/cm )
0
1
2
3
4
5
6
7
8
9 10 11 12 13
Electric field (M V/cm )
Fig. 5.28: Breakdown frequency as a function of applied electric field for Ba,
Sr, and Bi contaminated wafers as well as the reference wafers.
100
-2
Defect Density (cm )
Ba
Sr
Bi
10 Reference
1
0.1
10
11
10
12
10
13
10
14
10
15
2
Contamination level (at/cm )
Fig. 5.29: Defect density at 12 MV/cm as function of Ba, Sr, and Bi
contamination level for 1mm2 capacitor area.
5.4 Gate-Oxide Integrity Evaluation
109
To conclude the results from E-ramp measurement of Ba, Sr, and Bi contamination,
the defect density is presented in figure 5.29. The defect density is calculated
assuming a random distribution of defects, so that the Poisson yield model is used
for the calculation :
Y = exp(-A/D0)
(5.11)
where Y is the yield, A the area and D0 is the defect density. Clearly, and if compared
to the not contaminated reference wafers, Ba, Sr, or Bi do not cause high defect
densities.
It can be concluded from the E-ramp measurement that all the breakdown events
that occur after Ba, Sr, or Bi contamination are of intrinsic nature and that Ba, Sr, or
Bi contamination as high as 4x1014 at/cm2 has no detrimental effect on gate oxide
integrity.
5.4.1.2 Iridium Contaminated MOS Structures
10
-2
10
-2
10
-4
10
-4
10
-6
10
-8
10
-10
10
-12
Current (A)
Current (A)
A surprising effect with Ir is that in the I-E curves of the contaminated wafers no
significant breakdown events were apparent even for high contamination levels.
Figure 5.30 plots the worst case seen after measurement on wafers contaminated up
to 1000 ppm and annealed in N2 (contamination level of 6x1014 at/cm2). Only two out
of 118 capacitors fail at low breakdown field. Histograms of oxide breakdown fields
for 1 mm2 electrode area, presented in figure 5.31, do not reveal significant mode A
or mode B breakdown events. The main breakdown mode is the intrinsic one
occurring at nearly 12 MV/cm breakdown field. The breakdown mode was not
affected neither by the Ir concentration nor by the annealing atmosphere.
0
2
4
6
8
Electric field (MV/cm)
10
12
10
-6
10
-8
10
-10
10
-12
Reference
0
2
4
6
8
10
12
Electric field (MV/cm)
Fig. 5.30: Current-Electric field curves of 118 MOS capacitors of 1mm2 area,
contaminated with 1000 ppm (6x1014 at/cm2) Ir and annealed in N2
atmosphere (a) in comparison to the reference wafers (b).
110
5 Electrical Characterization of Intentionally Contaminated Samples
Breakdown Failure (%)
100
80
Reference
60
40
20
0
Breakdown Failure (%)
100
80
1000 ppm Ir in N2
14
2
(6 x 10 at/cm )
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Electric field (MV/cm)
60
100 ppm Ir in N2
13
2
(6 x 10 at/cm )
40
20
100
Electric field (MV/cm)
60
80
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Breakdown failure (%)
Breakdown Failure (%)
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Electric field (MV/cm)
80
60
1000 ppm Ir in O2
11
2
(8 x 10 at/cm )
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Electric field (MV/cm)
Fig. 5.31: Breakdown frequency as a function of applied electric field for
reference wafers and various Ir contaminated wafers. The case of maximal
concentration anneal in O2 is also evoked.
The effects under O2 annealing conditions are not surprising in the same manner as
those of annealing in N2 atmosphere, since a very important loss in Ir concentration
was observed in O2 atmosphere. If annealed in N2 atmosphere, however, Ir was
observed to diffuse through the poly-Si layer and even causes an increase in diodes
leakage current.
The diffusion of Ir to the substrate through the poly-Si, into the gate oxide is not
observed to increase the defect density as depicted in figure 5-32.
2
-2
Defect density (cm )
100
Ir concentration on the surface (at/cm )
6E13
6E14
8E11
10
1
0.1
Ref.
100 ppm-N2
1000 ppm-N2 1000 ppm-O2
Ir concentration-anneal atmosphere
Fig. 5.32: Defect density at 12 MV/cm of references wafers and various Ir
contaminated wafers upon annealing atmosphere. The capacitor area is 1mm2.
5.4 Gate-Oxide Integrity Evaluation
111
5.4.1.3 Platinum Contaminated MOS Structures
Current-electric field curves of Pt contaminated wafers up to 4x1014 at/cm2 are
presented in figure 5.33 for capacitor areas of 1 mm2. These curves reflect the worst
case, that could happen for Pt contamination up to levels of 4 x 1014 at/cm2. If
compared to non contaminated reference wafers, some failure cases at low
breakdown fields were apparent. However, most of the I-E curves of contaminated
wafers are tightly grouped and the main breakdown events occur in the intrinsic
range.
10
1 0 0 0 p p m in N 2
-2
1 0 0 p p m in N 2
10
-4
10
-6
10
-8
10
-1 0
10
-1 2
13
a t /c m
-2
10
-4
10
-6
10
-8
4 x 10
14
a t /c m
2
2
Current (A)
Current (A)
6 .8 x 1 0
10
10
-1 0
10
-1 2
(a)
0
2
4
6
8
10
(b)
12
0
10
-2
10
-4
10
-6
10
-8
1 0 0 0 p p m in O 2
4 x 10
10
-1 0
10
-1 2
14
a t/c m
2
4
6
8
2
10
-2
10
-4
2
4
6
8
E le c t r ic f ie ld ( M V /c m )
12
10
-6
10
-8
10
-1 0
10
-1 2
R e fe r e n c e
(c)
0
10
E le c t r ic f ile d ( M V /c m )
Current (A)
Current (A)
E le c t r ic f ie ld ( M V /c m )
10
(d)
12
0
2
4
6
8
10
12
E le c t r ic fie ld ( M V /c m )
Fig. 5.33: Voltage ramp I-E curves of MOS capacitors with a Pt contamination
level of 6.8x1013 at/cm2 (a), 4 x 1014 at/cm2 annealed in N2 (b) or in O2 (c) in
comparison to reference wafers (d). The capacitors area is 1 mm2.
112
5 Electrical Characterization of Intentionally Contaminated Samples
Histograms of oxide breakdown fields for an electrode area of 1 mm2 are shown in
figure 5.34. A breakdown frequency of 90%, close to 12 MV/cm is observed for the
contaminated wafers. Some breakdown events (approximately 10%) occur below 12
MV/cm, mainly in the A-mode range (E<1 MV/cm) and B-mode range
(1<E<5 MV/cm).
Breakdown Failure (%)
80
60
Reference
40
20
0
100
Breakdown Failure (%)
100
Electric field (MV/cm)
13
20
0
2
100 ppm Pt (6.8 x 10 at/cm )
40
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Electric field (MV/cm)
60
13
2
10 ppm Pt (1x10 at/cm )
40
20
100
80
60
80
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Breakdown failure (%)
Breakdown Failure (%)
100
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Electric field (MV/cm)
80
14
60
2
1000 ppm (4.4 x 10 at/cm )
40
20
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Electric field (MV/cm)
Fig. 5.34: Breakdown frequency as a function of applied electric field for
reference wafers and various Pt contaminated wafers.
Figure 5.35 shows the defect density as calculated from the E-Ramp results and
using the Poisson yield equation. The defect density appears to be slightly increased
by the Pt contamination and shows a weak systematic dependence on the Pt
concentration. The annealing atmosphere is also seen to not alter considerably the
Pt contamination effect.
It can be concluded from the E-Ramp results that platinum contamination up to
4x1014 at/cm2 does not have a pronounced effect on the gate oxide integrity if the
contamination occurs after poly-Si device fabrication.
5.4 Gate-Oxide Integrity Evaluation
113
2
Annealed in N2
Annealed in O2
-2
Defect density (cm )
100
Pt Concentration on the surface (at/cm )
1E13
6.8E13
4.4E14
10
1
0.1
Ref.
10
100
1000
Pt concentration in the solution (ppm)
Fig. 5.35 : Defect density at 12 MV/cm of references wafers and various Pt
contaminated wafers annealed either in N2 or O2 atmosphere. The capacitors
area is 1mm2.
5.4.2 Results from Constant Current Stress Charge to Breakdown
The result of E-ramp measurement show no impact at all of Ba, Sr, Bi, and Ir on the
oxide breakdown strength. For Pt, a slight effect, but not detrimental, was seen. In
order to get more insight on the impact of the contamination on the gate oxide
breakdown, Constant Charge Stress Charge to Breakdown (CCS-Qbd)
measurements were performed on large area capacitors (1 mm2, 4 mm2, and
16 mm2) to make the extrinsic breakdown more visible. Small area capacitors of
0.1 mm2, were also used as a indication of intrinsic breakdown.
In this assessment method, a current of electrons is injected by tunneling through the
oxide. The voltage applied on the capacitor to maintain a constant current density is
measured. The breakdown is defined when a large and sudden drop in the applied
voltage occurs. The measurements were done with injecting electrons from the gate
(poly-gate was negatively polarized with respect to the substrate). The injected
current is increased in steps as shown in the Table 5.1
In the preliminary test stage, defects like pin hole are determined. Early failure
behavior i.e. extrinsic breakdown, is determined in the main test. Population of
capacitors that survived, are considered for predominately intrinsic breakdown in a
follow-up test, in which the capacitors are stressed until they break. The time to
breakdown is measured and the breakdown charge density Qbd is then calculated
taking the capacitor area and the injected current into consideration. Measurements
were carried-out on 60 capacitors from each wafer, sufficient to determine the small
number of extrinsic breakdown.
114
5 Electrical Characterization of Intentionally Contaminated Samples
Table 5.1: Stress conditions used in CCS-Qbd measurements
Test
Level
Preliminary test
Main test
Current density
(mA/cm2)
0.05
0.1
0.2
0.5
1
2
5
10
20
50
100
100
1
2
3
4
5
6
7
8
9
10
Follow-up test
Injection time
(S)
0.2
1
1
1
1
1
1
1
1
1
1
<50*
*increased if necessary
5.4.2.1 Barium, Strontium, and Bismuth Contaminated MOS Structures
The results of charge to breakdown measurement of Ba contamination are presented
in figure 5.36a-b, for 0.1 mm2 and 1 mm2 area capacitors respectively. The results
were fitted to the model presented in section 3.2.5. A good agreement between the
experimental results and the model are obtained (also for the next results). The case
of 100 ppm ( 7x1013 at/cm2) and 1000 ppm Ba contamination level (4x1014 at/cm2),
annealed in O2, are presented in these figures in the form of a Weibull plot. If
compared to reference wafers, which were not contaminated, the intrinsic breakdown
parts are exactly the same.
2
99.9
1
Ref.
13
2
7 x 10 at/cm Ba
14
2
4 x 10 at/cm Ba
Model
ln[-ln(1-F)]
-1
70
50
30
20
-2
10
-3
5
-4
2
1
-5
-6
-8
10
10
-7
10
-6
10
-5
10
-4
10
-3
-2
10
2
Qbd (C/cm )
-1
10
10
0
10
1
10
2
Cumulative Failure F (%)
0
90
(a)
5.4 Gate-Oxide Integrity Evaluation
115
2
99.9
Ref.
13
2
7 x 10 at/cm Ba
14
2
4 x 10 at/cm Ba
Model
1
ln[-ln(1-F)]
70
50
-1
30
20
-2
10
-3
5
-4
2
Cumulative Failure F(%)
0
90
(b)
1
-5
-6
10
10
-5
-4
10
-3
10
10
-2
-1
10
10
0
1
10
10
2
2
Qbd (C/cm )
Fig. 5.36: Charge to breakdown distribution of various Ba contamination for
0.1 mm2 (a) and 1 mm2 area capacitors (b). The experimental results are fitted
to the distribution of equation (3.34).
Moreover, the examination of the extrinsic part in the Weibull plots indicates that the
extrinsic breakdown is not affected by Ba contamination and points out that a defectdriven breakdown process does not appear as the Ba contamination level increases.
Using the model of equation (3.31), the extracted fitting parameters are listed in
Table 5.2 for areas of 0.1 mm2 and 1 mm2.
Table 5.2: Intrinsic and extrinsic breakdown parameters, as well as the fraction
1-p, as determined from the fit of the measured charge to breakdown to the
model of Degraeve et al. [Deg 98b]. The case presented corresponds to a
4x1014 Ba/cm2 contamination.
Parameter\area
Ref.
1-p
ηi (C/cm2)
βi
ηe (C/cm2)
βe
0.1 mm2
7x1013
at/cm2
4x1014
at/cm2
Ref.
1 mm2
7x1013
at/cm2
4x1014
at/cm2
0.953± 0.01 0.966± 0.01 0.973± 0.01 0.89± 0.006 0.91± 0.007 0.89± 0.01
10.85± 0.02 11.26± 0.01 11.40± 0.02 7.16 ± 0.01 7.05 ± 0.01 7.26 ± 0.01
4.9 ± 0.06
5.22 ± 0.04
5.16 ± 0.05
5.14 ± 0.07
4.94 ± 0.06
5.3 ± 0.07
0.65 ± 0.3
0.73 ± 0.17
0.78 ± 0.33
0.1 ± 0.03
0.4 ± 0.06
0.1 ± 0.02
0.13 ± 0.02
0.21 ± 0.01 0.17± 0.01
0.31 ± 0.01
0.4 ± 0.01
0.31 ± 0.01
No difference between the extrinsic and intrinsic parameters of Ba contaminated
wafers and the non contaminated wafers is seen. The parameter 1-p (defect free part
of the population that fails fully intrinsically) as well as ηi and ηe (63% charge to
breakdown of intrinsic and extrinsic mode respectively) are area dependent and are
not affected by the Ba contamination. Most of capacitors (90% for area of 1mm2) still
116
5 Electrical Characterization of Intentionally Contaminated Samples
fail intrinsically after Ba contamination as high as 4x1014 at/cm2. β (the slope of
Weibull distribution) does not depend on the area for the intrinsic mode but is slightly
dependent on the area for the extrinsic mode.
To conclude the investigation of Ba contamination, the results are summarized and
grouped in the plot of defect density versus the charge to breakdown (figure 5.37), for
all measured areas.
10
5
10
4
10
3
10
2
10
1
10
0
-2
Defect Density (cm )
2
Ref.-4mm
2
0.1 mm
2
1 mm
2
4 mm
2
16 mm
10
-1
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
2
Qbd (C/cm )
Fig. 5.37: Defect density of 4 x 1014 Ba/cm2 contamination, as function of the
injected charge to breakdown for different areas. The case of reference is
given for the purpose of comparison.
Clearly, a unique area-independent extrinsic part is found, indicating that the extrinsic
breakdown mechanism is the same for the Ba contaminated wafers as for the
reference wafers and that the extrinsic breakdown sites are randomly distributed.
The case of Sr contamination annealed in O2 is shown below. If compared to the
parameters of reference wafers (Table 5.3), the breakdown characteristic of Sr
contaminated wafers are not affected. Statistically, no significant trends are observed
when comparing the Weibull plot of reference wafers to Sr contaminated wafers for
capacitors area of 0.1 mm2 (figure 5.38a) and 1 mm2 (figure 5.38b).
5.4 Gate-Oxide Integrity Evaluation
117
2
99.9
1
-1
70
50
30
20
-2
10
5
-3
2
-4
1
Cumulative Failure F(%)
0
ln[-ln(1-F)]
90
Ref.
14
2
1.5 x 10 at/cm
15
2
1 x 10 at/cm
Model
(a)
-5
-6
-7
10
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
0
10
1
10
10
2
2
Qbd (C/cm )
2
99.9
Ref.
14
2
1.5 x 10 at/cm
15
2
1 x 10 at/cm
Model
1
ln[-ln(1-F)]
50
-1
30
20
-2
10
-3
5
-4
2
Cumulative Failure F(%)
0
90
70
(b)
1
-5
-6
10
10
-5
10
-4
-3
10
10
-2
10
-1
10
0
10
1
10
2
2
Qbd (C/cm )
Fig. 5.38: Charge to breakdown distribution of various Sr contamination for 0.1
mm2 (a) and 1 mm2 area capacitors (b)
Table 5.3: Intrinsic and extrinsic breakdown parameters, as well as the fraction
1-p, as determined from the fit of the measured charge to breakdown of 1015
Sr/cm2 contamination.
1 mm2
1x1014
at/cm2
1x1015
at/cm2
0.958± 0.02 0.98± 0.02 0.97± 0.005 0.87± 0.01
10.8± 0.02 11.13± 0.01 10.93± 0.01 7.21 ± 0.02
0.83± 0.01
7.32 ± 0.01
0.80± 0.03
7.61 ± 0.03
4.9 ± 0.06
5.09 ± 0.03
5.03 ± 0.03
5.15 ± 0.09
5.15 ± 0.07
4.54± 0.12
0.83 ± 0.2
1.03 ± 0.17
0.88 ± 0.8
0.29 ± 0.04
0.32 ± 0.16
0.31 ± 0.39
0.12 ± 0.02
0.21 ± 0.01 0.4± 0.06
Parameter\area
Ref.
1-p
ηi (C/cm2)
βi
ηe (C/cm2)
βe
0.1 mm2
1x1014
at/cm2
1x1015
at/cm2
Ref.
0.27± 0.008 0.25± 0.008 0.22 ± 0.01
118
5 Electrical Characterization of Intentionally Contaminated Samples
The plot of defect density as function of charge to breakdown for different areas in
figure 5.39, shows that Sr contamination level as high as 1015 at/cm2 does not really
trigger an extrinsic breakdown. If one compares the extrinsic defect density of
reference wafers to the extrinsic defect density of Sr contaminated wafers, a distinct
effect or a clear defect-driven process does not appear for Sr contamination as high
as 1015 at/cm2.
10
5
10
4
10
3
10
2
10
1
10
0
-2
Defect density (cm )
2
10
-1
10
-2
10
Ref.-4mm
2
0.1 mm
2
1 mm
2
4 mm
2
16 mm
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
2
Qbd (C/cm )
Fig. 5.39 : Defect density of 1015 Sr/cm2 contamination as function of the
injected charge to breakdown for different areas.
The case of Bi is presented in figure 5.40a-b with the breakdown parameters listed in
Table 5.4. The general observation is that no change in oxide breakdown strength is
apparent and a distinct detrimental effect of Bi does not occur for contamination level
as high as 5 x 1014 at/cm2.
2
99.9
1
-1
70
50
30
20
-2
10
5
-3
2
-4
1
-5
-6
-7
10
-6
10
-5
10
10
-4
10
-3
10
2
-2
Qbd (C/cm )
10
-1
10
0
10
1
10
2
Cumulative Failure F(%)
0
ln[-ln(1-F)]
90
Ref.
14
2
1 x 10 at/cm
14
2
5 x 10 at/cm
Model
(a)
5.4 Gate-Oxide Integrity Evaluation
119
2
99.9
1
-1
70
50
30
20
-2
10
-3
5
-4
2
1
Cumulative Failure F(%)
0
ln[-ln(1-F)]
90
Ref.
14
2
1 x 10 at/cm
14
2
5 x 10 at/cm
Model
(b)
-5
-6
-7
10
-6
10
10
-5
10
-4
10
-3
-2
-1
10
10
10
0
10
1
2
10
2
Qbd (C/cm )
Fig. 5.40 : Charge to breakdown distribution of various Bi contamination for 0.1
mm2 (a) and 1 mm2 area capacitors (b)
Table 5.4: Intrinsic and extrinsic breakdown parameters, as well as the fraction
1-p, as determined from the fit of the measured charge to breakdown of 5x1014
Bi/cm2 contamination.
Parameter\area
Ref.
1-p
ηi (C/cm2)
βi
ηe (C/cm2)
βe
0.1 mm2
1x1014
at/cm2
14
5x10
at/cm2
Ref.
1 mm2
1x1014
at/cm2
5x1014
at/cm2
0.96± 0.02
10.8± 0.02
0.95± 0.02 0.96± 0.009 0.87± 0.01
10.83± 0.02 10.81± 0.01 7.16 ± 0.01
0.84± 0.01
7.01 ± 0.01
0.87± 0.02
7.21 ± 0.01
4.96 ± 0.06
5.12 ± 0.07
5.13 ± 0.04
5.15 ± 0.08
5.00 ± 0.03
5.00± 0.02
0.88 ± 0.2
0.63 ± 0.4
0.91 ± 0.5
0.20 ± 0.02
0.19 ± 0.09
0.11 ± 0.09
0.12 ± 0.01
0.15 ± 0.01 0.29± 0.03
0.28± 0.01
0.23± 0.01
0.37 ± 0.01
As in the case of Ba and Sr, the examination of defect density as function of the
injected charge in figure 5.41, demonstrates a unique area-independent extrinsic
breakdown mechanism, exactly the same as of the reference wafers.
It can be concluded from these results, in good agreement with the previous results
from the E-ramp method, that neither the intrinsic breakdown mode nor the extrinsic
mode are affected by Ba, Sr, or Bi contamination level as high as 4 x 1014 at/cm2.
5 Electrical Characterization of Intentionally Contaminated Samples
-2
Defect density (cm )
120
10
5
10
4
10
3
10
2
10
1
10
0
10
-1
10
-2
10
Ref.-4mm
2
0.1 mm
2
1 mm
2
4 mm
2
16 mm
-5
10
-4
2
10
-3
10
-2
10
-1
10
0
10
1
10
2
2
Qbd (C/cm )
Fig. 5.41: Defect density of 5 x 1014 Bi/cm2 contamination as function of the
injected charge to breakdown for different areas.
5.4.2.2 Iridium Contaminated MOS Structures
The surprising effect seen for Iridium contamination with E-Ramp method is also
confirmed with CCS method. For capacitors area of 0.1 mm2, only intrinsic failure
mechanism is apparent (if we neglect the two cases of 100 ppm annealed in N2) as
shown in figure 5.41a.
To render the predominance of intrinsic breakdown more visible, even for higher area
of 4 mm2, a Weibull plot is presented in figure 5-41b for different contamination
levels. In all cases, the Ir contaminated wafers exhibit no breakdown failure distinct
from the clean wafers. The general observation is that the Ir contaminated wafers
have an extrinsic branch not higher than the clean wafers followed by a unique
intrinsic breakdown. As listed in Table 5.5, the Ir contaminated wafers, break
intrinsically, and not distinctly from the reference wafers. While the effect when
annealing is performed in O2 atmosphere cannot be worst than annealing in N2
atmosphere, we present here the case of 1000 ppm concentration annealed in O2, for
the purpose to check the influence, if any.
5.4 Gate-Oxide Integrity Evaluation
121
2
99.9
Ref.
100 ppm, N2
1000 ppm, N2
1000 ppm, O2
Model
1
ln[-ln(1-F)]
-1
70
50
30
20
-2
10
-3
5
-4
2
Cumulative Failure F(%)
0
90
(a)
1
-5
10
-3
10
-2
10
-1
0
10
2
10
1
10
2
Qbd (C/cm )
2
99.9
Ref.
100ppm, N2
1000ppm, N2
1000ppm, O2
Model
1
ln[-ln(1-F)]
-1
70
50
30
20
-2
10
-3
5
-4
2
1
Cumulative Failure F(%)
0
90
(b)
-5
-6
-6
10
-5
10
-4
10
-3
10
-2
10
2
-1
10
0
10
1
10
Qbd (C/cm )
Fig. 5.41: Charge to breakdown distribution of various Ir contamination
annealed in N2 or O2, for 0.1 mm2 (a) and 4 mm2 area capacitors (b)
Table 5.5: Intrinsic and extrinsic breakdown parameters, as well as the fraction
1-p, as determined from the fit of the measured charge to breakdown of 6x1014
Ir/cm2 contamination for 4 mm2 capacitors area.
4 mm2
Parameter\area
Ref.
1-p
ηi (C/cm2)
βi
ηe (C/cm2)
βe
100 ppm in N2
( 6 x 1013 at/cm2)
1000 ppm in N2 1000 ppm in O2
( 6 x 1014 at/cm2) ( 8 x 1011 at/cm2)
0.85± 0.02
0.73± 0.001
0.93± 0.01
0.57± 0.001
0.89± 0.01
0.61± 0.001
0.89± 0.01
0.60± 0.001
4.76 ± 0.86
4.68 ± 0.06
4.32 ± 0.05
4.02 ± 0.04
0.24 ± 0.23
0.1 ± 0.08
0.1 ± 0.08
0.1 ± 0.06
0.28 ± 0.01
0.33 ± 0.03
0.28 ± 0.01
0.35 ± 0.01
122
5 Electrical Characterization of Intentionally Contaminated Samples
10
4
10
2
10
0
Ref.-4 mm
2
0.1 mm
2
1 mm
2
4 mm
2
16 mm
-2
Defect density (cm )
Evidence of Ir contamination to be harmless on oxide breakdown strength can be
seen in figure 5.42, where the plot of defect density as function of the injected charge
is presented for a contamination level of 6x1014 Ir/cm2. Here again, the case of 4 mm2
area reference wafers is shown for comparison. It can be seen in this figure that the
defect density of 4 mm2 area of clean wafers coincides exactly with the defect density
of 6x1014 at/cm2 Ir contaminated wafers. When normalizing all the distributions to a
capacitor area of 1 cm2 (that is the defect density plot), a unique extrinsic curve,
independently of the area, is obtained. This indicates that breakdown sites are
randomly distributed and not correlated with the Ir contamination, as concluded from
the comparison with defect density of reference wafers.
10
-2
10
-4
2
Ir-1000 ppm, N2
10
-4
10
-3
-2
10
10
-1
10
0
10
1
10
2
2
Qbd (C/cm )
Fig. 5.42: Defect density of 6 x 1014 Ir/cm2 contamination as function of the
injected charge to breakdown for different areas.
5.4.2.3 Platinum Contaminated MOS Structures
Pt was observed in the previous sections, to be gettered in the poly-Si, and does not
increase the leakage current of n+p diodes or enhance considerably the defect
density as concluded from E-ramp method. However, the results of constant current
stress charge to breakdown, presented in Weibull plots of charge to breakdown of Pt
contaminated wafers in figure 5.43, show an increase of the extrinsic breakdown part
with the increase of Pt concentration. While for 0.1 mm2, the reference wafers break
purely intrinsically, some breakdown events occur extrinsically with increasing Pt
concentration. The same observation is valid for 1 mm2 area capacitors. However,
the breakdown is not catastrophic in number, and the intrinsic breakdown is not
affected at all. Neither the 63% charge to breakdown (ηi) nor the slope (βi) decrease
if the wafers are contaminated with Pt concentration as high as 4x1014 at/cm2, as it
seen in figures 5.43 and listed in Table 5.6. However, the 63% charge to breakdown
(ηe) as well as the slope (βe) of the extrinsic part decrease with increasing the Pt
concentration. The annealing atmosphere is not seen to considerably alter the
breakdown properties of Pt contaminated MOS structures.
5.4 Gate-Oxide Integrity Evaluation
123
When plotting the defect density as a function of the charge to breakdown (figure
5.44a), it is observed that the defect density does not really fit the area.
Paradoxically, the defect density increases with decreasing area. However, and
when normalizing all the distribution to the capacitor perimeter, a unique extrinsic
curve, independent of the perimeter, is obtained as shown in figures 5.44b. This
indicates that the breakdown is related to the periphery and has the physical
meaning that the breakdown sites are not randomly distributed but located at the
periphery of the capacitors. This is the reason, why the defect density increases with
decreasing area.
2
99.9
Ref.
100 ppm, O2
100 ppm, N2
1000 ppm, O2
1000 ppm, N2
Model
1
ln[-ln(1-F)]
-1
70
50
30
20
-2
10
5
-3
2
-4
Cumulative Failure F(%)
0
90
(a)
1
-5
-6
10
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
2
Qbd (C/cm )
2
99.9
Ref.
100 ppm, O2
100 ppm, N2
1000 ppm, O2
1000 ppm, N2
Model
1
ln[-ln(1-F)]
-1
30
20
-2
10
5
-3
2
-4
1
Cumulative Failure F(%)
0
90
70
50
(b)
-5
-6
-7
10
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
2
Qbd (C/cm )
Fig. 5.43: Charge to breakdown distribution of various Pt contamination
annealed in N2 or O2, for 0.1 mm2 (a) and 1 mm2 area capacitors (b)
124
5 Electrical Characterization of Intentionally Contaminated Samples
Table 5.6: Intrinsic and extrinsic breakdown parameters, as well as the fraction
1-p, as determined from the fit of the measured charge to breakdown of
various Pt concentration annealed in N2 or O2. The capacitors area is 1 mm2.
Parameter\area
Ref.
1-p
ηi (C/cm2)
βi
ηe (C/cm2)
βe
Annealed in N2
100 ppm
1000 ppm
0.96± 0.006
7.92± 0.01
0.93± 0.01
7.94± 0.02
Annealed in O2
100 ppm
1000 ppm
0.84± 0.01
7.95± 0.02
0.95± 0.01
8.09 ± 0.02
0.81± 0.01
7.77 ± 0.01
4.6 ± 0.07
4.29 ± 0.05
4.71 ± 0.08
5.83± 0.1
0.77 ± 0.47
0.58 ± 0.4
0.44 ± 0.28
0.63 ± 0.6
0.33 ± 0.31
0.49 ± 0.05
0.29 ± 0.01
0.24± 0.009
0.38± 0.04
0.19 ± 0.008
10
4
10
3
10
2
10
1
10
0
-2
Defect Density (cm )
4.6 ± 0.04
10
(a)
2
0.1 mm
2
1 mm
2
4 mm
2
16 mm
-1
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
2
10
2
10
1
10
0
-1
Defect per lenght (cm )
Qbd (C/cm )
10
(b)
-1
2
10
-2
10
-3
10
0.1 mm
2
1 mm
2
4 mm
2
16 mm
-4
10
-3
10
-2
10
-1
2
10
0
10
1
10
2
Qbd (C/cm )
Fig. 5.44: Defect of 4 x 1014 Pt/cm2 contamination in function of the injected
charge to breakdown as normalized to the area (a) or to the perimeter (b) of
the capacitors.
5.4 Gate-Oxide Integrity Evaluation
125
The located defects at the periphery are not generated from the oxide over-etching at
the periphery because the reference wafers from the same lot proved that the defect
density fits very well the area. The plot of defect density as function of the charge to
breakdown of the reference wafers of this lot (withheld form Pt contamination) is
presented in figure 5.45. Clearly, the breakdown sites are area related and randomly
distributed. The reason why Pt creates defects at the periphery is clarified in the
following section.
4
10
2
0.1 mm
2
1 mm
2
4 mm
2
16 mm
3
-2
Defect Density (cm )
10
2
10
Reference
1
10
0
10
10
-1
10
-2
10
-4
10
-3
-2
10
-1
10
10
0
1
10
2
10
2
Qbd (C/cm )
Fig. 5.45: Defect density of the reference wafers as function of the injected
charge to breakdown for different areas.
5.4.3 Discussion of the Results
The results of E-ramp and CCS measurements presented above brought results
which in fact relaxed the concern of Ba, Sr, Bi. Considering the nature of Ba or Sr, as
one of the more critical contaminants with regard to gate oxide integrity, well
established from the work of Bearda, Mertens, and coworkers [Bea 99, Mer 99], the
slow diffusion of these elements in poly-silicon plays an important role to avoid their
diffusion to the gate oxide. At 800°C, Ba and Sr are located far away from the gate
oxide and do not reach this region. Bi, in contrast is not observed to diffuse at all at
800°C. This property renders Bi totally ineffective to cause any harmful effect, at least
in the BEOL. The example of Ba, Sr, and Bi clearly demonstrates that the
degradation strength depends on the ability of the contaminant to diffuse to the
already grown oxide.
For Ir and Pt, as transition metals, the case of oxide local thinning is unlikely to occur
under the tested conditions since the contamination is present much later after
several process steps and not prior to the gate oxide growth. Furthermore, we
showed that the poly-Si layer provide a beneficial effect to getter all Pt impurities or
at least to include the most concentration of Ir within, so that the Ir concentration that
126
5 Electrical Characterization of Intentionally Contaminated Samples
reaches the Si surface will not be sufficient to form precipitates and to cause a local
thinning of oxide. TEM analysis of unpatterned Si wafers contaminated with Ir and Pt
(section 4.3.3) showed that Pt or Ir precipitation does not occur easily like Cu, Ni, or
Fe. This is because the condition of presence of defects (for example oxygen
precipitation) necessary for the precipitation are not met in the type of wafer used in
this work. Graff pointed out that Pt precipitates heterogeneously, which means that
lattice defects or other impurities precipitates as nuclei are needed for formation of
platinum silicide [Gra 95]. Cross-sectional TEM and EDX analysis performed on
wafers with gate oxide and poly-Si, contaminated with Pt or Ir (4x1014 at/cm2 and
6x1014 at/cm2 respectively), confirmed the absence of Pt and Ir precipitation under
the tested conditions. As depicted in figures 5.46 and 5.47, we did not observed any
Pt or Ir precipitation, neither in the oxide, nor at the Si surface although the cooling
rate was sufficiently slow. Despite of the relatively high concentration, no structural
defects like staking faults or dislocation were clearly visible.
1
2
Poly-Si
3
4
Gate oxide
Si substrate
Point 2,3, or 4
Intensity (a.u.)
Intensity (a.u.)
Point 1
Energy (keV)
Energy (keV)
Fig 5.46: Cross-sectional TEM and EDX Analysis of structure with 300 nm
poly-Si on 7.5 nm gate oxide, contaminated with 4x1014 Pt/cm2 and annealed
in N2 atmosphere.
5.4 Gate-Oxide Integrity Evaluation
Poly-Si
127
Poly-Si
GOX
Si
Si
Point 2
Intensity (a.u.)
Intensity (a.u.)
Point 1
Energy (keV)
Energy (keV)
Fig 5.47: Cross-sectional TEM and EDX Analysis of structure with 300 nm
poly-Si on 7.5 nm gate oxide, contaminated with 6x1014 Ir/cm2 and annealed in
N2 atmosphere.
The micrographs show only a strong segregation of Ir on the surface, forming
particles of 100 nm size. Pt does not segregate as strongly as Ir, and the size of the
particles is 10 nm approximately. EDX measurements, done with a focused electron
beam on several points provide the following information:
1) The particles are constituted only of Ir or Pt (EDX of point 1 in figures)
2) No presence of Ir or Pt neither in the middle of the poly-Si nor in the oxide is
detectable (point 2, 3 or 4 in figures). This means that either the concentration is
very low that cannot be detected with EDX measurement or the impurities really
do not exist in the analyzed region. While the first explanation is valid for Ir, since
the measured concentration of Ir in the oxide was 3 x 1012 at/cm2, the second
explanation is true for Pt as concluded from the RBS measurement.
128
5 Electrical Characterization of Intentionally Contaminated Samples
TEM and EDX investigations are consistent with the literature since not much is
reported on Ir or Pt precipitation and the structure of their precipitates are still
unknown. The case of precipitation cannot be expected under the tested conditions.
The presence of the Ir in the oxide layer is totally ineffective. The Fowler-Nordheim
current is not increased, and the plot of logarithm I/E2 versus the reciprocal of the
electric field (figure 5.48) gives a good straight line with a slope of 3.4 eV, which is
very close to the oxide barrier height of 3.2 eV. This indicates that the tunneling
barrier height is not reduced and points out that no traps assisted tunneling are
generated from the Ir impurities present in the oxide [DeB 98]. C-V measurements
also demonstrate this passivity, since no shift in the flat band voltage is observed as
shown in figure 5.49. The explanation of this tendency could be the charge neutrality
of Ir in the oxide. The Ir impurities are not ionized but are present as neutral atoms in
the oxide. The ineffectiveness of Ir could also be an indication that Ir does not react
chemically with the silicon oxide to form a metal silicate or to decompose the oxide.
The inclusion of Ir in the oxide as iridium oxide embedded in the chemical oxide or
iridium silicate, as it is the case for Fe, is unlikely to happen, since Ir is not included
as the oxide grows, but diffuses into, through a poly-silicon layer. The reaction of Ir
with oxygen to form defects in the oxide occurs most likely during the oxide growth,
where the conditions are more favorable to form IrO2. The results of Ir confirm that
the oxide breakdown depends also on the chemical reaction of the contaminant in
the oxide.
-5
10
-7
I/E
2
10
-9
φb= 3.4 eV
10
-11
10
-13
10
0.075
0.100
0.125
0.150
-1
1/E (MV/cm)
Fig. 5.48 : Typical Fowler-Nordheim plot of 6 x1014 Ir/cm2 contaminated MOS
structures.
5.4 Gate-Oxide Integrity Evaluation
129
1.0
Forward
Backward
0.8
C/Cox
0.6
0.4
0.2
0.0
-3
-2
-1
0
1
2
Voltage (V)
Fig. 5.49: Typical C-V curve of MOS structures contaminated with 6x1014 Ir/cm2.
The observed effect of Pt at the periphery can be explained according to the model
presented in figure 5.50. The chemical patterning of the poly-electrodes leads to the
decomposition of the poly-silicon structure in the non-protected regions with the
photoresist and thus to the escape of the Pt atoms, which were trapped in these
regions. Direct deposition of Pt impurities on the gate oxide surface takes then place
on the denuded region from the poly-Si layer. Owing to its fast diffusion property,
even at 430°C, Pt diffuses into the gate oxide during the forming gas anneal that
follows the electrode patterning.
Trapped Pt
in the poly-Si
layer
Gate
oxide
Si
(a)
(b)
Fig. 5.50: Model of the Pt induced breakdown sites at the periphery; (a)
deposition of Pt on the surface after the electrodes patterning, (b) diffusion of
Pt into the gate oxide during the forming gas anneal.
130
5 Electrical Characterization of Intentionally Contaminated Samples
The diffusion of Pt into the oxide influences the oxide decomposition at the Si/SiO2
interface as established from the work of Liehr et al. [Lie 88], which explains the
effect seen at the periphery. The decomposition of the oxide at the Si/SiO2 interface
is consistent with the result of Deng et al., who measured the density of states using
the quasi-static C-V method and observed that Pt increases the density of states at
the interface Si/SiO2.
In further investigations of Pt effect on the gate oxide strength, C-V measurements
were performed at a frequency of 100 kHz. The results of the C-V measurements,
presented in figure 5.51, are consistent with the gettering of Pt in the poly-Si, since
no shift in flat band voltage was observed.
1.0
Forward
Backward
C/Cox
0.8
0.6
0.4
0.2
0.0
-3
-2
-1
0
Voltage (V)
1
2
10
-5
10
-7
10
-9
2
2
I/E (Acm /MV )
Fig. 5.51: Typical C-V curve of MOS structures contaminated with
4x1014 Pt/cm2.
2
φb=3.3 eV
10
-11
10
-13
0.07
0.08
0.09
0.10
0.11
0.12
-1
1/E (MV/cm)
Fig. 5.52: Typical Fowler-Nordheim plot of 4 x1014 Pt/cm2 contaminated MOS
structures.
5.4 Gate-Oxide Integrity Evaluation
131
This can be interpreted as an indication of a Pt-free oxide, under the capacitor area,
since it is well established from the work of Kato et al. [Kat 84] and Deng et al. [Den
95a] that the presence of Pt in the oxide causes an hysterisis in the C-V curve and
that Pt ions move easily in the oxide under the application of a voltage even at room
temperature. Furthermore, the examination of I-V curves of Pt contaminated MOS
structures, shows the usual oxide tunneling barrier of 3.2 eV, as it is concluded form
the slope of Fowler-Nordheim plot in figure 5.52.
6 Summary and Outlook
This thesis is aimed at contamination issues in integrating ferroelectric strontium
bismuth tantalate and high-k barium strontium titanate materials with noble metals
iridium/platinum as electrodes. To achieve this purpose, a comprehensive study of
the properties of barium, strontium, bismuth, iridium, and platinum in silicon was
necessary in addition to the assessment of the impact of these elements on the
device performance, reliability, and production yield.
6.1 Résumé of the Properties of the Contaminants
After annealing at high temperatures, most Ba and Sr atoms are dissolved in the
native oxide or included in the thermally grown oxide. This tendency prevents their
cross-contamination during annealing in N2 or O2 atmosphere. Whereas Bi
evaporates mainly if annealed in N2 and consequently leads to a critical crosscontamination, during oxidation Bi is included in the thermally grown oxide and is not
found in significant amounts on the facing surface of a neighboring, initially clean
wafer. In terms of cleaning, most Ba, Sr or Bi impurities are removed after a slight
etch of the oxide (native or thermal).
Another, beneficial property of Ba and Sr is that both are found to diffuse only over
distances of tens of nanometers after an anneal at high temperatures. They exhibit
low diffusivities in silicon and are found to belong to very slow diffusing elements. Bi
does not diffuse into silicon at temperatures of 800°C or below, and, therefore, is of
no concern in BEOL processing.
Ir diffusion into silicon is affected by the annealing atmosphere. Annealing in oxygen
atmosphere delays the diffusion of Ir, whereas if annealed in N2, Ir diffuses over
some ten microns at 800°C, which points out that Ir belongs to the moderately fast
diffusing elements at this temperature. Ir presents a critical cross-contamination
aspect during anneal in O2 or N2 atmosphere.
The annealing atmosphere affects the Pt properties only in the region near the
surface but not the Pt deep diffusion into the silicon. The concern with Pt is its very
fast diffusion property. After annealing at 800°C, Pt is found to have diffused through
the whole wafer, from one side to the opposite side of the wafer. This matter of
concern renders the integration of Pt even more complicated since a contamination
on the back-side, which can easily occur through the chuck in plasma processing for
example, can affect critically the performances of the devices at the front side.
The study of Pt properties showed the difficulty in detecting Pt using methods like
TXRF or VPD-TXRF. These methods, which are very successfully used to monitor
contamination, are, however, poorly suited for Pt. Pt in sub-monolayer range, if
133
6.2 Résumé of the Impact of the Contaminants
annealed in oxygen atmosphere cannot be easily detected on the wafer surface with
oxides thicker than 7 nm, or can be barely detected after oxide etching, although the
minority carrier lifetime is seriously affected.
Investigations on structural defects using TEM and local elemental analysis EDX
methods do not show any clear Ir or Pt precipitation in the form of silicide. It appears
that under the tested conditions, Ir and Pt remain rather dissolved in the silicon matrix
than precipitated. Therefore, the gate oxide thinning as cause of gate oxide integrity
degradation in real memory devices is rather unlikely because Ir and Pt precipitation,
in contrast to the Cu, Ni, and Fe, is difficult in crystal free from defects such as
dislocations, stacking faults, and oxygen precipitates.
While Pt is effectively gettered in the poly-silicon, Ba and Sr show a very slow
diffusion within the poly-silicon material and, therefore, cannot reach the already
grown gate oxide. Ir, however, cannot be effectively gettered in the poly-Si, and can
reach the active regions, which is a cause of concern.
6.2 Résumé of the Impact of the Contaminants
It was clearly demonstrated that Ba, Sr, and Bi do not degrade minority carrier
lifetime, so that BST or SBT dielectrics can be integrated in CMOS technologies
without major minority carrier lifetime concerns. Ir or Pt, on the other hand, have to
be carefully handled to avoid serious degradation of minority carrier lifetime even in
concentration range below 1011 at/cm2.
The effects of the contamination on the device properties were clearly demonstrated
by giving representative results of leakage current and gate oxide integrity in a
0.5 µm process technology. Ba, Sr, Bi, or Pt have no pronounced effect because of
the fabrication sequences. The phosphorus doped poly-silicon plug prevents Ba and
Sr from diffusing to the electrically active regions, or can totally getter the “poisoning”
Pt atoms. However, if Pt escapes from the gettering layers, it can critically affect the
reliability and product yield, even at low annealing temperatures of 430°C.
The most obvious risk of Ir contamination occurs when no diffusion barrier is used to
stop the diffusion of Ir to the active region, which results in increase of leakage
current. However, gate oxide breakdown characteristics of 7.5 nm oxides are not
affected by Ir contamination as high as 1012 at/cm2. Meanwhile, it cannot be
concluded that this is a general property of Ir, because the effect of higher
concentrations has not been examined (no available contamination source with
concentration higher than 1000 ppm). Several metals, which can degrade gate oxide,
have a pronounced effect only if their concentration is relatively high.
During this work, our expectation that the contamination issues will not be a blocking
point to the development of the ferroelectric memories, is confirmed. Evidence to
support this expectation is demonstrated from concrete results on an integrated
FeRAM module with SBT as ferroelectric layer.
Auger electron spectroscopy measurement of the device, in its final configuration
(including a diffusion barrier of TaN/Ti), indicates the absence of the above elements
in the active region of the transistor as shown in figure 6.1.
134
Intensity
6 Summary and Outlook
Sputter Time (min)
Pt
IrO2 Ir
Ti Poly-
TaN
SiO2/Si
Si
Fig. 6.1: Auger profile of a stacked cell ferroelectric memory showing the
effectiveness of a diffusion barrier.
2
99.9
Ln(-ln(1-F))
1
90
70
50
30
0
-1
-2
10
5
-3
-4
Cumulative Failure F(%)
Reference
Integrated capacitor
1
-5
10
-1
10
0
10
1
10
2
10
3
10
4
Time to breakdown (s)
Fig. 6.2: Cumulative Weibull plot of the reference wafers and wafers with
integrated ferroelectric capacitors. The measurements were performed at
8.25 V negative polarity, which corresponds to an electric field of 11MV/cm,
and at temperature of 150°C.
135
6.3 Future Work and General Conclusion
Reliability measurements investigated by constant voltage stress at wafer level
showed no deterioration of the gate oxide integrity after the processing of the
capacitor module. Time dependent dielectric breakdown measurements on wafers
with integrated capacitor module reveal no difference to the reference wafers from
the front-end of line, containing no capacitor module. Figure 6.2 shows the Weibull
plot of the reference wafers and the wafers with integrated capacitors.
6.3 Future Work and General Conclusion
This work is among the first of its kind to comprehensively examine the
contamination effects of elements commonly used in FeRAM technology. Several
aspects have been investigated but some of them are still open questions.
A contamination level of Ir in the gate oxide of about 1012 at/cm2 was found to have
no detrimental effect on GOI. The effect of higher concentrations has to be
examined. This requires to contaminate the test wafers with levels higher than
1015 at/cm2.
This work focused on the aspects in BEOL. Obviously, many areas of this research
can be extended to the FEOL:
•
Since it appears that the cleaning of Ba, Sr, or Bi based dielectric should not
be problematic, it is interesting to examine the effectiveness of the cleaning
of Ba, Sr or Bi contamination, that occurs prior to gate oxide for a complete
relaxation of Ba, Sr, and Bi contamination even in FEOL.
The critical concentration of Ir or Pt contamination prior to gate oxide growth,
which has a pronounced effect on GOI, is still not reported. It is necessary,
as a future work, to determine this threshold value.
Precipitation of transition metals at the interface Si/SiO2 has been thoroughly
investigated for metals such as Cu, Ni, and Fe but not for Pt and Ir. In this
work, the precipitation properties of Pt and Ir have been examined under
typical ferroelectric memory processing conditions but not investigated in
details. A full understanding of this property, which has a key technological
importance, needs further intensive studies.
•
•
It appears relatively certain from this work, that the risk of device processing with
ferroelectric and high-k capacitor dielectrics in future memories is manageable. The
dielectric films are even of no concern and the most feared contaminants Ir and Pt
can be mastered under the following precautions:
•
•
•
Use of an effective diffusion barrier to block the diffusion of Ir to the active
regions. This was the key solution for the successful implementation of Cu
in advanced interconnects, despite the fact that Cu has a higher
contamination risk than Ir because of its extremely high diffusivity, even at
low temperatures.
Need of a cap layer on the back-side of the wafer to prevent Pt diffusion to
the front-side.
Good cleaning strategy to avoid cross-contamination.
References
[Aha 97]
H. Aharoni, T. Ohmi, M. Massazumi Oka, A. Nakada, and Y. Tamai
J. Appl. Phys. 81, 1270 (1997)
[Avn 88] E. Avni and J. Shappir
J. Appl. Phys., 64, 743 (1988)
[Azi 76]
S. A. Azimov, M.S. Yunusov, B. V. Umarov,
Sov. Phys. Semicond. 10, 842 (1976)
[Azi 77]
S. A. Azimov, M.S. Yunusov, B. V. Umarov,
Sov. Phys. Semicond. 11, 979 (1977)
[Bac 84] G. Baccarani, M. Wordeman and R. Dennard
IEEE Trans. Elect. Dev., ED-31, 452 (1984)
[Bea 99] T. Bearda, S. de Gendt, L. Loewenstein, M. Knotter, P. Mertens and M.
Heyns
Fourth International Symposium on Ultra Clean Processing of Silicon
Surfaces, Scitec Publ. Ltd. Zuerich-Uetikon, Switzerland 1999, p.11
[Bec 73] J. D. Beck and R. Conradt
Sol. State Comm., 13, 93 (1973)
[Bei 99]
G. Beitel, H. wendt, E. Fritsch, V. Weinrich, M. Engelhardt, B. Hasler, T.
Röhr, R. Bergmann, U. Scheler, K.-H. Malek, N. Nagel, A.
Gschwandtner, W. Pamler, W. Hönlein, C. Dehm and C. Mazuré
Microelectronic Engineering 48, 299 (1999)
[Ben 75] A. Benninghoven
Surf. Sci., 53, 596 (1975)
[Ben 94] A. Benninghoven
Angew. Chem. Int. Ed. Engl., 33, 1023 (1994)
[Ben 98] V. Benda, M. Cernik, and D. Stepkova
Microelectronics J. 29, 695 (1998)
[Buc 96] D. A. Buchanan and S. H. Lo,
Presented at the Symposium on the Physics and Chemistry of SiO2 and
the Si-SiO2 Interface, Los Angels, 1996
[Buc 97] D. A. Buchanan and S. H. Lo
Microelectron. Eng. 36, 13 (1997)
[Buc 99] D. A. Buchanan
IBM J. Res. Develop., 43, 245 (1999)
[Cam 99] S. A. Campbell, H.-S. Kim, D. C. Gilmer, B. He, T. Ma, W. L. Gladfelter
IBM J. Res. Develop., 43, 383 (1999)
[Cha 95] S. Y. Cha, H. C. Lee, W. J. Lee, and H. G. Kim
Jpn. J. Appl. Phys., 34, 5220 (1995)
[Che 86] Chen I. C., S. Holland, K. K. Young, C. Chang and C. Hu
Appl. Phys. Lett., 49, 669 (1986)
[Cho 99] J.H. Choi, J.Y. Lee, Y.T. Kim
Appl. Phys. Lett., 74, 2933 (1999)
[Col 86]
E.G. Colas, E.R. Weber and R. Hull in Defects in Semicondcutors, Edited
by H. J. von Bardeleben, Materials Science Forum 10-12, 881 (1986)
137
[DeB 98]
[Deg 98a]
[Deg 98b]
[Deh 99]
[Den 95]
[Den 95a]
[Den 95b]
[DeW 00]
[Dor 00]
[Dum 94]
[Dun 86 ]
[Ent 89]
[Fab 95]
[Fal 85]
[Fal 98]
[Fan 90]
[Fan 91]
[Fij 93]
[Föl 91]
[Fos 83]
[Fra 56 ]
[Fra 84]
References
J. De Blauwe, J. Van Houdt, D. Wellekens, G. Groeseneken, H. E. Maes
IEEE Trans. Electron Devices, 45, 1745 (1998)
R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, P.
Roussel, and H. E. Maes
IEEE Trans. Electron Devices, 45, 904 (1998)
R. Degraeve, J. L. Ogier, P. Roussel, and H. E. Maes
IEEE Trans. Electron Devices, 45, 472 (1998)
C. Dehm, W. Hartner, G. Schindler, R. Bergmann, B. Hasler, I. Kasko, M.
Kastner, M. Schiele, V. Weinrich, and C. Mazuré
Integrated Ferroelectrics 26, 197 (1999)
B. Deng and H. Kuwano
Jpn. J. Appl. Phys., 34, 4587 (1995)
B. Deng, C. Shu and H. Kuwano
Jpn. J. Appl. Phys., 34, 2969 (1995)
Deng B., C. Shu and H. Kuwano
Jpn. J. Appl. Phys., 34, Part2, L879 (1995)
H. De Witte, S. De Gendt, M. Dougla, T. Conard, K. Kenis, P. W.
Mertens, W. Vandervorst, and R. Gijbels
J. Electrochem. Soc., 147, 1915 (2000)
D. Dornisch, G. Li, and M. Brongo
Sol.-State Technol. 137 (May 2000).
D. J. Dumin, J. R. Maddux, R. S. Scott, R. Subramoniam
IEEE Trans. Electron. Devices, 41, 1570 (1994)
S.T. Dunham, J. D. Plummer
J. Appl. Phys., 59, 2541 (1986)
Y. Enta, T. Kinoshita, S. Suzuki, and S. Kono
Phys. Rev., B 39, 1125 (1989)
L. Fabry, S. Pahlke and L. Kotz in ALTECH 95 : „Analytical Techniques
for Semiconductors Materials and Process Characterization II“, The
Electrochem. Soc., PV 95-30 (1995), p. 217, Pennington, N.J.
R. Falster
Appl. Phys. Lett., 46, 737 (1985)
R. Falster, G. Borionetti in “Recombination Lifetime Measurements in
Silicon” D.C. Gupta, F. R. Bacher, and W. M. Hughes, Edited by
American Society for Testing and Materials, 226 (1998)
W. C. Fan, A. Mesarwi, and A. Ignatiev
J. Vac. Sci. Technol., A 8, 4017 (1990)
W. C. Fan and A. Ignatiev
Surf. Sci 253, 297 (1991)
C. Fijihira, M. Moron, H. Hashizume and Friedt
Jpn. J. Apl. Phys., 32, L1362 (1993)
H. Föll
Appl. Phys. A, 53, 8 (1991)
J. G. Fossum, R. P. Mertens, D. S. Lee and J. F. Nijs
Sol. State Elect., 26, 569 (1983)
F. C. Frank, D. Turnbull
Phys. Rev., 104, 617 (1956)
W. Frank, U. Gösele, H. Mehrer and A. Seeger
In ”Diffusion in Cystalline Solids”, G.E. Murch and A. Nowick, eds. NewYork, Academic Press, p. 31 (1984)
References
[Fut 98]
138
T. Futatsuki
In Ultra Clean Surface Processing of Silicon Wafers, Ed. by T. Hattori,
Springer-Verlag, Berlin 1998, p. 57
[Gös 80] U. Gösele, W. Frank, A. Seeger
Appl. Phys., 23, 361 (1980)
[Gös 88] U. Gösele
Annual Review of Materials Science 18, 257 (1988)
[Gra 95] K. Graff in “Metal Impurities in Silicon-Device Fabrication”
Springer-Verlag Berlin 1995
[Gro 66] A. S. Grove and D. J. Fitzgerald
Solid State Electron. 9, 783 (1966)
[Gro 99] G. Groesenken, R. Degraeve and J. Wauters
European Semiconductors, 21, 22 (1999)
[Hal 52]
Hall R. N.
Phys. Rev., 87, 387 (1952)
[Hay 92] Y. Hayamizu, S. Ushio, T. Takenaka
In Defect Engineering in Semiconductor Growth, Processing and Device
Technology, ed. by S. Ashok, J. Chevallier, K. Sumino, E. Weber (Mater.
Res. Soc., Pittsburg 1992) p. 1005
[Hen 95] W. B. Henly, L. Jastrzebski and N. F. Haddad
J. Non-Cryst. Solids, 185, 134 (1995)
[Hin 98]
F. Hintermaier, B. Hendrix, D. Desrochers, J. Roeder, C. Dehm, E.
Fritsch, W. Hönlein, C. Mazuré, N. Nagel, P. Thwaite, H. Wendt, T. H.
Baum, P. van Buskirk, M. Schumacher, M. Grossmann, O. Lohse and R.
Waser
VLSI Technological Digest 1998, p 56
[Hol 95]
B. Holm and K. B. Nielsen
J. Appl. Phys. 78, 5970 (1995)
[Hom 84] Y. Homma, Y. Ishii, and M. Oshima
Mass spectroscopy 32, 345 (1984)
[Hon 85] K. Honda, A. Ohsawa, and N. Toyokura
Appl. Phys. Lett. 46, 582 (1985)
[Hon 94] S. Hongo, K. Ojima, S. Taniguchi, T. Urano and T. Kanaji
Appl. Surf. Sci. 82/83, 537 (1994)
[Hor 97] T. Hori
”Gate Dielectrics and MOS ULSIs”. Edt. I.P. Kaminov, W. Engl, and T.
Sugano. Springer-Verlag Berlin 1997
[Hou 88] M. Hourai, T. Naridomi, Y. Oka, K. Murakami, S. Sumita, N. Fujino, and
T. Shiraiwa
Jpn. J. Appl. Phys., 27, L2361 (1988)
[Hou 89] M. Hourai, K. Murakami, T. Shigematsu, N. Fujino and T. Shiraiwa
Jpn. J. Appl. Phys., 28, 2413 (1989)
[Hu 74]
S.M. Hu
J. Appl. Phys., 45, 1567 (1974)
[Hu 99]
X. Hu, C.A. Peterson, D. Sarid, Z. Yu, J. Wang, D.S. Marshall, R.
Droopad, J.A. Hallmark and W. J. Ooms
Surf. Sci 426, 69 (1999)
[Ish 89]
Y. Ishikawa, K. Yazaki and I. Nakamichi
Jpn. J. Appl. Phys., 28, 1272 (1989)
[Jac 97]
M. Jacob, P. Pichler, H. Ryssel, R. Fasler
J. Appl. Phys., 82, 182 (1997)
139
[Jeo 97]
References
Y.-C. Jeon, J.-M. Seon, J.-H Joo, K.-Y Oh, J.-S Roh, J.-J. Kim and D.-S
Kim
Integrated Ferroelectrics, 17, 489 (1997)
[Jeo 98] Y. Jeon, B.H. Lee, k. Zawadzki, W.-J. Qi, J.C. Lee
Rapid thermal and Integrated Processing VII Symposium, Mater. Res.
Soc., Ed. M.C. Ozturk, F. Roozeboom, P.J. Timans, S.H. Pas
San Francisco, CA, USA, 13-15 April 1998, p. 193-198
[Kat 84]
H. Kato, S. Mori, and H. Kuwano
J. Appl. Phys., 56, 1160 (1984)
[Kit 91]
M. Kittler, J. Lärz, W. Seifert, M. Seibt, W. Schröter
Appl. Phys. Lett. 58, 911 (1991)
[Klo 97]
R. Klockenkämper
in Chemical analysis. Edited by J. D. Winefordner, volume 140, WileyInterscience Publication 1997
[Kol 00]
B.O. Kolbesen
Private communication, September 2000
[Kom 99] M. Komai, M. Sasaki, R. Ozawa and S. Yamamoto
Appl. Surf. Sci., 146, 158 (1999)
[Kot 99]
D. E. Kotecki, J. D. Baniecki, H. Shen, R. B. Laibowitz, K. L. Saenger, J.
J. Lian, T. M. Shaw, S. D. Athavale, C. Cabral, Jr., P. R. Duncombe, M.
Gutsche, G. Kunkel, Y.-J. Park, Y.-Y. Wang, R. Wise
IBM J. Res. Develop., 43, 367 (1999)
[Kwo 87] Y. K. Kwon, T. Ishikawa, and H. Kuwano
J. Appl. Phys. 61, 1055 (1987)
[Lag 92] J. Lagowski, P. Edelman, M. Dexter, and W. Henly
Semicond. Sci. Technol. 7, A185 (1992)
[Lag 98] J. Lagowski, P. Edelman, and V. Faifer
In Recombination Lifetime measurement in Silicon, ASTM STP 1340,
ed. By D.C. Gupta, F.R. Bacher, and W.M. Hughes
American Society for Testing and Materials 1998, p.125
[Lan 74] D. V. Lang
J. Appl. Phys., 45, 3023 (1974)
[Leh 88] V. Lehmann and H. Föll
J. Electrochem. Soc., 135, 2831 (1988)
[Lie 88]
M. Liehr, H. Dallaporta, J.E. Lewis
Appl. Phys. Lett., 53, 589 (1988)
[Lis 75]
K.P. Lisiak, A.G. Milnes
J. Appl. Phys. 46, 5229 (1975)
[Lo 81]
M. Lo, J. Skalnik, P. Ordung
J. Electrochem. Soc., 128, 1569 (1981)
[Lo 97]
S.-H. Lo, D. A. Buchanan, Y. Taur and W. Wang
IEEE Electron Device Lett., 18, 209 (1997)
[Loe 98] L. M. Loewenstein and P. W. Mertens
J. Electrochem. Soc., 145, 2841 (1998)
[Loe 99] L. M. Loewenstein, F. Charpin, and P. W. Mertens
J. Electrochem. Soc., 146, 719 (1999)
[Low 80] J.E. Lowther
J. Phys. C 13, 3665, 3681 (1980)
[M´sa 94] H. M´saad, J. Michel, J.J. Lappe, L.C. Kimerling
AIP Conf. Proc. 306, 471 (1994)
References
[Man 86]
140
S. Mantovani, F. Nava, C. Nobili, G. Ottaviani
Phys. Rev., B 33, 5536 (1986)
[Mar 68] O. J. Marsh, R. Baron, G. A. Shifrin, and J. W. Mayer
Appl. Phys. Lett., 13, 199 (1968)
[Mar 98] A. Martin, P. O’sullivan and A. Mathewson
Microeletron. Reliab., 38, 37 (1998)
[Mas 74] J. Maserjian
J. Vac. Sci. Technol., 11, 996 (1974)
[Mas 82] J. Maserjian and N. Zamani
J. Vac. Sci. Technol., 20, 743 (1982)
[Mer 99] P.W. Mertens, T. Bearda, L.M. Loewenstein, A.R. Martin, W. Hub, B.O.
Kolbesen, I. Teerlinck, R. Vos, M. Baeyens, S. De Gent, K. Kenis and
M.M. Heyns in Defects in Silicon III, T. Abe, M. Bullis et al. (eds.) PV 991, The Electrochem. Soc. Symp. Ser., Pennington, N.J. 1999, p. 401
[Mes 90] A. Mesarwi, W.C. Fan, and A. Ignatiev
J. Appl. Phys., 68, 3609 (1990)
[Met 97] S. Metz, G. Kilian, G. Mainka, C. Angelkort, A. Fester and B.O. Kolbesen
The Electrochemical Society Symposium. Silicon Cleaning Technology,
Paris 1997, p. 458
[Miy 92]
M. Miyashita, T. Tusga, K. Makihara and T. Ohmi
J. Electrochem. Soc., 139, 2133 (1992)
[Miy 97]
M. Miyazaki, S. Miyazaki, T. Kitamura and Y. Yanase
Jpn. J. Apl. Phys., 36, 6187 (1997)
[Mom 94] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito,
and H. Iwai, IEDM Tech. Dig., 593 (1994).
[Mör 00] M. Mört, G. Schindler, W. Hartner, I. Kasko, M. Kastner, T. Mikolajick, C.
Dehm and R. Waser
Integrated Ferroelectrics, 30, 235 (2000)
[Mur 86] F. Murray, R. Carin, and P. Bogdanski
J. Appl. Phys., 60, 3592 (1986)
[Nak 94] T. Nakamura, Y. Nakao, A. Kamisawa, H. Takasu
Jpn. J. Appl. Phys., 33, 5207 (1994)
[Nar 88] K. Naruke, S. Taguchi and M. Wada
IEDM Tech. Dig. 1988, p. 424
[Nar 99] S. Narayan, V. Joshi, L. McMillan and C. Paz de Araujo
Integrated Ferroelectrics, 25, 169 (1999)
[Nig 98]
T. Nigam, R. Degraeve, G. Groeseneken, M. Heyns, and H. Maes
IEEE98CH36173, 36th Annual International Reliability Physics
Symposium, Reno, Nevada, p. 62 (1998)
[Obe 00] S. Obeidi and N. A. Stolwijk
Presented at the Int. Conf. on Diffusion in Materials (DIMAT 2000)
Paris 17-22, 2000
[Oel 86]
E. M. Oellig, and R. Miranda
Surf. Sci. 77, 947 (1986)
[Ogi 95]
J. L. Ogier, R. Degraeve, P. Roussel, G. Groeseneken and H. E. Maes
Proceedings of the European Solid State Device Research Conference
(ESSDERC), 1995
[Ogu 97] S. Ogushi, S. Sadamitsu, K. Marsden,Y. Koike and M. Sano
Jpn. J. Appl. Phys. 36, 6601 (1997)
[Ohm 92] T. Ohmi, T. Imaoka, I. Sugiyama, and T. Kezuka
J. Electrochem. Soc., 139, 3317 (1992)
141
[Ohs 84]
References
A. Ohsawa, K. Honda, N. Toyokura
J. Electrochem. Soc., 131, 2964 (1984)
[Oli 88]
P. Olivo, T. N. Nguyen and B. Riccò
IEEE Trans. Electron Devices, 35, 2259 (1988)
[Pic 72]
S. T. Picraux, W. L. Brown, and M. Gibson
Phys. Rev. B 6, 1382 (1972)
[Pol 88]
M.L. Polignano, G. F. Cerofolini, H. Bender, and C. Claeys
J. Appl. Phys., 64, 869 (1988)
[Ram 99] D. A. Ramappa and W. B. Henley
J. Electrochem. Soc., 146 , 2258 (1999)
[Rao 74] C.N.R. Rao and G.V. Subba Rao
in Transition Metal Oxides, (National Standard Reference Data System,
National Bureau of Standards 49, June 1974, p. 103 and p. 127
[Sac 97a] J.-U Sachse, E. Ö. Sveinbjörnsson, W. Jost, and J. Weber
Appl. Phys. Lett. 70, 1584 (1997)
[Sac 97b] J.-U. Sachse, E. Ö. Sveinbjörnsson, W. Jost, and J. Weber
Phys. Rev. B 55, 16176 (1997)
[San 91] M. Sano and N. Fujino
Ultra Clean Technol. 3, 10 (1991)
[Sch 94] K. F. Schuegraf and C. Hu
J. Appl. Phys., 76, 3695 (1994)
[Sch 99] D.C. Schmidt, B. G. Svensson, S. Godey, E. Ntsoenzok, J.F. Barbot
and C. Blanchard
Appl. Phys. Lett. 74, 3329 (1999)
[Sea 98] M.R. Seacrist
In Recombination Lifetime measurement in Silicon, ASTM STP 1340,
ed. By D.C. Gupta, F.R. Bacher, and W.M. Hughes
American Society for Testing and Materials 1998, p.318
[Shi 90]
T. Shimono, M. Morita, Y. Muramatsu and M. Tsuji
Proceeding of the 8th Workshop on ULSI Ultra Clean Technology, p. 59
(1990)
[Shi 99]
Y. Shimada, K. Arita, E. Fuji, T. Nasu, Y. Nagano, A. Noma, Y. Izutsu, K.
Nakao, Tanaka, T. Yamada, Y. Uemoto, K. Asari, G. Nakane, A. Inoue,
T. Sumi, T. Nakakuma, S. Chaya, H. Hirano, Y. Judai, Y. Sasai, T. Oisuki
Integrated Ferroelectrics, 27, 291 (1999)
[Shi 99b] K. Shiga, J. Komori, M. Katsumata, A. Teramoto, Y. Mashiko
IEICE Trans. Electron., E82-C, 589 (1999)
[Sho 52] W. Shockley and T. Read
Phys. Rev., 87, 835 (1952)
[Sma 98] R. J. Small, M. L. Peterson and A. Robles
Micro-contamination, p. 61, Junuary 1998
[Son 98] K.A. Son, A.Y. Mao, Y.M. Sun. B.Y. Kim,F. Liu, A. Kamath, J.M. White,
D.L. Kwong, D.AA. Roberts, and R.N. Vritis
Appl. Phys. Lett. 72, 1187 (1998)
[Spa 86] D. Sparks, R. Chapman, N. Alvi
Appl. Phys. Lett., 49, 525 (1986)
[Spr 93]
A.B Sproul and M.A. Green
J. Appl. Phys. 73, 1214 (1993)
[Sta 98]
J.H. Stathis and D.J. Dimaria
IEDM Tech. Dig., p. 167 (1998)
References
[Sug 86]
142
H. Suga
J. Jpn. Assoc. Cryst. Growth, 13, 173 (1986)
[Sun 90] J. Suné, I. Plancencia, N. Barniol, E. Farré, F. Martin and X. Aymerich
Thin Solid films, 185, 347 (1990)
[Tak 94] M. Takiyama, S. Ohtsuka, S. Hayashi, and M. Tachimori
Extended Abstracts of the 7th International Symposium on Silicon
Material Science and Technology, p. 346, San Francisco (1994)
[The 85] M.J.J. Theunissen and F.J. List
Solid-State Electron. 28, 417 (1985)
[Tre 01]
R. Treichler
“Analytiktag von SIEMENS CT MM7”
Munich, February 07, 2001
[Tru 60]
F. Trumbore
Bell Syst. Tech. J. 39, 205 (1960)
[Tsa 90] B. Y. Tsaur, C. K. Chen, and B. A. Nechay
IEEE Electron Device Lett. 11, 415 (1990)
[Tsu 90] N. Tsutiya, M. Tanaka, M. Kageyama, A. Kubota and Y. Matsushita
Extended Abstracts of the 22nd International Conference on Solid State
Devices and Materials, P. 1131 (1990)
[Ura 96] T. Urano, K. Tamiya, K. Ojima, S. Hongo, T. Kanaji
Surf. Sci 357-358, 459 (1996)
[Wat 96] K. Watanabe
Semicond. Sci. Technol., 11, 1713 (1996)
[Wei 92a] P.J.W. Weijs, J.C. Fuggle and P.A.M. van der Heide
Surf. Sci. 260, 97 (1992)
[Wei 92b] P.J.W. Weijs, J.F. van Acker, J.C. Fuggle, P.A.M. van der Heide, H.
Haak and K. Horn
Surf. Sci. 260, 102 (1992)
[Wen 84] D. E. Wendell, R. M. Swanson
J. Appl. Phys., 56, 1744 (1984)
[Wen 89] H. Wendt, H. Cerva, V. Lehmann and W. Pamler
J. Appl. Phys. 65, 2402 (1989)
[Woo 62] H. H. Woodbbury, and G. W. Ludwig
Phys. Rev., 126, 466 (1962)
[Yab 86] E. Yablonovitch, D.L. Allara, C.C. Chang, T. Gmitter, T.B. Bright
Phys. Rev. Lett. 57, 249 (1986)
[Yam 73] K. Yamasaki, M. Yoshida, and T. Sugano
Jpn. J. Appl. Phys. 18, 113 (1973)
[Yam 95] S. Yamamichi, Y. Muramatsu, P.-Y. Lesaicherre and H. Ono
Jpn. J. Appl. Phys. 34, 5188 (1995)
[Yos 96] T. Yoshida and Y. Kitagawa,
Electrochem. Soc. Proc., 96-13, 455 (1996)
[Zim 92] H. Zimmermann, H. Ryssel
Appl. Phy., A 55, 121 (1992)
List of Symbols and Abbreviations
A
α
AFM
Al
APCVD
Au
BHF
BL
BPC
BPSG
β
C
°C
CCS
Cl
CMOS
Cu
CV
CVD
CZ
Dit
DLTS
dox
DRAM
DSE
E
eEa
Ec
EDX
EEPROM
Ef
Eg
Elymat
ε0
εr
ET
Ev
eV
F
φB
FeRAM
FPC
GOI
Ampere 1A=1C/s, Area
Absorption coefficient
Atomic Force Microscopy
Aluminum
Atmospheric Pressure Chemical Vapor Deposition
Gold
Buffered Hydrofluoric acid
BitLine
Backside PhotoCurrent
Borophosphosilicate glass
Slope of Weibull distribution
Coulomb =unit of electric charge
Celsius
Constant Current Stress
Chlorine
Complementary Metal Oxide Semiconductor
Copper
Capacitance-Voltage
Chemical Vapor Deposition
Czochralski
Density of states at the interface
Deep Level Transient Spectroscopy
Oxide thickness
Dynamic Random Access Memory
Droplet Scan Etch
Electric field
Electron
Activation energy
Energy of conduction band edge
Energy Dispersive X-Ray
Electrically Erasable Programmable Read Only Memory
Fermi level
Bandgap energy of silicon, Eg=1.12 eV at 300K
Electrolytic Metal Tracer
Permittivity in vacuum ε0=8.85 x 10-12 F/m
Dielectric constant
Trap level
Energy of valence band edge
Electron volt 1 eV=1.602 x 10-19 J
Farad 1F=1C/V
Barrier height at the interface
Ferroelectric Random Access Memory
Frontside PhotoCurrent
Gate Oxide Integrity
144
H
h
HF
Hf
Hz
I
IC
I-E
IR
J
J
K
K
k
λ
LOCOS
LPCVD
LSI
µn
µp
ML
MOCVD
MOD
MOS
MOSFET
n
N
Na
ni
P
p
Pb
Poly-Si
ppm
QBD
RBS
rpm
σ
SEM
Si
SIMS
SiO2
SRAM
t
T
τ
TDDB
TEM
TEOS
ToF-SIMS
TXRF
List of Symbols and Abbreviations
Hydrogen
Planck constant h=6.62 x 10-34 Js
Hydrofluoric acid
Hafnium
Herz, unit of frequency
Current
Integrated Circuit
Current-Electric field
Infrared
Current density
Joule 1J=1N.1m
Kelvin
Potassium
Boltzmann constant = 1.38 x 10-23 J/K
Wavelength
LOCal Oxidation of Silicon
Low Pressure Chemical Vapor Deposition
Large Scale Integration
Electron mobility
Hole mobility
Mono-layer
Metal-Organic Chemical Vapor Deposition
Metal-Organic Deposition
Metal Oxide Semiconductor
Metal Oxide Semiconductor Field Effect Transistor
Electron concentration
Nitogen
Sodium
Intrinsic carrier concentration
Phosphorus
Hole concentration
Lead
Poly-silicon
Parts per million
Charge to breakdown
Rutherford Back-scattering Spectroscopy
Revolutions per minute
Capture cross section
Scanning Electron Microscopy
Silicon
Secondary Ion Mass Spectroscopy
Silicon dioxide
Static Random Access Memory
Time
Temperature
Minority carrier recombination lifetime
Time Dependent Dielectric Breakdown
Transmission Electron Microscopy
Tetraethoxysilane
Time of Flight Secondary Ion Mass Spectroscopy
Total Reflection X-Ray Fluorescence
List of Symbols and Abbreviations
Vox
VPD
VPD-AAS
VPD-ICPMS
W
WL
Z
Voltage drop over gate oxide
Vapor Phase Decomposition
Vapor Phase Decomposition-Atomic Absorption Spectroscopy
VPD-Inductively Coupled Plasma Mass Spectrometry
Space charge region width
WordLine
Atomic number
145
Curriculum Vitae
1. Civil Status
Name:
Date of birth:
Place of birth:
Nationality:
Marital status:
Hocine Boubekeur
14.05.1967
Tlemcen
Algerian
Single
2. Education
1973-1982
1982-1985
1985-1989
1989-1993
Primary and secondary school in Tlemcen
Upper secondary school (Baccalaureate in Mathematics)
Higher Education Diploma, Physics major from university of Tlemcen
Master of Science in Technology of Semiconductor Devices from
Center of Development of Advanced Technologies, Algiers
3. Employment
07.1993-10.1994
11.1994- 09.1997
10.1998- 03.2002
Attached researcher at Unit of Development of Silicon Technology,
Algiers
Teacher at University of Tlemcen/ Institute of Physics
Research Associate at Infineon Technologies, Memory Products,
Munich