ECE 6450 Introduction to Microelectronics Technology

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ECE 6450 Introduction to Microelectronics Technology Exam 1 September 26,2014 Dr. W. Alan Doolittle
Print your name clearly: Instructions:
Read all the problems carefully and thoroughly before you begin working. DO NOT
SEPARATE ANY PAGES OF THIS EXAM. You are allowed to use 1 sheet of notes (l page
front and back) as well as a calculator. There are 100 total points. Observe the point value of
each problem and allocate your time accordingly. SHOW ALL WORK ON THE PROVIDED
SHEETS AND CIRCLE YOUR FINAL ANSWER WITH THE PROPER UNITS
INDICATED. Write legibly. No work should be done on any other paper. If! cannot read it, it
will be considered to be a wrong answer. Do all work on the paper provided. Tum in all scratch
paper, even if it did not lead to an answer. Report any and all ethics violations to the instructor.
Good luck!
Sign your name on ONE of the two following cases:
I did not observe any ethical violations during this exam:
I observed an ethical violation during this exam:
Problem 1. (20 points total in 4, 5 point parts):
True/False and Multiple Choice and short answer/calculation:
a.) Based on the periodic table (see attached table) which of the following are true (one or
m~swers possible)?
c!yC will have a larger bandgap than Si 2.) CdTe will have a smaller bandgap than HgTe 3.) Cd2.2Mno.sS is a real semiconductor 4.) All of the above 5.) None of the above 6.) I wish I had gone to Clemson instead of Ga Tech. b.) Which of the following defects are considered planar (2D) defects (may have more than
one answer .... or not)? 1.) Vacancies 2.) Interstitials Dislocations .) Stacking faults .
ct.t
A~recipitates
&rain Boundaries
.
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c.) Given the diffusion profiles obtained below for the same temperature and identical dose
in all cases, which of the following are true (may have more than one answer ... or not)?
This is a pre-deposition diffusion.
1~ """"':---.~ - - , - - - - r - - - ,
. his is a drive in diffusion.
.). he area under each of the three
1'-' curves is the same. 4.) For the 0.20 urn characteristic diffusion length case, it was performed for a shorter time than the 0.15 urn case. @hiS is a Gaussian shaped profile.
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d.) True o@(Circlethe correct answer)
The present «22 nm node) Intel process uses exotic materials for the gate dielectrics
because the capacitance per unit area is greatly increased compared to what is possible
with thin Si02 • (Hint: consider the effective oxide thickness comparison, EDT, of the
alternative materials).
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Problem 2. (20 points total): Name and describe the process that produces silicon with the least concentrations of impurities like oxygen, carbon, and various undesirable metals. For full credit, keep your description to 4 sentences or less and feel free to draw diagrams to furthur explain your answer. b06 k
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je?Lf,lfi:<Jh, n"ie 5 Problem 3. (60 points total):
You are about to make your first MOSFET. This question makes a MOSFET in several steps. Assumptions: Assume no lateral oxidation nor diffusion occurs (I.E. consider only the 1 dimensional case), the wet oxide parameters are valid for all regions, regardless of initial conditions, and the porosity and density of wet and dry oxides are the same. To answer this question you must know which oxide, wet or dry is of higher quality. At 1000 degrees C: A=O.l65 )lm, B=0.0117 )lffi2/hr and t=O.3 7 hr for dry oxides A=0.226 )lm, B=0.287 )lm2/hr for wet oxides. At 1200 degrees C: A=0.040 )lm, B=0.045 )lm2/hr and t=0.027 hr for dry oxides A=0.05 )lm, B=0.720 )lm2/hr for wet oxides. Note: erfc(x)=l-erf(x), erf(O) =0, erf(oo)=l
~~~gstrom
A.
gate oxide is to be
grown and should be of the highest
possible electrical quality. What time at
1000 degrees C is required?
300 ASi0 2
Si wafer
-c
('()11-5)
B.) A 1700 angstrom thick polysilicon Gate metal is deposited and patterned which will act as a
subsequent mask for the later diffusions and oxidation steps. Openings in the oxide are also
created for the source and drain regions. Thus, the starting configuration for part (B) is as shown
in the figure below. Phosphorous (P) is first deposited on a p-type silicon wafer uniformly boron
1700 A"
poly-Si
a
300 A" Si0 2
300 A" Si0 2
300 A Si0 2
Si wafer
1,"""___-...IH.....-_-..."H"""-'"""W"--...II ,'---------',
'....._ _ _- . . . 1
Y
Field
Y
Source
Y
Gate
Region
,
Drain
Region
Y
Field Region
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);.-e('met;mr'tlt;.HiMittusing Phosphine (PH3) at 900 degrees C where the
solubility ofP In Silicon i 5xl02o cm-3. ssuming a neutral vacancy controlled diffusion with
Do=3.9 cm2/sec and Ea=3.
, w at is the time required to achieve a dose of lxlO 15
2
atoms/cm ? Note this is approximately a complete single atomic layer of Phosphorous on t~~.1
surface.
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C.)
is then introduced to the wafer, and simultaneously the phosphorous is driven
into the wafer at 1200 degrees C, how much time is required to achieve a final junction depth of
OrJv'e 1.. . . @.. J100C'G' 0.1 urn?
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What IS the thlckness of the oXlde(~bovejthe Source and Dram regIOns (assume the a'oped
oxide grows at the same rate as undoped oxides on Si)? .n.)
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E.) How much of ilie wafer w~ consumed (t~~;s~
J
~mcL; ~:~tJ
G.) Draw the final cross·sectional view (i.e. similar to the above figure) of the resulting structure
clearly showing the oxide-silicon interfaces.
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