Class 14: Timing and Delays
Topics:
1. Intro
2. Fan-In and Fan-Out
3. Gate Delays
4. Gate Delays
5. Gate Delays
6. Gate Delays
7. Gate Delays
8. Rise Time Delay
9. Rise Time Delay
10. Rise Time Delay
11. Fall Time Delay
12. Equal DelaysGate Capacitance
13. Junction Capacitance
14. Junction Capacitance
15. Junction Capacitance
16. Junction Capacitance
17. Junction Capacitance
18. Interconnect Capacitance
19. Delay of CMOS Gates
20. Delay of CMOS Gates
Joseph A. Elias, PhD
1
Class 14: Timing and Delays
Fan-In and Fan-Out (Weste p264-267)
•Fan-in is the number of inputs connected to a gate
•Fan-out is the number of outputs connected to a gate
•Who cares? DELAY due to loading (what loading?)
•How does one express delay of a circuit based on nodes?
Joseph A. Elias, PhD
2
Class 14: Timing and Delays
Gate Delays (Weste p215)
For a transistor in saturation,
which can be written as
I = β/2 (Vgs-Vtn)2
where
β = µ Cox (W / L)
β is a conductance, since I = G V
Joseph A. Elias, PhD
3
Class 14: Timing and Delays
Gate Delays (Weste p215)
Given the circuit on the right (what is it?)
•When the output is pulled down
what transistor(s) is(are) on?
•When the output is pulled up,
what transistor(s) is(are) on?
Given that three n-ch are in series,
what is the delay of the combination?
The R portion of the RC delay can be thought of
as the effective β of the transistors
Joseph A. Elias, PhD
4
Class 14: Timing and Delays
Gate Delays (Weste p215)
Equivalent β for three series (why?) n-ch transistors
Equivalent β for one (why?) p-ch transistors
Delay time α Cload
Delay time α (1 / β)
so the delay through three transistors with the
a capacitive load will be three times that of
a single transistor with the same capacitive load
Joseph A. Elias, PhD
5
Class 14: Timing and Delays
Gate Delays (Weste p215)
So given the 3-input NAND gate,
and assuming (why?):
One can find that the ratio:
Which is why one wants to make
p-ch in parallel and n-ch in series.
Joseph A. Elias, PhD
6
Class 14: Timing and Delays
Rise Time Delay (Weste p264-267)
So based on the 3-input NAND, for a large number of gates,
the number of series inputs should be limited to 2-5.
Consider the worst-case rise-time delay for an m-input NAND gate
Rise time delay
where
Why p-channel?
Joseph A. Elias, PhD
7
Class 14: Timing and Delays
Rise Time Delay (Weste p264-267)
Using
One can re-write the rise time delay as:
Joseph A. Elias, PhD
8
Class 14: Timing and Delays
Rise Time Delay (Weste p264-267)
The rise time delay:
once rewritten,
has the form:
where
mnkrThis is a way to break apart the rise time delay into two components:
1) Internal, based on the fixed internal delay of the transisto
2) Output, based on the loading
Joseph A. Elias, PhD
9
Class 14: Timing and Delays
Fall Time Delay (Weste p264-267)
Similar to rise time delay, the fall time delay as a
function of fan-in and fan-out:
What in the eq. is the
difference between
rise and fall times?
This was assuming equal-sized gates (n/p size fixed)
as is the case in standard cells and gate arrays
Joseph A. Elias, PhD
10
Class 14: Timing and Delays
Equal Delays (Weste p264-267)
Assuming equal delays gives
To achieve this, the ratios are
So p-ch would be made (βn / m βp) times wider
for equal rise and fall delay
Joseph A. Elias, PhD
11
Class 14: Timing and Delays
Gate Capacitance (Martin p.261)
Modeling of a gate capacitor is complex. Why?
Active region, gate is a combination of intrinsic gate capacitance
and overlap capacitance. Overlap of what?
What contributes to the terms in the equation?
Linear region, gate cap is dominated by what portion of the CV curve?
This leads to the expression
Once transistor gate ramps down, the channel is in what portion
of the CV curve?
That is the reason models are key to getting accurate AC
simulations.
Joseph A. Elias, PhD
12
Class 14: Timing and Delays
Junction Capacitance (Martin p.261-4)
Junction capacitances are due to what part of the transistor?
Assuming a 3.3V swing, it can be approximated as
What does the term Cj0 mean?
This is the junction of the gate. The other portion of
the junctions are those not against a gate.
The sidewall capacitance can be approximated by
This term accounts for the periphery not against the gate.
Joseph A. Elias, PhD
13
Class 14: Timing and Delays
Junction Capacitance (Martin p.261-4)
Where is the sidewall junction capacitance?
Where is the other junction capacitances?
Joseph A. Elias, PhD
14
Class 14: Timing and Delays
Junction Capacitance (Martin p.261-4)
The three types of layout to be considered to
determine junction capacitance are :
a) non-shared junctions with contacts
b) shared junctions without contacts
c) shared junctions with contacts
Joseph A. Elias, PhD
15
Class 14: Timing and Delays
Junction Capacitance (Martin p.261-4)
•Junction Area
•Junction Periphery
(w/o ct, each diff)
•Shared Junction Area
•Shared Junction Periphery
Both area and periphery much smaller.
Why does this matter?
Joseph A. Elias, PhD
16
Class 14: Timing and Delays
Junction Capacitance (Martin p.261-4)
•Distance gate to gate is 3L. Why?
•Shared Junction Area
•Shared Junction Periphery
•So it is better to use a shared drain when possible
Joseph A. Elias, PhD
17
Class 14: Timing and Delays
Interconnect Capacitance (Martin p.265-7)
What is used for interconnect?
•Metal
•Poly
•Diffusion
•LI-local interconnect
What components are in the capacitance?
•Parallel plate component
•Fringe component
Fringe component is empirically derived for a process
Interconnect is radically changing in the next few years to
copper and low-K dielectrics. More later in the semester.
Joseph A. Elias, PhD
18
Class 14: Timing and Delays
Delay of CMOS Logic Gates (Martin p.270-1)
Given the following circuit. How would one estimate the delay time?
What is this?
What is the 1->0 delay at node Vx when A input goes 0->1
•What are the parasitics due to junctions?
•Use the concept of equivalent resistance of a transistor to
estimate delay.
Joseph A. Elias, PhD
19
Class 14: Timing and Delays
Delay of CMOS Logic Gates (Martin p.270-1)
•Capacitance of Cp1 is due to Q1 drain, shared with Q2 source,
which is most likely a shared drain without a contact
•Capacitance of Cp2 is due to two inverters, along with
the junction capacitance of Q2 drain and Q3 & Q4 sources
•Q2 has an unshared drain with contact. How was this known?
•Q3 & Q4 share a source junction with a contact. Why?
•Loading due to the inverters is 4Cox x 1.8 um^2. Where did this come from?
•A goes 0->1, then Cp1 discharge through Q1 resistance.
•Cp2 will be discharged through what?
τ = Req1 Cp1 + (Req1 + Req2) Cp2
Joseph A. Elias, PhD
20