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High Speed Communication Circuits and Systems Lecture 9 Low Noise Amplifiers Michael H. Perrott March 3, 2004 Copyright © 2004 by Michael H. Perrott All rights reserved. M.H. Perrott 1 Narrowband LNA Design for Wireless Systems Zin From Antenna and Bandpass Filter PC board trace To Mixer Package Interface Zo LNA Design Issues - Noise Figure – impacts receiver sensitivity - Linearity (IIP3) – impacts receiver blocking performance - Gain – high gain reduces impact of noise from components that follow the LNA (such as the mixer) - Power match – want Z = Z (usually = 50 Ohms) - Power – want low power dissipation - Bandwidth – need to pass the entire RF band for the intended radio application (i.e., all of the relevant channels) - Sensitivity to process/temp variations – need to make it in o manufacturable in high volume M.H. Perrott 2 Our Focus in This Lecture Zin From Antenna and Bandpass Filter PC board trace Zo To Mixer Package Interface LNA Designing for low Noise Figure Achieving a good power match Hints at getting good IIP3 Impact of power dissipation on design Tradeoff in gain versus bandwidth M.H. Perrott 3 Our Focus: Inductor Degenerated Amp Source inout Rs ens Lg Zgs Cgs gmvgs indg Ldeg Source Rs vgs Iout Lg M1 vin Ldeg Vbias Same as amp in Lecture 7 except for inductor degeneration - Note that noise analysis in Tom Lee’s book does not include inductor degeneration (i.e., Table 11.1) M.H. Perrott 4 Recall Small Signal Model for Noise Calculations iout D Iout G D G S Zg Zg Zgs vgs Cgs gmvgs indg Zdeg S Zdeg M.H. Perrott 5 Key Assumption: Design for Power Match Zin Iout Lg vin Rs Vbias M1 Ldeg Input impedance (from Lec 6) Real! Set to achieve pure resistance = Rs at frequency wo M.H. Perrott 6 Process and Topology Parameters for Noise Calculation Source inout Rs ens Lg Zgs vgs Cgs gmvgs indg Ldeg Process parameters Circuit topology parameters Zg and Zdeg - For 0.18 CMOS, we will assume the following M.H. Perrott 7 Calculation of Zgs Source inout Rs ens Lg Zgs vgs Cgs gmvgs indg Ldeg M.H. Perrott 8 Calculation of Source inout Rs ens Lg Zgs vgs Cgs gmvgs indg Ldeg = Rs M.H. Perrott 9 Calculation of Zgsw By definition Calculation M.H. Perrott 10 Calculation of Output Current Noise Step 3: Plug in values to noise expression for indg M.H. Perrott 11 Compare Noise With and Without Inductor Degeneration Source inout Rs ens Lg Zgs vgs Cgs gmvgs indg Ldeg From Lecture 7, we derived for Ldeg = 0, wo2 = 1/(LgCgs) We now have for (gm/Cgs)Ldeg = Rs, wo2 = 1/((Lg + Ldeg)Cgs) M.H. Perrott 12 Derive Noise Factor for Inductor Degenerated Amp Source inout Rs ens Lg Zgs vgs Cgs gmvgs indg Ldeg Recall the alternate expression for Noise Factor derived in Lecture 8 We now know the output noise due to the transistor noise - We need to determine the output noise due to the source resistance M.H. Perrott 13 Output Noise Due to Source Resistance Source inout Rs ens Lg Zin Zgs vgs Cgs gmvgs indg Ldeg M.H. Perrott 14 Noise Factor for Inductor Degenerated Amplifier Noise Factor scaling coefficient M.H. Perrott 15 Noise Factor Scaling Coefficient Versus Q Noise Factor Scaling Coefficient Versus Q for 0.18 μ NMOS Device 7 Achievable values as a function of Q under the constraints that 1 = wo (Lg+Ldeg)Cgs gm L = Rs Cgs deg Noise Factor Scaling Coefficient 6.5 6 5.5 5 4.5 4 3.5 3 2.5 1 M.H. Perrott c = -j0 Note: 1 Q= 2RswoCgs c = -j0.55 c = -j1 1.5 2 2.5 3 Q 3.5 4 4.5 5 16 Achievable Noise Figure in 0.18 with Power Match Suppose we desire to build a narrowband LNA with center frequency of 1.8 GHz in 0.18 CMOS (c=-j0.55) - From Hspice – at V gs = 1 V with NMOS (W=1.8, L=0.18) measured gm =871 S, Cgs = 2.9 fF - Looking at previous curve, with Q ≈ 2 we achieve a Noise Factor scaling coefficient ≈ 3.5 M.H. Perrott 17 Component Values for Minimum NF with Power Match Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8 GHz -C gs -L calculated as deg -L g M.H. Perrott calculated as calculated as 18 Id Vgs M1 1.8μ W = L 0.18μ gm and gdo (milliAmps/Volts) and Vgs (Volts) Have We Chosen the Correct Bias Point? (Vgs = 1V) 4.5 Vgs , gm , and gdo versus Current Density for 0.18μ NMOS Chosen bias point is Vgs = 1 V 4 3.5 3 2.5 Lower power Higher power Higher ft Lower ft Lower IIP3 Higher IIP3 gdo gdo Lower g Higher g m m gdo 2 Vgs 1.5 gm 1 0.5 0 0 100 200 300 400 500 600 700 Current Density (microAmps/micron) Note: IIP3 is also a function of Q M.H. Perrott 19 Calculation of Bias Current for Example Design Calculate current density from previous plot Calculate W from Hspice simulation (assume L=0.18 m) - Could also compute this based on C ox value Calculate bias current - Problem: this is not low power!! M.H. Perrott 20 We Have Two “Handles” to Lower Power Dissipation Key formulas Lower current density, Iden Lower W - Benefits - Negatives - Benefit: lower power - Negatives M.H. Perrott 21 Id Vgs M1 1.8μ W = L 0.18μ gm and gdo (milliAmps/Volts) and Vgs (Volts) First Step in Redesign – Lower Current Density, Iden 4.5 Vgs , gm , and gdo versus Current Density for 0.18μ NMOS New bias point is Vgs = 0.8 V 4 3.5 gdo 3 2.5 2 Vgs 1.5 gm 1 0.5 0 0 100 200 300 400 500 600 700 Current Density (microAmps/micron) Need to verify that IIP3 still OK (once we know Q) M.H. Perrott 22 Recalculate Process Parameters Assume that the only thing that changes is gm/gdo and ft - From previous graph (I den = 100 A/ m) We now need to replot the Noise Factor scaling coefficient - Also plot over a wider range of Q Noise Factor scaling coefficient M.H. Perrott 23 Update Plot of Noise Factor Scaling Coefficient Noise Factor Scaling Coefficient Versus Q for 0.18 μ NMOS Device 18 Noise Factor Scaling Coefficient 16 14 12 10 Achievable values as a function of Q under the constraints that 1 = wo (Lg+Ldeg)Cgs gm L = Rs Cgs deg 8 c = -j0.55 6 c = -j0 Note: 1 Q= 2RswoCgs 4 c = -j1 2 1 2 3 4 5 6 7 8 9 10 Q M.H. Perrott 24 Second Step in Redesign – Lower W Recall Ibias can be related to Q as We previously chose Q = 2, let’s now choose Q = 6 - Cuts power dissipation by a factor of 3! - New value of W is one third the old one M.H. Perrott 25 Power Dissipation and Noise Figure of New Design Power dissipation - At 1.8 V supply Noise Figure - f previously calculated, get scaling coeff. from plot t M.H. Perrott 26 Updated Component Values Assume Rs = 50 Ohms, Q = 6, fo = 1.8 GHz, ft = 42.8 GHz -C gs -L calculated as deg -L g M.H. Perrott calculated as calculated as 27 Inclusion of Load (Resonant Tank) Add output load to achieve voltage gain - Note: in practice, use cascode device LL RL We’re ignoring Cgd in this analysis vout inout Rs vin Rs RL Iout iout Lg Zin LL Lg ens CL CL Zgs vgs Cgs gmvgs indg Ldeg Vout M1 vin Ldeg Vbias M.H. Perrott 28 Calculation of Gain Assume load tank resonates at frequency wo LL RL CL vout inout Rs vin Assume Zin = Rs M.H. Perrott ens iout Lg Zin Zgs vgs Cgs gmvgs indg Ldeg 29 Setting of Gain Parameters gm and Q were set by Noise Figure and IIP3 considerations - Note that Q is of the input matching network, not the amplifier load RL is the free parameter – use it to set the desired gain - Note that higher R - M.H. Perrott for a given resonant frequency and capacitive load will increase QL (i.e., Q of the amplifier load) There is a tradeoff between amplifier bandwidth and gain Generally set RL according to overall receiver noise and IIP3 requirements (higher gain is better for noise) Very large gain (i.e., high QL) is generally avoided to minimize sensitivity to process/temp variations that will shift the center frequency L 30 The Issue of Package Parasitics Noise Voltage LL Equivalent Source Rs RL Lbondwire2 CL Vout Lext Lbondwire3 Noise Current Mixer and Other Circuits M1 vin Ldeg Vbias Noise Voltage Noise Current Lbondwire1 Bondwire (and package) inductance causes two issues - Value of degeneration inductor is altered - Noise from other circuits couples into LNA M.H. Perrott 31 Differential LNA LL Rs RL CL Vout Lg M1 vin Ldeg CL RL LL Vout Ldeg Lg M2 2 -vin 2 Vbias Rs Ibias Advantages - Value of L is now much better controlled - Much less sensitivity to noise from other circuits deg Disadvantages - Twice the power as the single-ended version - Requires differential input at the chip M.H. Perrott 32 Note: Be Generous with Substrate Contact Placement To Ldeg To Lg GND To amplifer load GND G D S Substrate Contact N+ enRsub enRsub Hot electrons and other noise Rsub Substrate Contact N+ P- Rsub Hot electrons and other noise Having an abundance of nearby substrate contacts helps in three ways - Reduces possibility of latch up issues - Lowers R and its associated noise Impacts LNA through backgate effect (g ) - Absorbs stray electrons from other circuits that will sub mb otherwise inject noise into the LNA Negative: takes up a bit extra area M.H. Perrott 33 Another CMOS LNA Topology Consider increasing gm for a given current by using both PMOS and NMOS devices - Key idea: re-use of current (1/2)W/L Id gm1+gm2 Id gm M1 Id/2 M1 Id/2 gm1+gm2 M2 Id/2 Id/2 W/L (1/2)W/L M2 (1/2)W/L (1/2)W/L M1 - PMOS device has poorer transconductance than NMOS for a given amount of current, and f is lower - Not completely clear there is an advantage to using this Issues t technique, but published results are good See A. Karanicolas, “A 2.7 V 900-MHz CMOS LNA and Mixer”, JSSC, Dec 1996 M.H. Perrott 34 Biasing for LNA Employing Current Re-Use Stage 1 Stage 2 Rbig1 M4 M2 Vout1 Vout2 Ibias Rbig2 Cbig1 Vrf M1 Matching Network Cbig2 M3 Cbig3 opamp Vref PMOS is biased using a current mirror NMOS current adjusted to match the PMOS current Note: not clear how the matching network is achieving a 50 Ohm match - Perhaps parasitic bondwire inductance is degenerating the PMOS or NMOS transistors? M.H. Perrott 35 Another Recent Approach Feedback from output to base of transistor provides another degree of freedom LL RL CL Vout Q1 Rs α Cbypass α<1 vin Ldeg For details, check out: - Rossi, P. et. Al., “A 2.5 dB NF Direct-Conversion Receiver Front-End for HiperLan2/IEEE802.11a”, ISSCC 2004, pp. 102-103 M.H. Perrott 36 Broadband LNA Design Zin High Speed Broadband Signal PC board trace Zo Package Interface LNA Most broadband systems are not as stringent on their noise requirements as wireless counterparts Equivalent input voltage is often specified rather than a Noise Figure Typically use a resistor to achieve a broadband match to input source - We know from Lecture 8 that this will limit the noise figure to be higher than 3 dB For those cases where low Noise Figure is important, are there alternative ways to achieve a broadband match? M.H. Perrott 37 Recall Noise Factor Calculation for Resistor Load Source Source Rs Rs enRs enRL vin RL vout RL Total output noise Total output noise due to source Noise Factor M.H. Perrott vnout 38 Noise Figure For Amp with Resistor in Feedback Rf Source Source Rs Rs A Vin Vref Vout Rf enRf enRs incremental ground A Total output noise (assume A is large) Total output noise due to source (assume A is large) Noise Factor M.H. Perrott Vnout 39 Input Impedance For Amp with Resistor in Feedback Source Rf enRf enRs Rs A Vnout Zin Recall from Miller effect discussion that If we choose Zin to match Rs, then Therefore, Noise Figure lowered by being able to choose a large value for Rf since M.H. Perrott 40 Example – Series-Shunt Amplifier Rin Rs vin Rout RL Rf vx vout M1 Vbias R1 Recall that the above amplifier was analyzed in Lecture 5 Tom Lee points out that this amplifier topology is actually used in noise figure measurement systems such as the Hewlett-Packard 8970A - It is likely to be a much higher performance transistor than a CMOS device, though M.H. Perrott 41 Recent Broadband LNA Approaches Can create broadband matching networks using LC-ladder filter design techniques RL CMOS example: LL Vbias2 Rs L1 C1 M3 M2 Vout Lg M1 Cp vin L2 Vbias Ibias C2 Ldeg See Bevilacqua et. al, “An Ultra-Wideband CMOS LNA for 3.1 to 10.6 GHz Wireless Receivers”, ISSC 2004, pp. 382-383 M.H. Perrott 42 Recent Broadband LNA Approaches (Continued) Bipolar example: RL LL Vbias2 Rs C3 M3 C2 Vbias3 Q1 C1 vin Vout R1 Q2 C4 Ldeg2 L1 Ldeg Vbias See Ismail et. al., “A 3 to 10 GHz LNA Using a Wideband LC-ladder Matching Network”, ISSCC 2004, pp. 384-385 M.H. Perrott 43