Input and Reverse Transfer Capacitance Measurement
of MOS-Gated Power Transistors
under High Current Flow
Christoph Deml
Inneon Technologies AG, St.-Martin-Str. 76, 81541 Munich, Germany
Abstract
Nominal
Derivative
FHP
The measurement principle of the input and reverse transfer capacitance is shown. Function, stability and operation of the measurement circuits
is discussed. The on state capacitances of a power
DMOS transistor were measured under high current conditions of up to 250A. A strong nonlinear
characteristic is observed.
Capacitances are normally specied in data sheets without current ow. In the on state, there are only two capacitances signicant for a MOS-gated device with three
pins: input and reverse transfer capacitance. The measurement principles of these characteristics will be demonstrated using a power DMOS, but can be generally used
for MOS-gated transistors.
The characteristic of the reverse transfer capacitance
has, due to the Miller-eect the most signicant inuence
on the transient behaviour of power transistors and will
be considered rst.
For the measurement of CGD (gate drain capacitance
or respectively reverse transfer capacitance), VGS (gate
source voltage) is held constant and VDS (drain source
voltage) of the DUT (device under test) is varied. Normally this is done by applying the constant VDS bias with
an additive small signal sine wave. VGS is held constant
and IG (gate current) is measured.
CGD
= IG dV
DS VGS =const
High-PassFilter
Low-PassFilter
CHP
RHP
RLP
CLP
RD
VH
VP
FSI
Subtractor
Integrator
RI
VE VN
V ,VD
CI
FBUF
Buer
LG
VOP
C
CD
VGS
low magnetic eld
low current
A
IG
L1
FMM
VBUF
RG
MS
D
C0
L2
V0
LD
RG ;DUT
MDUT
RP
L3
ID
A
medium
high magnetic eld
magnetic eld
high current
Figure 1: Basic structure of the CGD measurement circuit.
Introduction
dt
,VDS V
FLP
(1)
This method is very accurate, but has a long T (measurement time). Applying the VDS bias while there is a
ID (drain current) owing results in the situation that
P = VDS ID (heating power) can not be conducted to
the heat sink as quickly as required. In this case the
E = VDS ID T (accumulated energy) would lead to self
heating and destruction of the DUT due to thermal overload.
The goal of the circuit (g. 1) is to produce a short
voltage ramp on the drain of the DUT replacing a sine
wave. The short ramp reduces the accumulated energy
tremendously and subsequent ramps are spaced with a
cooling time of several seconds.
CGD derives the VDS ramp using the relationship IG =
CGD dVdDS
t . Because the measurement result CGD is directely proportional to IB (equ. 1), the derivative of VDS
must be constant.1
Circuit Function
Subsequent VDS ramps have dierent VGS values and
are spaced by a cooling time. VGS is held constant for one
VDS ramp. This produces a group of CGD curves with
continuous VDS while VGS is a variable.
IG (t) is measured potential free using a current probe.
All transients should be measured with one oscilloscope,
so that they have the same time base and voltages of different channels are sampled at the same time. Of course
If the corresponding dVdDS
t is measured too and used for the calculation of CGD then mathematically everything is correct. Due to
parasitic elements ideal measurements are not possible and experience shows that a non constant dVdDS
t leads to unsatisfactory results.
1
2
3
[A]
9
1
ID
[nF]
V
12
,
C
GD
200
[V]
GS
6
0
20
12
V
100
GS
6
20
0
0
10
20
V
DS
[V]
0
30
9
[V]
0
3
0
10
DS
V
20
[V]
30
Figure 2: Measured gate-drain capacitance of the BUZ
103 SL.
Figure 3: Measured transfer characteristic of the BUZ 103
SL.
the measured values of dierent channels must be the result of the same ramp event.
Because the ramp event must be triggered by a pulse
generator, which has usually a common ground together
with the oscilloscope via earth, this ground level is placed
at the drain of MDUT . During the idle time, VE must be
positive, driving VOP to the negative supply voltage of the
operational amplier.
During the ramp time, ,VDS (t) is measured.
dVDS
is measured indirecty using a known capacitance
dt
CD between drain and source and measuring the current
VD (t) through it using a small series resistance R .
D
RD
For the transfer characteristic, ID can be measured potential free using a current probe between the source of
MDUT and C0 (g. 3). As is obvious by the slight decrease
of current, self-heating was not completely avoided.
In order to supply the correct control gate voltage to the
series MOS transistor corresponding to the VDS ramp, a
regulation circuit was constructed.
VD
D
CGD
D
dVDS
dt
(2)
(3)
= RD CD
is calculated using equ. 1 and 2 (g. 2).
I (t) CGD (VGS ; VDS (t)) D G VD (t) VGS =const
(4)
Next the VDS ramp should be supplied. This supply
must be able to supply a high current. Therefore a MOS
transistor MS is connected in series to MDUT . This series
MOS transistor is connected to a capacitance C0 capable of supplying the high current ID with a high current
RT
slew rate ddItD and the charge ID dt where T is the ramp
0
time. The parasitics must be suciently small while the
capacitance value must be large enough.
Regulation Circuit
VDS
4).
is reversed and fed into a high pass lter HP (g.
VH
HP (,V )
= 1 +pp
DS
HP}
|
{z
(5)
FHP
p = j 2f
HP = RHP CHP
(6)
(7)
For a frequency below
fHP
= 21
HP
(8)
the output voltage of the HP is the derivative of VDS .
VH (f < fHP ) pHP (,VDS )
(9)
The output voltage of the operational amplier can be
described by
VOP
=
VP
,
pI VE
p
I
k + 1+pI
1
1
1+
(10)
abs(F )[dB] |
- - - arg(F )[]
180
80
180
90
40
90
0
0
k
BUF
20
F
- - - arg(F )[]
abs(F )[dB] |
-20
-90
0
0
-90
-40
-40
180
180
20
20
Fo;N
0
-20
,
F
MM
90
0
-90
-40
90
0
0
-20
-90
-40
180
180
0
20
Fo;P
-20
0
-40
,
F
HP
90
-90
-60
90
0
0
-20
-90
-40
180
3
10
10
4
0
LP
5
6
10
f
90
F
10
-20
[Hz]
7
10
8
10
9
10
Figure 5: Open Loop Frequency Response of the Operational Amplier and Regulation Circuit.
0
-40
-90
-60
180
20
F
SI
90
0
0
-20
-90
-40
3
10
4
10
10
5
6
10
f
[Hz]
7
8
10
10
10
9
Figure 4: Open Loop Frequency Response of the Circuit
Components.
OP
= V V,
(11)
P VN
I = RI CI
(12)
The regulation principle is demonstrated now by removing the low-pass-lter and connecting the output of the
high-pass-lter directely to the subtractor-integrator part
(VP = VH , equn. 13 to 15).
k
pHP (,VDS ) , 1 VE
1+p1
VOP = pHP 1
p1
+
k 1+p1
(13)
1+
Using an ideal operational amplier this results in
lim V = HP (1 + pI ) (,VDS ) , p1 VE
(14)
k!1 OP I (1 + pHP )
I
Additionally, when choosing the same time constant for
HP and I
,VE = p
VDS
+ klim
!1 VOP HP =I =
(15)
it can be shown, that the dierence between the real
derivative dVdDS
t and the nominal derivative, which is adjusted by VE , is integrated and fed into the gate of MS .
So, when dVdDS
t becomes smaller, the gate voltage of MS
is rising faster, resulting in a faster pull up of VDS .
In order to keep the deviation from the nominal derivaDS must be as large as
tive small, the gain FMM = VVBUF
possible.
g
(R + pL )(R + pL2 )
FMM = m;MS DS2 2 D P
(1 + pR + p L )(RDS + RP + pL ) (16)
= RG CG
(17)
= LG CG
(18)
= LD + L2 + L3
(19)
where RDS is the small signal resistance of MDUT and
gm;MS is the gate transconductance, RG is the parasitic
gate resistance and CG is the gate capacitance of MS .2
The parallel resisor RP is needed for limiting the open
loop gain in case of MDUT saturation. L1 has no eect,
because MS is always in saturation.3
For the regulation circuit stability, both loops, ending
at the positive and the negative input of the operational
amplier, must be considered (g. 5).
R
L2
L
,Fo;N =
pI
(1 + pI )( k1 , VVOPP )
(20)
2 The Miller-eect is neglected for M . Parasitic source inducS
tances are neglected generally.
3 Channel length modulation and gate-drain capacitance of M
S
are neglected.
6
FBUF
L1
A
VGS
CI
RI
RD
V VD
C
low magnetic eld
low current
20
30
10
LD
RG ;DUT
V
C0
MDUT
L3
V0
[nF]
CD
ID
A
medium
magnetic eld high magnetic eld
high current
GG
IG
R
Figure 6: Basic structure of the CGG measurement circuit.
C
FSI
Nominal
Derivative Integrator Buer
5
4
0
2
DS
V
) VP
,Fo;P = , 1 +k(1(1++pk)Ip
I} VOP
{z
|
VP
VOP
(21)
FSI
= FBUF FMM (,1)FHP FLP
(22)
The stability is mainly aected by the parasitic inductances LD , L2 and L3 .
A low-pass-lter is inserted to increase the phasemargin.
1
FLP =
(23)
1 + pLP
LP = RLP CLP
(24)
If MS is switched o too fast at the end of a pulse, then
its drain-source voltage may increase above the maximum
blocking voltage due to the parasitic inductances. This
can be avoided either by limiting the turn o speed or by
adding D (transient absorbing Z-diode).
Input Capacitance
Fig. 6 shows the measurement circuit for the input capacitance, which is refered to as gate-gate capacitance in
this case.
d
t CGG = IG
(25)
dV Using
GS VDS =const
I (t) CGG (VGS (t); VDS ) D G VD (t) VDS =const
(26)
the result of this measurement is shown in g. 7.
The stability of this circuit is easily achived without
long calculations.
The L1 , L3 and LD (parasitic inductances) and the
R (parasitic resistance) must be as small as possible, because they induce a VDS drop when ID starts owing.
0
0
10
V
GS
[V]
[V]
20
Figure 7: Measured gate-gate capacitance of the BUZ 103
SL.
Parasitics, EMC and Measurement Setup
Due to the RG ;DUT (eective gate resistance) of the
device, there is an eective voltage drop across the gate
area caused by IG .
dV
VG = RG ;DUT IG RG ;DUT C
(27)
dt
where C is the measured capacitance of the DUT and ddVt
is the derivative of the voltage ramp. In order to keep this
voltage drop between supplyed gate voltage and eective,
inner gate voltage small, ddVt must be limited. For the measurements above, a slew rate of 2 Vs was chosen, leading
to a worst case voltage drop of 0:17V for RG ;DUT = 13
.
The resistance of the gate current probe has two eects.
First this resistance must be considered by adding it to the
gate resistance above. Second it causes a drop in the gate
current measurement.
The wire of the DUT gate has an C (parasitic capacitance) to the ground through the ribbon cable and the
case of the gate current probe.
Low pass lters must be inserted between the measurement circuit and the dc voltage sources, because sources
typically have parasitic capacitances to ground.
Malfunction usually ends up with destruction of all
power semiconductors. Some resistances should be added
to the circuits at appriproate nodes in order to achive a
fail save behaviour in case of unintentional removal of the
pulse generator or an incorrect sequence of connecting and
disconnecting the power supplies.
A high ddIt causes an emission of a magnetic eld through
the parasitic inductances. In order to keep this inuence
0, R
C
P
, I Current Probe
D
MDU T ; MS
Ribbon Cable
on the measurement result small, the DUT is seperated
from the C0 , RP and ID current probe using stacked copper strips insulated with a foil. The regulation and measurement circuit was additionally seperated using a ribbon
cable. Both, the regulation and measurement circuit and
the ribbon cable, are placed in one plane with the main
magnetic eld lines. The regulation and measurement circuit is shielded by two iron plates. This measurement
setup is shown in g. 8.
Reference
Regulation and Measurement Circuit
Magnetic Shielding
Stacked Copper Strips
Figure 8: Measurement Setup.
[1] Christoph Deml, Kurt Homann: Gate-Drain Capacitance Behaviour of the DMOS Power Transistor Under
High Current Flow. IEEE Power Electronics Specialists Conference. IEEE: Fukuoka 1998. Pages 1716 1719.