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The CMOS Inverter – Static Model
Outline
 First Glance
 Digital Gate Characterization
 Static Behavior (Robustness)
 VTC
 Switching Threshold
g
 Noise Margins
CMOS INVERTER
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The CMOS Inverter:
A First Glance
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CMOS Inverters (1)
VDD
VDD
PMOS
1.2 m
= 2
Vin
Out
In
Vout
Metal1
CL
Polysilicon
NMOS
GND
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



0
4
Digital Gate Fundamental
Parameters
CMOS Inverter Operation Principle
1
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1
0
Functionality
Reliability, Robustness
Area
Performance
 Speed (delay)
p
 Power Consumption
 Energy
VOH = VDD VOL = 0
§ 5.2
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1
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The Ideal Inverter
Static CMOS Properties
Basic inverter belongs to class of static
circuits: output always connected to either
VDD or VSS. Not ideal but:
 Rail to rail voltage swing
Vout
 Ratio less design
Ri = 
Ro = 0
 Low output impedance
Vout
 Extremely high input impedance
g = -
 No static power dissipation
g = -
 Good noise properties/margins
Vin
Vin
{TPS}: prioritize the list above
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Load Line (Ckt Theory)
2.5
2.5V
ID [10-4 A]
VGS = 2.5V
B
2.0
Voltage Transfer Characteristic (VTC)
R
VGS
1.0
Vout
Vin
i
VGS = 2.0V
1.5
A
VGS = 1.5V
VGS = 1.0V
1 0V
05
0.5
0V
0
0.5
1.0
1.5
2.0
VDS [V]
2.5
Exercise:
The blue
load line A corresponds to R = 25k
The orange load line B corresponds to R = 12.5k
Vout = approx 1.6 V
With load line A and VGS = 1V,
Draw a graph Vout(Vin) for load line A and B
§ 5.2
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PMOS Load Lines
Goal: Combine IDn and IDp in one graph
Kirchoff:
Vin = VDD + VGSp
IDn = - IDp
Voutt = VDD + VDSp
DS
-
VDSp
+
IDp
+
I n,p
Vout
IDn
IDn
Vin= 0
Vin=3
Vin=3
Vin= 3
VGSp=-2
VDSp
Vout
Vin= 4
VGSp=-5
Example: VDD=5V
Vin = VDD + VGSp
NMOS
Vin= 1
Vin=0
Vin= 5
PMOS
I Dn
Vin=0
VDSp
Vin= 5
Vin= 4
Vin= 2
Vin= 3
Vin= 3
Vin= 4
Vin= 2
Vin= 1
Vout = VDD + VDSp
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Vin= 2
V =1
in
Vin= 0
Vout
IDn = - IDp
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-
Vin
IDp
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CMOS Inverter Load Characteristics
VDD
VGSp
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Operating
Conditions
CMOS Inverter VTC
Need to know for proper dimensioning,
analysis of noise margin, etc.
 Vout
Vout
Vout = Vin - VTp
5
Vdd
NMOS
1 Vin = VGS < VTn  off
I n,p
4
Vin = 5
Vin = 0
NMOS
Vout = Vin - VTn
3
PMOS
Vin = 1
Vin = 4
Vin = 3
Vin = 2
Vin = 3
- VTp
Vdd - |VTp|
2
Vin = 4
VTp
Vin = 2
V in = 1
Vin = 2
Vin = 3
Vdd  Vin
VTn
PMOS
Vin = 0
Vin = 5
3 Vout < Vin - VTn  resistive
1
Vin = 4
2 Vout > Vin - VTn
VDS > VGS - VTn
VGD < VTn
 saturation
1
Vout
1
2
3
4
V in
5
2
6
3
5
4 Vin > VDD + VTp  off
4
Exercise: check
results for PMOS
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5 Vout < Vin - VTp  saturation
6 Vout > Vin - VTp  resistive
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Operating Conditions
 Vout
Vout = Vin - VTp
Vdd
Vout = Vin - VTn
- VTp
Vdd - |VTp|
Vout
Vdd  Vin
NMOS sat
PMOS lin
5
4
NMOS sat
PMOS sat
NMOS lin
PMOS satNMOS lin
PMOS off
1
6
3
3
2
2
1
Inverter Static Behavior
Regeneration
Noise margins
Delay metrics
NMOS off
PMOS lin
4
VTn
5
VTp
NMOS 1 off
2 saturation
3 resistive
PMOS 4 off
5 saturation
6 resistive
1
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2
3
4
5
§ 5.3
Vin
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The Realistic Inverter
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The Regenerative Property
Vout [V]
Vout
2.5
Ri = 
2.0
Ro = 0
1.5
g = -
A chain of inverters
 Regenerative
Propert ability
Property:
abilit to
regenerate (repair)
a weak signal in a
chain of gates
1.0
0.5
VIN [V]
Ideal Inverter
Vin
0
0.5
1.0
1.5
2.0
2.5
Realistic Inverter
Ex. 1.4
The regenerative property
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The Regenerative Property (2)
The regenerative Property (3)
...
v1
v0
v2
v3
v5
v4
v6
Exercise: what is the output voltage of a chain of 4
inverters with a piece-wise linear VTC passing through (0,
) (3,7),
( ) ((7,1)) and ((10,0)) [[Volt],
] as the result of an input
p
10),
voltage of 6 [Volt].
(a) A chain of inverters.
v1, v3, ...
v1, v3, ...
finv(v)
f(v)
v0, v2, ...
(b) Regenerative gate
Exercise: discuss the behavior for an input of 5 [Volt]
f(v)
finv(v)
v0, v2, ...
(c) Non-regenerative gate
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Inverter Switching Treshold
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Electrical Design Rule
Wp  2.5 Wn
See Figure 5.7
VM (V)
 Point of Vin = Vout
 Assumes Lp = Ln
 Should be applied
y
consistently
Vout
Wp / Wn
 Try to set Wn, Ln, Wp, Lp
so that VTC is symmetric
as this will improve noise
margins
optimize NMOS-PMOS ratio
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 Symmetrical VTC  Vm  ½ VDD  Wp/Wn  3.5
 In practice: somewhat smaller
 Why?
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Save area with only slight asymmetry
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Inverter Switching Threshold
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Inverter Switching Threshold
Analytical Derivation
Analytical Derivation (ctd)
 VM is Vin such that Vin = Vout

ID  kVDSAT VGS  VT  VDSAT / 2
IDSATn(VM) = - IDSATp(VM)
 VDS = VGS  VGD = 0  saturation

 k nVDSATn VM  VTn  VDSATn / 2  
 k pVDSATP VM  VDD  VTp  VDSATp / 2
 Assume VDSAT < VM - VT
 (velocity saturation)
 Ignore channel length modulation
 VM follows from
 IDSATn(VM) = - IDSATp(VM)
 VDSATn VM  VTn
T  VDSATn
DSAT / 2 

kp

( W / L )p
kn

k
VDSATP VM  VDD  VTp  VDSATp / 2 
( W / L )n


k'n VDSATn VM  VTn  VDSATn / 2
' V
k p DSATP VM  VDD  VTp  VDSATp

W '
k
L

/ 2
 See Example 5.1:
 (W/L)p = 3.5 (W/L)n for typical conditions and VM = ½ VDD
 Usually: Ln = Lp
§ 5.3.1
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Simulated Gate Switching Threshold
 Not the device threshold Vm = f(Ronn, Ronp)
Vin
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Gate Switching Threshold
w/o Velocity Saturation
Noise in Digital Integrated Circuits
 Long channel approximation
 Also applicable with low VDD
VDD
v(t)
i(t)
4.0
Exercise (Problem 5.1):
derive VM for longchannel approximation
as shown below
VM
3.0
2.0
(a) Inductive coupling (b) Capacitive coupling
(c) Power and ground
noise
1.00.1
VM 
0.3
1.0
kp/kn
3.2
r ( VDD  VTp  VTn )
1 r
with
10.0
r
 Study behavior of static CMOS Gates with noisy
signals
 kp
kn
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Noise in Digital Circuits
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Noise Margins
VDD
+
-
“0”
“1”
- +
Vnoise
VOH
VDD Drop
“X”
+
-
Ground Bounce
VOL
0
§ 1.3.2
§ 1.3.2
§ 5.3.2
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Noise Margins
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VIH
VDD
 VOL = Output Low Voltage
 VIL = Input Low Voltage
 VOH, VIH = …
§ 5.3.2
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Noise Margins
 VOL = Output Low Voltage
 VIL = Input Low Voltage
 VOH, VIH = …
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VIL
 NMH = VOH - VIH = High Noise Margin
 NML = VIL - VOL = Low Noise Margin
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5
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Noise Margin for Realistic Gates
Noise Margin Calculation
Piece-wise linear
approximation of
VTC
VIH  VIL  
 VOL not well defined
 Conveniently relate to slope s = -1
{TPS}: explain significance of slope = -1 for noise margin
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2.5
1 r
2
r
 Mostly determined by technology
VDD  VM
g
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k pVDSATp
k nVDSATn
1 r

VM  VT  VDSATp / 2 n   p 
Vin VM
0.2
0.15
1.5
Vout (V
V)
VM  VT  VDSATp / 2 n   p 
NML  VIL
Vout(V)

NMH  VDD  VIH
dV in
k pVDSATP Vin  VDD  VTp  VDSATp / 2 1   pVout   pVDD   0
Vin VM
VIL  VM 
dV
consider g  out
k nVDSAT n Vin  VTn  VDSATn / 2 1  nVout  
dVout
dV in
g
Gain as a function of VDD
 Approximate g as the slope in Vout vs. Vin at Vin = VM
g

g
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Noise Margin Calculation (2)
We know how
to compute VM
Next: how to
compute g
VOH  VOL   VDD
V
 VM  M
g
VIH
g = gain factor
(slope of VTC)
0.1
1
 See example 5.2
0.05
0.5
 Exercise: verify calculation
 Exercise: explain why we add channel length
modulation to the ID expressions (we did not do
this to determine VM )
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Gain=-1
0
0
0.5
1
1.5
2
2.5
Vin (V)
0
0
0.05
0.1
Vin (V)
0.15
0.2
Subthreshold!
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Dynamic Noise Margin
CMOS INVERTER
dynamic behavior (performance)
Noise Pulse Amplitude
 Previous definition was Static Noise Margin
 Dynamic Noise Margin: how does noise energy
determine behavior
 A short pulse may have higher amplitude than a
long pulse before problems occur.
p
may
y safely
y exceed Static Noise
 Short spikes
Margin
 Capacitances
 (Dis)charge times
 Delay
§ 5.4
Error free
Noise Pulse Duration
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Reducing tp
t pHL  0.69 
 Before: propagation delay analysis
3 VDD  5

t p  0.69 
 1 - VDD CL
4 IDSAT  6

IDSAT  k '
3 VDD  5

 1 -  VDD CL
4 IDSATn  6

=0
W

2
VGS  VT VDSAT  1VDSAT

2
L 
The Transistor as a Switch
N
Next:
t propagation
ti
d
delay
l
from a design perspective
inverter sizing
VGS  VT
t pHL  0.52
Ron
S
D ID
V GS = VD D
Rmid
{TPS}: How can you reduce propagation delay?
R0
V DS
Ex. 3.8
VDD/2
§ 5.4.1
CLVDD
(W / L)n k n' VDSATn (VDD  VTn  VDSATn / 2)
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VDD
12/03/05
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Propagation Delay tp can be reduced by
 Increasing VDD (until VDD >> VT + VDSAT/2)
 Increasing W
 Reducing CL
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Delay as a function of VDD
Propagation Delay tp can be reduced by
 Increasing VDD (until VDD >> VT + VDSAT/2)
 Increasing W
 Reducing CL
5
tp (Normalized)
4.5
t pHL  0.52
CLVDD
(W / L)n k n' VDSATn (VDD  VTn  VDSATn / 2)
3.5
t pHL  0.52
3

CL
W
 CL can be reduced by good layout design
 But part of CL depends on W!
2
1.5
1
CLVDD
(W / L) n k n' VDSATn (VDD  VTn  VDSATn / 2)
Spice
2.5
Fg.5.17
38
Sizing
5.5
4
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0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4
VDD (V)
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tp as a function of Wp/Wn
x 10-11
5
tp(sec)
 Ipd  tpHL
tpLH
4.5
Wn
tpHL
 CD  tpLH 
4
(tpHL + tpLH)/2
3.5
…
…
Wp
3
1
1.5
2
2.5
3
3.5
4
4.5
5
Wp/Wn
Min tp in general not when tpLH = tpHL
Save area, time at expense of robustness
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Isolated Inverter Sizing
Intrinsic vs Extrinsic vs Parasitic Load Cap
VDD
CGS4
M2
R0:
resistance of minimum size inverter
(assume proper  = Wp / Wn ratio)
C0:
intrinsic load (output, drain) cap of min. size inverter
tp0 = 0.69 R0C0:
intrinsic or unloaded delay
basic time constant for technology
minimum delay possible in technology given VDD
S:
sizing factor for Wn, Wp of driving inverter
Wn = S Wmin, Wp = S  Wmin
M4
CDB2
Vout
Vin
Vout2
CDB1
CGS3
CGD1+ CGD2
M1
M3
CW
 Cint = CDB1 + CDB2 + 2(CGD1 + CGD2)
 Cext = CGS3 + CGS4 + CGD3 + CGD4
 Cpar = Cw
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Intrinsic load
Extrinsic / fan-out load
Parasitic load
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
Req = R0 /S
Cint = SC0


C
 t p  t p 0  1  ext 
SC0 

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Isolated Inverter Sizing
 C
t p  t p0  1  ext
SC0

Assume Cpar can be
ignored or its effect can
be absorbed in other C
 C

t p  0.69Req (Cint  Cext )  0.69Req Cint  1  ext 
Cint 

VDD
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Inverter Chain



Assume size of inverter 1 is fixed.
 Increasing S of inverter 2 reduces tp of inverter 2
 But it increases tp of inverter 1 (higher load cap)
 Expect an optimum!
Increasing S reduces delay until SC0 >> Cext
In
2
1
Out
CL
tp
S
{TPS} If CL is given and knowing properties of input source:
- How many stages are needed to minimize the delay?
- How to size the inverters?
tp0
Cext
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Delay Formula
 C
t p  t p0  1  ext
SC0


f

  t p0  1  



In
Out
2
N
input gate capacitance
CL
 = Cint/Cgin = SC0 /Cgin
self
lf loading
l di coefficient
ffi i t
tp = tp,1 + tp,2 + …+ tp,N
property of technology, typically   1
fj

t p, j  t p0  1 


f = Cext /Cgin effective fanout
f

Cgin
C
 ext x
Cgin SC0


C

  t p0  1  gin, j  1 


 Cgin, j 


N
N 
Cgin, j  1 
, C
t p   t p, j  t p0   1 
 CL

Cgin, j  gin,N  1
j 1
j  1
[ tp = tp0(1+f/)
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Apply to Inverter Chain
1
Cgin
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f = Cext /Cgin effective fanout ]
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Apply to Inverter Chain
Optimal Tapering for Given N
Optimal size of each stage is geometric mean of 2 neighbors:
Delay equation has N-1 unknows, Cgin,2 … Cgin,N
N 
Cgin, j  1 
, C
t p   t p , j  t p0   1 
 CL

Cgin, j  gin,N  1
j 1
j  1
N
Cgin, j  Cgin, j  1  Cgin, j  1 ,
2
Cgin
, j  Cgin, j  1  Cgin, j  1
Make N-1 partial derivatives for Cgin,j zero for minimization:
t p
Cgin, j

Cgin, j  1 
1
 t p0 

 0,
 Cgin, j  1  C
2
gin, j 


Cgin, j
j  2N  1

Cgin, j  1
1 b

 c  ab
a c2
fj 
Optimal size of each stage is geometric mean of 2 neighbors:
Cgin, j  Cgin, j  1  Cgin, j  1 ,
13/03/15

Cgin, j  1
Cgin, j  1
Cgin, j
49
CL
NF
Cgin,1
N
F = CL/Cgin,1: path fan-out.
Same fan-out, same delay for
each stage.
NF
 C



  t p0  1  gin, j  1   t p0  1 



 Cgin, j 




TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
Optimal Tapering for Fixed-N
Summary
In
Load cap / input cap ratio
same for each stage
Cgin, j
fj

t p, j  t p0  1 


j  2N  1
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
j  2 N  1




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50
Example
Out
In
1
f
C1 = Cgin,1
1
C1 = Cgin,1
i 1
Delay per stage and total Path Delay
fj

t p, j  t p0  1 


Out
CL
f2
NF
 C



  t p0  1  gin, j  1   t p0  1 



 Cgin, j 




f1 = f2 = f3 = ... = F1/N
f1 x f2 x f3 x … = F
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter




 fj 
t p  Ntp0  1  
 

f
CL/C1 has to be evenly distributed across N = 3 stages:
38

  9t p0
t p  3t p0  1 

 

f  38  2
F = CL/Cgin,1
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51
Optimum Number of Stages
CL= 8 C1
f2
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
for   1
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52
Optimum Effective Fanout f
Optimum f for given process defined by 
For a given load, CL and given input capacitance Cin
find optimal f if N is free (and possibly non-integer)
CL  F  Cin  f N Cin with N 


f  exp  1  
f

ln F
ln f
f

=1
fopt
e=2.72
3.6
Nopt
lnF
0.78lnF

f


f  exp  1  
f

TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
=0
t p0 ln F   f  ln f  1

0

ln2 f
ln f  1 
ln F
ln f
(In practice, N must be rounded
up or down to integer value)
f 
f  t p0 ln F  

t p  Nt p0  1   





 ln f ln f 

t p
N
Closed-form solution
only for = 0
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TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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9
13/03/15
Normalized delay function of F
Normalized tp vs. f
With Self-Loading =1,
fopt = 3.6
 Slight increase of tp for
f > fopt
 Choosing too few
stages (f > fopt) is
relatively harmless for
delay and saves area
oo many
a y stages is
s
 Too
expensive in terms of
delay
NF


t p  Nt p0  1 

 

F
(= 1)
Inverter
Chain
Unbuffered
Two Stage
10
11
83
8.3
83
8.3
100
101
22
16.5
1000
1001
65
24.8
10,000
10,001
202
33.1
Fan-out of 4 (FO4) is safe common practice
http://en.wikipedia.org/wiki/FO4
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Buffer Design
Power
(= 1)
1
N
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
64
Dynamic Power
Static Power
Metrics
www.quietpc.com
1
22.6
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CMOS Power Dissipation
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58
Estimate
 Furnace: 2000 Watt, r=10cm
 P  6Watt/cm2
 Processor chip: 100 Watt, 3cm2  P  33Watt/cm2
§ 5.5
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
Power Density
 Power dissipation is a very important circuit
characteristic
 CMOS has relatively low static dissipation
 Power dissipation was the reason that CMOS
technology won over bipolar and NMOS
technology for digital IC’s
 (Extremely) high clock frequencies increase
dynamic dissipation
 Low VT increases leakage
 Advanced IC design is a continuous struggle to
contain the power requirements!
§ 1.3.4
24 hours audio
playback time
§ 5.5
Power-aware design, design for low power, is
blossoming subfield of VLSI Design
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60
10
13/03/15
Power Evolution over Technology Generations
14
© ASME 2004
 {TPS}: what is the difference in power between Bipolar and
CMOS technologies?
Module Heat Flux(watts/cm2)
 A: 10 years
CMOS
IBM ES9000
Prescott
Jayhawk(dual)
12
Bipolar
10
T-Rex
Mckinley
Squadrons
Fujitsu VP2000
8
IBM GP
IBM 3090S
NTT
IBM RY5
6
Pentium 4
IBM RY7
Fujitsu M-780
Pulsar
4
IBM 3090
Start of
Water Cooling
2
Vacuum
0
1950
IBM 370
IBM 360
CDC Cyber 205
IBM 4381
IBM 3081
Fujitsu M380
IBM 3033
IBM RY6
IBM RY4
Apache
Merced
Pentium II(DSIP)
1960
1970
1980
1990
2000
2010
Year of Announcement
Introduction of CMOS over bipolar bought industry 10 years
(example: IBM mainframe processors)
[From: Jan Rabaey, Low Power Design Essential, Ref: R. Chu, JEP’04]
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Low Power Design Essentials
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Where Does Power Go in CMOS
 Dynamic Power Consumption
Charging and discharging capacitors
 Short Circuit Currents
Short circuit path between supply rails during
switching (NMOS and PMOS on together)
 Leakage
Leaking diodes and transistors
May be important for battery-operated equipment
 Recommended reading
(available online via University Library and site (?) of book)
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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Dynamic Power
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
vDD
Equivalent circuit for lowto-high transition
i(t)
v0(t)
C
1
 Ei
T i
EC - Energy stored on C
 Ei = Power-Delay-Product P-D
 important quality measure

EC   iv 0dt
0

  Cv0
 Energy-Delay-Product E-D
 combines powerspeed performance
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
64
Low-to-High Transition Energy
Dynamic Power
 Ei = energy of switching event i
 independent of switching speed
 depends on process, layout
 Power = Energy/Time
P
13/03/15
13/03/15
0
v 0 = v 0 (t )
i  i (t )  C
dv 0
dt
dv0
dt
dt
V
VDD
DD
1
1
2
 CVDD
  Cv 0dv 0  Cv 02
2
2
0
0
65
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11
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Low-to-High Transition Energy
Low-to-High Transition Energy
vDD
i(t)
i(t)
vDD
v0(t)
v0(t)
C
EVDD
C
Energy delivered by supply

E diss
dv
2
EVDD   i t VDDdt  CVDD 0 dt CVDD
dt
0
0
1
2
2
EVDD  CVDD
Ec  CVDD
2
Where is the rest?
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
Ediss   i VDD  v 0 dt
0


0
0
  iVDDdt   iv 0dt
 EVDD  Ec
Dissipated in transistor
13/03/15
Energy dissipated in transistor

VDD
67
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
High-to-Low Transition Energy
C
68
Compare Charging Strategies
Constant voltage
i
13/03/15
Equivalent circuit
+
V
i C
dVC
dT
Constant current
R
CV
T
R
I
C
-


dV
ER   VR idt   V  VC C C dt
dt
0
0
Exercise: Show that the energy that is dissipated
in the transistor upon discharging C from VDD to
0 equals Ediss = ½CVDD2
I
V
1
  V  Vc CdVC  CV 2
2
0
C

T
ER   I  RI  dt   I  RI dt  RI 2T
0
0
RC
CV 2

T
 Reduced dissipation if T > 2RC = t76%
 Difficult to reap benefits in practice
 See ‘Adiabatic Logic’
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
CMOS Dynamic Power Dissipation
CLoad
2
 CVDD
f
input
waveform
 Can only reduce C, VDD or f to reduce dynamic
power
 (NMOS current is used for
discharging)
VTn
NMOS
turns on
71
 Shaded area is where both pull-up
and pull-down transistors are on
(this is when short-circuit current
can exist). This region is determined
by crossings of input waveform with
VTn and VDD-|VTp|.
 Short circuit current for output
going low is the current delivered by
the PMOS
|VTp|
 Independent of transistor on-resistances
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Short Circuit Current
Energy
Energy
# transitions
Power 


Time
transition
time
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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PMOS
turns off
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
 {TPS} Discuss the influence of CLoad
on the amount of short circuit
dissipation
higher CLOAD  higher dissipation?
or not?
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72
12
13/03/15
Short Circuit Current
|VDSp|
|VTp|
input
waveform
VTn
|VTp|
VTn
NMOS
turns on
Short Circuit Current
 Input and output waveforms of
inverter loaded with a large
capacitance (top) and with a small
capacitance (bottom).
output for
large CL
 Short-circuit current increases with
|VDSp|. This is clearly much larger
on average for small CL compared
to large CL.
 Similarly, short-circuit current can
exist for low-to-high transition at
output.
|VDSp|
Pull-up turns off
before VDSp becomes
significant
output for
small CL
Best to maintain approximately equal input/output slopes
PMOS
turns off
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TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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Sub-Threshold
Current
Leakage
 Leakage current of reverse biased S/D junctions
 Sub-threshold current of MOS devices
 no channel  parasitic bipolar device:
n+ (source) – p (bulk) – n+ (drain)
10-2
 Important source of leakage
 Rapidly becomes
bottleneck with lowering
threshold voltages
 Modern technologies offer
low-Vt and hi-Vt devices
Balance speed and power
Linear
10-4
10-6
Quadratic
ID(A)
§3.3
10-8
10-10
qVGS
I D  I 0e nkT
qVDS



kT
1 e




10-120
1    VDS 


TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
Exponential
VT
0.5
1
1.5
2
Y. Taur, CMOS design near the limit
of scaling, IBMJRD, Volume 46,
Numbers 2/3, 2002
2.5
VGS (V)
13/03/15
75
Sub-Threshold Current
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
In
Out
C G1
Linear
10-4
ID(A)
Quadratic
10-8
10-120
Exponential
VT
0.5
1
1.5
2
Ex.
5.13
2.5
VGS (V)
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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1
f
CL= FCG1
 Goal:
Goal Minimize
Minimi e Energy
Energ of whole
hole circuit
circ it
C VDD
t pHL
 0.52 parameters: f andLVDD
 Design
'
 VVTn =VVDSATn / 2)
)n k nVDSATn
 tp  tpref(Wof/ Lcircuit
with f =(V1DD
and
DD
ref
10-2
10-10
76
Transistor Sizing for Minimum Energy
 Rapidly becomes bottleneck with lowering threshold
voltages
 Modern technologies offer low-Vt and hi-Vt devices
Balance speed and power
10-6
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77

f 
F 
t p  t p0   1     1   
   f  

VDD
See Eq. 5.21
t p0 
VDD  VTE
VTE = VT + ½VDSAT : Effective VT
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13
13/03/15
Transistor Sizing (2)

f 
F
t p  t p0   1     1 
   f

t pref

VDD
VDD  VTE
4
3.5
F

2f  
t p 0 
f   VDD  Vref  VTE
 

t p 0ref 3  F 
 Vref  VDD  VTE
F

2  f  

f 
 3  F 

2
2.5
5
2
1.5




VTE: technology (0.5 V), Vref: standard supply (2.5 V)
F: fanout
VDD, f: design parameters
VDD is a function of f, given a fixed performance
VDD 
 Supply voltage needed
as a function of f to
maintain reference
performance
 Lowest supply voltage
needed for f = F 0.5
F=1
3
vdd (V)
v
tp
t p0 
(with = 1, tpref  f=1):
Performance Constraint
1

 

Transistor Sizing (3)
VDD=f(f)
10
1
20
0.5
0
1
2
3
4
5
6
VDD 
f 15  5F 
14f  8f 2  8F  10fF 
7
f
f 15  5F 
14f  8f 2  8F  10fF 
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TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
Transistor Sizing (4)
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Transistor Sizing (5)
E/Eref=f(f)
2 C 1   1  f   F 
E  VDD
g1
CL= FCG1
2
V
  2  2f  F 
  DD  

E ref  Vref   4  F 
E
normalized energy
Energy for single Transition:
1.5
Size of 1st +
2nd inverter
Cg1 + Cint
F=1
V
 2  2  2f  F 
E
  DD  

E ref  Vref   4  F 
2
1
5
10
0.5
F=20
VDD 
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
f 15  5F 
14f  8f 2  8F  10fF 
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0
1
6 7
f
 Device sizing is effective
 Oversizing is expensive for power
 Optimal sizing for energy slightly different from sizing for performance
81
2
3
4
5
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
4004
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Moore’s Law
The number of transistors
that can be integrated on a
single chip will double
every 18 months
Technology Scaling
Gordon Moore, co-founder of Intel
[El t
[Electronics,
i
Vol
V l 38,
38 No.
N 8,
8 1965]
Also see: IBM JRD, Vol 46, no 2/3, 2002
Scaling CMOS to the limit
http://www.research.ibm.com/journal/rd46-23.html
§ 5.6
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14
13/03/15
IC Technology Scaling
Why Scaling
Scaling improves density and performance
 Reduce price per function:
 Want to sell more functions (transistors) per
chip for the same money  better products
 Build same products cheaper, sell the same
part for less money  larger market
 Price of a transistor has to be reduced
 But also want to be faster, smaller, lower power
 First order scaling theory

dimensions,

voltages

intrinsic delay

power per transistor
1982
S5
85
Scaling Models
2008
S150
2010
S200
(65nm)
first proc
13/03/15
2008 / 1971
0.007
0.007
0.007
0 00004
0.00004
 Scaling trend
1971
S=1 (10m)
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
1/S
1/S
1/S
1/S2
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Scaling for Velocity Saturated Devices
Constant Field Scaling: S = U
Parameter
Fixed Voltage Scaling
 most common model until 1990’s
 only dimensions scale, voltages remain constant
Full Scaling (Constant Electrical Field)
 ideal model — dimensions and voltage
g scale together
g
by
y
the same factor S
General Scaling
 most realistic for today’s situation
 Two scaling factors:
dimensions scale with S
voltages scale with U
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
13/03/15
Relation
General Scaling
W, L, tox
1/S
VDD, VT
1/U
NSUB
V / Wdepl2
S2/U
Area / Device
WL
1/S2
Cox
1/tox
S
Cgate
Cox W L
1/S
kn, kp
Cox W / L
S
Isat
Cox W V
1/U
Current Density
Isat / Area
S2/U
Ron
V / Isat
1
Intrinsic Delay
Ron Cgate
1/S
Power / Device
Isat V
1/U2
Power Density
P / Area
S2/U2
87
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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89
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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Technology Practice & ITRS
 Scaling – Technology Generations
 S  1.4  20.5 per generation
 … – 250 – 180 – 130 – 90 – 65 – 45 – 35 – 22 – … nm
 ITRS: International Technology Roadmap for Semiconductors
Industry-wide organization for forecasting technology
developments – and (planning) requirements
http://www.itrs.net/home.html
Not really – it is more like science
(and a self-fulfilling prophecy at the same time)
TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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Summary
 Digital Gate Characterization (§ 1.3)
 Static Behavior (Robustness) (§ 5.3)
 VTC
 Switching Threshold
 Noise Margins
 Dynamic Behavior (Performance) (§ 5.4)
 Capacitances
 Delay
 Power (§ 5.5)
 Dynamic Power, Static Power, Metrics
 Scaling (§ 5.6)
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TUD/EE ET4293 - DigIC - 12/13 - © NvdM - 03 Inverter
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16